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AMDGPUAsmPrinter.cpp
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1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12 /// code. When passed an MCAsmStreamer it prints assembly and when passed
13 /// an MCObjectStreamer it outputs binary code.
14 //
15 //===----------------------------------------------------------------------===//
16 //
17 
18 #include "AMDGPUAsmPrinter.h"
19 #include "AMDGPU.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDGPUTargetMachine.h"
25 #include "R600AsmPrinter.h"
26 #include "R600Defines.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIInstrInfo.h"
31 #include "SIMachineFunctionInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "Utils/AMDGPUBaseInfo.h"
34 #include "llvm/BinaryFormat/ELF.h"
36 #include "llvm/IR/DiagnosticInfo.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCSectionELF.h"
39 #include "llvm/MC/MCStreamer.h"
45 
46 using namespace llvm;
47 using namespace llvm::AMDGPU;
48 using namespace llvm::AMDGPU::HSAMD;
49 
50 // TODO: This should get the default rounding mode from the kernel. We just set
51 // the default here, but this could change if the OpenCL rounding mode pragmas
52 // are used.
53 //
54 // The denormal mode here should match what is reported by the OpenCL runtime
55 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
56 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
57 //
58 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
59 // precision, and leaves single precision to flush all and does not report
60 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
61 // CL_FP_DENORM for both.
62 //
63 // FIXME: It seems some instructions do not support single precision denormals
64 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
65 // and sin_f32, cos_f32 on most parts).
66 
67 // We want to use these instructions, and using fp32 denormals also causes
68 // instructions to run at the double precision rate for the device so it's
69 // probably best to just report no single precision denormals.
72  // TODO: Is there any real use for the flush in only / flush out only modes?
73 
74  uint32_t FP32Denormals =
76 
77  uint32_t FP64Denormals =
79 
82  FP_DENORM_MODE_SP(FP32Denormals) |
83  FP_DENORM_MODE_DP(FP64Denormals);
84 }
85 
86 static AsmPrinter *
88  std::unique_ptr<MCStreamer> &&Streamer) {
89  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
90 }
91 
92 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
97 }
98 
100  std::unique_ptr<MCStreamer> Streamer)
101  : AsmPrinter(TM, std::move(Streamer)) {
103  HSAMetadataStream.reset(new MetadataStreamerV3());
104  else
105  HSAMetadataStream.reset(new MetadataStreamerV2());
106 }
107 
109  return "AMDGPU Assembly Printer";
110 }
111 
113  return TM.getMCSubtargetInfo();
114 }
115 
117  if (!OutStreamer)
118  return nullptr;
119  return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
120 }
121 
124  std::string ExpectedTarget;
125  raw_string_ostream ExpectedTargetOS(ExpectedTarget);
126  IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
127 
128  getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
129  }
130 
131  if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
133  return;
134 
136  HSAMetadataStream->begin(M);
137 
139  readPALMetadata(M);
140 
142  return;
143 
144  // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
147 
148  // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
151  Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
152 }
153 
155  // Following code requires TargetStreamer to be present.
156  if (!getTargetStreamer())
157  return;
158 
160  // Emit ISA Version (NT_AMD_AMDGPU_ISA).
161  std::string ISAVersionString;
162  raw_string_ostream ISAVersionStream(ISAVersionString);
163  IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
164  getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
165  }
166 
167  // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
168  if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
169  HSAMetadataStream->end();
170  bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
171  (void)Success;
172  assert(Success && "Malformed HSA Metadata");
173  }
174 
176  // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
177  if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
178  // Copy the PAL metadata from the map where we collected it into a vector,
179  // then write it as a .note.
180  PALMD::Metadata PALMetadataVector;
181  for (auto i : PALMetadataMap) {
182  PALMetadataVector.push_back(i.first);
183  PALMetadataVector.push_back(i.second);
184  }
185  getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
186  }
187  }
188 }
189 
191  const MachineBasicBlock *MBB) const {
193  return false;
194 
195  if (MBB->empty())
196  return true;
197 
198  // If this is a block implementing a long branch, an expression relative to
199  // the start of the block is needed. to the start of the block.
200  // XXX - Is there a smarter way to check this?
201  return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
202 }
203 
206  if (!MFI.isEntryFunction())
207  return;
208 
209  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
210  const Function &F = MF->getFunction();
211  if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
212  (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
213  F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
214  amd_kernel_code_t KernelCode;
215  getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
216  getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
217  }
218 
219  if (STM.isAmdHsaOS())
220  HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
221 }
222 
225  if (!MFI.isEntryFunction())
226  return;
227 
230  return;
231 
232  auto &Streamer = getTargetStreamer()->getStreamer();
233  auto &Context = Streamer.getContext();
234  auto &ObjectFileInfo = *Context.getObjectFileInfo();
235  auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
236 
237  Streamer.PushSection();
238  Streamer.SwitchSection(&ReadOnlySection);
239 
240  // CP microcode requires the kernel descriptor to be allocated on 64 byte
241  // alignment.
242  Streamer.EmitValueToAlignment(64, 0, 1, 0);
243  if (ReadOnlySection.getAlignment() < 64)
244  ReadOnlySection.setAlignment(64);
245 
246  const MCSubtargetInfo &STI = MF->getSubtarget();
247 
248  SmallString<128> KernelName;
249  getNameWithPrefix(KernelName, &MF->getFunction());
251  STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
252  CurrentProgramInfo.NumVGPRsForWavesPerEU,
253  CurrentProgramInfo.NumSGPRsForWavesPerEU -
255  CurrentProgramInfo.VCCUsed,
256  CurrentProgramInfo.FlatUsed),
257  CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
258  hasXNACK(STI));
259 
260  Streamer.PopSection();
261 }
262 
267  return;
268  }
269 
271  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
272  if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
274  getNameWithPrefix(SymbolName, &MF->getFunction()),
276  SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
277  }
278  if (STM.dumpCode()) {
279  // Disassemble function name label to text.
280  DisasmLines.push_back(MF->getName().str() + ":");
282  HexLines.push_back("");
283  }
284 
286 }
287 
289  const GCNSubtarget &STI = MBB.getParent()->getSubtarget<GCNSubtarget>();
290  if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
291  // Write a line for the basic block label if it is not only fallthrough.
292  DisasmLines.push_back(
293  (Twine("BB") + Twine(getFunctionNumber())
294  + "_" + Twine(MBB.getNumber()) + ":").str());
296  HexLines.push_back("");
297  }
299 }
300 
302 
303  // Group segment variables aren't emitted in HSA.
304  if (AMDGPU::isGroupSegment(GV))
305  return;
306 
308 }
309 
311  CallGraphResourceInfo.clear();
312  return AsmPrinter::doFinalization(M);
313 }
314 
315 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
316 // frontend into our PALMetadataMap, ready for per-function modification. It
317 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
318 // which is an integer value, and each two integer values forms a key=value
319 // pair that we store as PALMetadataMap[key]=value in the map.
320 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
321  auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
322  if (!NamedMD || !NamedMD->getNumOperands())
323  return;
324  auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
325  if (!Tuple)
326  return;
327  for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
328  auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
329  auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
330  if (!Key || !Val)
331  continue;
332  PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
333  }
334 }
335 
336 // Print comments that apply to both callable functions and entry points.
337 void AMDGPUAsmPrinter::emitCommonFunctionComments(
338  uint32_t NumVGPR,
339  uint32_t NumSGPR,
340  uint64_t ScratchSize,
341  uint64_t CodeSize,
342  const AMDGPUMachineFunction *MFI) {
343  OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
344  OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
345  OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
346  OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
347  OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
348  false);
349 }
350 
351 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
352  const MachineFunction &MF) const {
354  uint16_t KernelCodeProperties = 0;
355 
356  if (MFI.hasPrivateSegmentBuffer()) {
357  KernelCodeProperties |=
358  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
359  }
360  if (MFI.hasDispatchPtr()) {
361  KernelCodeProperties |=
362  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
363  }
364  if (MFI.hasQueuePtr()) {
365  KernelCodeProperties |=
366  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
367  }
368  if (MFI.hasKernargSegmentPtr()) {
369  KernelCodeProperties |=
370  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
371  }
372  if (MFI.hasDispatchID()) {
373  KernelCodeProperties |=
374  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
375  }
376  if (MFI.hasFlatScratchInit()) {
377  KernelCodeProperties |=
378  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
379  }
380 
381  return KernelCodeProperties;
382 }
383 
384 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
385  const MachineFunction &MF,
386  const SIProgramInfo &PI) const {
387  amdhsa::kernel_descriptor_t KernelDescriptor;
388  memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
389 
393 
394  KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
395  KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
396  KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
397  KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
398  KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
399 
400  return KernelDescriptor;
401 }
402 
404  CurrentProgramInfo = SIProgramInfo();
405 
407 
408  // The starting address of all shader programs must be 256 bytes aligned.
409  // Regular functions just need the basic required instruction alignment.
410  MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
411 
413 
414  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
416  // FIXME: This should be an explicit check for Mesa.
417  if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
418  MCSectionELF *ConfigSection =
419  Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
420  OutStreamer->SwitchSection(ConfigSection);
421  }
422 
423  if (MFI->isEntryFunction()) {
424  getSIProgramInfo(CurrentProgramInfo, MF);
425  } else {
426  auto I = CallGraphResourceInfo.insert(
427  std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
428  SIFunctionResourceInfo &Info = I.first->second;
429  assert(I.second && "should only be called once per function");
430  Info = analyzeResourceUsage(MF);
431  }
432 
433  if (STM.isAmdPalOS())
434  EmitPALMetadata(MF, CurrentProgramInfo);
435  else if (!STM.isAmdHsaOS()) {
436  EmitProgramInfoSI(MF, CurrentProgramInfo);
437  }
438 
439  DisasmLines.clear();
440  HexLines.clear();
441  DisasmLineMaxLen = 0;
442 
444 
445  if (isVerbose()) {
446  MCSectionELF *CommentSection =
447  Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
448  OutStreamer->SwitchSection(CommentSection);
449 
450  if (!MFI->isEntryFunction()) {
451  OutStreamer->emitRawComment(" Function info:", false);
452  SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
453  emitCommonFunctionComments(
454  Info.NumVGPR,
455  Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
456  Info.PrivateSegmentSize,
457  getFunctionCodeSize(MF), MFI);
458  return false;
459  }
460 
461  OutStreamer->emitRawComment(" Kernel info:", false);
462  emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
463  CurrentProgramInfo.NumSGPR,
464  CurrentProgramInfo.ScratchSize,
465  getFunctionCodeSize(MF), MFI);
466 
467  OutStreamer->emitRawComment(
468  " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
469  OutStreamer->emitRawComment(
470  " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
471  OutStreamer->emitRawComment(
472  " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
473  " bytes/workgroup (compile time only)", false);
474 
475  OutStreamer->emitRawComment(
476  " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
477  OutStreamer->emitRawComment(
478  " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
479 
480  OutStreamer->emitRawComment(
481  " NumSGPRsForWavesPerEU: " +
482  Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
483  OutStreamer->emitRawComment(
484  " NumVGPRsForWavesPerEU: " +
485  Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
486 
487  OutStreamer->emitRawComment(
488  " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
489 
491  OutStreamer->emitRawComment(
492  " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
493  Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
494  OutStreamer->emitRawComment(
495  " DebuggerPrivateSegmentBufferSGPR: s" +
496  Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
497  }
498 
499  OutStreamer->emitRawComment(
500  " COMPUTE_PGM_RSRC2:USER_SGPR: " +
501  Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
502  OutStreamer->emitRawComment(
503  " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
504  Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
505  OutStreamer->emitRawComment(
506  " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
507  Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
508  OutStreamer->emitRawComment(
509  " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
510  Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
511  OutStreamer->emitRawComment(
512  " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
513  Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
514  OutStreamer->emitRawComment(
515  " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
516  Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
517  false);
518  }
519 
520  if (STM.dumpCode()) {
521 
522  OutStreamer->SwitchSection(
523  Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
524 
525  for (size_t i = 0; i < DisasmLines.size(); ++i) {
526  std::string Comment = "\n";
527  if (!HexLines[i].empty()) {
528  Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
529  Comment += " ; " + HexLines[i] + "\n";
530  }
531 
532  OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
533  OutStreamer->EmitBytes(StringRef(Comment));
534  }
535  }
536 
537  return false;
538 }
539 
540 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
541  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
542  const SIInstrInfo *TII = STM.getInstrInfo();
543 
544  uint64_t CodeSize = 0;
545 
546  for (const MachineBasicBlock &MBB : MF) {
547  for (const MachineInstr &MI : MBB) {
548  // TODO: CodeSize should account for multiple functions.
549 
550  // TODO: Should we count size of debug info?
551  if (MI.isDebugInstr())
552  continue;
553 
554  CodeSize += TII->getInstSizeInBytes(MI);
555  }
556  }
557 
558  return CodeSize;
559 }
560 
562  const SIInstrInfo &TII,
563  unsigned Reg) {
564  for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
565  if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
566  return true;
567  }
568 
569  return false;
570 }
571 
573  const GCNSubtarget &ST) const {
574  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
575  UsesVCC, UsesFlatScratch);
576 }
577 
578 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
579  const MachineFunction &MF) const {
580  SIFunctionResourceInfo Info;
581 
583  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
584  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
585  const MachineRegisterInfo &MRI = MF.getRegInfo();
586  const SIInstrInfo *TII = ST.getInstrInfo();
587  const SIRegisterInfo &TRI = TII->getRegisterInfo();
588 
589  Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
590  MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
591 
592  // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
593  // instructions aren't used to access the scratch buffer. Inline assembly may
594  // need it though.
595  //
596  // If we only have implicit uses of flat_scr on flat instructions, it is not
597  // really needed.
598  if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
599  (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
600  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
601  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
602  Info.UsesFlatScratch = false;
603  }
604 
605  Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
606  Info.PrivateSegmentSize = FrameInfo.getStackSize();
607  if (MFI->isStackRealigned())
608  Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
609 
610 
611  Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
612  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
613 
614  // If there are no calls, MachineRegisterInfo can tell us the used register
615  // count easily.
616  // A tail call isn't considered a call for MachineFrameInfo's purposes.
617  if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
618  MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
619  for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
620  if (MRI.isPhysRegUsed(Reg)) {
621  HighestVGPRReg = Reg;
622  break;
623  }
624  }
625 
626  MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
627  for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
628  if (MRI.isPhysRegUsed(Reg)) {
629  HighestSGPRReg = Reg;
630  break;
631  }
632  }
633 
634  // We found the maximum register index. They start at 0, so add one to get the
635  // number of registers.
636  Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
637  TRI.getHWRegIndex(HighestVGPRReg) + 1;
638  Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
639  TRI.getHWRegIndex(HighestSGPRReg) + 1;
640 
641  return Info;
642  }
643 
644  int32_t MaxVGPR = -1;
645  int32_t MaxSGPR = -1;
646  uint64_t CalleeFrameSize = 0;
647 
648  for (const MachineBasicBlock &MBB : MF) {
649  for (const MachineInstr &MI : MBB) {
650  // TODO: Check regmasks? Do they occur anywhere except calls?
651  for (const MachineOperand &MO : MI.operands()) {
652  unsigned Width = 0;
653  bool IsSGPR = false;
654 
655  if (!MO.isReg())
656  continue;
657 
658  unsigned Reg = MO.getReg();
659  switch (Reg) {
660  case AMDGPU::EXEC:
661  case AMDGPU::EXEC_LO:
662  case AMDGPU::EXEC_HI:
663  case AMDGPU::SCC:
664  case AMDGPU::M0:
665  case AMDGPU::SRC_SHARED_BASE:
666  case AMDGPU::SRC_SHARED_LIMIT:
667  case AMDGPU::SRC_PRIVATE_BASE:
668  case AMDGPU::SRC_PRIVATE_LIMIT:
669  continue;
670 
671  case AMDGPU::NoRegister:
672  assert(MI.isDebugInstr());
673  continue;
674 
675  case AMDGPU::VCC:
676  case AMDGPU::VCC_LO:
677  case AMDGPU::VCC_HI:
678  Info.UsesVCC = true;
679  continue;
680 
681  case AMDGPU::FLAT_SCR:
682  case AMDGPU::FLAT_SCR_LO:
683  case AMDGPU::FLAT_SCR_HI:
684  continue;
685 
686  case AMDGPU::XNACK_MASK:
687  case AMDGPU::XNACK_MASK_LO:
688  case AMDGPU::XNACK_MASK_HI:
689  llvm_unreachable("xnack_mask registers should not be used");
690 
691  case AMDGPU::LDS_DIRECT:
692  llvm_unreachable("lds_direct register should not be used");
693 
694  case AMDGPU::TBA:
695  case AMDGPU::TBA_LO:
696  case AMDGPU::TBA_HI:
697  case AMDGPU::TMA:
698  case AMDGPU::TMA_LO:
699  case AMDGPU::TMA_HI:
700  llvm_unreachable("trap handler registers should not be used");
701 
702  default:
703  break;
704  }
705 
706  if (AMDGPU::SReg_32RegClass.contains(Reg)) {
707  assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
708  "trap handler registers should not be used");
709  IsSGPR = true;
710  Width = 1;
711  } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
712  IsSGPR = false;
713  Width = 1;
714  } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
715  assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
716  "trap handler registers should not be used");
717  IsSGPR = true;
718  Width = 2;
719  } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
720  IsSGPR = false;
721  Width = 2;
722  } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
723  IsSGPR = false;
724  Width = 3;
725  } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
726  assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
727  "trap handler registers should not be used");
728  IsSGPR = true;
729  Width = 4;
730  } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
731  IsSGPR = false;
732  Width = 4;
733  } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
734  assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
735  "trap handler registers should not be used");
736  IsSGPR = true;
737  Width = 8;
738  } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
739  IsSGPR = false;
740  Width = 8;
741  } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
742  assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
743  "trap handler registers should not be used");
744  IsSGPR = true;
745  Width = 16;
746  } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
747  IsSGPR = false;
748  Width = 16;
749  } else {
750  llvm_unreachable("Unknown register class");
751  }
752  unsigned HWReg = TRI.getHWRegIndex(Reg);
753  int MaxUsed = HWReg + Width - 1;
754  if (IsSGPR) {
755  MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
756  } else {
757  MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
758  }
759  }
760 
761  if (MI.isCall()) {
762  // Pseudo used just to encode the underlying global. Is there a better
763  // way to track this?
764 
765  const MachineOperand *CalleeOp
766  = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
767  const Function *Callee = cast<Function>(CalleeOp->getGlobal());
768  if (Callee->isDeclaration()) {
769  // If this is a call to an external function, we can't do much. Make
770  // conservative guesses.
771 
772  // 48 SGPRs - vcc, - flat_scr, -xnack
773  int MaxSGPRGuess =
774  47 - IsaInfo::getNumExtraSGPRs(&ST, true, ST.hasFlatAddressSpace());
775  MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
776  MaxVGPR = std::max(MaxVGPR, 23);
777 
778  CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
779  Info.UsesVCC = true;
780  Info.UsesFlatScratch = ST.hasFlatAddressSpace();
781  Info.HasDynamicallySizedStack = true;
782  } else {
783  // We force CodeGen to run in SCC order, so the callee's register
784  // usage etc. should be the cumulative usage of all callees.
785  auto I = CallGraphResourceInfo.find(Callee);
786  assert(I != CallGraphResourceInfo.end() &&
787  "callee should have been handled before caller");
788 
789  MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
790  MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
791  CalleeFrameSize
792  = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
793  Info.UsesVCC |= I->second.UsesVCC;
794  Info.UsesFlatScratch |= I->second.UsesFlatScratch;
795  Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
796  Info.HasRecursion |= I->second.HasRecursion;
797  }
798 
799  if (!Callee->doesNotRecurse())
800  Info.HasRecursion = true;
801  }
802  }
803  }
804 
805  Info.NumExplicitSGPR = MaxSGPR + 1;
806  Info.NumVGPR = MaxVGPR + 1;
807  Info.PrivateSegmentSize += CalleeFrameSize;
808 
809  return Info;
810 }
811 
812 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
813  const MachineFunction &MF) {
814  SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
815 
816  ProgInfo.NumVGPR = Info.NumVGPR;
817  ProgInfo.NumSGPR = Info.NumExplicitSGPR;
818  ProgInfo.ScratchSize = Info.PrivateSegmentSize;
819  ProgInfo.VCCUsed = Info.UsesVCC;
820  ProgInfo.FlatUsed = Info.UsesFlatScratch;
821  ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
822 
823  if (!isUInt<32>(ProgInfo.ScratchSize)) {
824  DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
825  ProgInfo.ScratchSize, DS_Error);
826  MF.getFunction().getContext().diagnose(DiagStackSize);
827  }
828 
829  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
831  const SIInstrInfo *TII = STM.getInstrInfo();
832  const SIRegisterInfo *RI = &TII->getRegisterInfo();
833 
834  // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
835  // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
836  // unified.
837  unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
838  &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
839 
840  // Check the addressable register limit before we add ExtraSGPRs.
842  !STM.hasSGPRInitBug()) {
843  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
844  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
845  // This can happen due to a compiler bug or when using inline asm.
846  LLVMContext &Ctx = MF.getFunction().getContext();
848  "addressable scalar registers",
849  ProgInfo.NumSGPR, DS_Error,
851  MaxAddressableNumSGPRs);
852  Ctx.diagnose(Diag);
853  ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
854  }
855  }
856 
857  // Account for extra SGPRs and VGPRs reserved for debugger use.
858  ProgInfo.NumSGPR += ExtraSGPRs;
859 
860  // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
861  // dispatch registers are function args.
862  unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
863  for (auto &Arg : MF.getFunction().args()) {
864  unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
865  if (Arg.hasAttribute(Attribute::InReg))
866  WaveDispatchNumSGPR += NumRegs;
867  else
868  WaveDispatchNumVGPR += NumRegs;
869  }
870  ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
871  ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
872 
873  // Adjust number of registers used to meet default/requested minimum/maximum
874  // number of waves per execution unit request.
875  ProgInfo.NumSGPRsForWavesPerEU = std::max(
876  std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
877  ProgInfo.NumVGPRsForWavesPerEU = std::max(
878  std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
879 
881  STM.hasSGPRInitBug()) {
882  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
883  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
884  // This can happen due to a compiler bug or when using inline asm to use
885  // the registers which are usually reserved for vcc etc.
886  LLVMContext &Ctx = MF.getFunction().getContext();
888  "scalar registers",
889  ProgInfo.NumSGPR, DS_Error,
891  MaxAddressableNumSGPRs);
892  Ctx.diagnose(Diag);
893  ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
894  ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
895  }
896  }
897 
898  if (STM.hasSGPRInitBug()) {
899  ProgInfo.NumSGPR =
901  ProgInfo.NumSGPRsForWavesPerEU =
903  }
904 
905  if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
906  LLVMContext &Ctx = MF.getFunction().getContext();
907  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
908  MFI->getNumUserSGPRs(), DS_Error);
909  Ctx.diagnose(Diag);
910  }
911 
912  if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
913  LLVMContext &Ctx = MF.getFunction().getContext();
914  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
915  MFI->getLDSSize(), DS_Error);
916  Ctx.diagnose(Diag);
917  }
918 
920  &STM, ProgInfo.NumSGPRsForWavesPerEU);
922  &STM, ProgInfo.NumVGPRsForWavesPerEU);
923 
924  // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
925  // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
926  // attribute was requested.
927  if (STM.debuggerEmitPrologue()) {
929  RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
931  RI->getHWRegIndex(MFI->getScratchRSrcReg());
932  }
933 
934  // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
935  // register.
936  ProgInfo.FloatMode = getFPMode(MF);
937 
938  ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
939 
940  // Make clamp modifier on NaN input returns 0.
941  ProgInfo.DX10Clamp = STM.enableDX10Clamp();
942 
943  unsigned LDSAlignShift;
945  // LDS is allocated in 64 dword blocks.
946  LDSAlignShift = 8;
947  } else {
948  // LDS is allocated in 128 dword blocks.
949  LDSAlignShift = 9;
950  }
951 
952  unsigned LDSSpillSize =
953  MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
954 
955  ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
956  ProgInfo.LDSBlocks =
957  alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
958 
959  // Scratch is allocated in 256 dword blocks.
960  unsigned ScratchAlignShift = 10;
961  // We need to program the hardware with the amount of scratch memory that
962  // is used by the entire wave. ProgInfo.ScratchSize is the amount of
963  // scratch memory used per thread.
964  ProgInfo.ScratchBlocks =
965  alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
966  1ULL << ScratchAlignShift) >>
967  ScratchAlignShift;
968 
969  ProgInfo.ComputePGMRSrc1 =
970  S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
971  S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
972  S_00B848_PRIORITY(ProgInfo.Priority) |
973  S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
974  S_00B848_PRIV(ProgInfo.Priv) |
975  S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
976  S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
977  S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
978 
979  // 0 = X, 1 = XY, 2 = XYZ
980  unsigned TIDIGCompCnt = 0;
981  if (MFI->hasWorkItemIDZ())
982  TIDIGCompCnt = 2;
983  else if (MFI->hasWorkItemIDY())
984  TIDIGCompCnt = 1;
985 
986  ProgInfo.ComputePGMRSrc2 =
987  S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
988  S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
989  // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
991  S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
992  S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
993  S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
994  S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
995  S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
997  // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
998  S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
999  S_00B84C_EXCP_EN(0);
1000 }
1001 
1002 static unsigned getRsrcReg(CallingConv::ID CallConv) {
1003  switch (CallConv) {
1004  default: LLVM_FALLTHROUGH;
1012  }
1013 }
1014 
1015 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1016  const SIProgramInfo &CurrentProgramInfo) {
1018  unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1019 
1021  OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1022 
1023  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1024 
1025  OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1026  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1027 
1028  OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1029  OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1030 
1031  // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1032  // 0" comment but I don't see a corresponding field in the register spec.
1033  } else {
1034  OutStreamer->EmitIntValue(RsrcReg, 4);
1035  OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1036  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1037  OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1038  OutStreamer->EmitIntValue(
1039  S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1040  }
1041 
1044  OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1045  OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1046  OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1047  OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1048  OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1049  }
1050 
1051  OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1052  OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1053  OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1054  OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1055 }
1056 
1057 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1058 // is AMDPAL. It stores each compute/SPI register setting and other PAL
1059 // metadata items into the PALMetadataMap, combining with any provided by the
1060 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1061 // then written as a single block in the .note section.
1062 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1063  const SIProgramInfo &CurrentProgramInfo) {
1065  // Given the calling convention, calculate the register number for rsrc1. In
1066  // principle the register number could change in future hardware, but we know
1067  // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1068  // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1069  // that we use a register number rather than a byte offset, so we need to
1070  // divide by 4.
1071  unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1072  unsigned Rsrc2Reg = Rsrc1Reg + 1;
1073  // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1074  // with a constant offset to access any non-register shader-specific PAL
1075  // metadata key.
1076  unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1077  switch (MF.getFunction().getCallingConv()) {
1079  ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1080  break;
1082  ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1083  break;
1085  ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1086  break;
1088  ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1089  break;
1091  ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1092  break;
1094  ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1095  break;
1096  }
1097  unsigned NumUsedVgprsKey = ScratchSizeKey +
1099  unsigned NumUsedSgprsKey = ScratchSizeKey +
1101  PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1102  PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1104  PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1105  PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1106  // ScratchSize is in bytes, 16 aligned.
1107  PALMetadataMap[ScratchSizeKey] |=
1108  alignTo(CurrentProgramInfo.ScratchSize, 16);
1109  } else {
1110  PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1111  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1112  if (CurrentProgramInfo.ScratchBlocks > 0)
1113  PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1114  // ScratchSize is in bytes, 16 aligned.
1115  PALMetadataMap[ScratchSizeKey] |=
1116  alignTo(CurrentProgramInfo.ScratchSize, 16);
1117  }
1119  PALMetadataMap[Rsrc2Reg] |=
1120  S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1121  PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1122  PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1123  }
1124 }
1125 
1126 // This is supposed to be log2(Size)
1128  switch (Size) {
1129  case 4:
1130  return AMD_ELEMENT_4_BYTES;
1131  case 8:
1132  return AMD_ELEMENT_8_BYTES;
1133  case 16:
1134  return AMD_ELEMENT_16_BYTES;
1135  default:
1136  llvm_unreachable("invalid private_element_size");
1137  }
1138 }
1139 
1140 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1141  const SIProgramInfo &CurrentProgramInfo,
1142  const MachineFunction &MF) const {
1143  const Function &F = MF.getFunction();
1146 
1148  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1149 
1151 
1153  CurrentProgramInfo.ComputePGMRSrc1 |
1154  (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1156 
1157  if (CurrentProgramInfo.DynamicCallStack)
1159 
1162  getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1163 
1164  if (MFI->hasPrivateSegmentBuffer()) {
1165  Out.code_properties |=
1167  }
1168 
1169  if (MFI->hasDispatchPtr())
1171 
1172  if (MFI->hasQueuePtr())
1174 
1175  if (MFI->hasKernargSegmentPtr())
1177 
1178  if (MFI->hasDispatchID())
1180 
1181  if (MFI->hasFlatScratchInit())
1183 
1184  if (MFI->hasDispatchPtr())
1186 
1187  if (STM.debuggerSupported())
1189 
1190  if (STM.isXNACKEnabled())
1192 
1193  unsigned MaxKernArgAlign;
1194  Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1195  Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1196  Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1197  Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1198  Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1199 
1200  // These alignment values are specified in powers of two, so alignment =
1201  // 2^n. The minimum alignment is 2^4 = 16.
1202  Out.kernarg_segment_alignment = std::max((size_t)4,
1203  countTrailingZeros(MaxKernArgAlign));
1204 
1205  if (STM.debuggerEmitPrologue()) {
1207  CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1209  CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1210  }
1211 }
1212 
1214  unsigned AsmVariant,
1215  const char *ExtraCode, raw_ostream &O) {
1216  // First try the generic code, which knows about modifiers like 'c' and 'n'.
1217  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1218  return false;
1219 
1220  if (ExtraCode && ExtraCode[0]) {
1221  if (ExtraCode[1] != 0)
1222  return true; // Unknown modifier.
1223 
1224  switch (ExtraCode[0]) {
1225  case 'r':
1226  break;
1227  default:
1228  return true;
1229  }
1230  }
1231 
1232  // TODO: Should be able to support other operand types like globals.
1233  const MachineOperand &MO = MI->getOperand(OpNo);
1234  if (MO.isReg()) {
1236  *MF->getSubtarget().getRegisterInfo());
1237  return false;
1238  }
1239 
1240  return true;
1241 }
bool enableIEEEBit(const MachineFunction &MF) const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:435
uint16_t DebuggerPrivateSegmentBufferSGPR
Definition: SIProgramInfo.h:61
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:206
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Interface definition for SIRegisterInfo.
Target & getTheGCNTarget()
The target for GCN GPUs.
#define S_00B848_VGPRS(x)
Definition: SIDefines.h:483
#define S_00B848_PRIV(x)
Definition: SIDefines.h:495
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
LLVMContext & Context
AMDGPU specific subclass of TargetSubtarget.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
#define FP_DENORM_MODE_SP(x)
Definition: SIDefines.h:528
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS
Definition: SIDefines.h:434
#define G_00B84C_USER_SGPR(x)
Definition: SIDefines.h:447
const MCSubtargetInfo * getGlobalSTI() const
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool doFinalization(Module &M) override
Shut down the asmprinter.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:298
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
#define G_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:459
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS
Definition: SIDefines.h:430
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
virtual void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK)=0
Instruction set architecture version.
Definition: TargetParser.h:131
#define S_00B84C_SCRATCH_EN(x)
Definition: SIDefines.h:443
const SIInstrInfo * getInstrInfo() const override
#define S_00B84C_TG_SIZE_EN(x)
Definition: SIDefines.h:461
#define S_00B848_DX10_CLAMP(x)
Definition: SIDefines.h:498
uint32_t NumSGPRsForWavesPerEU
Definition: SIProgramInfo.h:47
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
#define G_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:456
Interface definition for R600RegisterInfo.
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
#define R_0286CC_SPI_PS_INPUT_ENA
Definition: SIDefines.h:479
#define S_00B028_SGPRS(x)
Definition: SIDefines.h:440
AsmPrinter * createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr< MCStreamer > &&Streamer)
Track resource usage for kernels / entry functions.
Definition: SIProgramInfo.h:21
Tuple of metadata.
Definition: Metadata.h:1105
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type)=0
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:164
return AArch64::GPR64RegClass contains(Reg)
bool hasFP64Denormals() const
static amd_element_byte_size_t getElementByteSizeValue(unsigned Size)
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:523
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
uint32_t code_properties
Code properties.
Definition: BitVector.h:937
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:470
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
int getLocalMemorySize() const
AMD Kernel Code Object (amd_kernel_code_t).
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:136
bool enableDX10Clamp() const
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
#define G_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:450
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isTrapHandlerEnabled() const
uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR
Definition: SIProgramInfo.h:55
virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata)=0
#define FP_ROUND_MODE_SP(x)
Definition: SIDefines.h:517
Diagnostic information for stack size etc.
#define S_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:455
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
Context object for machine code objects.
Definition: MCContext.h:62
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
#define S_00B848_FLOAT_MODE(x)
Definition: SIDefines.h:492
#define R_00B848_COMPUTE_PGM_RSRC1
Definition: SIDefines.h:482
Key
PAL metadata keys.
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
void EmitFunctionBody()
This method emits the body and trailer for a function.
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:220
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getAddressableNumSGPRs() const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
bool isGroupSegment(const GlobalValue *GV)
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:250
#define S_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:449
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
uint64_t ComputePGMRSrc2
Definition: SIProgramInfo.h:39
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:199
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:188
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool dumpCode() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool debuggerEmitPrologue() const
uint32_t NumVGPRsForWavesPerEU
Definition: SIProgramInfo.h:50
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool hasFP32Denormals() const
#define S_00B848_IEEE_MODE(x)
Definition: SIDefines.h:504
bool isCompute(CallingConv::ID cc)
#define S_00B028_VGPRS(x)
Definition: SIDefines.h:439
static uint32_t getFPMode(const MachineFunction &F)
uint16_t wavefront_sgpr_count
Number of scalar registers used by a wavefront.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define G_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:453
#define S_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:464
#define FP_ROUND_MODE_DP(x)
Definition: SIDefines.h:518
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:425
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
#define S_00B84C_EXCP_EN_MSB(x)
Definition: SIDefines.h:468
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:215
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Generation getGeneration() const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const Triple & getTargetTriple() const
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS
Definition: SIDefines.h:431
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:520
#define S_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:458
The AMDGPU TargetMachine interface definition for hw codgen targets.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES
Definition: SIDefines.h:435
#define S_00B84C_LDS_SIZE(x)
Definition: SIDefines.h:472
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
void EmitBasicBlockStart(const MachineBasicBlock &MBB) const override
Targets can override this to emit stuff at the start of a basic block.
#define R_SPILLED_SGPRS
Definition: SIDefines.h:537
virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName)=0
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
amd_element_byte_size_t
The values used to define the number of bytes to use for the swizzle element size.
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
#define FP_ROUND_ROUND_TO_NEAREST
Definition: SIDefines.h:510
bool doesNotRecurse() const
Determine if the function is known not to recurse, directly or indirectly.
Definition: Function.h:555
#define S_00B84C_EXCP_EN(x)
Definition: SIDefines.h:475
void LLVMInitializeAMDGPUAsmPrinter()
IsaVersion getIsaVersion(StringRef GPU)
unsigned getWavefrontSize() const
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS
Definition: SIDefines.h:436
AMDGPUTargetStreamer * getTargetStreamer() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:202
#define G_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:465
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
std::vector< std::string > HexLines
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS
Definition: SIDefines.h:433
uint64_t kernarg_segment_byte_size
The size in bytes of the kernarg segment that holds the values of the arguments to the kernel...
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
R600 Assembly printer class.
MachineOperand class - Representation of each machine instruction operand.
uint16_t debug_wavefront_private_segment_offset_sgpr
If is_debug_supported is 0 then must be 0.
const MCSubtargetInfo * getMCSubtargetInfo() const
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header)=0
uint16_t workitem_vgpr_count
Number of vector registers used by each work-item.
bool hasSGPRInitBug() const
#define S_00B848_DEBUG_MODE(x)
Definition: SIDefines.h:501
#define FP_DENORM_MODE_DP(x)
Definition: SIDefines.h:529
#define S_0286E8_WAVESIZE(x)
Definition: SIDefines.h:535
const Function & getFunction() const
Return the LLVM function that this machine code represents.
#define S_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:452
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
uint32_t workgroup_group_segment_byte_size
The amount of group segment memory required by a work-group in bytes.
#define AMD_HSA_BITS_SET(dst, mask, val)
amdgpu Simplify well known AMD library false FunctionCallee Callee
std::vector< std::string > DisasmLines
virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor)=0
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
static AsmPrinter * createAMDGPUAsmPrinterPass(TargetMachine &tm, std::unique_ptr< MCStreamer > &&Streamer)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define Success
virtual bool EmitISAVersion(StringRef IsaVersionString)=0
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
void EmitFunctionBodyStart() override
Targets can override this to emit stuff before the first basic block in the function.
virtual void EmitDirectiveAMDGCNTarget(StringRef Target)=0
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool doFinalization(Module &M) override
Shut down the asmprinter.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
#define S_00B848_SGPRS(x)
Definition: SIDefines.h:486
virtual void EmitBasicBlockStart(const MachineBasicBlock &MBB) const
Targets can override this to emit stuff at the start of a basic block.
bool hasXNACK(const MCSubtargetInfo &STI)
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
uint32_t workitem_private_segment_byte_size
The amount of memory required for the combined private, spill and arg segments for a work-item in byt...
#define S_00B84C_USER_SGPR(x)
Definition: SIDefines.h:446
#define I(x, y, z)
Definition: MD5.cpp:58
AMDGPU Assembly printer class.
#define R_00B860_COMPUTE_TMPRING_SIZE
Definition: SIDefines.h:531
Generic base class for all target subtargets.
bool isAmdHsaOrMesa(const Function &F) const
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
uint32_t Size
Definition: Profile.cpp:46
#define R_SPILLED_VGPRS
Definition: SIDefines.h:538
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg)
virtual void EmitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:728
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:205
static unsigned getRsrcReg(CallingConv::ID CallConv)
static StringRef getCPU(StringRef CPU)
Processes a CPU name.
unsigned getMaxNumUserSGPRs() const
#define S_00B860_WAVESIZE(x)
Definition: SIDefines.h:532
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define R_00B84C_COMPUTE_PGM_RSRC2
Definition: SIDefines.h:442
#define S_00B848_PRIORITY(x)
Definition: SIDefines.h:489
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
uint64_t ComputePGMRSrc1
Definition: SIProgramInfo.h:33
#define R_0286E8_SPI_TMPRING_SIZE
Definition: SIDefines.h:534
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
void setAlignment(unsigned A)
setAlignment - Set the alignment (log2, not bytes) of the function.
unsigned getHWRegIndex(unsigned Reg) const
#define S_00B02C_EXTRA_LDS_SIZE(x)
Definition: SIDefines.h:432
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn)
RegisterAsmPrinter - Register an AsmPrinter implementation for the given target.
IRTranslator LLVM IR MI
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS
Definition: SIDefines.h:437
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AMDGPU metadata definitions and in-memory representations.
#define R_0286D0_SPI_PS_INPUT_ADDR
Definition: SIDefines.h:480
uint16_t debug_private_segment_buffer_sgpr
If is_debug_supported is 0 then must be 0.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
const uint64_t Version
Definition: InstrProf.h:894
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
std::vector< uint32_t > Metadata
PAL metadata represented as a vector.
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
iterator_range< arg_iterator > args()
Definition: Function.h:688
bool hasCodeObjectV3() const