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AMDGPUAsmPrinter.cpp
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1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
26 #include "R600AsmPrinter.h"
27 #include "R600Defines.h"
29 #include "R600RegisterInfo.h"
30 #include "SIDefines.h"
31 #include "SIInstrInfo.h"
32 #include "SIMachineFunctionInfo.h"
33 #include "SIRegisterInfo.h"
34 #include "Utils/AMDGPUBaseInfo.h"
35 #include "llvm/BinaryFormat/ELF.h"
37 #include "llvm/IR/DiagnosticInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCSectionELF.h"
40 #include "llvm/MC/MCStreamer.h"
46 
47 using namespace llvm;
48 using namespace llvm::AMDGPU;
49 
50 // TODO: This should get the default rounding mode from the kernel. We just set
51 // the default here, but this could change if the OpenCL rounding mode pragmas
52 // are used.
53 //
54 // The denormal mode here should match what is reported by the OpenCL runtime
55 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
56 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
57 //
58 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
59 // precision, and leaves single precision to flush all and does not report
60 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
61 // CL_FP_DENORM for both.
62 //
63 // FIXME: It seems some instructions do not support single precision denormals
64 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
65 // and sin_f32, cos_f32 on most parts).
66 
67 // We want to use these instructions, and using fp32 denormals also causes
68 // instructions to run at the double precision rate for the device so it's
69 // probably best to just report no single precision denormals.
72  // TODO: Is there any real use for the flush in only / flush out only modes?
73 
74  uint32_t FP32Denormals =
76 
77  uint32_t FP64Denormals =
79 
82  FP_DENORM_MODE_SP(FP32Denormals) |
83  FP_DENORM_MODE_DP(FP64Denormals);
84 }
85 
86 static AsmPrinter *
88  std::unique_ptr<MCStreamer> &&Streamer) {
89  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
90 }
91 
92 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
97 }
98 
100  std::unique_ptr<MCStreamer> Streamer)
101  : AsmPrinter(TM, std::move(Streamer)) {
102 }
103 
105  return "AMDGPU Assembly Printer";
106 }
107 
109  return TM.getMCSubtargetInfo();
110 }
111 
113  if (!OutStreamer)
114  return nullptr;
115  return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
116 }
117 
120  std::string ExpectedTarget;
121  raw_string_ostream ExpectedTargetOS(ExpectedTarget);
122  IsaInfo::streamIsaVersion(getSTI(), ExpectedTargetOS);
123 
124  getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
125 
127  return;
128  }
129 
130  if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
132  return;
133 
135  HSAMetadataStream.begin(M);
136 
138  readPALMetadata(M);
139 
140  // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
143 
144  // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
147  Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
148 }
149 
151  // TODO: Add metadata to code object v3.
154  return;
155 
156  // Following code requires TargetStreamer to be present.
157  if (!getTargetStreamer())
158  return;
159 
160  // Emit ISA Version (NT_AMD_AMDGPU_ISA).
161  std::string ISAVersionString;
162  raw_string_ostream ISAVersionStream(ISAVersionString);
163  IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
164  getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
165 
166  // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
167  if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
168  HSAMetadataStream.end();
169  getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
170  }
171 
172  // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
173  if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
174  // Copy the PAL metadata from the map where we collected it into a vector,
175  // then write it as a .note.
176  PALMD::Metadata PALMetadataVector;
177  for (auto i : PALMetadataMap) {
178  PALMetadataVector.push_back(i.first);
179  PALMetadataVector.push_back(i.second);
180  }
181  getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
182  }
183 }
184 
186  const MachineBasicBlock *MBB) const {
188  return false;
189 
190  if (MBB->empty())
191  return true;
192 
193  // If this is a block implementing a long branch, an expression relative to
194  // the start of the block is needed. to the start of the block.
195  // XXX - Is there a smarter way to check this?
196  return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
197 }
198 
201  if (!MFI.isEntryFunction())
202  return;
203 
204  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
205  const Function &F = MF->getFunction();
206  if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
207  (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
208  F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
209  amd_kernel_code_t KernelCode;
210  getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
211  getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
212  }
213 
215  return;
216 
217  if (!STM.hasCodeObjectV3() && STM.isAmdHsaOS())
218  HSAMetadataStream.emitKernel(*MF, CurrentProgramInfo);
219 }
220 
223  if (!MFI.isEntryFunction())
224  return;
227  return;
228 
229  auto &Streamer = getTargetStreamer()->getStreamer();
230  auto &Context = Streamer.getContext();
231  auto &ObjectFileInfo = *Context.getObjectFileInfo();
232  auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
233 
234  Streamer.PushSection();
235  Streamer.SwitchSection(&ReadOnlySection);
236 
237  // CP microcode requires the kernel descriptor to be allocated on 64 byte
238  // alignment.
239  Streamer.EmitValueToAlignment(64, 0, 1, 0);
240  if (ReadOnlySection.getAlignment() < 64)
241  ReadOnlySection.setAlignment(64);
242 
243  SmallString<128> KernelName;
244  getNameWithPrefix(KernelName, &MF->getFunction());
246  *getSTI(), KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
247  CurrentProgramInfo.NumVGPRsForWavesPerEU,
248  CurrentProgramInfo.NumSGPRsForWavesPerEU -
250  CurrentProgramInfo.VCCUsed,
251  CurrentProgramInfo.FlatUsed),
252  CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
253  hasXNACK(*getSTI()));
254 
255  Streamer.PopSection();
256 }
257 
262  return;
263  }
264 
266  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
267  if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
269  getNameWithPrefix(SymbolName, &MF->getFunction()),
271  SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
272  }
273  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
274  if (STI.dumpCode()) {
275  // Disassemble function name label to text.
276  DisasmLines.push_back(MF->getName().str() + ":");
278  HexLines.push_back("");
279  }
280 
282 }
283 
285  const GCNSubtarget &STI = MBB.getParent()->getSubtarget<GCNSubtarget>();
286  if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
287  // Write a line for the basic block label if it is not only fallthrough.
288  DisasmLines.push_back(
289  (Twine("BB") + Twine(getFunctionNumber())
290  + "_" + Twine(MBB.getNumber()) + ":").str());
292  HexLines.push_back("");
293  }
295 }
296 
298 
299  // Group segment variables aren't emitted in HSA.
300  if (AMDGPU::isGroupSegment(GV))
301  return;
302 
304 }
305 
307  CallGraphResourceInfo.clear();
308  return AsmPrinter::doFinalization(M);
309 }
310 
311 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
312 // frontend into our PALMetadataMap, ready for per-function modification. It
313 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
314 // which is an integer value, and each two integer values forms a key=value
315 // pair that we store as PALMetadataMap[key]=value in the map.
316 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
317  auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
318  if (!NamedMD || !NamedMD->getNumOperands())
319  return;
320  auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
321  if (!Tuple)
322  return;
323  for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
324  auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
325  auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
326  if (!Key || !Val)
327  continue;
328  PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
329  }
330 }
331 
332 // Print comments that apply to both callable functions and entry points.
333 void AMDGPUAsmPrinter::emitCommonFunctionComments(
334  uint32_t NumVGPR,
335  uint32_t NumSGPR,
336  uint64_t ScratchSize,
337  uint64_t CodeSize,
338  const AMDGPUMachineFunction *MFI) {
339  OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
340  OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
341  OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
342  OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
343  OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
344  false);
345 }
346 
347 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
348  const MachineFunction &MF) const {
350  uint16_t KernelCodeProperties = 0;
351 
352  if (MFI.hasPrivateSegmentBuffer()) {
353  KernelCodeProperties |=
354  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
355  }
356  if (MFI.hasDispatchPtr()) {
357  KernelCodeProperties |=
358  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
359  }
360  if (MFI.hasQueuePtr()) {
361  KernelCodeProperties |=
362  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
363  }
364  if (MFI.hasKernargSegmentPtr()) {
365  KernelCodeProperties |=
366  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
367  }
368  if (MFI.hasDispatchID()) {
369  KernelCodeProperties |=
370  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
371  }
372  if (MFI.hasFlatScratchInit()) {
373  KernelCodeProperties |=
374  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
375  }
376 
377  return KernelCodeProperties;
378 }
379 
380 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
381  const MachineFunction &MF,
382  const SIProgramInfo &PI) const {
383  amdhsa::kernel_descriptor_t KernelDescriptor;
384  memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
385 
389 
390  KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
391  KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
392  KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
393  KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
394  KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
395 
396  return KernelDescriptor;
397 }
398 
400  CurrentProgramInfo = SIProgramInfo();
401 
403 
404  // The starting address of all shader programs must be 256 bytes aligned.
405  // Regular functions just need the basic required instruction alignment.
406  MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
407 
409 
410  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
412  // FIXME: This should be an explicit check for Mesa.
413  if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
414  MCSectionELF *ConfigSection =
415  Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
416  OutStreamer->SwitchSection(ConfigSection);
417  }
418 
419  if (MFI->isEntryFunction()) {
420  getSIProgramInfo(CurrentProgramInfo, MF);
421  } else {
422  auto I = CallGraphResourceInfo.insert(
423  std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
424  SIFunctionResourceInfo &Info = I.first->second;
425  assert(I.second && "should only be called once per function");
426  Info = analyzeResourceUsage(MF);
427  }
428 
429  if (STM.isAmdPalOS())
430  EmitPALMetadata(MF, CurrentProgramInfo);
431  else if (!STM.isAmdHsaOS()) {
432  EmitProgramInfoSI(MF, CurrentProgramInfo);
433  }
434 
435  DisasmLines.clear();
436  HexLines.clear();
437  DisasmLineMaxLen = 0;
438 
440 
441  if (isVerbose()) {
442  MCSectionELF *CommentSection =
443  Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
444  OutStreamer->SwitchSection(CommentSection);
445 
446  if (!MFI->isEntryFunction()) {
447  OutStreamer->emitRawComment(" Function info:", false);
448  SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
449  emitCommonFunctionComments(
450  Info.NumVGPR,
451  Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
452  Info.PrivateSegmentSize,
453  getFunctionCodeSize(MF), MFI);
454  return false;
455  }
456 
457  OutStreamer->emitRawComment(" Kernel info:", false);
458  emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
459  CurrentProgramInfo.NumSGPR,
460  CurrentProgramInfo.ScratchSize,
461  getFunctionCodeSize(MF), MFI);
462 
463  OutStreamer->emitRawComment(
464  " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
465  OutStreamer->emitRawComment(
466  " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
467  OutStreamer->emitRawComment(
468  " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
469  " bytes/workgroup (compile time only)", false);
470 
471  OutStreamer->emitRawComment(
472  " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
473  OutStreamer->emitRawComment(
474  " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
475 
476  OutStreamer->emitRawComment(
477  " NumSGPRsForWavesPerEU: " +
478  Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
479  OutStreamer->emitRawComment(
480  " NumVGPRsForWavesPerEU: " +
481  Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
482 
483  OutStreamer->emitRawComment(
484  " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
485 
487  OutStreamer->emitRawComment(
488  " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
489  Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
490  OutStreamer->emitRawComment(
491  " DebuggerPrivateSegmentBufferSGPR: s" +
492  Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
493  }
494 
495  OutStreamer->emitRawComment(
496  " COMPUTE_PGM_RSRC2:USER_SGPR: " +
497  Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
498  OutStreamer->emitRawComment(
499  " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
500  Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
501  OutStreamer->emitRawComment(
502  " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
503  Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
504  OutStreamer->emitRawComment(
505  " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
506  Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
507  OutStreamer->emitRawComment(
508  " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
509  Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
510  OutStreamer->emitRawComment(
511  " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
512  Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
513  false);
514  }
515 
516  if (STM.dumpCode()) {
517 
518  OutStreamer->SwitchSection(
519  Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
520 
521  for (size_t i = 0; i < DisasmLines.size(); ++i) {
522  std::string Comment = "\n";
523  if (!HexLines[i].empty()) {
524  Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
525  Comment += " ; " + HexLines[i] + "\n";
526  }
527 
528  OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
529  OutStreamer->EmitBytes(StringRef(Comment));
530  }
531  }
532 
533  return false;
534 }
535 
536 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
537  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
538  const SIInstrInfo *TII = STM.getInstrInfo();
539 
540  uint64_t CodeSize = 0;
541 
542  for (const MachineBasicBlock &MBB : MF) {
543  for (const MachineInstr &MI : MBB) {
544  // TODO: CodeSize should account for multiple functions.
545 
546  // TODO: Should we count size of debug info?
547  if (MI.isDebugInstr())
548  continue;
549 
550  CodeSize += TII->getInstSizeInBytes(MI);
551  }
552  }
553 
554  return CodeSize;
555 }
556 
558  const SIInstrInfo &TII,
559  unsigned Reg) {
560  for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
561  if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
562  return true;
563  }
564 
565  return false;
566 }
567 
569  const GCNSubtarget &ST) const {
570  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
571  UsesVCC, UsesFlatScratch);
572 }
573 
574 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
575  const MachineFunction &MF) const {
576  SIFunctionResourceInfo Info;
577 
579  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
580  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
581  const MachineRegisterInfo &MRI = MF.getRegInfo();
582  const SIInstrInfo *TII = ST.getInstrInfo();
583  const SIRegisterInfo &TRI = TII->getRegisterInfo();
584 
585  Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
586  MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
587 
588  // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
589  // instructions aren't used to access the scratch buffer. Inline assembly may
590  // need it though.
591  //
592  // If we only have implicit uses of flat_scr on flat instructions, it is not
593  // really needed.
594  if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
595  (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
596  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
597  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
598  Info.UsesFlatScratch = false;
599  }
600 
601  Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
602  Info.PrivateSegmentSize = FrameInfo.getStackSize();
603  if (MFI->isStackRealigned())
604  Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
605 
606 
607  Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
608  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
609 
610  // If there are no calls, MachineRegisterInfo can tell us the used register
611  // count easily.
612  // A tail call isn't considered a call for MachineFrameInfo's purposes.
613  if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
614  MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
615  for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
616  if (MRI.isPhysRegUsed(Reg)) {
617  HighestVGPRReg = Reg;
618  break;
619  }
620  }
621 
622  MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
623  for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
624  if (MRI.isPhysRegUsed(Reg)) {
625  HighestSGPRReg = Reg;
626  break;
627  }
628  }
629 
630  // We found the maximum register index. They start at 0, so add one to get the
631  // number of registers.
632  Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
633  TRI.getHWRegIndex(HighestVGPRReg) + 1;
634  Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
635  TRI.getHWRegIndex(HighestSGPRReg) + 1;
636 
637  return Info;
638  }
639 
640  int32_t MaxVGPR = -1;
641  int32_t MaxSGPR = -1;
642  uint64_t CalleeFrameSize = 0;
643 
644  for (const MachineBasicBlock &MBB : MF) {
645  for (const MachineInstr &MI : MBB) {
646  // TODO: Check regmasks? Do they occur anywhere except calls?
647  for (const MachineOperand &MO : MI.operands()) {
648  unsigned Width = 0;
649  bool IsSGPR = false;
650 
651  if (!MO.isReg())
652  continue;
653 
654  unsigned Reg = MO.getReg();
655  switch (Reg) {
656  case AMDGPU::EXEC:
657  case AMDGPU::EXEC_LO:
658  case AMDGPU::EXEC_HI:
659  case AMDGPU::SCC:
660  case AMDGPU::M0:
661  case AMDGPU::SRC_SHARED_BASE:
662  case AMDGPU::SRC_SHARED_LIMIT:
663  case AMDGPU::SRC_PRIVATE_BASE:
664  case AMDGPU::SRC_PRIVATE_LIMIT:
665  continue;
666 
667  case AMDGPU::NoRegister:
668  assert(MI.isDebugInstr());
669  continue;
670 
671  case AMDGPU::VCC:
672  case AMDGPU::VCC_LO:
673  case AMDGPU::VCC_HI:
674  Info.UsesVCC = true;
675  continue;
676 
677  case AMDGPU::FLAT_SCR:
678  case AMDGPU::FLAT_SCR_LO:
679  case AMDGPU::FLAT_SCR_HI:
680  continue;
681 
682  case AMDGPU::XNACK_MASK:
683  case AMDGPU::XNACK_MASK_LO:
684  case AMDGPU::XNACK_MASK_HI:
685  llvm_unreachable("xnack_mask registers should not be used");
686 
687  case AMDGPU::TBA:
688  case AMDGPU::TBA_LO:
689  case AMDGPU::TBA_HI:
690  case AMDGPU::TMA:
691  case AMDGPU::TMA_LO:
692  case AMDGPU::TMA_HI:
693  llvm_unreachable("trap handler registers should not be used");
694 
695  default:
696  break;
697  }
698 
699  if (AMDGPU::SReg_32RegClass.contains(Reg)) {
700  assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
701  "trap handler registers should not be used");
702  IsSGPR = true;
703  Width = 1;
704  } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
705  IsSGPR = false;
706  Width = 1;
707  } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
708  assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
709  "trap handler registers should not be used");
710  IsSGPR = true;
711  Width = 2;
712  } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
713  IsSGPR = false;
714  Width = 2;
715  } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
716  IsSGPR = false;
717  Width = 3;
718  } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
719  assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
720  "trap handler registers should not be used");
721  IsSGPR = true;
722  Width = 4;
723  } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
724  IsSGPR = false;
725  Width = 4;
726  } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
727  assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
728  "trap handler registers should not be used");
729  IsSGPR = true;
730  Width = 8;
731  } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
732  IsSGPR = false;
733  Width = 8;
734  } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
735  assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
736  "trap handler registers should not be used");
737  IsSGPR = true;
738  Width = 16;
739  } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
740  IsSGPR = false;
741  Width = 16;
742  } else {
743  llvm_unreachable("Unknown register class");
744  }
745  unsigned HWReg = TRI.getHWRegIndex(Reg);
746  int MaxUsed = HWReg + Width - 1;
747  if (IsSGPR) {
748  MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
749  } else {
750  MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
751  }
752  }
753 
754  if (MI.isCall()) {
755  // Pseudo used just to encode the underlying global. Is there a better
756  // way to track this?
757 
758  const MachineOperand *CalleeOp
759  = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
760  const Function *Callee = cast<Function>(CalleeOp->getGlobal());
761  if (Callee->isDeclaration()) {
762  // If this is a call to an external function, we can't do much. Make
763  // conservative guesses.
764 
765  // 48 SGPRs - vcc, - flat_scr, -xnack
766  int MaxSGPRGuess =
767  47 - IsaInfo::getNumExtraSGPRs(getSTI(), true,
768  ST.hasFlatAddressSpace());
769  MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
770  MaxVGPR = std::max(MaxVGPR, 23);
771 
772  CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
773  Info.UsesVCC = true;
774  Info.UsesFlatScratch = ST.hasFlatAddressSpace();
775  Info.HasDynamicallySizedStack = true;
776  } else {
777  // We force CodeGen to run in SCC order, so the callee's register
778  // usage etc. should be the cumulative usage of all callees.
779  auto I = CallGraphResourceInfo.find(Callee);
780  assert(I != CallGraphResourceInfo.end() &&
781  "callee should have been handled before caller");
782 
783  MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
784  MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
785  CalleeFrameSize
786  = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
787  Info.UsesVCC |= I->second.UsesVCC;
788  Info.UsesFlatScratch |= I->second.UsesFlatScratch;
789  Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
790  Info.HasRecursion |= I->second.HasRecursion;
791  }
792 
793  if (!Callee->doesNotRecurse())
794  Info.HasRecursion = true;
795  }
796  }
797  }
798 
799  Info.NumExplicitSGPR = MaxSGPR + 1;
800  Info.NumVGPR = MaxVGPR + 1;
801  Info.PrivateSegmentSize += CalleeFrameSize;
802 
803  return Info;
804 }
805 
806 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
807  const MachineFunction &MF) {
808  SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
809 
810  ProgInfo.NumVGPR = Info.NumVGPR;
811  ProgInfo.NumSGPR = Info.NumExplicitSGPR;
812  ProgInfo.ScratchSize = Info.PrivateSegmentSize;
813  ProgInfo.VCCUsed = Info.UsesVCC;
814  ProgInfo.FlatUsed = Info.UsesFlatScratch;
815  ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
816 
817  if (!isUInt<32>(ProgInfo.ScratchSize)) {
818  DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
819  ProgInfo.ScratchSize, DS_Error);
820  MF.getFunction().getContext().diagnose(DiagStackSize);
821  }
822 
823  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
825  const SIInstrInfo *TII = STM.getInstrInfo();
826  const SIRegisterInfo *RI = &TII->getRegisterInfo();
827 
828  // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
829  // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
830  // unified.
831  unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
832  getSTI(), ProgInfo.VCCUsed, ProgInfo.FlatUsed);
833 
834  // Check the addressable register limit before we add ExtraSGPRs.
836  !STM.hasSGPRInitBug()) {
837  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
838  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
839  // This can happen due to a compiler bug or when using inline asm.
840  LLVMContext &Ctx = MF.getFunction().getContext();
842  "addressable scalar registers",
843  ProgInfo.NumSGPR, DS_Error,
845  MaxAddressableNumSGPRs);
846  Ctx.diagnose(Diag);
847  ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
848  }
849  }
850 
851  // Account for extra SGPRs and VGPRs reserved for debugger use.
852  ProgInfo.NumSGPR += ExtraSGPRs;
853 
854  // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
855  // dispatch registers are function args.
856  unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
857  for (auto &Arg : MF.getFunction().args()) {
858  unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
859  if (Arg.hasAttribute(Attribute::InReg))
860  WaveDispatchNumSGPR += NumRegs;
861  else
862  WaveDispatchNumVGPR += NumRegs;
863  }
864  ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
865  ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
866 
867  // Adjust number of registers used to meet default/requested minimum/maximum
868  // number of waves per execution unit request.
869  ProgInfo.NumSGPRsForWavesPerEU = std::max(
870  std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
871  ProgInfo.NumVGPRsForWavesPerEU = std::max(
872  std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
873 
875  STM.hasSGPRInitBug()) {
876  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
877  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
878  // This can happen due to a compiler bug or when using inline asm to use
879  // the registers which are usually reserved for vcc etc.
880  LLVMContext &Ctx = MF.getFunction().getContext();
882  "scalar registers",
883  ProgInfo.NumSGPR, DS_Error,
885  MaxAddressableNumSGPRs);
886  Ctx.diagnose(Diag);
887  ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
888  ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
889  }
890  }
891 
892  if (STM.hasSGPRInitBug()) {
893  ProgInfo.NumSGPR =
895  ProgInfo.NumSGPRsForWavesPerEU =
897  }
898 
899  if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
900  LLVMContext &Ctx = MF.getFunction().getContext();
901  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
902  MFI->getNumUserSGPRs(), DS_Error);
903  Ctx.diagnose(Diag);
904  }
905 
906  if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
907  LLVMContext &Ctx = MF.getFunction().getContext();
908  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
909  MFI->getLDSSize(), DS_Error);
910  Ctx.diagnose(Diag);
911  }
912 
914  getSTI(), ProgInfo.NumSGPRsForWavesPerEU);
916  getSTI(), ProgInfo.NumVGPRsForWavesPerEU);
917 
918  // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
919  // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
920  // attribute was requested.
921  if (STM.debuggerEmitPrologue()) {
923  RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
925  RI->getHWRegIndex(MFI->getScratchRSrcReg());
926  }
927 
928  // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
929  // register.
930  ProgInfo.FloatMode = getFPMode(MF);
931 
932  ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
933 
934  // Make clamp modifier on NaN input returns 0.
935  ProgInfo.DX10Clamp = STM.enableDX10Clamp();
936 
937  unsigned LDSAlignShift;
939  // LDS is allocated in 64 dword blocks.
940  LDSAlignShift = 8;
941  } else {
942  // LDS is allocated in 128 dword blocks.
943  LDSAlignShift = 9;
944  }
945 
946  unsigned LDSSpillSize =
947  MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
948 
949  ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
950  ProgInfo.LDSBlocks =
951  alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
952 
953  // Scratch is allocated in 256 dword blocks.
954  unsigned ScratchAlignShift = 10;
955  // We need to program the hardware with the amount of scratch memory that
956  // is used by the entire wave. ProgInfo.ScratchSize is the amount of
957  // scratch memory used per thread.
958  ProgInfo.ScratchBlocks =
959  alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
960  1ULL << ScratchAlignShift) >>
961  ScratchAlignShift;
962 
963  ProgInfo.ComputePGMRSrc1 =
964  S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
965  S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
966  S_00B848_PRIORITY(ProgInfo.Priority) |
967  S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
968  S_00B848_PRIV(ProgInfo.Priv) |
969  S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
970  S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
971  S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
972 
973  // 0 = X, 1 = XY, 2 = XYZ
974  unsigned TIDIGCompCnt = 0;
975  if (MFI->hasWorkItemIDZ())
976  TIDIGCompCnt = 2;
977  else if (MFI->hasWorkItemIDY())
978  TIDIGCompCnt = 1;
979 
980  ProgInfo.ComputePGMRSrc2 =
981  S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
982  S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
983  // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
985  S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
986  S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
987  S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
988  S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
989  S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
991  // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
992  S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
993  S_00B84C_EXCP_EN(0);
994 }
995 
996 static unsigned getRsrcReg(CallingConv::ID CallConv) {
997  switch (CallConv) {
998  default: LLVM_FALLTHROUGH;
1006  }
1007 }
1008 
1009 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1010  const SIProgramInfo &CurrentProgramInfo) {
1011  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1013  unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1014 
1016  OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1017 
1018  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1019 
1020  OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1021  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1022 
1023  OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1024  OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1025 
1026  // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1027  // 0" comment but I don't see a corresponding field in the register spec.
1028  } else {
1029  OutStreamer->EmitIntValue(RsrcReg, 4);
1030  OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1031  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1032  if (STM.isVGPRSpillingEnabled(MF.getFunction())) {
1033  OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1034  OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1035  }
1036  }
1037 
1040  OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1041  OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1042  OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1043  OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1044  OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1045  }
1046 
1047  OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1048  OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1049  OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1050  OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1051 }
1052 
1053 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1054 // is AMDPAL. It stores each compute/SPI register setting and other PAL
1055 // metadata items into the PALMetadataMap, combining with any provided by the
1056 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1057 // then written as a single block in the .note section.
1058 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1059  const SIProgramInfo &CurrentProgramInfo) {
1061  // Given the calling convention, calculate the register number for rsrc1. In
1062  // principle the register number could change in future hardware, but we know
1063  // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1064  // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1065  // that we use a register number rather than a byte offset, so we need to
1066  // divide by 4.
1067  unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1068  unsigned Rsrc2Reg = Rsrc1Reg + 1;
1069  // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1070  // with a constant offset to access any non-register shader-specific PAL
1071  // metadata key.
1072  unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1073  switch (MF.getFunction().getCallingConv()) {
1075  ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1076  break;
1078  ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1079  break;
1081  ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1082  break;
1084  ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1085  break;
1087  ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1088  break;
1090  ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1091  break;
1092  }
1093  unsigned NumUsedVgprsKey = ScratchSizeKey +
1095  unsigned NumUsedSgprsKey = ScratchSizeKey +
1097  PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1098  PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1100  PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1101  PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1102  // ScratchSize is in bytes, 16 aligned.
1103  PALMetadataMap[ScratchSizeKey] |=
1104  alignTo(CurrentProgramInfo.ScratchSize, 16);
1105  } else {
1106  PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1107  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1108  if (CurrentProgramInfo.ScratchBlocks > 0)
1109  PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1110  // ScratchSize is in bytes, 16 aligned.
1111  PALMetadataMap[ScratchSizeKey] |=
1112  alignTo(CurrentProgramInfo.ScratchSize, 16);
1113  }
1115  PALMetadataMap[Rsrc2Reg] |=
1116  S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1117  PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1118  PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1119  }
1120 }
1121 
1122 // This is supposed to be log2(Size)
1124  switch (Size) {
1125  case 4:
1126  return AMD_ELEMENT_4_BYTES;
1127  case 8:
1128  return AMD_ELEMENT_8_BYTES;
1129  case 16:
1130  return AMD_ELEMENT_16_BYTES;
1131  default:
1132  llvm_unreachable("invalid private_element_size");
1133  }
1134 }
1135 
1136 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1137  const SIProgramInfo &CurrentProgramInfo,
1138  const MachineFunction &MF) const {
1139  const Function &F = MF.getFunction();
1142 
1144  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1145 
1147 
1149  CurrentProgramInfo.ComputePGMRSrc1 |
1150  (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1152 
1153  if (CurrentProgramInfo.DynamicCallStack)
1155 
1158  getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1159 
1160  if (MFI->hasPrivateSegmentBuffer()) {
1161  Out.code_properties |=
1163  }
1164 
1165  if (MFI->hasDispatchPtr())
1167 
1168  if (MFI->hasQueuePtr())
1170 
1171  if (MFI->hasKernargSegmentPtr())
1173 
1174  if (MFI->hasDispatchID())
1176 
1177  if (MFI->hasFlatScratchInit())
1179 
1180  if (MFI->hasDispatchPtr())
1182 
1183  if (STM.debuggerSupported())
1185 
1186  if (STM.isXNACKEnabled())
1188 
1189  unsigned MaxKernArgAlign;
1190  Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1191  Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1192  Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1193  Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1194  Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1195 
1196  // These alignment values are specified in powers of two, so alignment =
1197  // 2^n. The minimum alignment is 2^4 = 16.
1198  Out.kernarg_segment_alignment = std::max((size_t)4,
1199  countTrailingZeros(MaxKernArgAlign));
1200 
1201  if (STM.debuggerEmitPrologue()) {
1203  CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1205  CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1206  }
1207 }
1208 
1210  unsigned AsmVariant,
1211  const char *ExtraCode, raw_ostream &O) {
1212  // First try the generic code, which knows about modifiers like 'c' and 'n'.
1213  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1214  return false;
1215 
1216  if (ExtraCode && ExtraCode[0]) {
1217  if (ExtraCode[1] != 0)
1218  return true; // Unknown modifier.
1219 
1220  switch (ExtraCode[0]) {
1221  case 'r':
1222  break;
1223  default:
1224  return true;
1225  }
1226  }
1227 
1228  // TODO: Should be able to support other operand types like globals.
1229  const MachineOperand &MO = MI->getOperand(OpNo);
1230  if (MO.isReg()) {
1232  *MF->getSubtarget().getRegisterInfo());
1233  return false;
1234  }
1235 
1236  return true;
1237 }
bool enableIEEEBit(const MachineFunction &MF) const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:433
uint16_t DebuggerPrivateSegmentBufferSGPR
Definition: SIProgramInfo.h:62
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:349
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:210
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Interface definition for SIRegisterInfo.
Target & getTheGCNTarget()
The target for GCN GPUs.
#define S_00B848_VGPRS(x)
Definition: SIDefines.h:481
#define S_00B848_PRIV(x)
Definition: SIDefines.h:493
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
LLVMContext & Context
AMDGPU specific subclass of TargetSubtarget.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
#define FP_DENORM_MODE_SP(x)
Definition: SIDefines.h:526
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS
Definition: SIDefines.h:432
#define G_00B84C_USER_SGPR(x)
Definition: SIDefines.h:445
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
bool doFinalization(Module &M) override
Shut down the asmprinter.
void emitKernel(const MachineFunction &MF, const SIProgramInfo &ProgramInfo)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:298
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
#define G_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:457
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS
Definition: SIDefines.h:428
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
virtual void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK)=0
Instruction set architecture version.
Definition: TargetParser.h:326
#define S_00B84C_SCRATCH_EN(x)
Definition: SIDefines.h:441
const SIInstrInfo * getInstrInfo() const override
#define S_00B84C_TG_SIZE_EN(x)
Definition: SIDefines.h:459
#define S_00B848_DX10_CLAMP(x)
Definition: SIDefines.h:496
uint32_t NumSGPRsForWavesPerEU
Definition: SIProgramInfo.h:48
unsigned const TargetRegisterInfo * TRI
F(f)
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:216
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
#define G_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:454
const MCSubtargetInfo * getSTI() const
Interface definition for R600RegisterInfo.
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:208
#define R_0286CC_SPI_PS_INPUT_ENA
Definition: SIDefines.h:477
#define S_00B028_SGPRS(x)
Definition: SIDefines.h:438
AsmPrinter * createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr< MCStreamer > &&Streamer)
Track resource usage for kernels / entry functions.
Definition: SIProgramInfo.h:22
Tuple of metadata.
Definition: Metadata.h:1106
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type)=0
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:154
return AArch64::GPR64RegClass contains(Reg)
bool hasFP64Denormals() const
static amd_element_byte_size_t getElementByteSizeValue(unsigned Size)
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:521
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:221
uint32_t code_properties
Code properties.
virtual bool EmitHSAMetadata(StringRef HSAMetadataString)
Definition: BitVector.h:938
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:459
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
int getLocalMemorySize() const
AMD Kernel Code Object (amd_kernel_code_t).
bool enableDX10Clamp() const
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
#define G_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:448
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
bool isTrapHandlerEnabled() const
uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR
Definition: SIProgramInfo.h:56
virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata)=0
#define FP_ROUND_MODE_SP(x)
Definition: SIDefines.h:515
Diagnostic information for stack size etc.
#define S_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:453
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
Context object for machine code objects.
Definition: MCContext.h:63
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:251
#define S_00B848_FLOAT_MODE(x)
Definition: SIDefines.h:490
#define R_00B848_COMPUTE_PGM_RSRC1
Definition: SIDefines.h:480
Key
PAL metadata keys.
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
void EmitFunctionBody()
This method emits the body and trailer for a function.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:201
unsigned getAddressableNumSGPRs() const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
bool isGroupSegment(const GlobalValue *GV)
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:245
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
#define S_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:447
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
uint64_t ComputePGMRSrc2
Definition: SIProgramInfo.h:40
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:199
amdgpu Simplify well known AMD library false Value * Callee
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool dumpCode() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool debuggerEmitPrologue() const
uint32_t NumVGPRsForWavesPerEU
Definition: SIProgramInfo.h:51
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool hasFP32Denormals() const
#define S_00B848_IEEE_MODE(x)
Definition: SIDefines.h:502
bool isCompute(CallingConv::ID cc)
#define S_00B028_VGPRS(x)
Definition: SIDefines.h:437
static uint32_t getFPMode(const MachineFunction &F)
uint16_t wavefront_sgpr_count
Number of scalar registers used by a wavefront.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:120
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:137
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define G_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:451
#define S_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:462
#define FP_ROUND_MODE_DP(x)
Definition: SIDefines.h:516
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:423
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
#define S_00B84C_EXCP_EN_MSB(x)
Definition: SIDefines.h:466
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Generation getGeneration() const
const Triple & getTargetTriple() const
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS
Definition: SIDefines.h:429
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:518
#define S_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:456
The AMDGPU TargetMachine interface definition for hw codgen targets.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES
Definition: SIDefines.h:433
#define S_00B84C_LDS_SIZE(x)
Definition: SIDefines.h:470
void EmitBasicBlockStart(const MachineBasicBlock &MBB) const override
Targets can override this to emit stuff at the start of a basic block.
#define R_SPILLED_SGPRS
Definition: SIDefines.h:535
virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName)=0
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:499
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
amd_element_byte_size_t
The values used to define the number of bytes to use for the swizzle element size.
#define FP_ROUND_ROUND_TO_NEAREST
Definition: SIDefines.h:508
bool doesNotRecurse() const
Determine if the function is known not to recurse, directly or indirectly.
Definition: Function.h:556
#define S_00B84C_EXCP_EN(x)
Definition: SIDefines.h:473
void LLVMInitializeAMDGPUAsmPrinter()
IsaVersion getIsaVersion(StringRef GPU)
unsigned getWavefrontSize() const
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS
Definition: SIDefines.h:434
AMDGPUTargetStreamer * getTargetStreamer() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:206
#define G_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:463
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
std::vector< std::string > HexLines
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1023
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS
Definition: SIDefines.h:431
uint64_t kernarg_segment_byte_size
The size in bytes of the kernarg segment that holds the values of the arguments to the kernel...
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
R600 Assembly printer class.
MachineOperand class - Representation of each machine instruction operand.
uint16_t debug_wavefront_private_segment_offset_sgpr
If is_debug_supported is 0 then must be 0.
const MCSubtargetInfo * getMCSubtargetInfo() const
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header)=0
uint16_t workitem_vgpr_count
Number of vector registers used by each work-item.
bool hasSGPRInitBug() const
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
#define S_00B848_DEBUG_MODE(x)
Definition: SIDefines.h:499
#define FP_DENORM_MODE_DP(x)
Definition: SIDefines.h:527
#define S_0286E8_WAVESIZE(x)
Definition: SIDefines.h:533
const Function & getFunction() const
Return the LLVM function that this machine code represents.
#define S_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:450
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
bool isVGPRSpillingEnabled(const Function &F) const
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
uint32_t workgroup_group_segment_byte_size
The amount of group segment memory required by a work-group in bytes.
#define AMD_HSA_BITS_SET(dst, mask, val)
std::vector< std::string > DisasmLines
virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor)=0
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
static AsmPrinter * createAMDGPUAsmPrinterPass(TargetMachine &tm, std::unique_ptr< MCStreamer > &&Streamer)
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool EmitISAVersion(StringRef IsaVersionString)=0
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
void EmitFunctionBodyStart() override
Targets can override this to emit stuff before the first basic block in the function.
virtual void EmitDirectiveAMDGCNTarget(StringRef Target)=0
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool doFinalization(Module &M) override
Shut down the asmprinter.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
#define S_00B848_SGPRS(x)
Definition: SIDefines.h:484
virtual void EmitBasicBlockStart(const MachineBasicBlock &MBB) const
Targets can override this to emit stuff at the start of a basic block.
bool hasXNACK(const MCSubtargetInfo &STI)
uint32_t workitem_private_segment_byte_size
The amount of memory required for the combined private, spill and arg segments for a work-item in byt...
#define S_00B84C_USER_SGPR(x)
Definition: SIDefines.h:444
#define I(x, y, z)
Definition: MD5.cpp:58
AMDGPU Assembly printer class.
#define R_00B860_COMPUTE_TMPRING_SIZE
Definition: SIDefines.h:529
Generic base class for all target subtargets.
bool isAmdHsaOrMesa(const Function &F) const
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:28
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
uint32_t Size
Definition: Profile.cpp:47
#define R_SPILLED_VGPRS
Definition: SIDefines.h:536
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg)
virtual void EmitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:724
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:206
static unsigned getRsrcReg(CallingConv::ID CallConv)
static StringRef getCPU(StringRef CPU)
Processes a CPU name.
unsigned getMaxNumUserSGPRs() const
#define S_00B860_WAVESIZE(x)
Definition: SIDefines.h:530
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define R_00B84C_COMPUTE_PGM_RSRC2
Definition: SIDefines.h:440
#define S_00B848_PRIORITY(x)
Definition: SIDefines.h:487
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:483
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
uint64_t ComputePGMRSrc1
Definition: SIProgramInfo.h:34
#define R_0286E8_SPI_TMPRING_SIZE
Definition: SIDefines.h:532
void setAlignment(unsigned A)
setAlignment - Set the alignment (log2, not bytes) of the function.
unsigned getHWRegIndex(unsigned Reg) const
#define S_00B02C_EXTRA_LDS_SIZE(x)
Definition: SIDefines.h:430
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:189
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn)
RegisterAsmPrinter - Register an AsmPrinter implementation for the given target.
IRTranslator LLVM IR MI
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS
Definition: SIDefines.h:435
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AMDGPU metadata definitions and in-memory representations.
#define R_0286D0_SPI_PS_INPUT_ADDR
Definition: SIDefines.h:478
uint16_t debug_private_segment_buffer_sgpr
If is_debug_supported is 0 then must be 0.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
const uint64_t Version
Definition: InstrProf.h:895
std::vector< uint32_t > Metadata
PAL metadata represented as a vector.
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
iterator_range< arg_iterator > args()
Definition: Function.h:689
bool hasCodeObjectV3() const