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AMDGPUAsmPrinter.cpp
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1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
26 #include "R600AsmPrinter.h"
27 #include "R600Defines.h"
29 #include "R600RegisterInfo.h"
30 #include "SIDefines.h"
31 #include "SIInstrInfo.h"
32 #include "SIMachineFunctionInfo.h"
33 #include "SIRegisterInfo.h"
34 #include "Utils/AMDGPUBaseInfo.h"
35 #include "llvm/BinaryFormat/ELF.h"
37 #include "llvm/IR/DiagnosticInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCSectionELF.h"
40 #include "llvm/MC/MCStreamer.h"
45 
46 using namespace llvm;
47 using namespace llvm::AMDGPU;
48 
49 // TODO: This should get the default rounding mode from the kernel. We just set
50 // the default here, but this could change if the OpenCL rounding mode pragmas
51 // are used.
52 //
53 // The denormal mode here should match what is reported by the OpenCL runtime
54 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
55 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
56 //
57 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
58 // precision, and leaves single precision to flush all and does not report
59 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
60 // CL_FP_DENORM for both.
61 //
62 // FIXME: It seems some instructions do not support single precision denormals
63 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
64 // and sin_f32, cos_f32 on most parts).
65 
66 // We want to use these instructions, and using fp32 denormals also causes
67 // instructions to run at the double precision rate for the device so it's
68 // probably best to just report no single precision denormals.
71  // TODO: Is there any real use for the flush in only / flush out only modes?
72 
73  uint32_t FP32Denormals =
75 
76  uint32_t FP64Denormals =
78 
81  FP_DENORM_MODE_SP(FP32Denormals) |
82  FP_DENORM_MODE_DP(FP64Denormals);
83 }
84 
85 static AsmPrinter *
87  std::unique_ptr<MCStreamer> &&Streamer) {
88  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
89 }
90 
91 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
96 }
97 
99  std::unique_ptr<MCStreamer> Streamer)
100  : AsmPrinter(TM, std::move(Streamer)) {
101  AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
102  }
103 
105  return "AMDGPU Assembly Printer";
106 }
107 
109  return TM.getMCSubtargetInfo();
110 }
111 
113  if (!OutStreamer)
114  return nullptr;
115  return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
116 }
117 
121  return;
122 
123  if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
125  return;
126 
128  HSAMetadataStream.begin(M);
129 
131  readPALMetadata(M);
132 
133  // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
136 
137  // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
138  IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
140  ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
141 }
142 
144  // TODO: Add metadata to code object v3.
147  return;
148 
149  // Following code requires TargetStreamer to be present.
150  if (!getTargetStreamer())
151  return;
152 
153  // Emit ISA Version (NT_AMD_AMDGPU_ISA).
154  std::string ISAVersionString;
155  raw_string_ostream ISAVersionStream(ISAVersionString);
156  IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
157  getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
158 
159  // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
160  if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
161  HSAMetadataStream.end();
162  getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
163  }
164 
165  // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
166  if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
167  // Copy the PAL metadata from the map where we collected it into a vector,
168  // then write it as a .note.
169  PALMD::Metadata PALMetadataVector;
170  for (auto i : PALMetadataMap) {
171  PALMetadataVector.push_back(i.first);
172  PALMetadataVector.push_back(i.second);
173  }
174  getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
175  }
176 }
177 
179  const MachineBasicBlock *MBB) const {
181  return false;
182 
183  if (MBB->empty())
184  return true;
185 
186  // If this is a block implementing a long branch, an expression relative to
187  // the start of the block is needed. to the start of the block.
188  // XXX - Is there a smarter way to check this?
189  return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
190 }
191 
194  if (!MFI.isEntryFunction())
195  return;
198  return;
199 
200  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
201  amd_kernel_code_t KernelCode;
202  if (STM.isAmdCodeObjectV2(MF->getFunction())) {
203  getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
204  getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
205  }
206 
208  return;
209 
210  HSAMetadataStream.emitKernel(*MF, CurrentProgramInfo);
211 }
212 
215  if (!MFI.isEntryFunction())
216  return;
219  return;
220 
221  auto &Streamer = getTargetStreamer()->getStreamer();
222  auto &Context = Streamer.getContext();
223  auto &ObjectFileInfo = *Context.getObjectFileInfo();
224  auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
225 
226  Streamer.PushSection();
227  Streamer.SwitchSection(&ReadOnlySection);
228 
229  // CP microcode requires the kernel descriptor to be allocated on 64 byte
230  // alignment.
231  Streamer.EmitValueToAlignment(64, 0, 1, 0);
232  if (ReadOnlySection.getAlignment() < 64)
233  ReadOnlySection.setAlignment(64);
234 
235  SmallString<128> KernelName;
236  getNameWithPrefix(KernelName, &MF->getFunction());
238  *getSTI(), KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
239  CurrentProgramInfo.NumVGPRsForWavesPerEU,
240  CurrentProgramInfo.NumSGPRsForWavesPerEU -
241  IsaInfo::getNumExtraSGPRs(getSTI()->getFeatureBits(),
242  CurrentProgramInfo.VCCUsed,
243  CurrentProgramInfo.FlatUsed),
244  CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
245  hasXNACK(*getSTI()));
246 
247  Streamer.PopSection();
248 }
249 
254  return;
255  }
256 
258  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
259  if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(MF->getFunction())) {
261  getNameWithPrefix(SymbolName, &MF->getFunction()),
263  SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
264  }
265  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
266  if (STI.dumpCode()) {
267  // Disassemble function name label to text.
268  DisasmLines.push_back(MF->getName().str() + ":");
270  HexLines.push_back("");
271  }
272 
274 }
275 
277  const GCNSubtarget &STI = MBB.getParent()->getSubtarget<GCNSubtarget>();
278  if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
279  // Write a line for the basic block label if it is not only fallthrough.
280  DisasmLines.push_back(
281  (Twine("BB") + Twine(getFunctionNumber())
282  + "_" + Twine(MBB.getNumber()) + ":").str());
284  HexLines.push_back("");
285  }
287 }
288 
290 
291  // Group segment variables aren't emitted in HSA.
292  if (AMDGPU::isGroupSegment(GV))
293  return;
294 
296 }
297 
299  CallGraphResourceInfo.clear();
300  return AsmPrinter::doFinalization(M);
301 }
302 
303 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
304 // frontend into our PALMetadataMap, ready for per-function modification. It
305 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
306 // which is an integer value, and each two integer values forms a key=value
307 // pair that we store as PALMetadataMap[key]=value in the map.
308 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
309  auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
310  if (!NamedMD || !NamedMD->getNumOperands())
311  return;
312  auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
313  if (!Tuple)
314  return;
315  for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
316  auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
317  auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
318  if (!Key || !Val)
319  continue;
320  PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
321  }
322 }
323 
324 // Print comments that apply to both callable functions and entry points.
325 void AMDGPUAsmPrinter::emitCommonFunctionComments(
326  uint32_t NumVGPR,
327  uint32_t NumSGPR,
328  uint64_t ScratchSize,
329  uint64_t CodeSize,
330  const AMDGPUMachineFunction *MFI) {
331  OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
332  OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
333  OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
334  OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
335  OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
336  false);
337 }
338 
339 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
340  const MachineFunction &MF) const {
342  uint16_t KernelCodeProperties = 0;
343 
344  if (MFI.hasPrivateSegmentBuffer()) {
345  KernelCodeProperties |=
346  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
347  }
348  if (MFI.hasDispatchPtr()) {
349  KernelCodeProperties |=
350  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
351  }
352  if (MFI.hasQueuePtr()) {
353  KernelCodeProperties |=
354  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
355  }
356  if (MFI.hasKernargSegmentPtr()) {
357  KernelCodeProperties |=
358  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
359  }
360  if (MFI.hasDispatchID()) {
361  KernelCodeProperties |=
362  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
363  }
364  if (MFI.hasFlatScratchInit()) {
365  KernelCodeProperties |=
366  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
367  }
368 
369  return KernelCodeProperties;
370 }
371 
372 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
373  const MachineFunction &MF,
374  const SIProgramInfo &PI) const {
375  amdhsa::kernel_descriptor_t KernelDescriptor;
376  memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
377 
381 
382  KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
383  KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
384  KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
385  KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
386  KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
387 
388  return KernelDescriptor;
389 }
390 
392  CurrentProgramInfo = SIProgramInfo();
393 
395 
396  // The starting address of all shader programs must be 256 bytes aligned.
397  // Regular functions just need the basic required instruction alignment.
398  MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
399 
401 
402  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
404  // FIXME: This should be an explicit check for Mesa.
405  if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
406  MCSectionELF *ConfigSection =
407  Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
408  OutStreamer->SwitchSection(ConfigSection);
409  }
410 
411  if (MFI->isEntryFunction()) {
412  getSIProgramInfo(CurrentProgramInfo, MF);
413  } else {
414  auto I = CallGraphResourceInfo.insert(
415  std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
416  SIFunctionResourceInfo &Info = I.first->second;
417  assert(I.second && "should only be called once per function");
418  Info = analyzeResourceUsage(MF);
419  }
420 
421  if (STM.isAmdPalOS())
422  EmitPALMetadata(MF, CurrentProgramInfo);
423  else if (!STM.isAmdHsaOS()) {
424  EmitProgramInfoSI(MF, CurrentProgramInfo);
425  }
426 
427  DisasmLines.clear();
428  HexLines.clear();
429  DisasmLineMaxLen = 0;
430 
432 
433  if (isVerbose()) {
434  MCSectionELF *CommentSection =
435  Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
436  OutStreamer->SwitchSection(CommentSection);
437 
438  if (!MFI->isEntryFunction()) {
439  OutStreamer->emitRawComment(" Function info:", false);
440  SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
441  emitCommonFunctionComments(
442  Info.NumVGPR,
443  Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
444  Info.PrivateSegmentSize,
445  getFunctionCodeSize(MF), MFI);
446  return false;
447  }
448 
449  OutStreamer->emitRawComment(" Kernel info:", false);
450  emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
451  CurrentProgramInfo.NumSGPR,
452  CurrentProgramInfo.ScratchSize,
453  getFunctionCodeSize(MF), MFI);
454 
455  OutStreamer->emitRawComment(
456  " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
457  OutStreamer->emitRawComment(
458  " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
459  OutStreamer->emitRawComment(
460  " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
461  " bytes/workgroup (compile time only)", false);
462 
463  OutStreamer->emitRawComment(
464  " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
465  OutStreamer->emitRawComment(
466  " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
467 
468  OutStreamer->emitRawComment(
469  " NumSGPRsForWavesPerEU: " +
470  Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
471  OutStreamer->emitRawComment(
472  " NumVGPRsForWavesPerEU: " +
473  Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
474 
475  OutStreamer->emitRawComment(
476  " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
477 
479  OutStreamer->emitRawComment(
480  " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
481  Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
482  OutStreamer->emitRawComment(
483  " DebuggerPrivateSegmentBufferSGPR: s" +
484  Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
485  }
486 
487  OutStreamer->emitRawComment(
488  " COMPUTE_PGM_RSRC2:USER_SGPR: " +
489  Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
490  OutStreamer->emitRawComment(
491  " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
492  Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
493  OutStreamer->emitRawComment(
494  " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
495  Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
496  OutStreamer->emitRawComment(
497  " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
498  Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
499  OutStreamer->emitRawComment(
500  " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
501  Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
502  OutStreamer->emitRawComment(
503  " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
504  Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
505  false);
506  }
507 
508  if (STM.dumpCode()) {
509 
510  OutStreamer->SwitchSection(
511  Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
512 
513  for (size_t i = 0; i < DisasmLines.size(); ++i) {
514  std::string Comment = "\n";
515  if (!HexLines[i].empty()) {
516  Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
517  Comment += " ; " + HexLines[i] + "\n";
518  }
519 
520  OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
521  OutStreamer->EmitBytes(StringRef(Comment));
522  }
523  }
524 
525  return false;
526 }
527 
528 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
529  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
530  const SIInstrInfo *TII = STM.getInstrInfo();
531 
532  uint64_t CodeSize = 0;
533 
534  for (const MachineBasicBlock &MBB : MF) {
535  for (const MachineInstr &MI : MBB) {
536  // TODO: CodeSize should account for multiple functions.
537 
538  // TODO: Should we count size of debug info?
539  if (MI.isDebugInstr())
540  continue;
541 
542  CodeSize += TII->getInstSizeInBytes(MI);
543  }
544  }
545 
546  return CodeSize;
547 }
548 
550  const SIInstrInfo &TII,
551  unsigned Reg) {
552  for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
553  if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
554  return true;
555  }
556 
557  return false;
558 }
559 
561  const GCNSubtarget &ST) const {
562  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(ST.getFeatureBits(),
563  UsesVCC, UsesFlatScratch);
564 }
565 
566 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
567  const MachineFunction &MF) const {
568  SIFunctionResourceInfo Info;
569 
571  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
572  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
573  const MachineRegisterInfo &MRI = MF.getRegInfo();
574  const SIInstrInfo *TII = ST.getInstrInfo();
575  const SIRegisterInfo &TRI = TII->getRegisterInfo();
576 
577  Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
578  MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
579 
580  // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
581  // instructions aren't used to access the scratch buffer. Inline assembly may
582  // need it though.
583  //
584  // If we only have implicit uses of flat_scr on flat instructions, it is not
585  // really needed.
586  if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
587  (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
588  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
589  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
590  Info.UsesFlatScratch = false;
591  }
592 
593  Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
594  Info.PrivateSegmentSize = FrameInfo.getStackSize();
595  if (MFI->isStackRealigned())
596  Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
597 
598 
599  Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
600  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
601 
602  // If there are no calls, MachineRegisterInfo can tell us the used register
603  // count easily.
604  // A tail call isn't considered a call for MachineFrameInfo's purposes.
605  if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
606  MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
607  for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
608  if (MRI.isPhysRegUsed(Reg)) {
609  HighestVGPRReg = Reg;
610  break;
611  }
612  }
613 
614  MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
615  for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
616  if (MRI.isPhysRegUsed(Reg)) {
617  HighestSGPRReg = Reg;
618  break;
619  }
620  }
621 
622  // We found the maximum register index. They start at 0, so add one to get the
623  // number of registers.
624  Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
625  TRI.getHWRegIndex(HighestVGPRReg) + 1;
626  Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
627  TRI.getHWRegIndex(HighestSGPRReg) + 1;
628 
629  return Info;
630  }
631 
632  int32_t MaxVGPR = -1;
633  int32_t MaxSGPR = -1;
634  uint64_t CalleeFrameSize = 0;
635 
636  for (const MachineBasicBlock &MBB : MF) {
637  for (const MachineInstr &MI : MBB) {
638  // TODO: Check regmasks? Do they occur anywhere except calls?
639  for (const MachineOperand &MO : MI.operands()) {
640  unsigned Width = 0;
641  bool IsSGPR = false;
642 
643  if (!MO.isReg())
644  continue;
645 
646  unsigned Reg = MO.getReg();
647  switch (Reg) {
648  case AMDGPU::EXEC:
649  case AMDGPU::EXEC_LO:
650  case AMDGPU::EXEC_HI:
651  case AMDGPU::SCC:
652  case AMDGPU::M0:
653  case AMDGPU::SRC_SHARED_BASE:
654  case AMDGPU::SRC_SHARED_LIMIT:
655  case AMDGPU::SRC_PRIVATE_BASE:
656  case AMDGPU::SRC_PRIVATE_LIMIT:
657  continue;
658 
659  case AMDGPU::NoRegister:
660  assert(MI.isDebugInstr());
661  continue;
662 
663  case AMDGPU::VCC:
664  case AMDGPU::VCC_LO:
665  case AMDGPU::VCC_HI:
666  Info.UsesVCC = true;
667  continue;
668 
669  case AMDGPU::FLAT_SCR:
670  case AMDGPU::FLAT_SCR_LO:
671  case AMDGPU::FLAT_SCR_HI:
672  continue;
673 
674  case AMDGPU::XNACK_MASK:
675  case AMDGPU::XNACK_MASK_LO:
676  case AMDGPU::XNACK_MASK_HI:
677  llvm_unreachable("xnack_mask registers should not be used");
678 
679  case AMDGPU::TBA:
680  case AMDGPU::TBA_LO:
681  case AMDGPU::TBA_HI:
682  case AMDGPU::TMA:
683  case AMDGPU::TMA_LO:
684  case AMDGPU::TMA_HI:
685  llvm_unreachable("trap handler registers should not be used");
686 
687  default:
688  break;
689  }
690 
691  if (AMDGPU::SReg_32RegClass.contains(Reg)) {
692  assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
693  "trap handler registers should not be used");
694  IsSGPR = true;
695  Width = 1;
696  } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
697  IsSGPR = false;
698  Width = 1;
699  } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
700  assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
701  "trap handler registers should not be used");
702  IsSGPR = true;
703  Width = 2;
704  } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
705  IsSGPR = false;
706  Width = 2;
707  } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
708  IsSGPR = false;
709  Width = 3;
710  } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
711  assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
712  "trap handler registers should not be used");
713  IsSGPR = true;
714  Width = 4;
715  } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
716  IsSGPR = false;
717  Width = 4;
718  } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
719  assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
720  "trap handler registers should not be used");
721  IsSGPR = true;
722  Width = 8;
723  } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
724  IsSGPR = false;
725  Width = 8;
726  } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
727  assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
728  "trap handler registers should not be used");
729  IsSGPR = true;
730  Width = 16;
731  } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
732  IsSGPR = false;
733  Width = 16;
734  } else {
735  llvm_unreachable("Unknown register class");
736  }
737  unsigned HWReg = TRI.getHWRegIndex(Reg);
738  int MaxUsed = HWReg + Width - 1;
739  if (IsSGPR) {
740  MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
741  } else {
742  MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
743  }
744  }
745 
746  if (MI.isCall()) {
747  // Pseudo used just to encode the underlying global. Is there a better
748  // way to track this?
749 
750  const MachineOperand *CalleeOp
751  = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
752  const Function *Callee = cast<Function>(CalleeOp->getGlobal());
753  if (Callee->isDeclaration()) {
754  // If this is a call to an external function, we can't do much. Make
755  // conservative guesses.
756 
757  // 48 SGPRs - vcc, - flat_scr, -xnack
758  int MaxSGPRGuess =
759  47 - IsaInfo::getNumExtraSGPRs(ST.getFeatureBits(), true,
760  ST.hasFlatAddressSpace());
761  MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
762  MaxVGPR = std::max(MaxVGPR, 23);
763 
764  CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
765  Info.UsesVCC = true;
766  Info.UsesFlatScratch = ST.hasFlatAddressSpace();
767  Info.HasDynamicallySizedStack = true;
768  } else {
769  // We force CodeGen to run in SCC order, so the callee's register
770  // usage etc. should be the cumulative usage of all callees.
771  auto I = CallGraphResourceInfo.find(Callee);
772  assert(I != CallGraphResourceInfo.end() &&
773  "callee should have been handled before caller");
774 
775  MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
776  MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
777  CalleeFrameSize
778  = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
779  Info.UsesVCC |= I->second.UsesVCC;
780  Info.UsesFlatScratch |= I->second.UsesFlatScratch;
781  Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
782  Info.HasRecursion |= I->second.HasRecursion;
783  }
784 
785  if (!Callee->doesNotRecurse())
786  Info.HasRecursion = true;
787  }
788  }
789  }
790 
791  Info.NumExplicitSGPR = MaxSGPR + 1;
792  Info.NumVGPR = MaxVGPR + 1;
793  Info.PrivateSegmentSize += CalleeFrameSize;
794 
795  return Info;
796 }
797 
798 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
799  const MachineFunction &MF) {
800  SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
801 
802  ProgInfo.NumVGPR = Info.NumVGPR;
803  ProgInfo.NumSGPR = Info.NumExplicitSGPR;
804  ProgInfo.ScratchSize = Info.PrivateSegmentSize;
805  ProgInfo.VCCUsed = Info.UsesVCC;
806  ProgInfo.FlatUsed = Info.UsesFlatScratch;
807  ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
808 
809  if (!isUInt<32>(ProgInfo.ScratchSize)) {
810  DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
811  ProgInfo.ScratchSize, DS_Error);
812  MF.getFunction().getContext().diagnose(DiagStackSize);
813  }
814 
815  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
817  const SIInstrInfo *TII = STM.getInstrInfo();
818  const SIRegisterInfo *RI = &TII->getRegisterInfo();
819 
820  // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
821  // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
822  // unified.
823  unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
824  STM.getFeatureBits(), ProgInfo.VCCUsed, ProgInfo.FlatUsed);
825 
826  // Check the addressable register limit before we add ExtraSGPRs.
828  !STM.hasSGPRInitBug()) {
829  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
830  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
831  // This can happen due to a compiler bug or when using inline asm.
832  LLVMContext &Ctx = MF.getFunction().getContext();
834  "addressable scalar registers",
835  ProgInfo.NumSGPR, DS_Error,
837  MaxAddressableNumSGPRs);
838  Ctx.diagnose(Diag);
839  ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
840  }
841  }
842 
843  // Account for extra SGPRs and VGPRs reserved for debugger use.
844  ProgInfo.NumSGPR += ExtraSGPRs;
845 
846  // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
847  // dispatch registers are function args.
848  unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
849  for (auto &Arg : MF.getFunction().args()) {
850  unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
851  if (Arg.hasAttribute(Attribute::InReg))
852  WaveDispatchNumSGPR += NumRegs;
853  else
854  WaveDispatchNumVGPR += NumRegs;
855  }
856  ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
857  ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
858 
859  // Adjust number of registers used to meet default/requested minimum/maximum
860  // number of waves per execution unit request.
861  ProgInfo.NumSGPRsForWavesPerEU = std::max(
862  std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
863  ProgInfo.NumVGPRsForWavesPerEU = std::max(
864  std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
865 
867  STM.hasSGPRInitBug()) {
868  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
869  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
870  // This can happen due to a compiler bug or when using inline asm to use
871  // the registers which are usually reserved for vcc etc.
872  LLVMContext &Ctx = MF.getFunction().getContext();
874  "scalar registers",
875  ProgInfo.NumSGPR, DS_Error,
877  MaxAddressableNumSGPRs);
878  Ctx.diagnose(Diag);
879  ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
880  ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
881  }
882  }
883 
884  if (STM.hasSGPRInitBug()) {
885  ProgInfo.NumSGPR =
887  ProgInfo.NumSGPRsForWavesPerEU =
889  }
890 
891  if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
892  LLVMContext &Ctx = MF.getFunction().getContext();
893  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
894  MFI->getNumUserSGPRs(), DS_Error);
895  Ctx.diagnose(Diag);
896  }
897 
898  if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
899  LLVMContext &Ctx = MF.getFunction().getContext();
900  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
901  MFI->getLDSSize(), DS_Error);
902  Ctx.diagnose(Diag);
903  }
904 
906  STM.getFeatureBits(), ProgInfo.NumSGPRsForWavesPerEU);
908  STM.getFeatureBits(), ProgInfo.NumVGPRsForWavesPerEU);
909 
910  // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
911  // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
912  // attribute was requested.
913  if (STM.debuggerEmitPrologue()) {
915  RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
917  RI->getHWRegIndex(MFI->getScratchRSrcReg());
918  }
919 
920  // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
921  // register.
922  ProgInfo.FloatMode = getFPMode(MF);
923 
924  ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
925 
926  // Make clamp modifier on NaN input returns 0.
927  ProgInfo.DX10Clamp = STM.enableDX10Clamp();
928 
929  unsigned LDSAlignShift;
931  // LDS is allocated in 64 dword blocks.
932  LDSAlignShift = 8;
933  } else {
934  // LDS is allocated in 128 dword blocks.
935  LDSAlignShift = 9;
936  }
937 
938  unsigned LDSSpillSize =
939  MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
940 
941  ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
942  ProgInfo.LDSBlocks =
943  alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
944 
945  // Scratch is allocated in 256 dword blocks.
946  unsigned ScratchAlignShift = 10;
947  // We need to program the hardware with the amount of scratch memory that
948  // is used by the entire wave. ProgInfo.ScratchSize is the amount of
949  // scratch memory used per thread.
950  ProgInfo.ScratchBlocks =
951  alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
952  1ULL << ScratchAlignShift) >>
953  ScratchAlignShift;
954 
955  ProgInfo.ComputePGMRSrc1 =
956  S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
957  S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
958  S_00B848_PRIORITY(ProgInfo.Priority) |
959  S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
960  S_00B848_PRIV(ProgInfo.Priv) |
961  S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
962  S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
963  S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
964 
965  // 0 = X, 1 = XY, 2 = XYZ
966  unsigned TIDIGCompCnt = 0;
967  if (MFI->hasWorkItemIDZ())
968  TIDIGCompCnt = 2;
969  else if (MFI->hasWorkItemIDY())
970  TIDIGCompCnt = 1;
971 
972  ProgInfo.ComputePGMRSrc2 =
973  S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
974  S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
975  // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
977  S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
978  S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
979  S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
980  S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
981  S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
983  // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
984  S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
985  S_00B84C_EXCP_EN(0);
986 }
987 
988 static unsigned getRsrcReg(CallingConv::ID CallConv) {
989  switch (CallConv) {
990  default: LLVM_FALLTHROUGH;
998  }
999 }
1000 
1001 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1002  const SIProgramInfo &CurrentProgramInfo) {
1003  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1005  unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1006 
1008  OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1009 
1010  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1011 
1012  OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1013  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1014 
1015  OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1016  OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1017 
1018  // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1019  // 0" comment but I don't see a corresponding field in the register spec.
1020  } else {
1021  OutStreamer->EmitIntValue(RsrcReg, 4);
1022  OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1023  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1024  if (STM.isVGPRSpillingEnabled(MF.getFunction())) {
1025  OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1026  OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1027  }
1028  }
1029 
1032  OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1033  OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1034  OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1035  OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1036  OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1037  }
1038 
1039  OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1040  OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1041  OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1042  OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1043 }
1044 
1045 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1046 // is AMDPAL. It stores each compute/SPI register setting and other PAL
1047 // metadata items into the PALMetadataMap, combining with any provided by the
1048 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1049 // then written as a single block in the .note section.
1050 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1051  const SIProgramInfo &CurrentProgramInfo) {
1053  // Given the calling convention, calculate the register number for rsrc1. In
1054  // principle the register number could change in future hardware, but we know
1055  // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1056  // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1057  // that we use a register number rather than a byte offset, so we need to
1058  // divide by 4.
1059  unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1060  unsigned Rsrc2Reg = Rsrc1Reg + 1;
1061  // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1062  // with a constant offset to access any non-register shader-specific PAL
1063  // metadata key.
1064  unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1065  switch (MF.getFunction().getCallingConv()) {
1067  ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1068  break;
1070  ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1071  break;
1073  ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1074  break;
1076  ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1077  break;
1079  ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1080  break;
1082  ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1083  break;
1084  }
1085  unsigned NumUsedVgprsKey = ScratchSizeKey +
1087  unsigned NumUsedSgprsKey = ScratchSizeKey +
1089  PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1090  PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1092  PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1093  PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1094  // ScratchSize is in bytes, 16 aligned.
1095  PALMetadataMap[ScratchSizeKey] |=
1096  alignTo(CurrentProgramInfo.ScratchSize, 16);
1097  } else {
1098  PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1099  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1100  if (CurrentProgramInfo.ScratchBlocks > 0)
1101  PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1102  // ScratchSize is in bytes, 16 aligned.
1103  PALMetadataMap[ScratchSizeKey] |=
1104  alignTo(CurrentProgramInfo.ScratchSize, 16);
1105  }
1107  PALMetadataMap[Rsrc2Reg] |=
1108  S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1109  PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1110  PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1111  }
1112 }
1113 
1114 // This is supposed to be log2(Size)
1116  switch (Size) {
1117  case 4:
1118  return AMD_ELEMENT_4_BYTES;
1119  case 8:
1120  return AMD_ELEMENT_8_BYTES;
1121  case 16:
1122  return AMD_ELEMENT_16_BYTES;
1123  default:
1124  llvm_unreachable("invalid private_element_size");
1125  }
1126 }
1127 
1128 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1129  const SIProgramInfo &CurrentProgramInfo,
1130  const MachineFunction &MF) const {
1132  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1133 
1134  AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1135 
1137  CurrentProgramInfo.ComputePGMRSrc1 |
1138  (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1140 
1141  if (CurrentProgramInfo.DynamicCallStack)
1143 
1146  getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1147 
1148  if (MFI->hasPrivateSegmentBuffer()) {
1149  Out.code_properties |=
1151  }
1152 
1153  if (MFI->hasDispatchPtr())
1155 
1156  if (MFI->hasQueuePtr())
1158 
1159  if (MFI->hasKernargSegmentPtr())
1161 
1162  if (MFI->hasDispatchID())
1164 
1165  if (MFI->hasFlatScratchInit())
1167 
1168  if (MFI->hasDispatchPtr())
1170 
1171  if (STM.debuggerSupported())
1173 
1174  if (STM.isXNACKEnabled())
1176 
1177  // FIXME: Should use getKernArgSize
1179  STM.getKernArgSegmentSize(MF.getFunction(), MFI->getExplicitKernArgSize());
1180  Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1181  Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1182  Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1183  Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1184 
1185  // These alignment values are specified in powers of two, so alignment =
1186  // 2^n. The minimum alignment is 2^4 = 16.
1187  Out.kernarg_segment_alignment = std::max((size_t)4,
1189 
1190  if (STM.debuggerEmitPrologue()) {
1192  CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1194  CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1195  }
1196 }
1197 
1199  unsigned AsmVariant,
1200  const char *ExtraCode, raw_ostream &O) {
1201  // First try the generic code, which knows about modifiers like 'c' and 'n'.
1202  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1203  return false;
1204 
1205  if (ExtraCode && ExtraCode[0]) {
1206  if (ExtraCode[1] != 0)
1207  return true; // Unknown modifier.
1208 
1209  switch (ExtraCode[0]) {
1210  case 'r':
1211  break;
1212  default:
1213  return true;
1214  }
1215  }
1216 
1217  // TODO: Should be able to support other operand types like globals.
1218  const MachineOperand &MO = MI->getOperand(OpNo);
1219  if (MO.isReg()) {
1221  *MF->getSubtarget().getRegisterInfo());
1222  return false;
1223  }
1224 
1225  return true;
1226 }
bool enableIEEEBit(const MachineFunction &MF) const
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:431
uint16_t DebuggerPrivateSegmentBufferSGPR
Definition: SIProgramInfo.h:62
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:349
unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:208
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Interface definition for SIRegisterInfo.
Target & getTheGCNTarget()
The target for GCN GPUs.
#define S_00B848_VGPRS(x)
Definition: SIDefines.h:481
#define S_00B848_PRIV(x)
Definition: SIDefines.h:493
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
LLVMContext & Context
AMDGPU specific subclass of TargetSubtarget.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
#define FP_DENORM_MODE_SP(x)
Definition: SIDefines.h:526
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS
Definition: SIDefines.h:432
#define G_00B84C_USER_SGPR(x)
Definition: SIDefines.h:445
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool doFinalization(Module &M) override
Shut down the asmprinter.
void emitKernel(const MachineFunction &MF, const SIProgramInfo &ProgramInfo)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:294
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:208
#define G_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:457
unsigned getReg() const
getReg - Returns the register number.
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
unsigned Reg
AMDGPUAS getAMDGPUAS(const Module &M)
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS
Definition: SIDefines.h:428
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
virtual void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK)=0
#define S_00B84C_SCRATCH_EN(x)
Definition: SIDefines.h:441
const SIInstrInfo * getInstrInfo() const override
#define S_00B84C_TG_SIZE_EN(x)
Definition: SIDefines.h:459
#define S_00B848_DX10_CLAMP(x)
Definition: SIDefines.h:496
bool isAmdCodeObjectV2(const Function &F) const
uint32_t NumSGPRsForWavesPerEU
Definition: SIProgramInfo.h:48
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
#define G_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:454
const MCSubtargetInfo * getSTI() const
Interface definition for R600RegisterInfo.
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
#define R_0286CC_SPI_PS_INPUT_ENA
Definition: SIDefines.h:477
#define S_00B028_SGPRS(x)
Definition: SIDefines.h:438
AsmPrinter * createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr< MCStreamer > &&Streamer)
Track resource usage for kernels / entry functions.
Definition: SIProgramInfo.h:22
Tuple of metadata.
Definition: Metadata.h:1104
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type)=0
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:152
return AArch64::GPR64RegClass contains(Reg)
bool hasFP64Denormals() const
static amd_element_byte_size_t getElementByteSizeValue(unsigned Size)
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:521
uint32_t code_properties
Code properties.
virtual bool EmitHSAMetadata(StringRef HSAMetadataString)
Definition: BitVector.h:921
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:454
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
int getLocalMemorySize() const
AMD Kernel Code Object (amd_kernel_code_t).
bool enableDX10Clamp() const
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
#define G_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:448
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
bool isTrapHandlerEnabled() const
uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR
Definition: SIProgramInfo.h:56
virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata)=0
#define FP_ROUND_MODE_SP(x)
Definition: SIDefines.h:515
Diagnostic information for stack size etc.
#define S_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:453
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
Context object for machine code objects.
Definition: MCContext.h:63
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:237
#define S_00B848_FLOAT_MODE(x)
Definition: SIDefines.h:490
#define R_00B848_COMPUTE_PGM_RSRC1
Definition: SIDefines.h:480
Key
PAL metadata keys.
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
void EmitFunctionBody()
This method emits the body and trailer for a function.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
unsigned getAddressableNumSGPRs() const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
bool isGroupSegment(const GlobalValue *GV)
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:242
#define S_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:447
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
uint64_t ComputePGMRSrc2
Definition: SIProgramInfo.h:40
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:199
amdgpu Simplify well known AMD library false Value * Callee
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool dumpCode() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool debuggerEmitPrologue() const
uint32_t NumVGPRsForWavesPerEU
Definition: SIProgramInfo.h:51
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool hasFP32Denormals() const
#define S_00B848_IEEE_MODE(x)
Definition: SIDefines.h:502
unsigned getNumSGPRBlocks(const FeatureBitset &Features, unsigned NumSGPRs)
bool isCompute(CallingConv::ID cc)
#define S_00B028_VGPRS(x)
Definition: SIDefines.h:437
static uint32_t getFPMode(const MachineFunction &F)
uint16_t wavefront_sgpr_count
Number of scalar registers used by a wavefront.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:120
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
unsigned getTotalNumSGPRs(const FeatureBitset &Features)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define G_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:451
#define S_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:462
#define FP_ROUND_MODE_DP(x)
Definition: SIDefines.h:516
const GlobalValue * getGlobal() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:421
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
#define S_00B84C_EXCP_EN_MSB(x)
Definition: SIDefines.h:466
Instruction set architecture version.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Generation getGeneration() const
const Triple & getTargetTriple() const
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS
Definition: SIDefines.h:429
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:518
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
#define S_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:456
The AMDGPU TargetMachine interface definition for hw codgen targets.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES
Definition: SIDefines.h:433
#define S_00B84C_LDS_SIZE(x)
Definition: SIDefines.h:470
void EmitBasicBlockStart(const MachineBasicBlock &MBB) const override
Targets can override this to emit stuff at the start of a basic block.
#define R_SPILLED_SGPRS
Definition: SIDefines.h:535
virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName)=0
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features)
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:493
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
amd_element_byte_size_t
The values used to define the number of bytes to use for the swizzle element size.
#define FP_ROUND_ROUND_TO_NEAREST
Definition: SIDefines.h:508
bool doesNotRecurse() const
Determine if the function is known not to recurse, directly or indirectly.
Definition: Function.h:542
#define S_00B84C_EXCP_EN(x)
Definition: SIDefines.h:473
void LLVMInitializeAMDGPUAsmPrinter()
unsigned getWavefrontSize() const
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS
Definition: SIDefines.h:434
AMDGPUTargetStreamer * getTargetStreamer() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:204
#define G_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:463
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
std::vector< std::string > HexLines
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1032
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS
Definition: SIDefines.h:431
uint64_t kernarg_segment_byte_size
The size in bytes of the kernarg segment that holds the values of the arguments to the kernel...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
R600 Assembly printer class.
MachineOperand class - Representation of each machine instruction operand.
uint16_t debug_wavefront_private_segment_offset_sgpr
If is_debug_supported is 0 then must be 0.
const MCSubtargetInfo * getMCSubtargetInfo() const
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header)=0
uint16_t workitem_vgpr_count
Number of vector registers used by each work-item.
bool hasSGPRInitBug() const
#define S_00B848_DEBUG_MODE(x)
Definition: SIDefines.h:499
#define FP_DENORM_MODE_DP(x)
Definition: SIDefines.h:527
#define S_0286E8_WAVESIZE(x)
Definition: SIDefines.h:533
const Function & getFunction() const
Return the LLVM function that this machine code represents.
#define S_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:450
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
bool isVGPRSpillingEnabled(const Function &F) const
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
uint32_t workgroup_group_segment_byte_size
The amount of group segment memory required by a work-group in bytes.
unsigned getNumVGPRBlocks(const FeatureBitset &Features, unsigned NumVGPRs)
#define AMD_HSA_BITS_SET(dst, mask, val)
std::vector< std::string > DisasmLines
virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor)=0
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
static AsmPrinter * createAMDGPUAsmPrinterPass(TargetMachine &tm, std::unique_ptr< MCStreamer > &&Streamer)
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual bool EmitISAVersion(StringRef IsaVersionString)=0
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:60
void EmitFunctionBodyStart() override
Targets can override this to emit stuff before the first basic block in the function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool doFinalization(Module &M) override
Shut down the asmprinter.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define S_00B848_SGPRS(x)
Definition: SIDefines.h:484
virtual void EmitBasicBlockStart(const MachineBasicBlock &MBB) const
Targets can override this to emit stuff at the start of a basic block.
bool hasXNACK(const MCSubtargetInfo &STI)
uint32_t workitem_private_segment_byte_size
The amount of memory required for the combined private, spill and arg segments for a work-item in byt...
#define S_00B84C_USER_SGPR(x)
Definition: SIDefines.h:444
#define I(x, y, z)
Definition: MD5.cpp:58
AMDGPU Assembly printer class.
#define R_00B860_COMPUTE_TMPRING_SIZE
Definition: SIDefines.h:529
Generic base class for all target subtargets.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:28
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
#define R_SPILLED_VGPRS
Definition: SIDefines.h:536
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:221
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg)
virtual void EmitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:722
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:216
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:201
static unsigned getRsrcReg(CallingConv::ID CallConv)
unsigned getMaxNumUserSGPRs() const
#define S_00B860_WAVESIZE(x)
Definition: SIDefines.h:530
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define R_00B84C_COMPUTE_PGM_RSRC2
Definition: SIDefines.h:440
#define S_00B848_PRIORITY(x)
Definition: SIDefines.h:487
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:477
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
uint64_t ComputePGMRSrc1
Definition: SIProgramInfo.h:34
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
#define R_0286E8_SPI_TMPRING_SIZE
Definition: SIDefines.h:532
void setAlignment(unsigned A)
setAlignment - Set the alignment (log2, not bytes) of the function.
unsigned getHWRegIndex(unsigned Reg) const
#define S_00B02C_EXTRA_LDS_SIZE(x)
Definition: SIDefines.h:430
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn)
RegisterAsmPrinter - Register an AsmPrinter implementation for the given target.
IRTranslator LLVM IR MI
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS
Definition: SIDefines.h:435
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:238
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AMDGPU metadata definitions and in-memory representations.
#define R_0286D0_SPI_PS_INPUT_ADDR
Definition: SIDefines.h:478
uint16_t debug_private_segment_buffer_sgpr
If is_debug_supported is 0 then must be 0.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
IsaVersion getIsaVersion(const FeatureBitset &Features)
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:189
std::vector< uint32_t > Metadata
PAL metadata represented as a vector.
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
iterator_range< arg_iterator > args()
Definition: Function.h:675