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AMDGPUAsmPrinter.cpp
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1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12 /// code. When passed an MCAsmStreamer it prints assembly and when passed
13 /// an MCObjectStreamer it outputs binary code.
14 //
15 //===----------------------------------------------------------------------===//
16 //
17 
18 #include "AMDGPUAsmPrinter.h"
19 #include "AMDGPU.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDGPUTargetMachine.h"
25 #include "R600AsmPrinter.h"
26 #include "R600Defines.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIInstrInfo.h"
31 #include "SIMachineFunctionInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "Utils/AMDGPUBaseInfo.h"
34 #include "llvm/BinaryFormat/ELF.h"
36 #include "llvm/IR/DiagnosticInfo.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCSectionELF.h"
39 #include "llvm/MC/MCStreamer.h"
45 
46 using namespace llvm;
47 using namespace llvm::AMDGPU;
48 using namespace llvm::AMDGPU::HSAMD;
49 
50 // TODO: This should get the default rounding mode from the kernel. We just set
51 // the default here, but this could change if the OpenCL rounding mode pragmas
52 // are used.
53 //
54 // The denormal mode here should match what is reported by the OpenCL runtime
55 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
56 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
57 //
58 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
59 // precision, and leaves single precision to flush all and does not report
60 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
61 // CL_FP_DENORM for both.
62 //
63 // FIXME: It seems some instructions do not support single precision denormals
64 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
65 // and sin_f32, cos_f32 on most parts).
66 
67 // We want to use these instructions, and using fp32 denormals also causes
68 // instructions to run at the double precision rate for the device so it's
69 // probably best to just report no single precision denormals.
72  // TODO: Is there any real use for the flush in only / flush out only modes?
73 
74  uint32_t FP32Denormals =
76 
77  uint32_t FP64Denormals =
79 
82  FP_DENORM_MODE_SP(FP32Denormals) |
83  FP_DENORM_MODE_DP(FP64Denormals);
84 }
85 
86 static AsmPrinter *
88  std::unique_ptr<MCStreamer> &&Streamer) {
89  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
90 }
91 
92 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
97 }
98 
100  std::unique_ptr<MCStreamer> Streamer)
101  : AsmPrinter(TM, std::move(Streamer)) {
103  HSAMetadataStream.reset(new MetadataStreamerV3());
104  else
105  HSAMetadataStream.reset(new MetadataStreamerV2());
106 }
107 
109  return "AMDGPU Assembly Printer";
110 }
111 
113  return TM.getMCSubtargetInfo();
114 }
115 
117  if (!OutStreamer)
118  return nullptr;
119  return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
120 }
121 
124  std::string ExpectedTarget;
125  raw_string_ostream ExpectedTargetOS(ExpectedTarget);
126  IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
127 
128  getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
129  }
130 
131  if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
133  return;
134 
136  HSAMetadataStream->begin(M);
137 
140 
142  return;
143 
144  // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
147 
148  // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
151  Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
152 }
153 
155  // Following code requires TargetStreamer to be present.
156  if (!getTargetStreamer())
157  return;
158 
160  // Emit ISA Version (NT_AMD_AMDGPU_ISA).
161  std::string ISAVersionString;
162  raw_string_ostream ISAVersionStream(ISAVersionString);
163  IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
164  getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
165  }
166 
167  // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
168  if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
169  HSAMetadataStream->end();
170  bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
171  (void)Success;
172  assert(Success && "Malformed HSA Metadata");
173  }
174 }
175 
177  const MachineBasicBlock *MBB) const {
179  return false;
180 
181  if (MBB->empty())
182  return true;
183 
184  // If this is a block implementing a long branch, an expression relative to
185  // the start of the block is needed. to the start of the block.
186  // XXX - Is there a smarter way to check this?
187  return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
188 }
189 
192  if (!MFI.isEntryFunction())
193  return;
194 
195  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
196  const Function &F = MF->getFunction();
197  if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
198  (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
199  F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
200  amd_kernel_code_t KernelCode;
201  getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
202  getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
203  }
204 
205  if (STM.isAmdHsaOS())
206  HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
207 }
208 
211  if (!MFI.isEntryFunction())
212  return;
213 
216  return;
217 
218  auto &Streamer = getTargetStreamer()->getStreamer();
219  auto &Context = Streamer.getContext();
220  auto &ObjectFileInfo = *Context.getObjectFileInfo();
221  auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
222 
223  Streamer.PushSection();
224  Streamer.SwitchSection(&ReadOnlySection);
225 
226  // CP microcode requires the kernel descriptor to be allocated on 64 byte
227  // alignment.
228  Streamer.EmitValueToAlignment(64, 0, 1, 0);
229  if (ReadOnlySection.getAlignment() < 64)
230  ReadOnlySection.setAlignment(64);
231 
232  const MCSubtargetInfo &STI = MF->getSubtarget();
233 
234  SmallString<128> KernelName;
235  getNameWithPrefix(KernelName, &MF->getFunction());
237  STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
238  CurrentProgramInfo.NumVGPRsForWavesPerEU,
239  CurrentProgramInfo.NumSGPRsForWavesPerEU -
241  CurrentProgramInfo.VCCUsed,
242  CurrentProgramInfo.FlatUsed),
243  CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
244  hasXNACK(STI));
245 
246  Streamer.PopSection();
247 }
248 
253  return;
254  }
255 
257  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
258  if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
260  getNameWithPrefix(SymbolName, &MF->getFunction()),
262  SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
263  }
264  if (STM.dumpCode()) {
265  // Disassemble function name label to text.
266  DisasmLines.push_back(MF->getName().str() + ":");
268  HexLines.push_back("");
269  }
270 
272 }
273 
275  const GCNSubtarget &STI = MBB.getParent()->getSubtarget<GCNSubtarget>();
276  if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
277  // Write a line for the basic block label if it is not only fallthrough.
278  DisasmLines.push_back(
279  (Twine("BB") + Twine(getFunctionNumber())
280  + "_" + Twine(MBB.getNumber()) + ":").str());
282  HexLines.push_back("");
283  }
285 }
286 
288 
289  // Group segment variables aren't emitted in HSA.
290  if (AMDGPU::isGroupSegment(GV))
291  return;
292 
294 }
295 
297  CallGraphResourceInfo.clear();
298  return AsmPrinter::doFinalization(M);
299 }
300 
301 // Print comments that apply to both callable functions and entry points.
302 void AMDGPUAsmPrinter::emitCommonFunctionComments(
303  uint32_t NumVGPR,
304  uint32_t NumSGPR,
305  uint64_t ScratchSize,
306  uint64_t CodeSize,
307  const AMDGPUMachineFunction *MFI) {
308  OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
309  OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
310  OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
311  OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
312  OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
313  false);
314 }
315 
316 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
317  const MachineFunction &MF) const {
319  uint16_t KernelCodeProperties = 0;
320 
321  if (MFI.hasPrivateSegmentBuffer()) {
322  KernelCodeProperties |=
323  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
324  }
325  if (MFI.hasDispatchPtr()) {
326  KernelCodeProperties |=
327  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
328  }
329  if (MFI.hasQueuePtr()) {
330  KernelCodeProperties |=
331  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
332  }
333  if (MFI.hasKernargSegmentPtr()) {
334  KernelCodeProperties |=
335  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
336  }
337  if (MFI.hasDispatchID()) {
338  KernelCodeProperties |=
339  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
340  }
341  if (MFI.hasFlatScratchInit()) {
342  KernelCodeProperties |=
343  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
344  }
345 
346  return KernelCodeProperties;
347 }
348 
349 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
350  const MachineFunction &MF,
351  const SIProgramInfo &PI) const {
352  amdhsa::kernel_descriptor_t KernelDescriptor;
353  memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
354 
358 
359  KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
360  KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
361  KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
362  KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
363  KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
364 
365  return KernelDescriptor;
366 }
367 
369  CurrentProgramInfo = SIProgramInfo();
370 
372 
373  // The starting address of all shader programs must be 256 bytes aligned.
374  // Regular functions just need the basic required instruction alignment.
375  MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
376 
378 
379  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
381  // FIXME: This should be an explicit check for Mesa.
382  if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
383  MCSectionELF *ConfigSection =
384  Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
385  OutStreamer->SwitchSection(ConfigSection);
386  }
387 
388  if (MFI->isEntryFunction()) {
389  getSIProgramInfo(CurrentProgramInfo, MF);
390  } else {
391  auto I = CallGraphResourceInfo.insert(
392  std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
393  SIFunctionResourceInfo &Info = I.first->second;
394  assert(I.second && "should only be called once per function");
395  Info = analyzeResourceUsage(MF);
396  }
397 
398  if (STM.isAmdPalOS())
399  EmitPALMetadata(MF, CurrentProgramInfo);
400  else if (!STM.isAmdHsaOS()) {
401  EmitProgramInfoSI(MF, CurrentProgramInfo);
402  }
403 
404  DisasmLines.clear();
405  HexLines.clear();
406  DisasmLineMaxLen = 0;
407 
409 
410  if (isVerbose()) {
411  MCSectionELF *CommentSection =
412  Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
413  OutStreamer->SwitchSection(CommentSection);
414 
415  if (!MFI->isEntryFunction()) {
416  OutStreamer->emitRawComment(" Function info:", false);
417  SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
418  emitCommonFunctionComments(
419  Info.NumVGPR,
420  Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
421  Info.PrivateSegmentSize,
422  getFunctionCodeSize(MF), MFI);
423  return false;
424  }
425 
426  OutStreamer->emitRawComment(" Kernel info:", false);
427  emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
428  CurrentProgramInfo.NumSGPR,
429  CurrentProgramInfo.ScratchSize,
430  getFunctionCodeSize(MF), MFI);
431 
432  OutStreamer->emitRawComment(
433  " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
434  OutStreamer->emitRawComment(
435  " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
436  OutStreamer->emitRawComment(
437  " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
438  " bytes/workgroup (compile time only)", false);
439 
440  OutStreamer->emitRawComment(
441  " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
442  OutStreamer->emitRawComment(
443  " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
444 
445  OutStreamer->emitRawComment(
446  " NumSGPRsForWavesPerEU: " +
447  Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
448  OutStreamer->emitRawComment(
449  " NumVGPRsForWavesPerEU: " +
450  Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
451 
452  OutStreamer->emitRawComment(
453  " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
454 
455  OutStreamer->emitRawComment(
456  " COMPUTE_PGM_RSRC2:USER_SGPR: " +
457  Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
458  OutStreamer->emitRawComment(
459  " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
460  Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
461  OutStreamer->emitRawComment(
462  " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
463  Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
464  OutStreamer->emitRawComment(
465  " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
466  Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
467  OutStreamer->emitRawComment(
468  " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
469  Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
470  OutStreamer->emitRawComment(
471  " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
472  Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
473  false);
474  }
475 
476  if (STM.dumpCode()) {
477 
478  OutStreamer->SwitchSection(
479  Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
480 
481  for (size_t i = 0; i < DisasmLines.size(); ++i) {
482  std::string Comment = "\n";
483  if (!HexLines[i].empty()) {
484  Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
485  Comment += " ; " + HexLines[i] + "\n";
486  }
487 
488  OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
489  OutStreamer->EmitBytes(StringRef(Comment));
490  }
491  }
492 
493  return false;
494 }
495 
496 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
497  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
498  const SIInstrInfo *TII = STM.getInstrInfo();
499 
500  uint64_t CodeSize = 0;
501 
502  for (const MachineBasicBlock &MBB : MF) {
503  for (const MachineInstr &MI : MBB) {
504  // TODO: CodeSize should account for multiple functions.
505 
506  // TODO: Should we count size of debug info?
507  if (MI.isDebugInstr())
508  continue;
509 
510  CodeSize += TII->getInstSizeInBytes(MI);
511  }
512  }
513 
514  return CodeSize;
515 }
516 
518  const SIInstrInfo &TII,
519  unsigned Reg) {
520  for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
521  if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
522  return true;
523  }
524 
525  return false;
526 }
527 
529  const GCNSubtarget &ST) const {
530  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
531  UsesVCC, UsesFlatScratch);
532 }
533 
534 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
535  const MachineFunction &MF) const {
536  SIFunctionResourceInfo Info;
537 
539  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
540  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
541  const MachineRegisterInfo &MRI = MF.getRegInfo();
542  const SIInstrInfo *TII = ST.getInstrInfo();
543  const SIRegisterInfo &TRI = TII->getRegisterInfo();
544 
545  Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
546  MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
547 
548  // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
549  // instructions aren't used to access the scratch buffer. Inline assembly may
550  // need it though.
551  //
552  // If we only have implicit uses of flat_scr on flat instructions, it is not
553  // really needed.
554  if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
555  (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
556  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
557  !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
558  Info.UsesFlatScratch = false;
559  }
560 
561  Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
562  Info.PrivateSegmentSize = FrameInfo.getStackSize();
563  if (MFI->isStackRealigned())
564  Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
565 
566 
567  Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
568  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
569 
570  // If there are no calls, MachineRegisterInfo can tell us the used register
571  // count easily.
572  // A tail call isn't considered a call for MachineFrameInfo's purposes.
573  if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
574  MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
575  for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
576  if (MRI.isPhysRegUsed(Reg)) {
577  HighestVGPRReg = Reg;
578  break;
579  }
580  }
581 
582  MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
583  for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
584  if (MRI.isPhysRegUsed(Reg)) {
585  HighestSGPRReg = Reg;
586  break;
587  }
588  }
589 
590  // We found the maximum register index. They start at 0, so add one to get the
591  // number of registers.
592  Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
593  TRI.getHWRegIndex(HighestVGPRReg) + 1;
594  Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
595  TRI.getHWRegIndex(HighestSGPRReg) + 1;
596 
597  return Info;
598  }
599 
600  int32_t MaxVGPR = -1;
601  int32_t MaxSGPR = -1;
602  uint64_t CalleeFrameSize = 0;
603 
604  for (const MachineBasicBlock &MBB : MF) {
605  for (const MachineInstr &MI : MBB) {
606  // TODO: Check regmasks? Do they occur anywhere except calls?
607  for (const MachineOperand &MO : MI.operands()) {
608  unsigned Width = 0;
609  bool IsSGPR = false;
610 
611  if (!MO.isReg())
612  continue;
613 
614  unsigned Reg = MO.getReg();
615  switch (Reg) {
616  case AMDGPU::EXEC:
617  case AMDGPU::EXEC_LO:
618  case AMDGPU::EXEC_HI:
619  case AMDGPU::SCC:
620  case AMDGPU::M0:
621  case AMDGPU::SRC_SHARED_BASE:
622  case AMDGPU::SRC_SHARED_LIMIT:
623  case AMDGPU::SRC_PRIVATE_BASE:
624  case AMDGPU::SRC_PRIVATE_LIMIT:
625  continue;
626 
627  case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
628  llvm_unreachable("src_pops_exiting_wave_id should not be used");
629 
630  case AMDGPU::NoRegister:
631  assert(MI.isDebugInstr());
632  continue;
633 
634  case AMDGPU::VCC:
635  case AMDGPU::VCC_LO:
636  case AMDGPU::VCC_HI:
637  Info.UsesVCC = true;
638  continue;
639 
640  case AMDGPU::FLAT_SCR:
641  case AMDGPU::FLAT_SCR_LO:
642  case AMDGPU::FLAT_SCR_HI:
643  continue;
644 
645  case AMDGPU::XNACK_MASK:
646  case AMDGPU::XNACK_MASK_LO:
647  case AMDGPU::XNACK_MASK_HI:
648  llvm_unreachable("xnack_mask registers should not be used");
649 
650  case AMDGPU::LDS_DIRECT:
651  llvm_unreachable("lds_direct register should not be used");
652 
653  case AMDGPU::TBA:
654  case AMDGPU::TBA_LO:
655  case AMDGPU::TBA_HI:
656  case AMDGPU::TMA:
657  case AMDGPU::TMA_LO:
658  case AMDGPU::TMA_HI:
659  llvm_unreachable("trap handler registers should not be used");
660 
661  default:
662  break;
663  }
664 
665  if (AMDGPU::SReg_32RegClass.contains(Reg)) {
666  assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
667  "trap handler registers should not be used");
668  IsSGPR = true;
669  Width = 1;
670  } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
671  IsSGPR = false;
672  Width = 1;
673  } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
674  assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
675  "trap handler registers should not be used");
676  IsSGPR = true;
677  Width = 2;
678  } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
679  IsSGPR = false;
680  Width = 2;
681  } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
682  IsSGPR = false;
683  Width = 3;
684  } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
685  assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
686  "trap handler registers should not be used");
687  IsSGPR = true;
688  Width = 4;
689  } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
690  IsSGPR = false;
691  Width = 4;
692  } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
693  assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
694  "trap handler registers should not be used");
695  IsSGPR = true;
696  Width = 8;
697  } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
698  IsSGPR = false;
699  Width = 8;
700  } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
701  assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
702  "trap handler registers should not be used");
703  IsSGPR = true;
704  Width = 16;
705  } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
706  IsSGPR = false;
707  Width = 16;
708  } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
709  IsSGPR = true;
710  Width = 3;
711  } else {
712  llvm_unreachable("Unknown register class");
713  }
714  unsigned HWReg = TRI.getHWRegIndex(Reg);
715  int MaxUsed = HWReg + Width - 1;
716  if (IsSGPR) {
717  MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
718  } else {
719  MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
720  }
721  }
722 
723  if (MI.isCall()) {
724  // Pseudo used just to encode the underlying global. Is there a better
725  // way to track this?
726 
727  const MachineOperand *CalleeOp
728  = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
729  const Function *Callee = cast<Function>(CalleeOp->getGlobal());
730  if (Callee->isDeclaration()) {
731  // If this is a call to an external function, we can't do much. Make
732  // conservative guesses.
733 
734  // 48 SGPRs - vcc, - flat_scr, -xnack
735  int MaxSGPRGuess =
736  47 - IsaInfo::getNumExtraSGPRs(&ST, true, ST.hasFlatAddressSpace());
737  MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
738  MaxVGPR = std::max(MaxVGPR, 23);
739 
740  CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
741  Info.UsesVCC = true;
742  Info.UsesFlatScratch = ST.hasFlatAddressSpace();
743  Info.HasDynamicallySizedStack = true;
744  } else {
745  // We force CodeGen to run in SCC order, so the callee's register
746  // usage etc. should be the cumulative usage of all callees.
747 
748  auto I = CallGraphResourceInfo.find(Callee);
749  if (I == CallGraphResourceInfo.end()) {
750  // Avoid crashing on undefined behavior with an illegal call to a
751  // kernel. If a callsite's calling convention doesn't match the
752  // function's, it's undefined behavior. If the callsite calling
753  // convention does match, that would have errored earlier.
754  // FIXME: The verifier shouldn't allow this.
756  report_fatal_error("invalid call to entry function");
757 
758  llvm_unreachable("callee should have been handled before caller");
759  }
760 
761  MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
762  MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
763  CalleeFrameSize
764  = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
765  Info.UsesVCC |= I->second.UsesVCC;
766  Info.UsesFlatScratch |= I->second.UsesFlatScratch;
767  Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
768  Info.HasRecursion |= I->second.HasRecursion;
769  }
770 
771  if (!Callee->doesNotRecurse())
772  Info.HasRecursion = true;
773  }
774  }
775  }
776 
777  Info.NumExplicitSGPR = MaxSGPR + 1;
778  Info.NumVGPR = MaxVGPR + 1;
779  Info.PrivateSegmentSize += CalleeFrameSize;
780 
781  return Info;
782 }
783 
784 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
785  const MachineFunction &MF) {
786  SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
787 
788  ProgInfo.NumVGPR = Info.NumVGPR;
789  ProgInfo.NumSGPR = Info.NumExplicitSGPR;
790  ProgInfo.ScratchSize = Info.PrivateSegmentSize;
791  ProgInfo.VCCUsed = Info.UsesVCC;
792  ProgInfo.FlatUsed = Info.UsesFlatScratch;
793  ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
794 
795  if (!isUInt<32>(ProgInfo.ScratchSize)) {
796  DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
797  ProgInfo.ScratchSize, DS_Error);
798  MF.getFunction().getContext().diagnose(DiagStackSize);
799  }
800 
801  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
803 
804  // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
805  // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
806  // unified.
807  unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
808  &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
809 
810  // Check the addressable register limit before we add ExtraSGPRs.
812  !STM.hasSGPRInitBug()) {
813  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
814  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
815  // This can happen due to a compiler bug or when using inline asm.
816  LLVMContext &Ctx = MF.getFunction().getContext();
818  "addressable scalar registers",
819  ProgInfo.NumSGPR, DS_Error,
821  MaxAddressableNumSGPRs);
822  Ctx.diagnose(Diag);
823  ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
824  }
825  }
826 
827  // Account for extra SGPRs and VGPRs reserved for debugger use.
828  ProgInfo.NumSGPR += ExtraSGPRs;
829 
830  // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
831  // dispatch registers are function args.
832  unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
833  for (auto &Arg : MF.getFunction().args()) {
834  unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
835  if (Arg.hasAttribute(Attribute::InReg))
836  WaveDispatchNumSGPR += NumRegs;
837  else
838  WaveDispatchNumVGPR += NumRegs;
839  }
840  ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
841  ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
842 
843  // Adjust number of registers used to meet default/requested minimum/maximum
844  // number of waves per execution unit request.
845  ProgInfo.NumSGPRsForWavesPerEU = std::max(
846  std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
847  ProgInfo.NumVGPRsForWavesPerEU = std::max(
848  std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
849 
851  STM.hasSGPRInitBug()) {
852  unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
853  if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
854  // This can happen due to a compiler bug or when using inline asm to use
855  // the registers which are usually reserved for vcc etc.
856  LLVMContext &Ctx = MF.getFunction().getContext();
858  "scalar registers",
859  ProgInfo.NumSGPR, DS_Error,
861  MaxAddressableNumSGPRs);
862  Ctx.diagnose(Diag);
863  ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
864  ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
865  }
866  }
867 
868  if (STM.hasSGPRInitBug()) {
869  ProgInfo.NumSGPR =
871  ProgInfo.NumSGPRsForWavesPerEU =
873  }
874 
875  if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
876  LLVMContext &Ctx = MF.getFunction().getContext();
877  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
878  MFI->getNumUserSGPRs(), DS_Error);
879  Ctx.diagnose(Diag);
880  }
881 
882  if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
883  LLVMContext &Ctx = MF.getFunction().getContext();
884  DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
885  MFI->getLDSSize(), DS_Error);
886  Ctx.diagnose(Diag);
887  }
888 
890  &STM, ProgInfo.NumSGPRsForWavesPerEU);
892  &STM, ProgInfo.NumVGPRsForWavesPerEU);
893 
894  // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
895  // register.
896  ProgInfo.FloatMode = getFPMode(MF);
897 
898  const SIModeRegisterDefaults Mode = MFI->getMode();
899  ProgInfo.IEEEMode = Mode.IEEE;
900 
901  // Make clamp modifier on NaN input returns 0.
902  ProgInfo.DX10Clamp = Mode.DX10Clamp;
903 
904  unsigned LDSAlignShift;
906  // LDS is allocated in 64 dword blocks.
907  LDSAlignShift = 8;
908  } else {
909  // LDS is allocated in 128 dword blocks.
910  LDSAlignShift = 9;
911  }
912 
913  unsigned LDSSpillSize =
914  MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
915 
916  ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
917  ProgInfo.LDSBlocks =
918  alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
919 
920  // Scratch is allocated in 256 dword blocks.
921  unsigned ScratchAlignShift = 10;
922  // We need to program the hardware with the amount of scratch memory that
923  // is used by the entire wave. ProgInfo.ScratchSize is the amount of
924  // scratch memory used per thread.
925  ProgInfo.ScratchBlocks =
926  alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
927  1ULL << ScratchAlignShift) >>
928  ScratchAlignShift;
929 
930  ProgInfo.ComputePGMRSrc1 =
931  S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
932  S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
933  S_00B848_PRIORITY(ProgInfo.Priority) |
934  S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
935  S_00B848_PRIV(ProgInfo.Priv) |
936  S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
937  S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
938  S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
939 
940  // 0 = X, 1 = XY, 2 = XYZ
941  unsigned TIDIGCompCnt = 0;
942  if (MFI->hasWorkItemIDZ())
943  TIDIGCompCnt = 2;
944  else if (MFI->hasWorkItemIDY())
945  TIDIGCompCnt = 1;
946 
947  ProgInfo.ComputePGMRSrc2 =
948  S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
949  S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
950  // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
952  S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
953  S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
954  S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
955  S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
956  S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
958  // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
959  S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
960  S_00B84C_EXCP_EN(0);
961 }
962 
963 static unsigned getRsrcReg(CallingConv::ID CallConv) {
964  switch (CallConv) {
965  default: LLVM_FALLTHROUGH;
973  }
974 }
975 
976 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
977  const SIProgramInfo &CurrentProgramInfo) {
979  unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
980 
982  OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
983 
984  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
985 
986  OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
987  OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
988 
989  OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
990  OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
991 
992  // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
993  // 0" comment but I don't see a corresponding field in the register spec.
994  } else {
995  OutStreamer->EmitIntValue(RsrcReg, 4);
996  OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
997  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
998  OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
999  OutStreamer->EmitIntValue(
1000  S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1001  }
1002 
1005  OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1006  OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1007  OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1008  OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1009  OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1010  }
1011 
1012  OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1013  OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1014  OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1015  OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1016 }
1017 
1018 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1019 // is AMDPAL. It stores each compute/SPI register setting and other PAL
1020 // metadata items into the PALMD::Metadata, combining with any provided by the
1021 // frontend as LLVM metadata. Once all functions are written, the PAL metadata
1022 // is then written as a single block in the .note section.
1023 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1024  const SIProgramInfo &CurrentProgramInfo) {
1026  auto CC = MF.getFunction().getCallingConv();
1027  auto MD = getTargetStreamer()->getPALMetadata();
1028 
1029  MD->setEntryPoint(CC, MF.getFunction().getName());
1030  MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
1031  MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
1033  MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1);
1034  MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
1035  } else {
1036  MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1037  S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
1038  if (CurrentProgramInfo.ScratchBlocks > 0)
1039  MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1040  }
1041  // ScratchSize is in bytes, 16 aligned.
1042  MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16));
1044  MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1045  MD->setSpiPsInputEna(MFI->getPSInputEnable());
1046  MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1047  }
1048 }
1049 
1050 // This is supposed to be log2(Size)
1052  switch (Size) {
1053  case 4:
1054  return AMD_ELEMENT_4_BYTES;
1055  case 8:
1056  return AMD_ELEMENT_8_BYTES;
1057  case 16:
1058  return AMD_ELEMENT_16_BYTES;
1059  default:
1060  llvm_unreachable("invalid private_element_size");
1061  }
1062 }
1063 
1064 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1065  const SIProgramInfo &CurrentProgramInfo,
1066  const MachineFunction &MF) const {
1067  const Function &F = MF.getFunction();
1070 
1072  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1073 
1075 
1077  CurrentProgramInfo.ComputePGMRSrc1 |
1078  (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1080 
1081  if (CurrentProgramInfo.DynamicCallStack)
1083 
1086  getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1087 
1088  if (MFI->hasPrivateSegmentBuffer()) {
1089  Out.code_properties |=
1091  }
1092 
1093  if (MFI->hasDispatchPtr())
1095 
1096  if (MFI->hasQueuePtr())
1098 
1099  if (MFI->hasKernargSegmentPtr())
1101 
1102  if (MFI->hasDispatchID())
1104 
1105  if (MFI->hasFlatScratchInit())
1107 
1108  if (MFI->hasDispatchPtr())
1110 
1111  if (STM.isXNACKEnabled())
1113 
1114  unsigned MaxKernArgAlign;
1115  Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1116  Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1117  Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1118  Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1119  Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1120 
1121  // These alignment values are specified in powers of two, so alignment =
1122  // 2^n. The minimum alignment is 2^4 = 16.
1123  Out.kernarg_segment_alignment = std::max((size_t)4,
1124  countTrailingZeros(MaxKernArgAlign));
1125 }
1126 
1128  const char *ExtraCode, raw_ostream &O) {
1129  // First try the generic code, which knows about modifiers like 'c' and 'n'.
1130  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1131  return false;
1132 
1133  if (ExtraCode && ExtraCode[0]) {
1134  if (ExtraCode[1] != 0)
1135  return true; // Unknown modifier.
1136 
1137  switch (ExtraCode[0]) {
1138  case 'r':
1139  break;
1140  default:
1141  return true;
1142  }
1143  }
1144 
1145  // TODO: Should be able to support other operand types like globals.
1146  const MachineOperand &MO = MI->getOperand(OpNo);
1147  if (MO.isReg()) {
1149  *MF->getSubtarget().getRegisterInfo());
1150  return false;
1151  }
1152 
1153  return true;
1154 }
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:445
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:213
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Interface definition for SIRegisterInfo.
Target & getTheGCNTarget()
The target for GCN GPUs.
#define S_00B848_VGPRS(x)
Definition: SIDefines.h:502
#define S_00B848_PRIV(x)
Definition: SIDefines.h:514
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
LLVMContext & Context
AMDGPU specific subclass of TargetSubtarget.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
SI Whole Quad Mode
#define FP_DENORM_MODE_SP(x)
Definition: SIDefines.h:547
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS
Definition: SIDefines.h:453
#define G_00B84C_USER_SGPR(x)
Definition: SIDefines.h:466
const MCSubtargetInfo * getGlobalSTI() const
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool doFinalization(Module &M) override
Shut down the asmprinter.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:300
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
#define G_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:478
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS
Definition: SIDefines.h:449
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
virtual void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK)=0
Instruction set architecture version.
Definition: TargetParser.h:131
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
#define S_00B84C_SCRATCH_EN(x)
Definition: SIDefines.h:462
const SIInstrInfo * getInstrInfo() const override
#define S_00B84C_TG_SIZE_EN(x)
Definition: SIDefines.h:480
#define S_00B848_DX10_CLAMP(x)
Definition: SIDefines.h:517
uint32_t NumSGPRsForWavesPerEU
Definition: SIProgramInfo.h:47
unsigned const TargetRegisterInfo * TRI
F(f)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
#define G_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:475
Interface definition for R600RegisterInfo.
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
#define R_0286CC_SPI_PS_INPUT_ENA
Definition: SIDefines.h:498
#define S_00B028_SGPRS(x)
Definition: SIDefines.h:459
AsmPrinter * createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr< MCStreamer > &&Streamer)
Track resource usage for kernels / entry functions.
Definition: SIProgramInfo.h:21
void setEntryPoint(unsigned CC, StringRef Name)
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type)=0
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:165
return AArch64::GPR64RegClass contains(Reg)
bool hasFP64Denormals() const
static amd_element_byte_size_t getElementByteSizeValue(unsigned Size)
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:542
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
uint32_t code_properties
Code properties.
Definition: BitVector.h:937
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:474
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
int getLocalMemorySize() const
AMD Kernel Code Object (amd_kernel_code_t).
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
#define G_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:469
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isTrapHandlerEnabled() const
#define FP_ROUND_MODE_SP(x)
Definition: SIDefines.h:536
Diagnostic information for stack size etc.
#define S_00B84C_TGID_Y_EN(x)
Definition: SIDefines.h:474
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
Context object for machine code objects.
Definition: MCContext.h:62
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
#define S_00B848_FLOAT_MODE(x)
Definition: SIDefines.h:511
#define R_00B848_COMPUTE_PGM_RSRC1
Definition: SIDefines.h:501
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
void EmitFunctionBody()
This method emits the body and trailer for a function.
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getAddressableNumSGPRs() const
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
bool isGroupSegment(const GlobalValue *GV)
#define S_00B84C_TRAP_HANDLER(x)
Definition: SIDefines.h:468
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
uint64_t ComputePGMRSrc2
Definition: SIProgramInfo.h:39
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:199
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool dumpCode() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
uint32_t NumVGPRsForWavesPerEU
Definition: SIProgramInfo.h:50
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool hasFP32Denormals() const
#define S_00B848_IEEE_MODE(x)
Definition: SIDefines.h:523
bool isCompute(CallingConv::ID cc)
#define S_00B028_VGPRS(x)
Definition: SIDefines.h:458
static uint32_t getFPMode(const MachineFunction &F)
uint16_t wavefront_sgpr_count
Number of scalar registers used by a wavefront.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
AMDGPUPALMetadata * getPALMetadata()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
#define G_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:472
#define S_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:483
#define FP_ROUND_MODE_DP(x)
Definition: SIDefines.h:537
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
const GlobalValue * getGlobal() const
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool isEntryFunctionCC(CallingConv::ID CC)
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:435
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
#define S_00B84C_EXCP_EN_MSB(x)
Definition: SIDefines.h:487
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Generation getGeneration() const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const Triple & getTargetTriple() const
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS
Definition: SIDefines.h:450
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:539
#define S_00B84C_TGID_Z_EN(x)
Definition: SIDefines.h:477
The AMDGPU TargetMachine interface definition for hw codgen targets.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES
Definition: SIDefines.h:454
#define S_00B84C_LDS_SIZE(x)
Definition: SIDefines.h:491
void EmitBasicBlockStart(const MachineBasicBlock &MBB) const override
Targets can override this to emit stuff at the start of a basic block.
#define R_SPILLED_SGPRS
Definition: SIDefines.h:556
virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName)=0
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
amd_element_byte_size_t
The values used to define the number of bytes to use for the swizzle element size.
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:188
#define FP_ROUND_ROUND_TO_NEAREST
Definition: SIDefines.h:529
bool doesNotRecurse() const
Determine if the function is known not to recurse, directly or indirectly.
Definition: Function.h:555
#define S_00B84C_EXCP_EN(x)
Definition: SIDefines.h:494
void LLVMInitializeAMDGPUAsmPrinter()
IsaVersion getIsaVersion(StringRef GPU)
unsigned getWavefrontSize() const
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS
Definition: SIDefines.h:455
AMDGPUTargetStreamer * getTargetStreamer() const
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:209
#define G_00B84C_TIDIG_COMP_CNT(x)
Definition: SIDefines.h:484
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
std::vector< std::string > HexLines
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS
Definition: SIDefines.h:452
uint64_t kernarg_segment_byte_size
The size in bytes of the kernarg segment that holds the values of the arguments to the kernel...
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
R600 Assembly printer class.
MachineOperand class - Representation of each machine instruction operand.
const MCSubtargetInfo * getMCSubtargetInfo() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header)=0
uint16_t workitem_vgpr_count
Number of vector registers used by each work-item.
bool hasSGPRInitBug() const
#define S_00B848_DEBUG_MODE(x)
Definition: SIDefines.h:520
#define FP_DENORM_MODE_DP(x)
Definition: SIDefines.h:548
#define S_0286E8_WAVESIZE(x)
Definition: SIDefines.h:554
const Function & getFunction() const
Return the LLVM function that this machine code represents.
#define S_00B84C_TGID_X_EN(x)
Definition: SIDefines.h:471
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
uint32_t workgroup_group_segment_byte_size
The amount of group segment memory required by a work-group in bytes.
#define AMD_HSA_BITS_SET(dst, mask, val)
amdgpu Simplify well known AMD library false FunctionCallee Callee
std::vector< std::string > DisasmLines
virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor)=0
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
static AsmPrinter * createAMDGPUAsmPrinterPass(TargetMachine &tm, std::unique_ptr< MCStreamer > &&Streamer)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define Success
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:215
virtual bool EmitISAVersion(StringRef IsaVersionString)=0
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
void EmitFunctionBodyStart() override
Targets can override this to emit stuff before the first basic block in the function.
virtual void EmitDirectiveAMDGCNTarget(StringRef Target)=0
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool doFinalization(Module &M) override
Shut down the asmprinter.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
#define S_00B848_SGPRS(x)
Definition: SIDefines.h:505
virtual void EmitBasicBlockStart(const MachineBasicBlock &MBB) const
Targets can override this to emit stuff at the start of a basic block.
bool hasXNACK(const MCSubtargetInfo &STI)
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
uint32_t workitem_private_segment_byte_size
The amount of memory required for the combined private, spill and arg segments for a work-item in byt...
#define S_00B84C_USER_SGPR(x)
Definition: SIDefines.h:465
#define I(x, y, z)
Definition: MD5.cpp:58
AMDGPU Assembly printer class.
#define R_00B860_COMPUTE_TMPRING_SIZE
Definition: SIDefines.h:550
Generic base class for all target subtargets.
bool isAmdHsaOrMesa(const Function &F) const
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
uint32_t Size
Definition: Profile.cpp:46
#define R_SPILLED_VGPRS
Definition: SIDefines.h:557
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI, const SIInstrInfo &TII, unsigned Reg)
virtual void EmitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:738
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:205
static unsigned getRsrcReg(CallingConv::ID CallConv)
static StringRef getCPU(StringRef CPU)
Processes a CPU name.
unsigned getMaxNumUserSGPRs() const
#define S_00B860_WAVESIZE(x)
Definition: SIDefines.h:551
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define R_00B84C_COMPUTE_PGM_RSRC2
Definition: SIDefines.h:461
#define S_00B848_PRIORITY(x)
Definition: SIDefines.h:508
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
uint64_t ComputePGMRSrc1
Definition: SIProgramInfo.h:33
#define R_0286E8_SPI_TMPRING_SIZE
Definition: SIDefines.h:553
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
void setAlignment(unsigned A)
setAlignment - Set the alignment (log2, not bytes) of the function.
unsigned getHWRegIndex(unsigned Reg) const
#define S_00B02C_EXTRA_LDS_SIZE(x)
Definition: SIDefines.h:451
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn)
RegisterAsmPrinter - Register an AsmPrinter implementation for the given target.
IRTranslator LLVM IR MI
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS
Definition: SIDefines.h:456
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AMDGPU metadata definitions and in-memory representations.
#define R_0286D0_SPI_PS_INPUT_ADDR
Definition: SIDefines.h:499
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
const uint64_t Version
Definition: InstrProf.h:904
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:220
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:136
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
iterator_range< arg_iterator > args()
Definition: Function.h:691
bool hasCodeObjectV3() const