LLVM 19.0.0git
AMDGPUAsmUtils.cpp
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1//===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8#include "AMDGPUAsmUtils.h"
9#include "AMDGPUBaseInfo.h"
10#include "SIDefines.h"
11
12namespace llvm {
13namespace AMDGPU {
14
15namespace DepCtr {
16
17// NOLINTBEGIN
18const CustomOperandVal DepCtrInfo[] = {
19 // Name max dflt offset width constraint
20 {{"depctr_hold_cnt"}, 1, 1, 7, 1, isGFX10_BEncoding},
21 {{"depctr_sa_sdst"}, 1, 1, 0, 1},
22 {{"depctr_va_vdst"}, 15, 15, 12, 4},
23 {{"depctr_va_sdst"}, 7, 7, 9, 3},
24 {{"depctr_va_ssrc"}, 1, 1, 8, 1},
25 {{"depctr_va_vcc"}, 1, 1, 1, 1},
26 {{"depctr_vm_vsrc"}, 7, 7, 2, 3},
27};
28// NOLINTEND
29
30const int DEP_CTR_SIZE =
31 static_cast<int>(sizeof(DepCtrInfo) / sizeof(CustomOperandVal));
32
33} // namespace DepCtr
34
35namespace SendMsg {
36
37// Disable lint checking for this block since it makes the table unreadable.
38// NOLINTBEGIN
39// clang-format off
40const CustomOperand<const MCSubtargetInfo &> Msg[] = {
41 {{""}},
42 {{"MSG_INTERRUPT"}, ID_INTERRUPT},
43 {{"MSG_GS"}, ID_GS_PreGFX11, isNotGFX11Plus},
44 {{"MSG_GS_DONE"}, ID_GS_DONE_PreGFX11, isNotGFX11Plus},
45 {{"MSG_SAVEWAVE"}, ID_SAVEWAVE, isGFX8_GFX9_GFX10},
46 {{"MSG_STALL_WAVE_GEN"}, ID_STALL_WAVE_GEN, isGFX9_GFX10_GFX11},
47 {{"MSG_HALT_WAVES"}, ID_HALT_WAVES, isGFX9_GFX10_GFX11},
48 {{"MSG_ORDERED_PS_DONE"}, ID_ORDERED_PS_DONE, isGFX9_GFX10},
49 {{"MSG_EARLY_PRIM_DEALLOC"}, ID_EARLY_PRIM_DEALLOC, isGFX9_GFX10},
50 {{"MSG_GS_ALLOC_REQ"}, ID_GS_ALLOC_REQ, isGFX9Plus},
51 {{"MSG_GET_DOORBELL"}, ID_GET_DOORBELL, isGFX9_GFX10},
52 {{"MSG_GET_DDID"}, ID_GET_DDID, isGFX10},
53 {{"MSG_HS_TESSFACTOR"}, ID_HS_TESSFACTOR_GFX11Plus, isGFX11Plus},
54 {{"MSG_DEALLOC_VGPRS"}, ID_DEALLOC_VGPRS_GFX11Plus, isGFX11Plus},
55 {{""}},
56 {{"MSG_SYSMSG"}, ID_SYSMSG},
57 {{"MSG_RTN_GET_DOORBELL"}, ID_RTN_GET_DOORBELL, isGFX11Plus},
58 {{"MSG_RTN_GET_DDID"}, ID_RTN_GET_DDID, isGFX11Plus},
59 {{"MSG_RTN_GET_TMA"}, ID_RTN_GET_TMA, isGFX11Plus},
60 {{"MSG_RTN_GET_REALTIME"}, ID_RTN_GET_REALTIME, isGFX11Plus},
61 {{"MSG_RTN_SAVE_WAVE"}, ID_RTN_SAVE_WAVE, isGFX11Plus},
62 {{"MSG_RTN_GET_TBA"}, ID_RTN_GET_TBA, isGFX11Plus},
63 {{"MSG_RTN_GET_TBA_TO_PC"}, ID_RTN_GET_TBA_TO_PC, isGFX11Plus},
64 {{"MSG_RTN_GET_SE_AID_ID"}, ID_RTN_GET_SE_AID_ID, isGFX12Plus},
65};
66// clang-format on
67// NOLINTEND
68
69const int MSG_SIZE = static_cast<int>(
70 sizeof(Msg) / sizeof(CustomOperand<const MCSubtargetInfo &>));
71
72// These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h.
73const char *const OpSysSymbolic[OP_SYS_LAST_] = {
74 nullptr,
75 "SYSMSG_OP_ECC_ERR_INTERRUPT",
76 "SYSMSG_OP_REG_RD",
77 "SYSMSG_OP_HOST_TRAP_ACK",
78 "SYSMSG_OP_TTRACE_PC"
79};
80
81const char *const OpGsSymbolic[OP_GS_LAST_] = {
82 "GS_OP_NOP",
83 "GS_OP_CUT",
84 "GS_OP_EMIT",
85 "GS_OP_EMIT_CUT"
86};
87
88} // namespace SendMsg
89
90namespace Hwreg {
91
92// Disable lint checking for this block since it makes the table unreadable.
93// NOLINTBEGIN
94// clang-format off
95const CustomOperand<const MCSubtargetInfo &> Opr[] = {
96 {{""}},
97 {{"HW_REG_MODE"}, ID_MODE},
98 {{"HW_REG_STATUS"}, ID_STATUS},
99 {{"HW_REG_TRAPSTS"}, ID_TRAPSTS, isNotGFX12Plus},
100 {{"HW_REG_HW_ID"}, ID_HW_ID, isNotGFX10Plus},
101 {{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC},
102 {{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC},
103 {{"HW_REG_IB_STS"}, ID_IB_STS},
104 {{""}},
105 {{""}},
106 {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx12, isGFX12Plus},
107 {{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx12, isGFX12Plus},
108 {{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx12, isGFX12Plus},
109 {{""}},
110 {{""}},
111 {{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9_GFX10_GFX11},
112 {{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10},
113 {{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10},
114 {{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10},
115 {{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10},
116 {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10_GFX11},
117 {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10_GFX11},
118 {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030},
119 {{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
120 {{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
121 {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
122 {{""}},
123 {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11},
124 {{""}},
125 {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
126 {{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus},
127 {{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
128 {{"HW_REG_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},
129
130 // Register numbers reused in GFX11
131 {{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx11, isGFX11},
132 {{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx11, isGFX11},
133
134 // Register numbers reused in GFX12+
135 {{"HW_REG_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
136 {{"HW_REG_PERF_SNAPSHOT_DATA1"}, ID_PERF_SNAPSHOT_DATA1, isGFX12Plus},
137 {{"HW_REG_PERF_SNAPSHOT_DATA2"}, ID_PERF_SNAPSHOT_DATA2, isGFX12Plus},
138 {{"HW_REG_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
139 {{"HW_REG_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
140 {{"HW_REG_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
141 {{"HW_REG_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
142 {{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
143 {{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus},
144
145 // GFX940 specific registers
146 {{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
147 {{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940},
148 {{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940},
149 {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940},
150 {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940},
151
152 // Aliases
153 {{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10},
154};
155// clang-format on
156// NOLINTEND
157
158const int OPR_SIZE = static_cast<int>(
159 sizeof(Opr) / sizeof(CustomOperand<const MCSubtargetInfo &>));
160
161} // namespace Hwreg
162
163namespace MTBUFFormat {
164
165StringLiteral const DfmtSymbolic[] = {
166 "BUF_DATA_FORMAT_INVALID",
167 "BUF_DATA_FORMAT_8",
168 "BUF_DATA_FORMAT_16",
169 "BUF_DATA_FORMAT_8_8",
170 "BUF_DATA_FORMAT_32",
171 "BUF_DATA_FORMAT_16_16",
172 "BUF_DATA_FORMAT_10_11_11",
173 "BUF_DATA_FORMAT_11_11_10",
174 "BUF_DATA_FORMAT_10_10_10_2",
175 "BUF_DATA_FORMAT_2_10_10_10",
176 "BUF_DATA_FORMAT_8_8_8_8",
177 "BUF_DATA_FORMAT_32_32",
178 "BUF_DATA_FORMAT_16_16_16_16",
179 "BUF_DATA_FORMAT_32_32_32",
180 "BUF_DATA_FORMAT_32_32_32_32",
181 "BUF_DATA_FORMAT_RESERVED_15"
182};
183
184StringLiteral const NfmtSymbolicGFX10[] = {
185 "BUF_NUM_FORMAT_UNORM",
186 "BUF_NUM_FORMAT_SNORM",
187 "BUF_NUM_FORMAT_USCALED",
188 "BUF_NUM_FORMAT_SSCALED",
189 "BUF_NUM_FORMAT_UINT",
190 "BUF_NUM_FORMAT_SINT",
191 "",
192 "BUF_NUM_FORMAT_FLOAT"
193};
194
195StringLiteral const NfmtSymbolicSICI[] = {
196 "BUF_NUM_FORMAT_UNORM",
197 "BUF_NUM_FORMAT_SNORM",
198 "BUF_NUM_FORMAT_USCALED",
199 "BUF_NUM_FORMAT_SSCALED",
200 "BUF_NUM_FORMAT_UINT",
201 "BUF_NUM_FORMAT_SINT",
202 "BUF_NUM_FORMAT_SNORM_OGL",
203 "BUF_NUM_FORMAT_FLOAT"
204};
205
206StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9
207 "BUF_NUM_FORMAT_UNORM",
208 "BUF_NUM_FORMAT_SNORM",
209 "BUF_NUM_FORMAT_USCALED",
210 "BUF_NUM_FORMAT_SSCALED",
211 "BUF_NUM_FORMAT_UINT",
212 "BUF_NUM_FORMAT_SINT",
213 "BUF_NUM_FORMAT_RESERVED_6",
214 "BUF_NUM_FORMAT_FLOAT"
215};
216
217StringLiteral const UfmtSymbolicGFX10[] = {
218 "BUF_FMT_INVALID",
219
220 "BUF_FMT_8_UNORM",
221 "BUF_FMT_8_SNORM",
222 "BUF_FMT_8_USCALED",
223 "BUF_FMT_8_SSCALED",
224 "BUF_FMT_8_UINT",
225 "BUF_FMT_8_SINT",
226
227 "BUF_FMT_16_UNORM",
228 "BUF_FMT_16_SNORM",
229 "BUF_FMT_16_USCALED",
230 "BUF_FMT_16_SSCALED",
231 "BUF_FMT_16_UINT",
232 "BUF_FMT_16_SINT",
233 "BUF_FMT_16_FLOAT",
234
235 "BUF_FMT_8_8_UNORM",
236 "BUF_FMT_8_8_SNORM",
237 "BUF_FMT_8_8_USCALED",
238 "BUF_FMT_8_8_SSCALED",
239 "BUF_FMT_8_8_UINT",
240 "BUF_FMT_8_8_SINT",
241
242 "BUF_FMT_32_UINT",
243 "BUF_FMT_32_SINT",
244 "BUF_FMT_32_FLOAT",
245
246 "BUF_FMT_16_16_UNORM",
247 "BUF_FMT_16_16_SNORM",
248 "BUF_FMT_16_16_USCALED",
249 "BUF_FMT_16_16_SSCALED",
250 "BUF_FMT_16_16_UINT",
251 "BUF_FMT_16_16_SINT",
252 "BUF_FMT_16_16_FLOAT",
253
254 "BUF_FMT_10_11_11_UNORM",
255 "BUF_FMT_10_11_11_SNORM",
256 "BUF_FMT_10_11_11_USCALED",
257 "BUF_FMT_10_11_11_SSCALED",
258 "BUF_FMT_10_11_11_UINT",
259 "BUF_FMT_10_11_11_SINT",
260 "BUF_FMT_10_11_11_FLOAT",
261
262 "BUF_FMT_11_11_10_UNORM",
263 "BUF_FMT_11_11_10_SNORM",
264 "BUF_FMT_11_11_10_USCALED",
265 "BUF_FMT_11_11_10_SSCALED",
266 "BUF_FMT_11_11_10_UINT",
267 "BUF_FMT_11_11_10_SINT",
268 "BUF_FMT_11_11_10_FLOAT",
269
270 "BUF_FMT_10_10_10_2_UNORM",
271 "BUF_FMT_10_10_10_2_SNORM",
272 "BUF_FMT_10_10_10_2_USCALED",
273 "BUF_FMT_10_10_10_2_SSCALED",
274 "BUF_FMT_10_10_10_2_UINT",
275 "BUF_FMT_10_10_10_2_SINT",
276
277 "BUF_FMT_2_10_10_10_UNORM",
278 "BUF_FMT_2_10_10_10_SNORM",
279 "BUF_FMT_2_10_10_10_USCALED",
280 "BUF_FMT_2_10_10_10_SSCALED",
281 "BUF_FMT_2_10_10_10_UINT",
282 "BUF_FMT_2_10_10_10_SINT",
283
284 "BUF_FMT_8_8_8_8_UNORM",
285 "BUF_FMT_8_8_8_8_SNORM",
286 "BUF_FMT_8_8_8_8_USCALED",
287 "BUF_FMT_8_8_8_8_SSCALED",
288 "BUF_FMT_8_8_8_8_UINT",
289 "BUF_FMT_8_8_8_8_SINT",
290
291 "BUF_FMT_32_32_UINT",
292 "BUF_FMT_32_32_SINT",
293 "BUF_FMT_32_32_FLOAT",
294
295 "BUF_FMT_16_16_16_16_UNORM",
296 "BUF_FMT_16_16_16_16_SNORM",
297 "BUF_FMT_16_16_16_16_USCALED",
298 "BUF_FMT_16_16_16_16_SSCALED",
299 "BUF_FMT_16_16_16_16_UINT",
300 "BUF_FMT_16_16_16_16_SINT",
301 "BUF_FMT_16_16_16_16_FLOAT",
302
303 "BUF_FMT_32_32_32_UINT",
304 "BUF_FMT_32_32_32_SINT",
305 "BUF_FMT_32_32_32_FLOAT",
306 "BUF_FMT_32_32_32_32_UINT",
307 "BUF_FMT_32_32_32_32_SINT",
308 "BUF_FMT_32_32_32_32_FLOAT"
309};
310
311unsigned const DfmtNfmt2UFmtGFX10[] = {
312 DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT),
313
314 DFMT_8 | (NFMT_UNORM << NFMT_SHIFT),
315 DFMT_8 | (NFMT_SNORM << NFMT_SHIFT),
316 DFMT_8 | (NFMT_USCALED << NFMT_SHIFT),
317 DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT),
318 DFMT_8 | (NFMT_UINT << NFMT_SHIFT),
319 DFMT_8 | (NFMT_SINT << NFMT_SHIFT),
320
321 DFMT_16 | (NFMT_UNORM << NFMT_SHIFT),
322 DFMT_16 | (NFMT_SNORM << NFMT_SHIFT),
323 DFMT_16 | (NFMT_USCALED << NFMT_SHIFT),
324 DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT),
325 DFMT_16 | (NFMT_UINT << NFMT_SHIFT),
326 DFMT_16 | (NFMT_SINT << NFMT_SHIFT),
327 DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT),
328
329 DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT),
330 DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT),
331 DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT),
332 DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT),
333 DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT),
334 DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT),
335
336 DFMT_32 | (NFMT_UINT << NFMT_SHIFT),
337 DFMT_32 | (NFMT_SINT << NFMT_SHIFT),
338 DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT),
339
340 DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT),
341 DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT),
342 DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT),
343 DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT),
344 DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT),
345 DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT),
346 DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT),
347
348 DFMT_10_11_11 | (NFMT_UNORM << NFMT_SHIFT),
349 DFMT_10_11_11 | (NFMT_SNORM << NFMT_SHIFT),
350 DFMT_10_11_11 | (NFMT_USCALED << NFMT_SHIFT),
351 DFMT_10_11_11 | (NFMT_SSCALED << NFMT_SHIFT),
352 DFMT_10_11_11 | (NFMT_UINT << NFMT_SHIFT),
353 DFMT_10_11_11 | (NFMT_SINT << NFMT_SHIFT),
354 DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT),
355
356 DFMT_11_11_10 | (NFMT_UNORM << NFMT_SHIFT),
357 DFMT_11_11_10 | (NFMT_SNORM << NFMT_SHIFT),
358 DFMT_11_11_10 | (NFMT_USCALED << NFMT_SHIFT),
359 DFMT_11_11_10 | (NFMT_SSCALED << NFMT_SHIFT),
360 DFMT_11_11_10 | (NFMT_UINT << NFMT_SHIFT),
361 DFMT_11_11_10 | (NFMT_SINT << NFMT_SHIFT),
362 DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT),
363
364 DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT),
365 DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT),
366 DFMT_10_10_10_2 | (NFMT_USCALED << NFMT_SHIFT),
367 DFMT_10_10_10_2 | (NFMT_SSCALED << NFMT_SHIFT),
368 DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT),
369 DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT),
370
371 DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT),
372 DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT),
373 DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT),
374 DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT),
375 DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT),
376 DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT),
377
378 DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT),
379 DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT),
380 DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT),
381 DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT),
382 DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT),
383 DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT),
384
385 DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT),
386 DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT),
387 DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT),
388
389 DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT),
390 DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT),
391 DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT),
392 DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT),
393 DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT),
394 DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT),
395 DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT),
396
397 DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT),
398 DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT),
399 DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT),
400 DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT),
401 DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT),
402 DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT)
403};
404
405StringLiteral const UfmtSymbolicGFX11[] = {
406 "BUF_FMT_INVALID",
407
408 "BUF_FMT_8_UNORM",
409 "BUF_FMT_8_SNORM",
410 "BUF_FMT_8_USCALED",
411 "BUF_FMT_8_SSCALED",
412 "BUF_FMT_8_UINT",
413 "BUF_FMT_8_SINT",
414
415 "BUF_FMT_16_UNORM",
416 "BUF_FMT_16_SNORM",
417 "BUF_FMT_16_USCALED",
418 "BUF_FMT_16_SSCALED",
419 "BUF_FMT_16_UINT",
420 "BUF_FMT_16_SINT",
421 "BUF_FMT_16_FLOAT",
422
423 "BUF_FMT_8_8_UNORM",
424 "BUF_FMT_8_8_SNORM",
425 "BUF_FMT_8_8_USCALED",
426 "BUF_FMT_8_8_SSCALED",
427 "BUF_FMT_8_8_UINT",
428 "BUF_FMT_8_8_SINT",
429
430 "BUF_FMT_32_UINT",
431 "BUF_FMT_32_SINT",
432 "BUF_FMT_32_FLOAT",
433
434 "BUF_FMT_16_16_UNORM",
435 "BUF_FMT_16_16_SNORM",
436 "BUF_FMT_16_16_USCALED",
437 "BUF_FMT_16_16_SSCALED",
438 "BUF_FMT_16_16_UINT",
439 "BUF_FMT_16_16_SINT",
440 "BUF_FMT_16_16_FLOAT",
441
442 "BUF_FMT_10_11_11_FLOAT",
443
444 "BUF_FMT_11_11_10_FLOAT",
445
446 "BUF_FMT_10_10_10_2_UNORM",
447 "BUF_FMT_10_10_10_2_SNORM",
448 "BUF_FMT_10_10_10_2_UINT",
449 "BUF_FMT_10_10_10_2_SINT",
450
451 "BUF_FMT_2_10_10_10_UNORM",
452 "BUF_FMT_2_10_10_10_SNORM",
453 "BUF_FMT_2_10_10_10_USCALED",
454 "BUF_FMT_2_10_10_10_SSCALED",
455 "BUF_FMT_2_10_10_10_UINT",
456 "BUF_FMT_2_10_10_10_SINT",
457
458 "BUF_FMT_8_8_8_8_UNORM",
459 "BUF_FMT_8_8_8_8_SNORM",
460 "BUF_FMT_8_8_8_8_USCALED",
461 "BUF_FMT_8_8_8_8_SSCALED",
462 "BUF_FMT_8_8_8_8_UINT",
463 "BUF_FMT_8_8_8_8_SINT",
464
465 "BUF_FMT_32_32_UINT",
466 "BUF_FMT_32_32_SINT",
467 "BUF_FMT_32_32_FLOAT",
468
469 "BUF_FMT_16_16_16_16_UNORM",
470 "BUF_FMT_16_16_16_16_SNORM",
471 "BUF_FMT_16_16_16_16_USCALED",
472 "BUF_FMT_16_16_16_16_SSCALED",
473 "BUF_FMT_16_16_16_16_UINT",
474 "BUF_FMT_16_16_16_16_SINT",
475 "BUF_FMT_16_16_16_16_FLOAT",
476
477 "BUF_FMT_32_32_32_UINT",
478 "BUF_FMT_32_32_32_SINT",
479 "BUF_FMT_32_32_32_FLOAT",
480 "BUF_FMT_32_32_32_32_UINT",
481 "BUF_FMT_32_32_32_32_SINT",
482 "BUF_FMT_32_32_32_32_FLOAT"
483};
484
485unsigned const DfmtNfmt2UFmtGFX11[] = {
486 DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT),
487
488 DFMT_8 | (NFMT_UNORM << NFMT_SHIFT),
489 DFMT_8 | (NFMT_SNORM << NFMT_SHIFT),
490 DFMT_8 | (NFMT_USCALED << NFMT_SHIFT),
491 DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT),
492 DFMT_8 | (NFMT_UINT << NFMT_SHIFT),
493 DFMT_8 | (NFMT_SINT << NFMT_SHIFT),
494
495 DFMT_16 | (NFMT_UNORM << NFMT_SHIFT),
496 DFMT_16 | (NFMT_SNORM << NFMT_SHIFT),
497 DFMT_16 | (NFMT_USCALED << NFMT_SHIFT),
498 DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT),
499 DFMT_16 | (NFMT_UINT << NFMT_SHIFT),
500 DFMT_16 | (NFMT_SINT << NFMT_SHIFT),
501 DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT),
502
503 DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT),
504 DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT),
505 DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT),
506 DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT),
507 DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT),
508 DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT),
509
510 DFMT_32 | (NFMT_UINT << NFMT_SHIFT),
511 DFMT_32 | (NFMT_SINT << NFMT_SHIFT),
512 DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT),
513
514 DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT),
515 DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT),
516 DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT),
517 DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT),
518 DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT),
519 DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT),
520 DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT),
521
522 DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT),
523
524 DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT),
525
526 DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT),
527 DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT),
528 DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT),
529 DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT),
530
531 DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT),
532 DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT),
533 DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT),
534 DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT),
535 DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT),
536 DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT),
537
538 DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT),
539 DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT),
540 DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT),
541 DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT),
542 DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT),
543 DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT),
544
545 DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT),
546 DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT),
547 DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT),
548
549 DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT),
550 DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT),
551 DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT),
552 DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT),
553 DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT),
554 DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT),
555 DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT),
556
557 DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT),
558 DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT),
559 DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT),
560 DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT),
561 DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT),
562 DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT)
563};
564
565} // namespace MTBUFFormat
566
567namespace Swizzle {
568
569// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
570const char* const IdSymbolic[] = {
571 "QUAD_PERM",
572 "BITMASK_PERM",
573 "SWAP",
574 "REVERSE",
575 "BROADCAST",
576};
577
578} // namespace Swizzle
579
580namespace VGPRIndexMode {
581
582// This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h.
583const char* const IdSymbolic[] = {
584 "SRC0",
585 "SRC1",
586 "SRC2",
587 "DST",
588};
589
590} // namespace VGPRIndexMode
591
592} // namespace AMDGPU
593} // namespace llvm
Swizzle
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
Definition: R600InstrInfo.cpp:350
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:849
llvm::AMDGPU::DepCtr::DepCtrInfo
const CustomOperandVal DepCtrInfo[]
Definition: AMDGPUAsmUtils.cpp:18
llvm::AMDGPU::Hwreg::Opr
const CustomOperand< const MCSubtargetInfo & > Opr[]
Definition: AMDGPUAsmUtils.cpp:95
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX11
StringLiteral const UfmtSymbolicGFX11[]
Definition: AMDGPUAsmUtils.cpp:405
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX10
unsigned const DfmtNfmt2UFmtGFX10[]
Definition: AMDGPUAsmUtils.cpp:311
llvm::AMDGPU::MTBUFFormat::DfmtSymbolic
StringLiteral const DfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:165
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicGFX10
StringLiteral const NfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:184
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX11
unsigned const DfmtNfmt2UFmtGFX11[]
Definition: AMDGPUAsmUtils.cpp:485
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicVI
StringLiteral const NfmtSymbolicVI[]
Definition: AMDGPUAsmUtils.cpp:206
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicSICI
StringLiteral const NfmtSymbolicSICI[]
Definition: AMDGPUAsmUtils.cpp:195
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX10
StringLiteral const UfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:217
llvm::AMDGPU::SendMsg::OpGsSymbolic
const char *const OpGsSymbolic[OP_GS_LAST_]
Definition: AMDGPUAsmUtils.cpp:81
llvm::AMDGPU::SendMsg::OpSysSymbolic
const char *const OpSysSymbolic[OP_SYS_LAST_]
Definition: AMDGPUAsmUtils.cpp:73
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:40
llvm::AMDGPU::Swizzle::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:570
llvm::AMDGPU::VGPRIndexMode::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:583
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2237
llvm::AMDGPU::isGFX10_GFX11
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2193
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2225
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2189
llvm::AMDGPU::isGFX12Plus
bool isGFX12Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2213
llvm::AMDGPU::isGFX940
bool isGFX940(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2253
llvm::AMDGPU::isGFX11
bool isGFX11(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2201
llvm::AMDGPU::isGFX10_3_GFX11
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2245
llvm::AMDGPU::isGFX8_GFX9_GFX10
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2177
llvm::AMDGPU::isNotGFX10Plus
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2221
llvm::AMDGPU::isNotGFX11Plus
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2217
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2205
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2197
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2185
llvm::AMDGPU::isNotGFX12Plus
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2215
llvm::AMDGPU::isGFX9_GFX10_GFX11
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2173
llvm::AMDGPU::isGFX9_GFX10
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2169
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
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