LLVM  9.0.0svn
AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUBaseInfo.h"
11 #include "AMDGPU.h"
12 #include "SIDefines.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/BinaryFormat/ELF.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/IR/LLVMContext.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSectionELF.h"
31 #include "llvm/Support/Casting.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <cstring>
38 #include <utility>
39 
41 
42 #define GET_INSTRINFO_NAMED_OPS
43 #define GET_INSTRMAP_INFO
44 #include "AMDGPUGenInstrInfo.inc"
45 #undef GET_INSTRMAP_INFO
46 #undef GET_INSTRINFO_NAMED_OPS
47 
48 namespace {
49 
50 /// \returns Bit mask for given bit \p Shift and bit \p Width.
51 unsigned getBitMask(unsigned Shift, unsigned Width) {
52  return ((1 << Width) - 1) << Shift;
53 }
54 
55 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
56 ///
57 /// \returns Packed \p Dst.
58 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
59  Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
60  Dst |= (Src << Shift) & getBitMask(Shift, Width);
61  return Dst;
62 }
63 
64 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
65 ///
66 /// \returns Unpacked bits.
67 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
68  return (Src & getBitMask(Shift, Width)) >> Shift;
69 }
70 
71 /// \returns Vmcnt bit shift (lower bits).
72 unsigned getVmcntBitShiftLo() { return 0; }
73 
74 /// \returns Vmcnt bit width (lower bits).
75 unsigned getVmcntBitWidthLo() { return 4; }
76 
77 /// \returns Expcnt bit shift.
78 unsigned getExpcntBitShift() { return 4; }
79 
80 /// \returns Expcnt bit width.
81 unsigned getExpcntBitWidth() { return 3; }
82 
83 /// \returns Lgkmcnt bit shift.
84 unsigned getLgkmcntBitShift() { return 8; }
85 
86 /// \returns Lgkmcnt bit width.
87 unsigned getLgkmcntBitWidth() { return 4; }
88 
89 /// \returns Vmcnt bit shift (higher bits).
90 unsigned getVmcntBitShiftHi() { return 14; }
91 
92 /// \returns Vmcnt bit width (higher bits).
93 unsigned getVmcntBitWidthHi() { return 2; }
94 
95 } // end namespace anonymous
96 
97 namespace llvm {
98 
99 namespace AMDGPU {
100 
101 struct MIMGInfo {
102  uint16_t Opcode;
103  uint16_t BaseOpcode;
104  uint8_t MIMGEncoding;
105  uint8_t VDataDwords;
106  uint8_t VAddrDwords;
107 };
108 
109 #define GET_MIMGBaseOpcodesTable_IMPL
110 #define GET_MIMGDimInfoTable_IMPL
111 #define GET_MIMGInfoTable_IMPL
112 #define GET_MIMGLZMappingTable_IMPL
113 #include "AMDGPUGenSearchableTables.inc"
114 
115 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
116  unsigned VDataDwords, unsigned VAddrDwords) {
117  const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
118  VDataDwords, VAddrDwords);
119  return Info ? Info->Opcode : -1;
120 }
121 
122 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
123  const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
124  const MIMGInfo *NewInfo =
125  getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
126  NewChannels, OrigInfo->VAddrDwords);
127  return NewInfo ? NewInfo->Opcode : -1;
128 }
129 
130 struct MUBUFInfo {
131  uint16_t Opcode;
132  uint16_t BaseOpcode;
133  uint8_t dwords;
134  bool has_vaddr;
135  bool has_srsrc;
137 };
138 
139 #define GET_MUBUFInfoTable_DECL
140 #define GET_MUBUFInfoTable_IMPL
141 #include "AMDGPUGenSearchableTables.inc"
142 
143 int getMUBUFBaseOpcode(unsigned Opc) {
144  const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
145  return Info ? Info->BaseOpcode : -1;
146 }
147 
148 int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords) {
149  const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndDwords(BaseOpc, Dwords);
150  return Info ? Info->Opcode : -1;
151 }
152 
153 int getMUBUFDwords(unsigned Opc) {
154  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
155  return Info ? Info->dwords : 0;
156 }
157 
158 bool getMUBUFHasVAddr(unsigned Opc) {
159  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
160  return Info ? Info->has_vaddr : false;
161 }
162 
163 bool getMUBUFHasSrsrc(unsigned Opc) {
164  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
165  return Info ? Info->has_srsrc : false;
166 }
167 
168 bool getMUBUFHasSoffset(unsigned Opc) {
169  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
170  return Info ? Info->has_soffset : false;
171 }
172 
173 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
174 // header files, so we need to wrap it in a function that takes unsigned
175 // instead.
176 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
177  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
178 }
179 
180 namespace IsaInfo {
181 
182 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
183  auto TargetTriple = STI->getTargetTriple();
184  auto Version = getIsaVersion(STI->getCPU());
185 
186  Stream << TargetTriple.getArchName() << '-'
187  << TargetTriple.getVendorName() << '-'
188  << TargetTriple.getOSName() << '-'
189  << TargetTriple.getEnvironmentName() << '-'
190  << "gfx"
191  << Version.Major
192  << Version.Minor
193  << Version.Stepping;
194 
195  if (hasXNACK(*STI))
196  Stream << "+xnack";
197  if (hasSRAMECC(*STI))
198  Stream << "+sram-ecc";
199 
200  Stream.flush();
201 }
202 
204  return STI->getTargetTriple().getOS() == Triple::AMDHSA &&
205  STI->getFeatureBits().test(FeatureCodeObjectV3);
206 }
207 
208 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
209  if (STI->getFeatureBits().test(FeatureWavefrontSize16))
210  return 16;
211  if (STI->getFeatureBits().test(FeatureWavefrontSize32))
212  return 32;
213 
214  return 64;
215 }
216 
217 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
218  if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
219  return 32768;
220  if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
221  return 65536;
222 
223  return 0;
224 }
225 
226 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
227  return 4;
228 }
229 
231  unsigned FlatWorkGroupSize) {
232  assert(FlatWorkGroupSize != 0);
233  if (STI->getTargetTriple().getArch() != Triple::amdgcn)
234  return 8;
235  unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
236  if (N == 1)
237  return 40;
238  N = 40 / N;
239  return std::min(N, 16u);
240 }
241 
242 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI) {
243  return getMaxWavesPerEU() * getEUsPerCU(STI);
244 }
245 
246 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,
247  unsigned FlatWorkGroupSize) {
248  return getWavesPerWorkGroup(STI, FlatWorkGroupSize);
249 }
250 
251 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
252  return 1;
253 }
254 
255 unsigned getMaxWavesPerEU() {
256  // FIXME: Need to take scratch memory into account.
257  return 10;
258 }
259 
260 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
261  unsigned FlatWorkGroupSize) {
262  return alignTo(getMaxWavesPerCU(STI, FlatWorkGroupSize),
263  getEUsPerCU(STI)) / getEUsPerCU(STI);
264 }
265 
267  return 1;
268 }
269 
271  return 2048;
272 }
273 
275  unsigned FlatWorkGroupSize) {
276  return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) /
277  getWavefrontSize(STI);
278 }
279 
280 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
282  if (Version.Major >= 8)
283  return 16;
284  return 8;
285 }
286 
288  return 8;
289 }
290 
291 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
293  if (Version.Major >= 8)
294  return 800;
295  return 512;
296 }
297 
299  if (STI->getFeatureBits().test(FeatureSGPRInitBug))
301 
303  if (Version.Major >= 8)
304  return 102;
305  return 104;
306 }
307 
308 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
309  assert(WavesPerEU != 0);
310 
311  if (WavesPerEU >= getMaxWavesPerEU())
312  return 0;
313 
314  unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
315  if (STI->getFeatureBits().test(FeatureTrapHandler))
316  MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
317  MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
318  return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
319 }
320 
321 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
322  bool Addressable) {
323  assert(WavesPerEU != 0);
324 
326  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
327  if (Version.Major >= 8 && !Addressable)
328  AddressableNumSGPRs = 112;
329  unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
330  if (STI->getFeatureBits().test(FeatureTrapHandler))
331  MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
332  MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
333  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
334 }
335 
336 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
337  bool FlatScrUsed, bool XNACKUsed) {
338  unsigned ExtraSGPRs = 0;
339  if (VCCUsed)
340  ExtraSGPRs = 2;
341 
343  if (Version.Major < 8) {
344  if (FlatScrUsed)
345  ExtraSGPRs = 4;
346  } else {
347  if (XNACKUsed)
348  ExtraSGPRs = 4;
349 
350  if (FlatScrUsed)
351  ExtraSGPRs = 6;
352  }
353 
354  return ExtraSGPRs;
355 }
356 
357 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
358  bool FlatScrUsed) {
359  return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
360  STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
361 }
362 
363 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
364  NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(STI));
365  // SGPRBlocks is actual number of SGPR blocks minus 1.
366  return NumSGPRs / getSGPREncodingGranule(STI) - 1;
367 }
368 
369 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI) {
370  return 4;
371 }
372 
374  return getVGPRAllocGranule(STI);
375 }
376 
377 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
378  return 256;
379 }
380 
382  return getTotalNumVGPRs(STI);
383 }
384 
385 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
386  assert(WavesPerEU != 0);
387 
388  if (WavesPerEU >= getMaxWavesPerEU())
389  return 0;
390  unsigned MinNumVGPRs =
391  alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
392  getVGPRAllocGranule(STI)) + 1;
393  return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
394 }
395 
396 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
397  assert(WavesPerEU != 0);
398 
399  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
400  getVGPRAllocGranule(STI));
401  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
402  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
403 }
404 
405 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs) {
406  NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(STI));
407  // VGPRBlocks is actual number of VGPR blocks minus 1.
408  return NumVGPRs / getVGPREncodingGranule(STI) - 1;
409 }
410 
411 } // end namespace IsaInfo
412 
414  const MCSubtargetInfo *STI) {
416 
417  memset(&Header, 0, sizeof(Header));
418 
421  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
422  Header.amd_machine_version_major = Version.Major;
423  Header.amd_machine_version_minor = Version.Minor;
424  Header.amd_machine_version_stepping = Version.Stepping;
425  Header.kernel_code_entry_byte_offset = sizeof(Header);
426  // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
427  Header.wavefront_size = 6;
428 
429  // If the code object does not support indirect functions, then the value must
430  // be 0xffffffff.
431  Header.call_convention = -1;
432 
433  // These alignment values are specified in powers of two, so alignment =
434  // 2^n. The minimum alignment is 2^4 = 16.
435  Header.kernarg_segment_alignment = 4;
436  Header.group_segment_alignment = 4;
437  Header.private_segment_alignment = 4;
438 }
439 
442  memset(&KD, 0, sizeof(KD));
444  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
447  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
449  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
451  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
452  return KD;
453 }
454 
455 bool isGroupSegment(const GlobalValue *GV) {
457 }
458 
459 bool isGlobalSegment(const GlobalValue *GV) {
461 }
462 
466 }
467 
469  return TT.getOS() != Triple::AMDHSA;
470 }
471 
472 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
473  Attribute A = F.getFnAttribute(Name);
474  int Result = Default;
475 
476  if (A.isStringAttribute()) {
477  StringRef Str = A.getValueAsString();
478  if (Str.getAsInteger(0, Result)) {
479  LLVMContext &Ctx = F.getContext();
480  Ctx.emitError("can't parse integer attribute " + Name);
481  }
482  }
483 
484  return Result;
485 }
486 
487 std::pair<int, int> getIntegerPairAttribute(const Function &F,
488  StringRef Name,
489  std::pair<int, int> Default,
490  bool OnlyFirstRequired) {
491  Attribute A = F.getFnAttribute(Name);
492  if (!A.isStringAttribute())
493  return Default;
494 
495  LLVMContext &Ctx = F.getContext();
496  std::pair<int, int> Ints = Default;
497  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
498  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
499  Ctx.emitError("can't parse first integer attribute " + Name);
500  return Default;
501  }
502  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
503  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
504  Ctx.emitError("can't parse second integer attribute " + Name);
505  return Default;
506  }
507  }
508 
509  return Ints;
510 }
511 
513  unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
514  if (Version.Major < 9)
515  return VmcntLo;
516 
517  unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
518  return VmcntLo | VmcntHi;
519 }
520 
522  return (1 << getExpcntBitWidth()) - 1;
523 }
524 
526  return (1 << getLgkmcntBitWidth()) - 1;
527 }
528 
530  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
531  unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
532  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
533  unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
534  if (Version.Major < 9)
535  return Waitcnt;
536 
537  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
538  return Waitcnt | VmcntHi;
539 }
540 
541 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
542  unsigned VmcntLo =
543  unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
544  if (Version.Major < 9)
545  return VmcntLo;
546 
547  unsigned VmcntHi =
548  unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
549  VmcntHi <<= getVmcntBitWidthLo();
550  return VmcntLo | VmcntHi;
551 }
552 
553 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
554  return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
555 }
556 
557 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
558  return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
559 }
560 
561 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
562  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
563  Vmcnt = decodeVmcnt(Version, Waitcnt);
564  Expcnt = decodeExpcnt(Version, Waitcnt);
565  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
566 }
567 
568 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
569  Waitcnt Decoded;
570  Decoded.VmCnt = decodeVmcnt(Version, Encoded);
571  Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
572  Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
573  return Decoded;
574 }
575 
576 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
577  unsigned Vmcnt) {
578  Waitcnt =
579  packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
580  if (Version.Major < 9)
581  return Waitcnt;
582 
583  Vmcnt >>= getVmcntBitWidthLo();
584  return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
585 }
586 
587 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
588  unsigned Expcnt) {
589  return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
590 }
591 
592 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
593  unsigned Lgkmcnt) {
594  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
595 }
596 
598  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
599  unsigned Waitcnt = getWaitcntBitMask(Version);
600  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
601  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
602  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
603  return Waitcnt;
604 }
605 
606 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
607  return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
608 }
609 
610 unsigned getInitialPSInputAddr(const Function &F) {
611  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
612 }
613 
615  switch(cc) {
623  return true;
624  default:
625  return false;
626  }
627 }
628 
630  return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
631 }
632 
634  switch (CC) {
644  return true;
645  default:
646  return false;
647  }
648 }
649 
650 bool hasXNACK(const MCSubtargetInfo &STI) {
651  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
652 }
653 
654 bool hasSRAMECC(const MCSubtargetInfo &STI) {
655  return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
656 }
657 
658 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
659  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
660 }
661 
662 bool hasPackedD16(const MCSubtargetInfo &STI) {
663  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
664 }
665 
666 bool isSI(const MCSubtargetInfo &STI) {
667  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
668 }
669 
670 bool isCI(const MCSubtargetInfo &STI) {
671  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
672 }
673 
674 bool isVI(const MCSubtargetInfo &STI) {
675  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
676 }
677 
678 bool isGFX9(const MCSubtargetInfo &STI) {
679  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
680 }
681 
682 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
683  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
684 }
685 
686 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
687  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
688  const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
689  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
690  Reg == AMDGPU::SCC;
691 }
692 
693 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
694  for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
695  if (*R == Reg1) return true;
696  }
697  return false;
698 }
699 
700 #define MAP_REG2REG \
701  using namespace AMDGPU; \
702  switch(Reg) { \
703  default: return Reg; \
704  CASE_CI_VI(FLAT_SCR) \
705  CASE_CI_VI(FLAT_SCR_LO) \
706  CASE_CI_VI(FLAT_SCR_HI) \
707  CASE_VI_GFX9(TTMP0) \
708  CASE_VI_GFX9(TTMP1) \
709  CASE_VI_GFX9(TTMP2) \
710  CASE_VI_GFX9(TTMP3) \
711  CASE_VI_GFX9(TTMP4) \
712  CASE_VI_GFX9(TTMP5) \
713  CASE_VI_GFX9(TTMP6) \
714  CASE_VI_GFX9(TTMP7) \
715  CASE_VI_GFX9(TTMP8) \
716  CASE_VI_GFX9(TTMP9) \
717  CASE_VI_GFX9(TTMP10) \
718  CASE_VI_GFX9(TTMP11) \
719  CASE_VI_GFX9(TTMP12) \
720  CASE_VI_GFX9(TTMP13) \
721  CASE_VI_GFX9(TTMP14) \
722  CASE_VI_GFX9(TTMP15) \
723  CASE_VI_GFX9(TTMP0_TTMP1) \
724  CASE_VI_GFX9(TTMP2_TTMP3) \
725  CASE_VI_GFX9(TTMP4_TTMP5) \
726  CASE_VI_GFX9(TTMP6_TTMP7) \
727  CASE_VI_GFX9(TTMP8_TTMP9) \
728  CASE_VI_GFX9(TTMP10_TTMP11) \
729  CASE_VI_GFX9(TTMP12_TTMP13) \
730  CASE_VI_GFX9(TTMP14_TTMP15) \
731  CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
732  CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
733  CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
734  CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
735  CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
736  CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
737  CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
738  CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
739  }
740 
741 #define CASE_CI_VI(node) \
742  assert(!isSI(STI)); \
743  case node: return isCI(STI) ? node##_ci : node##_vi;
744 
745 #define CASE_VI_GFX9(node) \
746  case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
747 
748 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
749  if (STI.getTargetTriple().getArch() == Triple::r600)
750  return Reg;
752 }
753 
754 #undef CASE_CI_VI
755 #undef CASE_VI_GFX9
756 
757 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
758 #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
759 
760 unsigned mc2PseudoReg(unsigned Reg) {
762 }
763 
764 #undef CASE_CI_VI
765 #undef CASE_VI_GFX9
766 #undef MAP_REG2REG
767 
768 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
769  assert(OpNo < Desc.NumOperands);
770  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
771  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
772  OpType <= AMDGPU::OPERAND_SRC_LAST;
773 }
774 
775 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
776  assert(OpNo < Desc.NumOperands);
777  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
778  switch (OpType) {
786  return true;
787  default:
788  return false;
789  }
790 }
791 
792 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
793  assert(OpNo < Desc.NumOperands);
794  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
795  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
797 }
798 
799 // Avoid using MCRegisterClass::getSize, since that function will go away
800 // (move from MC* level to Target* level). Return size in bits.
801 unsigned getRegBitWidth(unsigned RCID) {
802  switch (RCID) {
803  case AMDGPU::SGPR_32RegClassID:
804  case AMDGPU::VGPR_32RegClassID:
805  case AMDGPU::VRegOrLds_32RegClassID:
806  case AMDGPU::VS_32RegClassID:
807  case AMDGPU::SReg_32RegClassID:
808  case AMDGPU::SReg_32_XM0RegClassID:
809  case AMDGPU::SRegOrLds_32RegClassID:
810  return 32;
811  case AMDGPU::SGPR_64RegClassID:
812  case AMDGPU::VS_64RegClassID:
813  case AMDGPU::SReg_64RegClassID:
814  case AMDGPU::VReg_64RegClassID:
815  case AMDGPU::SReg_64_XEXECRegClassID:
816  return 64;
817  case AMDGPU::SGPR_96RegClassID:
818  case AMDGPU::SReg_96RegClassID:
819  case AMDGPU::VReg_96RegClassID:
820  return 96;
821  case AMDGPU::SGPR_128RegClassID:
822  case AMDGPU::SReg_128RegClassID:
823  case AMDGPU::VReg_128RegClassID:
824  return 128;
825  case AMDGPU::SReg_256RegClassID:
826  case AMDGPU::VReg_256RegClassID:
827  return 256;
828  case AMDGPU::SReg_512RegClassID:
829  case AMDGPU::VReg_512RegClassID:
830  return 512;
831  default:
832  llvm_unreachable("Unexpected register class");
833  }
834 }
835 
836 unsigned getRegBitWidth(const MCRegisterClass &RC) {
837  return getRegBitWidth(RC.getID());
838 }
839 
840 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
841  unsigned OpNo) {
842  assert(OpNo < Desc.NumOperands);
843  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
844  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
845 }
846 
847 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
848  if (Literal >= -16 && Literal <= 64)
849  return true;
850 
851  uint64_t Val = static_cast<uint64_t>(Literal);
852  return (Val == DoubleToBits(0.0)) ||
853  (Val == DoubleToBits(1.0)) ||
854  (Val == DoubleToBits(-1.0)) ||
855  (Val == DoubleToBits(0.5)) ||
856  (Val == DoubleToBits(-0.5)) ||
857  (Val == DoubleToBits(2.0)) ||
858  (Val == DoubleToBits(-2.0)) ||
859  (Val == DoubleToBits(4.0)) ||
860  (Val == DoubleToBits(-4.0)) ||
861  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
862 }
863 
864 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
865  if (Literal >= -16 && Literal <= 64)
866  return true;
867 
868  // The actual type of the operand does not seem to matter as long
869  // as the bits match one of the inline immediate values. For example:
870  //
871  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
872  // so it is a legal inline immediate.
873  //
874  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
875  // floating-point, so it is a legal inline immediate.
876 
877  uint32_t Val = static_cast<uint32_t>(Literal);
878  return (Val == FloatToBits(0.0f)) ||
879  (Val == FloatToBits(1.0f)) ||
880  (Val == FloatToBits(-1.0f)) ||
881  (Val == FloatToBits(0.5f)) ||
882  (Val == FloatToBits(-0.5f)) ||
883  (Val == FloatToBits(2.0f)) ||
884  (Val == FloatToBits(-2.0f)) ||
885  (Val == FloatToBits(4.0f)) ||
886  (Val == FloatToBits(-4.0f)) ||
887  (Val == 0x3e22f983 && HasInv2Pi);
888 }
889 
890 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
891  if (!HasInv2Pi)
892  return false;
893 
894  if (Literal >= -16 && Literal <= 64)
895  return true;
896 
897  uint16_t Val = static_cast<uint16_t>(Literal);
898  return Val == 0x3C00 || // 1.0
899  Val == 0xBC00 || // -1.0
900  Val == 0x3800 || // 0.5
901  Val == 0xB800 || // -0.5
902  Val == 0x4000 || // 2.0
903  Val == 0xC000 || // -2.0
904  Val == 0x4400 || // 4.0
905  Val == 0xC400 || // -4.0
906  Val == 0x3118; // 1/2pi
907 }
908 
909 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
910  assert(HasInv2Pi);
911 
912  int16_t Lo16 = static_cast<int16_t>(Literal);
913  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
914  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
915 }
916 
917 bool isArgPassedInSGPR(const Argument *A) {
918  const Function *F = A->getParent();
919 
920  // Arguments to compute shaders are never a source of divergence.
922  switch (CC) {
925  return true;
933  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
934  // Everything else is in VGPRs.
935  return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
936  F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
937  default:
938  // TODO: Should calls support inreg for SGPR inputs?
939  return false;
940  }
941 }
942 
943 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
944  if (isGCN3Encoding(ST))
945  return ByteOffset;
946  return ByteOffset >> 2;
947 }
948 
949 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
950  int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
951  return isGCN3Encoding(ST) ?
952  isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
953 }
954 
955 // Given Imm, split it into the values to put into the SOffset and ImmOffset
956 // fields in an MUBUF instruction. Return false if it is not possible (due to a
957 // hardware bug needing a workaround).
958 //
959 // The required alignment ensures that individual address components remain
960 // aligned if they are aligned to begin with. It also ensures that additional
961 // offsets within the given alignment can be added to the resulting ImmOffset.
962 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
963  const GCNSubtarget *Subtarget, uint32_t Align) {
964  const uint32_t MaxImm = alignDown(4095, Align);
965  uint32_t Overflow = 0;
966 
967  if (Imm > MaxImm) {
968  if (Imm <= MaxImm + 64) {
969  // Use an SOffset inline constant for 4..64
970  Overflow = Imm - MaxImm;
971  Imm = MaxImm;
972  } else {
973  // Try to keep the same value in SOffset for adjacent loads, so that
974  // the corresponding register contents can be re-used.
975  //
976  // Load values with all low-bits (except for alignment bits) set into
977  // SOffset, so that a larger range of values can be covered using
978  // s_movk_i32.
979  //
980  // Atomic operations fail to work correctly when individual address
981  // components are unaligned, even if their sum is aligned.
982  uint32_t High = (Imm + Align) & ~4095;
983  uint32_t Low = (Imm + Align) & 4095;
984  Imm = Low;
985  Overflow = High - Align;
986  }
987  }
988 
989  // There is a hardware bug in SI and CI which prevents address clamping in
990  // MUBUF instructions from working correctly with SOffsets. The immediate
991  // offset is unaffected.
992  if (Overflow > 0 &&
994  return false;
995 
996  ImmOffset = Imm;
997  SOffset = Overflow;
998  return true;
999 }
1000 
1001 namespace {
1002 
1003 struct SourceOfDivergence {
1004  unsigned Intr;
1005 };
1006 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
1007 
1008 #define GET_SourcesOfDivergence_IMPL
1009 #include "AMDGPUGenSearchableTables.inc"
1010 
1011 } // end anonymous namespace
1012 
1013 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
1014  return lookupSourceOfDivergence(IntrID);
1015 }
1016 } // namespace AMDGPU
1017 } // namespace llvm
int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords)
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:251
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine...
bool hasPackedD16(const MCSubtargetInfo &STI)
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
bool getMUBUFHasSrsrc(unsigned Opc)
Address space for constant memory (VTX2).
Definition: AMDGPU.h:254
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getExpcntBitMask(const IsaVersion &Version)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:299
Represents the counter values to wait for in an s_waitcnt instruction.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Instruction set architecture version.
Definition: TargetParser.h:131
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
int getMUBUFDwords(unsigned Opc)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
uint64_t High
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
const Triple & getTargetTriple() const
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:136
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor()
unsigned getID() const
getID() - Return the register class ID number.
uint32_t amd_kernel_code_version_major
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:717
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
bool isStringAttribute() const
Return true if the attribute is a string (target-dependent) attribute.
Definition: Attributes.cpp:169
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
uint16_t amd_machine_version_major
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs)
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned Intr
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:78
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, uint32_t Align)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:290
uint8_t group_segment_alignment
bool isGroupSegment(const GlobalValue *GV)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
bool isReadOnlySegment(const GlobalValue *GV)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
uint16_t amd_machine_version_minor
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint32_t amd_kernel_code_version_minor
MCRegisterClass - Base class of TargetRegisterClass.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned short NumOperands
Definition: MCInstrDesc.h:166
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:600
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Address space for 32-bit constant memory.
Definition: AMDGPU.h:258
bool hasSRAMECC(const MCSubtargetInfo &STI)
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isCompute(CallingConv::ID cc)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
bool isSI(const MCSubtargetInfo &STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:342
unsigned const MachineRegisterInfo * MRI
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
bool getMUBUFHasSoffset(unsigned Opc)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
bool hasMIMG_R128(const MCSubtargetInfo &STI)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isEntryFunctionCC(CallingConv::ID CC)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
int getMUBUFBaseOpcode(unsigned Opc)
uint8_t private_segment_alignment
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
MCRegAliasIterator enumerates all registers aliasing Reg.
Generation getGeneration() const
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:526
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
#define AMDHSA_BITS_SET(DST, MSK, VAL)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Address space for local memory.
Definition: AMDGPU.h:255
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
IsaVersion getIsaVersion(StringRef GPU)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI)
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
bool hasParamAttribute(unsigned ArgNo, Attribute::AttrKind Kind) const
Equivalent to hasAttribute(ArgNo + FirstArgIndex, Kind).
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Module.h This file contains the declarations for the Module class.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
uint16_t amd_machine_version_stepping
uint8_t wavefront_size
Wavefront size expressed as a power of two.
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:220
bool isArgPassedInSGPR(const Argument *A)
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:590
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)
StringRef getCPU() const
bool isShader(CallingConv::ID cc)
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
Definition: Argument.h:47
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
bool isGCN3Encoding(const MCSubtargetInfo &STI)
#define MAP_REG2REG
bool isCI(const MCSubtargetInfo &STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getInitialPSInputAddr(const Function &F)
bool isGFX9(const MCSubtargetInfo &STI)
Provides AMDGPU specific target descriptions.
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:215
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:188
const Function * getParent() const
Definition: Argument.h:41
bool isVI(const MCSubtargetInfo &STI)
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
bool hasXNACK(const MCSubtargetInfo &STI)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
#define N
Generic base class for all target subtargets.
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool shouldEmitConstantsToTextSection(const Triple &TT)
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel&#39;s entry point instru...
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
uint16_t amd_machine_kind
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFHasVAddr(unsigned Opc)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
const uint64_t Version
Definition: InstrProf.h:904
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned getVmcntBitMask(const IsaVersion &Version)
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...