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AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPUBaseInfo.h"
11 #include "AMDGPU.h"
12 #include "SIDefines.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/BinaryFormat/ELF.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/IR/Instruction.h"
22 #include "llvm/IR/LLVMContext.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSectionELF.h"
31 #include "llvm/Support/Casting.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstdint>
37 #include <cstring>
38 #include <utility>
39 
41 
42 #define GET_INSTRINFO_NAMED_OPS
43 #define GET_INSTRMAP_INFO
44 #include "AMDGPUGenInstrInfo.inc"
45 #undef GET_INSTRMAP_INFO
46 #undef GET_INSTRINFO_NAMED_OPS
47 
48 namespace {
49 
50 /// \returns Bit mask for given bit \p Shift and bit \p Width.
51 unsigned getBitMask(unsigned Shift, unsigned Width) {
52  return ((1 << Width) - 1) << Shift;
53 }
54 
55 /// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
56 ///
57 /// \returns Packed \p Dst.
58 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
59  Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
60  Dst |= (Src << Shift) & getBitMask(Shift, Width);
61  return Dst;
62 }
63 
64 /// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
65 ///
66 /// \returns Unpacked bits.
67 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
68  return (Src & getBitMask(Shift, Width)) >> Shift;
69 }
70 
71 /// \returns Vmcnt bit shift (lower bits).
72 unsigned getVmcntBitShiftLo() { return 0; }
73 
74 /// \returns Vmcnt bit width (lower bits).
75 unsigned getVmcntBitWidthLo() { return 4; }
76 
77 /// \returns Expcnt bit shift.
78 unsigned getExpcntBitShift() { return 4; }
79 
80 /// \returns Expcnt bit width.
81 unsigned getExpcntBitWidth() { return 3; }
82 
83 /// \returns Lgkmcnt bit shift.
84 unsigned getLgkmcntBitShift() { return 8; }
85 
86 /// \returns Lgkmcnt bit width.
87 unsigned getLgkmcntBitWidth() { return 4; }
88 
89 /// \returns Vmcnt bit shift (higher bits).
90 unsigned getVmcntBitShiftHi() { return 14; }
91 
92 /// \returns Vmcnt bit width (higher bits).
93 unsigned getVmcntBitWidthHi() { return 2; }
94 
95 } // end namespace anonymous
96 
97 namespace llvm {
98 
99 static cl::opt<bool> EnablePackedInlinableLiterals(
100  "enable-packed-inlinable-literals",
101  cl::desc("Enable packed inlinable literals (v2f16, v2i16)"),
102  cl::init(false));
103 
104 namespace AMDGPU {
105 
107 static inline Channels indexToChannel(unsigned Channel) {
108  switch (Channel) {
109  case 1:
110  return AMDGPU::Channels_1;
111  case 2:
112  return AMDGPU::Channels_2;
113  case 3:
114  return AMDGPU::Channels_3;
115  case 4:
116  return AMDGPU::Channels_4;
117  default:
118  llvm_unreachable("invalid MIMG channel");
119  }
120 }
121 
122 
123 // FIXME: Need to handle d16 images correctly.
124 static unsigned rcToChannels(unsigned RCID) {
125  switch (RCID) {
126  case AMDGPU::VGPR_32RegClassID:
127  return 1;
128  case AMDGPU::VReg_64RegClassID:
129  return 2;
130  case AMDGPU::VReg_96RegClassID:
131  return 3;
132  case AMDGPU::VReg_128RegClassID:
133  return 4;
134  default:
135  llvm_unreachable("invalid MIMG register class");
136  }
137 }
138 
139 int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
140  AMDGPU::Channels Channel = AMDGPU::indexToChannel(NewChannels);
141  unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
142  if (NewChannels == OrigChannels)
143  return Opc;
144 
145  switch (OrigChannels) {
146  case 1:
147  return AMDGPU::getMaskedMIMGOp1(Opc, Channel);
148  case 2:
149  return AMDGPU::getMaskedMIMGOp2(Opc, Channel);
150  case 3:
151  return AMDGPU::getMaskedMIMGOp3(Opc, Channel);
152  case 4:
153  return AMDGPU::getMaskedMIMGOp4(Opc, Channel);
154  default:
155  llvm_unreachable("invalid MIMG channel");
156  }
157 }
158 
159 int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels) {
160  assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1);
161  assert(NewChannels == 1 || NewChannels == 2 || NewChannels == 4);
162 
163  unsigned OrigChannels = rcToChannels(MII.get(Opc).OpInfo[0].RegClass);
164  assert(OrigChannels == 1 || OrigChannels == 2 || OrigChannels == 4);
165 
166  if (NewChannels == OrigChannels) return Opc;
167 
168  if (OrigChannels <= 2 && NewChannels <= 2) {
169  // This is an ordinary atomic (not an atomic_cmpswap)
170  return (OrigChannels == 1)?
171  AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
172  } else if (OrigChannels >= 2 && NewChannels >= 2) {
173  // This is an atomic_cmpswap
174  return (OrigChannels == 2)?
175  AMDGPU::getMIMGAtomicOp1(Opc) : AMDGPU::getMIMGAtomicOp2(Opc);
176  } else { // invalid OrigChannels/NewChannels value
177  return -1;
178  }
179 }
180 
181 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
182 // header files, so we need to wrap it in a function that takes unsigned
183 // instead.
184 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
185  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
186 }
187 
188 namespace IsaInfo {
189 
191  // GCN GFX6 (Southern Islands (SI)).
192  if (Features.test(FeatureISAVersion6_0_0))
193  return {6, 0, 0};
194  if (Features.test(FeatureISAVersion6_0_1))
195  return {6, 0, 1};
196 
197  // GCN GFX7 (Sea Islands (CI)).
198  if (Features.test(FeatureISAVersion7_0_0))
199  return {7, 0, 0};
200  if (Features.test(FeatureISAVersion7_0_1))
201  return {7, 0, 1};
202  if (Features.test(FeatureISAVersion7_0_2))
203  return {7, 0, 2};
204  if (Features.test(FeatureISAVersion7_0_3))
205  return {7, 0, 3};
206  if (Features.test(FeatureISAVersion7_0_4))
207  return {7, 0, 4};
208 
209  // GCN GFX8 (Volcanic Islands (VI)).
210  if (Features.test(FeatureISAVersion8_0_1))
211  return {8, 0, 1};
212  if (Features.test(FeatureISAVersion8_0_2))
213  return {8, 0, 2};
214  if (Features.test(FeatureISAVersion8_0_3))
215  return {8, 0, 3};
216  if (Features.test(FeatureISAVersion8_1_0))
217  return {8, 1, 0};
218 
219  // GCN GFX9.
220  if (Features.test(FeatureISAVersion9_0_0))
221  return {9, 0, 0};
222  if (Features.test(FeatureISAVersion9_0_2))
223  return {9, 0, 2};
224 
225  if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
226  return {0, 0, 0};
227  return {7, 0, 0};
228 }
229 
230 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
231  auto TargetTriple = STI->getTargetTriple();
232  auto ISAVersion = IsaInfo::getIsaVersion(STI->getFeatureBits());
233 
234  Stream << TargetTriple.getArchName() << '-'
235  << TargetTriple.getVendorName() << '-'
236  << TargetTriple.getOSName() << '-'
237  << TargetTriple.getEnvironmentName() << '-'
238  << "gfx"
239  << ISAVersion.Major
240  << ISAVersion.Minor
241  << ISAVersion.Stepping;
242  Stream.flush();
243 }
244 
246  return Features.test(FeatureCodeObjectV3);
247 }
248 
250  if (Features.test(FeatureWavefrontSize16))
251  return 16;
252  if (Features.test(FeatureWavefrontSize32))
253  return 32;
254 
255  return 64;
256 }
257 
259  if (Features.test(FeatureLocalMemorySize32768))
260  return 32768;
261  if (Features.test(FeatureLocalMemorySize65536))
262  return 65536;
263 
264  return 0;
265 }
266 
268  return 4;
269 }
270 
272  unsigned FlatWorkGroupSize) {
273  if (!Features.test(FeatureGCN))
274  return 8;
275  unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
276  if (N == 1)
277  return 40;
278  N = 40 / N;
279  return std::min(N, 16u);
280 }
281 
283  return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
284 }
285 
287  unsigned FlatWorkGroupSize) {
288  return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
289 }
290 
292  return 1;
293 }
294 
296  if (!Features.test(FeatureGCN))
297  return 8;
298  // FIXME: Need to take scratch memory into account.
299  return 10;
300 }
301 
303  unsigned FlatWorkGroupSize) {
304  return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
305  getEUsPerCU(Features)) / getEUsPerCU(Features);
306 }
307 
309  return 1;
310 }
311 
313  return 2048;
314 }
315 
317  unsigned FlatWorkGroupSize) {
318  return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
319  getWavefrontSize(Features);
320 }
321 
323  IsaVersion Version = getIsaVersion(Features);
324  if (Version.Major >= 8)
325  return 16;
326  return 8;
327 }
328 
330  return 8;
331 }
332 
334  IsaVersion Version = getIsaVersion(Features);
335  if (Version.Major >= 8)
336  return 800;
337  return 512;
338 }
339 
341  if (Features.test(FeatureSGPRInitBug))
343 
344  IsaVersion Version = getIsaVersion(Features);
345  if (Version.Major >= 8)
346  return 102;
347  return 104;
348 }
349 
350 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
351  assert(WavesPerEU != 0);
352 
353  if (WavesPerEU >= getMaxWavesPerEU(Features))
354  return 0;
355  unsigned MinNumSGPRs =
356  alignDown(getTotalNumSGPRs(Features) / (WavesPerEU + 1),
357  getSGPRAllocGranule(Features)) + 1;
358  return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
359 }
360 
361 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
362  bool Addressable) {
363  assert(WavesPerEU != 0);
364 
365  IsaVersion Version = getIsaVersion(Features);
366  unsigned MaxNumSGPRs = alignDown(getTotalNumSGPRs(Features) / WavesPerEU,
367  getSGPRAllocGranule(Features));
368  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
369  if (Version.Major >= 8 && !Addressable)
370  AddressableNumSGPRs = 112;
371  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
372 }
373 
375  return 4;
376 }
377 
379  return getVGPRAllocGranule(Features);
380 }
381 
383  return 256;
384 }
385 
387  return getTotalNumVGPRs(Features);
388 }
389 
390 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
391  assert(WavesPerEU != 0);
392 
393  if (WavesPerEU >= getMaxWavesPerEU(Features))
394  return 0;
395  unsigned MinNumVGPRs =
396  alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
397  getVGPRAllocGranule(Features)) + 1;
398  return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
399 }
400 
401 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
402  assert(WavesPerEU != 0);
403 
404  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
405  getVGPRAllocGranule(Features));
406  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
407  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
408 }
409 
410 } // end namespace IsaInfo
411 
413  const FeatureBitset &Features) {
415 
416  memset(&Header, 0, sizeof(Header));
417 
420  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
421  Header.amd_machine_version_major = ISA.Major;
422  Header.amd_machine_version_minor = ISA.Minor;
424  Header.kernel_code_entry_byte_offset = sizeof(Header);
425  // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
426  Header.wavefront_size = 6;
427 
428  // If the code object does not support indirect functions, then the value must
429  // be 0xffffffff.
430  Header.call_convention = -1;
431 
432  // These alignment values are specified in powers of two, so alignment =
433  // 2^n. The minimum alignment is 2^4 = 16.
434  Header.kernarg_segment_alignment = 4;
435  Header.group_segment_alignment = 4;
436  Header.private_segment_alignment = 4;
437 }
438 
439 bool isGroupSegment(const GlobalValue *GV) {
441 }
442 
443 bool isGlobalSegment(const GlobalValue *GV) {
445 }
446 
450 }
451 
453  return TT.getOS() != Triple::AMDHSA;
454 }
455 
456 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
457  Attribute A = F.getFnAttribute(Name);
458  int Result = Default;
459 
460  if (A.isStringAttribute()) {
461  StringRef Str = A.getValueAsString();
462  if (Str.getAsInteger(0, Result)) {
463  LLVMContext &Ctx = F.getContext();
464  Ctx.emitError("can't parse integer attribute " + Name);
465  }
466  }
467 
468  return Result;
469 }
470 
471 std::pair<int, int> getIntegerPairAttribute(const Function &F,
472  StringRef Name,
473  std::pair<int, int> Default,
474  bool OnlyFirstRequired) {
475  Attribute A = F.getFnAttribute(Name);
476  if (!A.isStringAttribute())
477  return Default;
478 
479  LLVMContext &Ctx = F.getContext();
480  std::pair<int, int> Ints = Default;
481  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
482  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
483  Ctx.emitError("can't parse first integer attribute " + Name);
484  return Default;
485  }
486  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
487  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
488  Ctx.emitError("can't parse second integer attribute " + Name);
489  return Default;
490  }
491  }
492 
493  return Ints;
494 }
495 
497  unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
498  if (Version.Major < 9)
499  return VmcntLo;
500 
501  unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
502  return VmcntLo | VmcntHi;
503 }
504 
506  return (1 << getExpcntBitWidth()) - 1;
507 }
508 
510  return (1 << getLgkmcntBitWidth()) - 1;
511 }
512 
514  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
515  unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
516  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
517  unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
518  if (Version.Major < 9)
519  return Waitcnt;
520 
521  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
522  return Waitcnt | VmcntHi;
523 }
524 
525 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
526  unsigned VmcntLo =
527  unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
528  if (Version.Major < 9)
529  return VmcntLo;
530 
531  unsigned VmcntHi =
532  unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
533  VmcntHi <<= getVmcntBitWidthLo();
534  return VmcntLo | VmcntHi;
535 }
536 
537 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
538  return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
539 }
540 
541 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
542  return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
543 }
544 
545 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
546  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
547  Vmcnt = decodeVmcnt(Version, Waitcnt);
548  Expcnt = decodeExpcnt(Version, Waitcnt);
549  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
550 }
551 
552 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
553  unsigned Vmcnt) {
554  Waitcnt =
555  packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
556  if (Version.Major < 9)
557  return Waitcnt;
558 
559  Vmcnt >>= getVmcntBitWidthLo();
560  return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
561 }
562 
563 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
564  unsigned Expcnt) {
565  return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
566 }
567 
568 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
569  unsigned Lgkmcnt) {
570  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
571 }
572 
574  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
575  unsigned Waitcnt = getWaitcntBitMask(Version);
576  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
577  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
578  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
579  return Waitcnt;
580 }
581 
582 unsigned getInitialPSInputAddr(const Function &F) {
583  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
584 }
585 
587  switch(cc) {
595  return true;
596  default:
597  return false;
598  }
599 }
600 
602  return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
603 }
604 
606  switch (CC) {
616  return true;
617  default:
618  return false;
619  }
620 }
621 
622 bool hasXNACK(const MCSubtargetInfo &STI) {
623  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
624 }
625 
626 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
627  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
628 }
629 
630 bool hasPackedD16(const MCSubtargetInfo &STI) {
631  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
632 }
633 
634 bool isSI(const MCSubtargetInfo &STI) {
635  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
636 }
637 
638 bool isCI(const MCSubtargetInfo &STI) {
639  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
640 }
641 
642 bool isVI(const MCSubtargetInfo &STI) {
643  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
644 }
645 
646 bool isGFX9(const MCSubtargetInfo &STI) {
647  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
648 }
649 
650 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
651  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
652 }
653 
654 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
655  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
656  const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
657  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
658  Reg == AMDGPU::SCC;
659 }
660 
661 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
662  for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
663  if (*R == Reg1) return true;
664  }
665  return false;
666 }
667 
668 #define MAP_REG2REG \
669  using namespace AMDGPU; \
670  switch(Reg) { \
671  default: return Reg; \
672  CASE_CI_VI(FLAT_SCR) \
673  CASE_CI_VI(FLAT_SCR_LO) \
674  CASE_CI_VI(FLAT_SCR_HI) \
675  CASE_VI_GFX9(TTMP0) \
676  CASE_VI_GFX9(TTMP1) \
677  CASE_VI_GFX9(TTMP2) \
678  CASE_VI_GFX9(TTMP3) \
679  CASE_VI_GFX9(TTMP4) \
680  CASE_VI_GFX9(TTMP5) \
681  CASE_VI_GFX9(TTMP6) \
682  CASE_VI_GFX9(TTMP7) \
683  CASE_VI_GFX9(TTMP8) \
684  CASE_VI_GFX9(TTMP9) \
685  CASE_VI_GFX9(TTMP10) \
686  CASE_VI_GFX9(TTMP11) \
687  CASE_VI_GFX9(TTMP12) \
688  CASE_VI_GFX9(TTMP13) \
689  CASE_VI_GFX9(TTMP14) \
690  CASE_VI_GFX9(TTMP15) \
691  CASE_VI_GFX9(TTMP0_TTMP1) \
692  CASE_VI_GFX9(TTMP2_TTMP3) \
693  CASE_VI_GFX9(TTMP4_TTMP5) \
694  CASE_VI_GFX9(TTMP6_TTMP7) \
695  CASE_VI_GFX9(TTMP8_TTMP9) \
696  CASE_VI_GFX9(TTMP10_TTMP11) \
697  CASE_VI_GFX9(TTMP12_TTMP13) \
698  CASE_VI_GFX9(TTMP14_TTMP15) \
699  CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
700  CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
701  CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
702  CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
703  CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
704  CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
705  CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
706  CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
707  }
708 
709 #define CASE_CI_VI(node) \
710  assert(!isSI(STI)); \
711  case node: return isCI(STI) ? node##_ci : node##_vi;
712 
713 #define CASE_VI_GFX9(node) \
714  case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
715 
716 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
718 }
719 
720 #undef CASE_CI_VI
721 #undef CASE_VI_GFX9
722 
723 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
724 #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
725 
726 unsigned mc2PseudoReg(unsigned Reg) {
728 }
729 
730 #undef CASE_CI_VI
731 #undef CASE_VI_GFX9
732 #undef MAP_REG2REG
733 
734 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
735  assert(OpNo < Desc.NumOperands);
736  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
737  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
738  OpType <= AMDGPU::OPERAND_SRC_LAST;
739 }
740 
741 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
742  assert(OpNo < Desc.NumOperands);
743  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
744  switch (OpType) {
752  return true;
753  default:
754  return false;
755  }
756 }
757 
758 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
759  assert(OpNo < Desc.NumOperands);
760  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
761  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
763 }
764 
765 // Avoid using MCRegisterClass::getSize, since that function will go away
766 // (move from MC* level to Target* level). Return size in bits.
767 unsigned getRegBitWidth(unsigned RCID) {
768  switch (RCID) {
769  case AMDGPU::SGPR_32RegClassID:
770  case AMDGPU::VGPR_32RegClassID:
771  case AMDGPU::VS_32RegClassID:
772  case AMDGPU::SReg_32RegClassID:
773  case AMDGPU::SReg_32_XM0RegClassID:
774  return 32;
775  case AMDGPU::SGPR_64RegClassID:
776  case AMDGPU::VS_64RegClassID:
777  case AMDGPU::SReg_64RegClassID:
778  case AMDGPU::VReg_64RegClassID:
779  return 64;
780  case AMDGPU::VReg_96RegClassID:
781  return 96;
782  case AMDGPU::SGPR_128RegClassID:
783  case AMDGPU::SReg_128RegClassID:
784  case AMDGPU::VReg_128RegClassID:
785  return 128;
786  case AMDGPU::SReg_256RegClassID:
787  case AMDGPU::VReg_256RegClassID:
788  return 256;
789  case AMDGPU::SReg_512RegClassID:
790  case AMDGPU::VReg_512RegClassID:
791  return 512;
792  default:
793  llvm_unreachable("Unexpected register class");
794  }
795 }
796 
797 unsigned getRegBitWidth(const MCRegisterClass &RC) {
798  return getRegBitWidth(RC.getID());
799 }
800 
801 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
802  unsigned OpNo) {
803  assert(OpNo < Desc.NumOperands);
804  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
805  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
806 }
807 
808 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
809  if (Literal >= -16 && Literal <= 64)
810  return true;
811 
812  uint64_t Val = static_cast<uint64_t>(Literal);
813  return (Val == DoubleToBits(0.0)) ||
814  (Val == DoubleToBits(1.0)) ||
815  (Val == DoubleToBits(-1.0)) ||
816  (Val == DoubleToBits(0.5)) ||
817  (Val == DoubleToBits(-0.5)) ||
818  (Val == DoubleToBits(2.0)) ||
819  (Val == DoubleToBits(-2.0)) ||
820  (Val == DoubleToBits(4.0)) ||
821  (Val == DoubleToBits(-4.0)) ||
822  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
823 }
824 
825 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
826  if (Literal >= -16 && Literal <= 64)
827  return true;
828 
829  // The actual type of the operand does not seem to matter as long
830  // as the bits match one of the inline immediate values. For example:
831  //
832  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
833  // so it is a legal inline immediate.
834  //
835  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
836  // floating-point, so it is a legal inline immediate.
837 
838  uint32_t Val = static_cast<uint32_t>(Literal);
839  return (Val == FloatToBits(0.0f)) ||
840  (Val == FloatToBits(1.0f)) ||
841  (Val == FloatToBits(-1.0f)) ||
842  (Val == FloatToBits(0.5f)) ||
843  (Val == FloatToBits(-0.5f)) ||
844  (Val == FloatToBits(2.0f)) ||
845  (Val == FloatToBits(-2.0f)) ||
846  (Val == FloatToBits(4.0f)) ||
847  (Val == FloatToBits(-4.0f)) ||
848  (Val == 0x3e22f983 && HasInv2Pi);
849 }
850 
851 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
852  if (!HasInv2Pi)
853  return false;
854 
855  if (Literal >= -16 && Literal <= 64)
856  return true;
857 
858  uint16_t Val = static_cast<uint16_t>(Literal);
859  return Val == 0x3C00 || // 1.0
860  Val == 0xBC00 || // -1.0
861  Val == 0x3800 || // 0.5
862  Val == 0xB800 || // -0.5
863  Val == 0x4000 || // 2.0
864  Val == 0xC000 || // -2.0
865  Val == 0x4400 || // 4.0
866  Val == 0xC400 || // -4.0
867  Val == 0x3118; // 1/2pi
868 }
869 
870 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
871  assert(HasInv2Pi);
872 
873  if (!EnablePackedInlinableLiterals)
874  return false;
875 
876  int16_t Lo16 = static_cast<int16_t>(Literal);
877  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
878  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
879 }
880 
881 bool isArgPassedInSGPR(const Argument *A) {
882  const Function *F = A->getParent();
883 
884  // Arguments to compute shaders are never a source of divergence.
886  switch (CC) {
889  return true;
897  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
898  // Everything else is in VGPRs.
899  return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
900  F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
901  default:
902  // TODO: Should calls support inreg for SGPR inputs?
903  return false;
904  }
905 }
906 
907 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
908  if (isGCN3Encoding(ST))
909  return ByteOffset;
910  return ByteOffset >> 2;
911 }
912 
913 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
914  int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
915  return isGCN3Encoding(ST) ?
916  isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
917 }
918 
919 } // end namespace AMDGPU
920 
921 } // end namespace llvm
922 
923 namespace llvm {
924 namespace AMDGPU {
925 
927  AMDGPUAS AS;
928  AS.FLAT_ADDRESS = 0;
929  AS.PRIVATE_ADDRESS = 5;
930  AS.REGION_ADDRESS = 2;
931  return AS;
932 }
933 
935  return getAMDGPUAS(M.getTargetTriple());
936 }
937 
939  return getAMDGPUAS(Triple(M.getTargetTriple()));
940 }
941 } // namespace AMDGPU
942 } // namespace llvm
unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU)
Address space for 32-bit constant memory.
Definition: AMDGPU.h:228
const std::string & getTargetTriple() const
Get the target triple which is a string describing the target host.
Definition: Module.h:233
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getAddressableNumVGPRs(const FeatureBitset &Features)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:294
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:189
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features, unsigned FlatWorkGroupSize)
AMDGPUAS getAMDGPUAS(const Module &M)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
F(f)
unsigned getTotalNumVGPRs(const FeatureBitset &Features)
unsigned getMinWavesPerEU(const FeatureBitset &Features)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:677
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:137
unsigned getWavesPerWorkGroup(const FeatureBitset &Features, unsigned FlatWorkGroupSize)
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
unsigned getVGPREncodingGranule(const FeatureBitset &Features)
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
unsigned getID() const
getID() - Return the register class ID number.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
uint32_t amd_kernel_code_version_major
unsigned getEUsPerCU(const FeatureBitset &Features)
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:710
unsigned getWavefrontSize(const FeatureBitset &Features)
Address space for local memory.
Definition: AMDGPU.h:226
unsigned getVGPRAllocGranule(const FeatureBitset &Features)
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
bool isStringAttribute() const
Return true if the attribute is a string (target-dependent) attribute.
Definition: Attributes.cpp:170
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:214
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
uint16_t amd_machine_version_major
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features)
bool hasCodeObjectV3(const FeatureBitset &Features)
unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Calling convention used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
unsigned getMaxWavesPerCU(const FeatureBitset &Features)
unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU, bool Addressable)
unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
uint8_t group_segment_alignment
bool isGroupSegment(const GlobalValue *GV)
static LLVM_READNONE Channels indexToChannel(unsigned Channel)
unsigned getMaxWavesPerEU(const FeatureBitset &Features)
bool isReadOnlySegment(const GlobalValue *GV)
static cl::opt< bool > EnablePackedInlinableLiterals("enable-packed-inlinable-literals", cl::desc("Enable packed inlinable literals (v2f16, v2i16)"), cl::init(false))
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
uint16_t amd_machine_version_minor
unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features)
uint32_t amd_kernel_code_version_minor
MCRegisterClass - Base class of TargetRegisterClass.
unsigned short NumOperands
Definition: MCInstrDesc.h:166
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:593
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isCompute(CallingConv::ID cc)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:335
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
unsigned getTotalNumSGPRs(const FeatureBitset &Features)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isEntryFunctionCC(CallingConv::ID CC)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU)
uint8_t private_segment_alignment
MCRegAliasIterator enumerates all registers aliasing Reg.
Instruction set architecture version.
const Triple & getTargetTriple() const
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:495
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned REGION_ADDRESS
Address space for region memory.
Definition: AMDGPU.h:218
const AMDGPUAS & AS
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
Address space for constant memory (VTX2)
Definition: AMDGPU.h:225
unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version)
bool hasParamAttribute(unsigned ArgNo, Attribute::AttrKind Kind) const
Equivalent to hasAttribute(ArgNo + FirstArgIndex, Kind).
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
Module.h This file contains the declarations for the Module class.
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use...
Definition: CallingConv.h:221
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:208
static unsigned rcToChannels(unsigned RCID)
uint16_t amd_machine_version_stepping
unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version)
uint8_t wavefront_size
Wavefront size expressed as a power of two.
bool isArgPassedInSGPR(const Argument *A)
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:583
unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
bool isShader(CallingConv::ID cc)
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
Definition: Argument.h:48
bool isGCN3Encoding(const MCSubtargetInfo &STI)
#define MAP_REG2REG
bool isCI(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
bool isGFX9(const MCSubtargetInfo &STI)
Provides AMDGPU specific target descriptions.
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
const Function * getParent() const
Definition: Argument.h:42
bool isVI(const MCSubtargetInfo &STI)
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
Calling convention used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:216
unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
bool hasXNACK(const MCSubtargetInfo &STI)
unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define LLVM_READNONE
Definition: Compiler.h:161
unsigned FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:217
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
#define N
MCSubtargetInfo - Generic base class for all target subtargets.
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:224
bool shouldEmitConstantsToTextSection(const Triple &TT)
unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version)
unsigned getAddressableNumSGPRs(const FeatureBitset &Features)
unsigned getSGPREncodingGranule(const FeatureBitset &Features)
int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel&#39;s entry point instru...
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const FeatureBitset Features
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:312
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
uint16_t amd_machine_kind
unsigned getSGPRAllocGranule(const FeatureBitset &Features)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:201
unsigned getLocalMemorySize(const FeatureBitset &Features)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU)
const uint64_t Version
Definition: InstrProf.h:867
IsaVersion getIsaVersion(const FeatureBitset &Features)
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
unsigned PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:216
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.