LLVM  6.0.0svn
Classes | Namespaces | Enumerations | Functions
AMDGPUBaseInfo.h File Reference
#include "AMDGPU.h"
#include "AMDKernelCodeT.h"
#include "SIDefines.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include <cstdint>
#include <string>
#include <utility>
Include dependency graph for AMDGPUBaseInfo.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  llvm::AMDGPU::IsaInfo::IsaVersion
 Instruction set architecture version. More...
 

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::AMDGPU
 
 llvm::AMDGPU::IsaInfo
 

Enumerations

enum  { llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG = 96 }
 

Functions

IsaVersion llvm::AMDGPU::IsaInfo::getIsaVersion (const FeatureBitset &Features)
 
void llvm::AMDGPU::IsaInfo::streamIsaVersion (const MCSubtargetInfo *STI, raw_ostream &Stream)
 Streams isa version string for given subtarget STI into Stream. More...
 
bool llvm::AMDGPU::IsaInfo::hasCodeObjectV3 (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerCU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerCU (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const FeatureBitset &Features, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const FeatureBitset &Features, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const FeatureBitset &Features, unsigned WavesPerEU, bool Addressable)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const FeatureBitset &Features)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const FeatureBitset &Features, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const FeatureBitset &Features, unsigned WavesPerEU)
 
LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
int llvm::AMDGPU::getMaskedMIMGOp (const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
 
int llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)
 
void llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features)
 
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
 
int llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned llvm::AMDGPU::getVmcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::getExpcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::getLgkmcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::getWaitcntBitMask (const IsaInfo::IsaVersion &Version)
 
unsigned llvm::AMDGPU::decodeVmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeExpcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeLgkmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
 
void llvm::AMDGPU::decodeWaitcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
unsigned llvm::AMDGPU::encodeVmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned llvm::AMDGPU::encodeExpcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned llvm::AMDGPU::encodeLgkmcnt (const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaInfo::IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
 
bool llvm::AMDGPU::isShader (CallingConv::ID cc)
 
bool llvm::AMDGPU::isCompute (CallingConv::ID cc)
 
bool llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)
 
LLVM_READNONE bool llvm::AMDGPU::isKernel (CallingConv::ID CC)
 
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool llvm::AMDGPU::isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned llvm::AMDGPU::mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)
 
bool llvm::AMDGPU::isUniformMMO (const MachineMemOperand *MMO)
 
int64_t llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool llvm::AMDGPU::isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)