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AMDGPUDisassembler.cpp
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1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //===----------------------------------------------------------------------===//
11 //
12 /// \file
13 ///
14 /// This file contains definition for AMDGPU ISA disassembler
15 //
16 //===----------------------------------------------------------------------===//
17 
18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
19 
21 #include "AMDGPU.h"
22 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Endian.h"
41 #include <algorithm>
42 #include <cassert>
43 #include <cstddef>
44 #include <cstdint>
45 #include <iterator>
46 #include <tuple>
47 #include <vector>
48 
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "amdgpu-disassembler"
52 
54 
55 inline static MCDisassembler::DecodeStatus
56 addOperand(MCInst &Inst, const MCOperand& Opnd) {
57  Inst.addOperand(Opnd);
58  return Opnd.isValid() ?
61 }
62 
64  uint16_t NameIdx) {
65  int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
66  if (OpIdx != -1) {
67  auto I = MI.begin();
68  std::advance(I, OpIdx);
69  MI.insert(I, Op);
70  }
71  return OpIdx;
72 }
73 
74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
75  uint64_t Addr, const void *Decoder) {
76  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
77 
78  APInt SignedOffset(18, Imm * 4, true);
79  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
80 
81  if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
83  return addOperand(Inst, MCOperand::createImm(Imm));
84 }
85 
86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
87 static DecodeStatus StaticDecoderName(MCInst &Inst, \
88  unsigned Imm, \
89  uint64_t /*Addr*/, \
90  const void *Decoder) { \
91  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
92  return addOperand(Inst, DAsm->DecoderName(Imm)); \
93 }
94 
95 #define DECODE_OPERAND_REG(RegClass) \
96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
97 
98 DECODE_OPERAND_REG(VGPR_32)
99 DECODE_OPERAND_REG(VS_32)
100 DECODE_OPERAND_REG(VS_64)
101 DECODE_OPERAND_REG(VS_128)
102 
103 DECODE_OPERAND_REG(VReg_64)
104 DECODE_OPERAND_REG(VReg_96)
105 DECODE_OPERAND_REG(VReg_128)
106 
107 DECODE_OPERAND_REG(SReg_32)
108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
110 DECODE_OPERAND_REG(SReg_64)
111 DECODE_OPERAND_REG(SReg_64_XEXEC)
112 DECODE_OPERAND_REG(SReg_128)
113 DECODE_OPERAND_REG(SReg_256)
114 DECODE_OPERAND_REG(SReg_512)
115 
117  unsigned Imm,
118  uint64_t Addr,
119  const void *Decoder) {
120  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
121  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
122 }
123 
125  unsigned Imm,
126  uint64_t Addr,
127  const void *Decoder) {
128  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
129  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
130 }
131 
132 #define DECODE_SDWA(DecName) \
133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
134 
135 DECODE_SDWA(Src32)
136 DECODE_SDWA(Src16)
137 DECODE_SDWA(VopcDst)
138 
139 #include "AMDGPUGenDisassemblerTables.inc"
140 
141 //===----------------------------------------------------------------------===//
142 //
143 //===----------------------------------------------------------------------===//
144 
145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
146  assert(Bytes.size() >= sizeof(T));
147  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
148  Bytes = Bytes.slice(sizeof(T));
149  return Res;
150 }
151 
153  MCInst &MI,
154  uint64_t Inst,
155  uint64_t Address) const {
156  assert(MI.getOpcode() == 0);
157  assert(MI.getNumOperands() == 0);
158  MCInst TmpInst;
159  HasLiteral = false;
160  const auto SavedBytes = Bytes;
161  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
162  MI = TmpInst;
164  }
165  Bytes = SavedBytes;
166  return MCDisassembler::Fail;
167 }
168 
170  ArrayRef<uint8_t> Bytes_,
171  uint64_t Address,
172  raw_ostream &WS,
173  raw_ostream &CS) const {
174  CommentStream = &CS;
175  bool IsSDWA = false;
176 
177  // ToDo: AMDGPUDisassembler supports only VI ISA.
178  if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding])
179  report_fatal_error("Disassembly not yet supported for subtarget");
180 
181  const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
182  Bytes = Bytes_.slice(0, MaxInstBytesNum);
183 
185  do {
186  // ToDo: better to switch encoding length using some bit predicate
187  // but it is unknown yet, so try all we can
188 
189  // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
190  // encodings
191  if (Bytes.size() >= 8) {
192  const uint64_t QW = eatBytes<uint64_t>(Bytes);
193  Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
194  if (Res) break;
195 
196  Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
197  if (Res) { IsSDWA = true; break; }
198 
199  Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
200  if (Res) { IsSDWA = true; break; }
201  }
202 
203  // Reinitialize Bytes as DPP64 could have eaten too much
204  Bytes = Bytes_.slice(0, MaxInstBytesNum);
205 
206  // Try decode 32-bit instruction
207  if (Bytes.size() < 4) break;
208  const uint32_t DW = eatBytes<uint32_t>(Bytes);
209  Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
210  if (Res) break;
211 
212  Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
213  if (Res) break;
214 
215  Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
216  if (Res) break;
217 
218  if (Bytes.size() < 4) break;
219  const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
220  Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
221  if (Res) break;
222 
223  Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
224  if (Res) break;
225 
226  Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
227  } while (false);
228 
229  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
230  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
231  MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {
232  // Insert dummy unused src2_modifiers.
234  AMDGPU::OpName::src2_modifiers);
235  }
236 
237  if (Res && IsSDWA)
238  Res = convertSDWAInst(MI);
239 
240  Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
241  return Res;
242 }
243 
245  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
246  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
247  // VOPC - insert clamp
248  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
249  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
250  int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
251  if (SDst != -1) {
252  // VOPC - insert VCC register as sdst
254  AMDGPU::OpName::sdst);
255  } else {
256  // VOP1/2 - insert omod if present in instruction
257  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
258  }
259  }
261 }
262 
263 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
264  return getContext().getRegisterInfo()->
265  getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
266 }
267 
268 inline
270  const Twine& ErrMsg) const {
271  *CommentStream << "Error: " + ErrMsg;
272 
273  // ToDo: add support for error operands to MCInst.h
274  // return MCOperand::createError(V);
275  return MCOperand();
276 }
277 
278 inline
280  return MCOperand::createReg(RegId);
281 }
282 
283 inline
285  unsigned Val) const {
286  const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
287  if (Val >= RegCl.getNumRegs())
288  return errOperand(Val, Twine(getRegClassName(RegClassID)) +
289  ": unknown register " + Twine(Val));
290  return createRegOperand(RegCl.getRegister(Val));
291 }
292 
293 inline
295  unsigned Val) const {
296  // ToDo: SI/CI have 104 SGPRs, VI - 102
297  // Valery: here we accepting as much as we can, let assembler sort it out
298  int shift = 0;
299  switch (SRegClassID) {
300  case AMDGPU::SGPR_32RegClassID:
301  case AMDGPU::TTMP_32RegClassID:
302  break;
303  case AMDGPU::SGPR_64RegClassID:
304  case AMDGPU::TTMP_64RegClassID:
305  shift = 1;
306  break;
307  case AMDGPU::SGPR_128RegClassID:
308  case AMDGPU::TTMP_128RegClassID:
309  // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
310  // this bundle?
311  case AMDGPU::SReg_256RegClassID:
312  // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
313  // this bundle?
314  case AMDGPU::SReg_512RegClassID:
315  shift = 2;
316  break;
317  // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
318  // this bundle?
319  default:
320  llvm_unreachable("unhandled register class");
321  }
322 
323  if (Val % (1 << shift)) {
324  *CommentStream << "Warning: " << getRegClassName(SRegClassID)
325  << ": scalar reg isn't aligned " << Val;
326  }
327 
328  return createRegOperand(SRegClassID, Val >> shift);
329 }
330 
332  return decodeSrcOp(OPW32, Val);
333 }
334 
336  return decodeSrcOp(OPW64, Val);
337 }
338 
340  return decodeSrcOp(OPW128, Val);
341 }
342 
344  return decodeSrcOp(OPW16, Val);
345 }
346 
348  return decodeSrcOp(OPWV216, Val);
349 }
350 
352  // Some instructions have operand restrictions beyond what the encoding
353  // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
354  // high bit.
355  Val &= 255;
356 
357  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
358 }
359 
361  return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
362 }
363 
365  return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
366 }
367 
369  return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
370 }
371 
373  // table-gen generated disassembler doesn't care about operand types
374  // leaving only registry class so SSrc_32 operand turns into SReg_32
375  // and therefore we accept immediates and literals here as well
376  return decodeSrcOp(OPW32, Val);
377 }
378 
380  unsigned Val) const {
381  // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
382  return decodeOperand_SReg_32(Val);
383 }
384 
386  unsigned Val) const {
387  // SReg_32_XM0 is SReg_32 without EXEC_HI
388  return decodeOperand_SReg_32(Val);
389 }
390 
392  return decodeSrcOp(OPW64, Val);
393 }
394 
396  return decodeSrcOp(OPW64, Val);
397 }
398 
400  return decodeSrcOp(OPW128, Val);
401 }
402 
404  return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
405 }
406 
408  return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
409 }
410 
412  // For now all literal constants are supposed to be unsigned integer
413  // ToDo: deal with signed/unsigned 64-bit integer constants
414  // ToDo: deal with float/double constants
415  if (!HasLiteral) {
416  if (Bytes.size() < 4) {
417  return errOperand(0, "cannot read literal, inst bytes left " +
418  Twine(Bytes.size()));
419  }
420  HasLiteral = true;
421  Literal = eatBytes<uint32_t>(Bytes);
422  }
423  return MCOperand::createImm(Literal);
424 }
425 
427  using namespace AMDGPU::EncValues;
428 
431  (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
432  (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
433  // Cast prevents negative overflow.
434 }
435 
436 static int64_t getInlineImmVal32(unsigned Imm) {
437  switch (Imm) {
438  case 240:
439  return FloatToBits(0.5f);
440  case 241:
441  return FloatToBits(-0.5f);
442  case 242:
443  return FloatToBits(1.0f);
444  case 243:
445  return FloatToBits(-1.0f);
446  case 244:
447  return FloatToBits(2.0f);
448  case 245:
449  return FloatToBits(-2.0f);
450  case 246:
451  return FloatToBits(4.0f);
452  case 247:
453  return FloatToBits(-4.0f);
454  case 248: // 1 / (2 * PI)
455  return 0x3e22f983;
456  default:
457  llvm_unreachable("invalid fp inline imm");
458  }
459 }
460 
461 static int64_t getInlineImmVal64(unsigned Imm) {
462  switch (Imm) {
463  case 240:
464  return DoubleToBits(0.5);
465  case 241:
466  return DoubleToBits(-0.5);
467  case 242:
468  return DoubleToBits(1.0);
469  case 243:
470  return DoubleToBits(-1.0);
471  case 244:
472  return DoubleToBits(2.0);
473  case 245:
474  return DoubleToBits(-2.0);
475  case 246:
476  return DoubleToBits(4.0);
477  case 247:
478  return DoubleToBits(-4.0);
479  case 248: // 1 / (2 * PI)
480  return 0x3fc45f306dc9c882;
481  default:
482  llvm_unreachable("invalid fp inline imm");
483  }
484 }
485 
486 static int64_t getInlineImmVal16(unsigned Imm) {
487  switch (Imm) {
488  case 240:
489  return 0x3800;
490  case 241:
491  return 0xB800;
492  case 242:
493  return 0x3C00;
494  case 243:
495  return 0xBC00;
496  case 244:
497  return 0x4000;
498  case 245:
499  return 0xC000;
500  case 246:
501  return 0x4400;
502  case 247:
503  return 0xC400;
504  case 248: // 1 / (2 * PI)
505  return 0x3118;
506  default:
507  llvm_unreachable("invalid fp inline imm");
508  }
509 }
510 
514 
515  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
516  switch (Width) {
517  case OPW32:
519  case OPW64:
521  case OPW16:
522  case OPWV216:
524  default:
525  llvm_unreachable("implement me");
526  }
527 }
528 
529 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
530  using namespace AMDGPU;
531 
532  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
533  switch (Width) {
534  default: // fall
535  case OPW32:
536  case OPW16:
537  case OPWV216:
538  return VGPR_32RegClassID;
539  case OPW64: return VReg_64RegClassID;
540  case OPW128: return VReg_128RegClassID;
541  }
542 }
543 
544 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
545  using namespace AMDGPU;
546 
547  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
548  switch (Width) {
549  default: // fall
550  case OPW32:
551  case OPW16:
552  case OPWV216:
553  return SGPR_32RegClassID;
554  case OPW64: return SGPR_64RegClassID;
555  case OPW128: return SGPR_128RegClassID;
556  }
557 }
558 
559 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
560  using namespace AMDGPU;
561 
562  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
563  switch (Width) {
564  default: // fall
565  case OPW32:
566  case OPW16:
567  case OPWV216:
568  return TTMP_32RegClassID;
569  case OPW64: return TTMP_64RegClassID;
570  case OPW128: return TTMP_128RegClassID;
571  }
572 }
573 
574 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
575  using namespace AMDGPU::EncValues;
576 
577  assert(Val < 512); // enum9
578 
579  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
580  return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
581  }
582  if (Val <= SGPR_MAX) {
583  assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
584  return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
585  }
586  if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
587  return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
588  }
589 
590  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
591  return decodeIntImmed(Val);
592 
593  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
594  return decodeFPImmed(Width, Val);
595 
596  if (Val == LITERAL_CONST)
597  return decodeLiteralConstant();
598 
599  switch (Width) {
600  case OPW32:
601  case OPW16:
602  case OPWV216:
603  return decodeSpecialReg32(Val);
604  case OPW64:
605  return decodeSpecialReg64(Val);
606  default:
607  llvm_unreachable("unexpected immediate type");
608  }
609 }
610 
612  using namespace AMDGPU;
613 
614  switch (Val) {
615  case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
616  case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
617  // ToDo: no support for xnack_mask_lo/_hi register
618  case 104:
619  case 105: break;
620  case 106: return createRegOperand(VCC_LO);
621  case 107: return createRegOperand(VCC_HI);
622  case 108: return createRegOperand(TBA_LO);
623  case 109: return createRegOperand(TBA_HI);
624  case 110: return createRegOperand(TMA_LO);
625  case 111: return createRegOperand(TMA_HI);
626  case 124: return createRegOperand(M0);
627  case 126: return createRegOperand(EXEC_LO);
628  case 127: return createRegOperand(EXEC_HI);
629  case 235: return createRegOperand(SRC_SHARED_BASE);
630  case 236: return createRegOperand(SRC_SHARED_LIMIT);
631  case 237: return createRegOperand(SRC_PRIVATE_BASE);
632  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
633  // TODO: SRC_POPS_EXITING_WAVE_ID
634  // ToDo: no support for vccz register
635  case 251: break;
636  // ToDo: no support for execz register
637  case 252: break;
638  case 253: return createRegOperand(SCC);
639  default: break;
640  }
641  return errOperand(Val, "unknown operand encoding " + Twine(Val));
642 }
643 
645  using namespace AMDGPU;
646 
647  switch (Val) {
648  case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
649  case 106: return createRegOperand(VCC);
650  case 108: return createRegOperand(TBA);
651  case 110: return createRegOperand(TMA);
652  case 126: return createRegOperand(EXEC);
653  default: break;
654  }
655  return errOperand(Val, "unknown operand encoding " + Twine(Val));
656 }
657 
659  unsigned Val) const {
660  using namespace AMDGPU::SDWA;
661 
662  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
663  // XXX: static_cast<int> is needed to avoid stupid warning:
664  // compare with unsigned is always true
665  if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) &&
667  return createRegOperand(getVgprClassId(Width),
669  }
670  if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
672  return createSRegOperand(getSgprClassId(Width),
674  }
675 
677  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
678  return createRegOperand(getVgprClassId(Width), Val);
679  }
680  llvm_unreachable("unsupported target");
681 }
682 
684  return decodeSDWASrc(OPW16, Val);
685 }
686 
688  return decodeSDWASrc(OPW32, Val);
689 }
690 
692  using namespace AMDGPU::SDWA;
693 
694  assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] &&
695  "SDWAVopcDst should be present only on GFX9");
698  if (Val > AMDGPU::EncValues::SGPR_MAX) {
699  return decodeSpecialReg64(Val);
700  } else {
701  return createSRegOperand(getSgprClassId(OPW64), Val);
702  }
703  } else {
704  return createRegOperand(AMDGPU::VCC);
705  }
706 }
707 
708 //===----------------------------------------------------------------------===//
709 // AMDGPUSymbolizer
710 //===----------------------------------------------------------------------===//
711 
712 // Try to find symbol name for specified label
714  raw_ostream &/*cStream*/, int64_t Value,
715  uint64_t /*Address*/, bool IsBranch,
716  uint64_t /*Offset*/, uint64_t /*InstSize*/) {
717  using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
718  using SectionSymbolsTy = std::vector<SymbolInfoTy>;
719 
720  if (!IsBranch) {
721  return false;
722  }
723 
724  auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
725  auto Result = std::find_if(Symbols->begin(), Symbols->end(),
726  [Value](const SymbolInfoTy& Val) {
727  return std::get<0>(Val) == static_cast<uint64_t>(Value)
728  && std::get<2>(Val) == ELF::STT_NOTYPE;
729  });
730  if (Result != Symbols->end()) {
731  auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
732  const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
734  return true;
735  }
736  return false;
737 }
738 
740  int64_t Value,
741  uint64_t Address) {
742  llvm_unreachable("unimplemented");
743 }
744 
745 //===----------------------------------------------------------------------===//
746 // Initialization
747 //===----------------------------------------------------------------------===//
748 
750  LLVMOpInfoCallback /*GetOpInfo*/,
751  LLVMSymbolLookupCallback /*SymbolLookUp*/,
752  void *DisInfo,
753  MCContext *Ctx,
754  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
755  return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
756 }
757 
759  const MCSubtargetInfo &STI,
760  MCContext &Ctx) {
761  return new AMDGPUDisassembler(STI, Ctx);
762 }
763 
769 }
MCOperand createRegOperand(unsigned int RegId) const
static int64_t getInlineImmVal16(unsigned Imm)
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
iterator begin()
Definition: MCInst.h:192
Target & getTheGCNTarget()
The target for GCN GPUs.
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:841
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
#define DECODE_OPERAND_REG(RegClass)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_VS_128(unsigned Val) const
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
MCOperand decodeOperand_SReg_512(unsigned Val) const
Superclass for all disassemblers.
raw_ostream * CommentStream
const char * getRegClassName(unsigned RegClassID) const
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: Disassembler.h:54
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeLiteralConstant() const
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
MCOperand decodeSDWAVopcDst(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
This file implements a class to represent arbitrary precision integral constant values and operations...
TargetRegisterInfo interface that is implemented by all hw codegen targets.
static int64_t getInlineImmVal32(unsigned Imm)
Context object for machine code objects.
Definition: MCContext.h:59
DecodeStatus convertSDWAInst(MCInst &MI) const
const MCSubtargetInfo & STI
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
MCOperand decodeSDWASrc32(unsigned Val) const
#define T
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:197
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:593
unsigned getVgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_VReg_128(unsigned Val) const
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
MCOperand decodeOperand_VS_64(unsigned Val) const
unsigned getNumOperands() const
Definition: MCInst.h:182
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:841
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static int64_t getInlineImmVal64(unsigned Imm)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const T * data() const
Definition: ArrayRef.h:146
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCOperand decodeSDWASrc16(unsigned Val) const
MCContext & getContext() const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:583
static MCOperand decodeIntImmed(unsigned Imm)
#define DECODE_SDWA(DecName)
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: Disassembler.h:124
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:179
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
void LLVMInitializeAMDGPUDisassembler()
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
This file contains declaration for AMDGPU ISA disassembler.
MCOperand decodeOperand_VSrc16(unsigned Val) const
#define I(x, y, z)
Definition: MD5.cpp:58
MCSubtargetInfo - Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
MCOperand decodeOperand_SReg_64(unsigned Val) const
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:285
MCOperand decodeOperand_VReg_96(unsigned Val) const
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeSpecialReg64(unsigned Val) const
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
bool isValid() const
Definition: MCInst.h:57
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getOpcode() const
Definition: MCInst.h:172
MCOperand decodeSpecialReg32(unsigned Val) const
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123