LLVM  9.0.0svn
AMDGPUDisassembler.cpp
Go to the documentation of this file.
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
20 #include "AMDGPU.h"
21 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm-c/Disassembler.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/BinaryFormat/ELF.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/Endian.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstddef>
46 #include <cstdint>
47 #include <iterator>
48 #include <tuple>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "amdgpu-disassembler"
54 
55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
56  : AMDGPU::EncValues::SGPR_MAX_SI)
57 
59 
61  MCContext &Ctx,
62  MCInstrInfo const *MCII) :
63  MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
64  TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 
66  // ToDo: AMDGPUDisassembler supports only VI ISA.
67  if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
68  report_fatal_error("Disassembly not yet supported for subtarget");
69 }
70 
71 inline static MCDisassembler::DecodeStatus
72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
73  Inst.addOperand(Opnd);
74  return Opnd.isValid() ?
77 }
78 
80  uint16_t NameIdx) {
81  int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
82  if (OpIdx != -1) {
83  auto I = MI.begin();
84  std::advance(I, OpIdx);
85  MI.insert(I, Op);
86  }
87  return OpIdx;
88 }
89 
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
91  uint64_t Addr, const void *Decoder) {
92  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
93 
94  // Our branches take a simm16, but we need two extra bits to account for the
95  // factor of 4.
96  APInt SignedOffset(18, Imm * 4, true);
97  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
98 
99  if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
101  return addOperand(Inst, MCOperand::createImm(Imm));
102 }
103 
104 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
105 static DecodeStatus StaticDecoderName(MCInst &Inst, \
106  unsigned Imm, \
107  uint64_t /*Addr*/, \
108  const void *Decoder) { \
109  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
110  return addOperand(Inst, DAsm->DecoderName(Imm)); \
111 }
112 
113 #define DECODE_OPERAND_REG(RegClass) \
114 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
115 
116 DECODE_OPERAND_REG(VGPR_32)
117 DECODE_OPERAND_REG(VRegOrLds_32)
118 DECODE_OPERAND_REG(VS_32)
119 DECODE_OPERAND_REG(VS_64)
120 DECODE_OPERAND_REG(VS_128)
121 
122 DECODE_OPERAND_REG(VReg_64)
123 DECODE_OPERAND_REG(VReg_96)
124 DECODE_OPERAND_REG(VReg_128)
125 
126 DECODE_OPERAND_REG(SReg_32)
127 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
128 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
129 DECODE_OPERAND_REG(SRegOrLds_32)
130 DECODE_OPERAND_REG(SReg_64)
131 DECODE_OPERAND_REG(SReg_64_XEXEC)
132 DECODE_OPERAND_REG(SReg_128)
133 DECODE_OPERAND_REG(SReg_256)
134 DECODE_OPERAND_REG(SReg_512)
135 
137  unsigned Imm,
138  uint64_t Addr,
139  const void *Decoder) {
140  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
141  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
142 }
143 
145  unsigned Imm,
146  uint64_t Addr,
147  const void *Decoder) {
148  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
149  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
150 }
151 
152 #define DECODE_SDWA(DecName) \
153 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
154 
155 DECODE_SDWA(Src32)
156 DECODE_SDWA(Src16)
157 DECODE_SDWA(VopcDst)
158 
159 #include "AMDGPUGenDisassemblerTables.inc"
160 
161 //===----------------------------------------------------------------------===//
162 //
163 //===----------------------------------------------------------------------===//
164 
165 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
166  assert(Bytes.size() >= sizeof(T));
167  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
168  Bytes = Bytes.slice(sizeof(T));
169  return Res;
170 }
171 
173  MCInst &MI,
174  uint64_t Inst,
175  uint64_t Address) const {
176  assert(MI.getOpcode() == 0);
177  assert(MI.getNumOperands() == 0);
178  MCInst TmpInst;
179  HasLiteral = false;
180  const auto SavedBytes = Bytes;
181  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
182  MI = TmpInst;
184  }
185  Bytes = SavedBytes;
186  return MCDisassembler::Fail;
187 }
188 
190  ArrayRef<uint8_t> Bytes_,
191  uint64_t Address,
192  raw_ostream &WS,
193  raw_ostream &CS) const {
194  CommentStream = &CS;
195  bool IsSDWA = false;
196 
197  unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
198  Bytes = Bytes_.slice(0, MaxInstBytesNum);
199 
201  do {
202  // ToDo: better to switch encoding length using some bit predicate
203  // but it is unknown yet, so try all we can
204 
205  // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
206  // encodings
207  if (Bytes.size() >= 8) {
208  const uint64_t QW = eatBytes<uint64_t>(Bytes);
209  Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
210  if (Res) break;
211 
212  Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
213  if (Res) { IsSDWA = true; break; }
214 
215  Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
216  if (Res) { IsSDWA = true; break; }
217 
218  Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
219  if (Res) { IsSDWA = true; break; }
220 
221  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
222  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
223  // table first so we print the correct name.
224 
225  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
226  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
227  if (Res) break;
228  }
229 
230  if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
231  Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
232  if (Res)
233  break;
234  }
235 
236  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
237  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
238  // table first so we print the correct name.
239  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
240  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
241  if (Res)
242  break;
243  }
244  }
245 
246  // Reinitialize Bytes as DPP64 could have eaten too much
247  Bytes = Bytes_.slice(0, MaxInstBytesNum);
248 
249  // Try decode 32-bit instruction
250  if (Bytes.size() < 4) break;
251  const uint32_t DW = eatBytes<uint32_t>(Bytes);
252  Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
253  if (Res) break;
254 
255  Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
256  if (Res) break;
257 
258  Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
259  if (Res) break;
260 
261  Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
262  if (Res) break;
263 
264  if (Bytes.size() < 4) break;
265  const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
266  Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
267  if (Res) break;
268 
269  Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
270  if (Res) break;
271 
272  Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
273  if (Res) break;
274 
275  Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
276  } while (false);
277 
278  if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
279  !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
280  MaxInstBytesNum = 8;
281  Bytes = Bytes_.slice(0, MaxInstBytesNum);
282  eatBytes<uint64_t>(Bytes);
283  }
284 
285  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
286  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
287  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
288  MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
289  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
290  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
291  MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
292  // Insert dummy unused src2_modifiers.
294  AMDGPU::OpName::src2_modifiers);
295  }
296 
297  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
298  int VAddr0Idx =
299  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
300  int RsrcIdx =
301  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
302  unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
303  if (VAddr0Idx >= 0 && NSAArgs > 0) {
304  unsigned NSAWords = (NSAArgs + 3) / 4;
305  if (Bytes.size() < 4 * NSAWords) {
306  Res = MCDisassembler::Fail;
307  } else {
308  for (unsigned i = 0; i < NSAArgs; ++i) {
309  MI.insert(MI.begin() + VAddr0Idx + 1 + i,
310  decodeOperand_VGPR_32(Bytes[i]));
311  }
312  Bytes = Bytes.slice(4 * NSAWords);
313  }
314  }
315 
316  if (Res)
317  Res = convertMIMGInst(MI);
318  }
319 
320  if (Res && IsSDWA)
321  Res = convertSDWAInst(MI);
322 
323  int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
324  AMDGPU::OpName::vdst_in);
325  if (VDstIn_Idx != -1) {
326  int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
328  if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
329  !MI.getOperand(VDstIn_Idx).isReg() ||
330  MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
331  if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
332  MI.erase(&MI.getOperand(VDstIn_Idx));
335  AMDGPU::OpName::vdst_in);
336  }
337  }
338 
339  // if the opcode was not recognized we'll assume a Size of 4 bytes
340  // (unless there are fewer bytes left)
341  Size = Res ? (MaxInstBytesNum - Bytes.size())
342  : std::min((size_t)4, Bytes_.size());
343  return Res;
344 }
345 
347  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
348  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
349  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
350  // VOPC - insert clamp
351  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
352  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
353  int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
354  if (SDst != -1) {
355  // VOPC - insert VCC register as sdst
356  insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
357  AMDGPU::OpName::sdst);
358  } else {
359  // VOP1/2 - insert omod if present in instruction
360  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
361  }
362  }
364 }
365 
366 // Note that before gfx10, the MIMG encoding provided no information about
367 // VADDR size. Consequently, decoded instructions always show address as if it
368 // has 1 dword, which could be not really so.
370 
371  int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
372  AMDGPU::OpName::vdst);
373 
374  int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
375  AMDGPU::OpName::vdata);
376  int VAddr0Idx =
377  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
378  int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
379  AMDGPU::OpName::dmask);
380 
381  int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
382  AMDGPU::OpName::tfe);
383  int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
384  AMDGPU::OpName::d16);
385 
386  assert(VDataIdx != -1);
387  assert(DMaskIdx != -1);
388  assert(TFEIdx != -1);
389 
391  bool IsAtomic = (VDstIdx != -1);
392  bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
393 
394  bool IsNSA = false;
395  unsigned AddrSize = Info->VAddrDwords;
396 
397  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
398  unsigned DimIdx =
399  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
400  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
402  const AMDGPU::MIMGDimInfo *Dim =
404 
405  AddrSize = BaseOpcode->NumExtraArgs +
406  (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
407  (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
408  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
409  IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
410  if (!IsNSA) {
411  if (AddrSize > 8)
412  AddrSize = 16;
413  else if (AddrSize > 4)
414  AddrSize = 8;
415  } else {
416  if (AddrSize > Info->VAddrDwords) {
417  // The NSA encoding does not contain enough operands for the combination
418  // of base opcode / dimension. Should this be an error?
420  }
421  }
422  }
423 
424  unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
425  unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
426 
427  bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
428  if (D16 && AMDGPU::hasPackedD16(STI)) {
429  DstSize = (DstSize + 1) / 2;
430  }
431 
432  // FIXME: Add tfe support
433  if (MI.getOperand(TFEIdx).getImm())
435 
436  if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
438 
439  int NewOpcode =
440  AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
441  if (NewOpcode == -1)
443 
444  // Widen the register to the correct number of enabled channels.
445  unsigned NewVdata = AMDGPU::NoRegister;
446  if (DstSize != Info->VDataDwords) {
447  auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
448 
449  // Get first subregister of VData
450  unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
451  unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
452  Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
453 
454  NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
455  &MRI.getRegClass(DataRCID));
456  if (NewVdata == AMDGPU::NoRegister) {
457  // It's possible to encode this such that the low register + enabled
458  // components exceeds the register count.
460  }
461  }
462 
463  unsigned NewVAddr0 = AMDGPU::NoRegister;
464  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
465  AddrSize != Info->VAddrDwords) {
466  unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
467  unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
468  VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
469 
470  auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
471  NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
472  &MRI.getRegClass(AddrRCID));
473  if (NewVAddr0 == AMDGPU::NoRegister)
475  }
476 
477  MI.setOpcode(NewOpcode);
478 
479  if (NewVdata != AMDGPU::NoRegister) {
480  MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
481 
482  if (IsAtomic) {
483  // Atomic operations have an additional operand (a copy of data)
484  MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
485  }
486  }
487 
488  if (NewVAddr0 != AMDGPU::NoRegister) {
489  MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
490  } else if (IsNSA) {
491  assert(AddrSize <= Info->VAddrDwords);
492  MI.erase(MI.begin() + VAddr0Idx + AddrSize,
493  MI.begin() + VAddr0Idx + Info->VAddrDwords);
494  }
495 
497 }
498 
499 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
500  return getContext().getRegisterInfo()->
501  getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
502 }
503 
504 inline
506  const Twine& ErrMsg) const {
507  *CommentStream << "Error: " + ErrMsg;
508 
509  // ToDo: add support for error operands to MCInst.h
510  // return MCOperand::createError(V);
511  return MCOperand();
512 }
513 
514 inline
516  return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
517 }
518 
519 inline
521  unsigned Val) const {
522  const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
523  if (Val >= RegCl.getNumRegs())
524  return errOperand(Val, Twine(getRegClassName(RegClassID)) +
525  ": unknown register " + Twine(Val));
526  return createRegOperand(RegCl.getRegister(Val));
527 }
528 
529 inline
531  unsigned Val) const {
532  // ToDo: SI/CI have 104 SGPRs, VI - 102
533  // Valery: here we accepting as much as we can, let assembler sort it out
534  int shift = 0;
535  switch (SRegClassID) {
536  case AMDGPU::SGPR_32RegClassID:
537  case AMDGPU::TTMP_32RegClassID:
538  break;
539  case AMDGPU::SGPR_64RegClassID:
540  case AMDGPU::TTMP_64RegClassID:
541  shift = 1;
542  break;
543  case AMDGPU::SGPR_128RegClassID:
544  case AMDGPU::TTMP_128RegClassID:
545  // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
546  // this bundle?
547  case AMDGPU::SGPR_256RegClassID:
548  case AMDGPU::TTMP_256RegClassID:
549  // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
550  // this bundle?
551  case AMDGPU::SGPR_512RegClassID:
552  case AMDGPU::TTMP_512RegClassID:
553  shift = 2;
554  break;
555  // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
556  // this bundle?
557  default:
558  llvm_unreachable("unhandled register class");
559  }
560 
561  if (Val % (1 << shift)) {
562  *CommentStream << "Warning: " << getRegClassName(SRegClassID)
563  << ": scalar reg isn't aligned " << Val;
564  }
565 
566  return createRegOperand(SRegClassID, Val >> shift);
567 }
568 
570  return decodeSrcOp(OPW32, Val);
571 }
572 
574  return decodeSrcOp(OPW64, Val);
575 }
576 
578  return decodeSrcOp(OPW128, Val);
579 }
580 
582  return decodeSrcOp(OPW16, Val);
583 }
584 
586  return decodeSrcOp(OPWV216, Val);
587 }
588 
590  // Some instructions have operand restrictions beyond what the encoding
591  // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
592  // high bit.
593  Val &= 255;
594 
595  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
596 }
597 
599  return decodeSrcOp(OPW32, Val);
600 }
601 
603  return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
604 }
605 
607  return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
608 }
609 
611  return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
612 }
613 
615  // table-gen generated disassembler doesn't care about operand types
616  // leaving only registry class so SSrc_32 operand turns into SReg_32
617  // and therefore we accept immediates and literals here as well
618  return decodeSrcOp(OPW32, Val);
619 }
620 
622  unsigned Val) const {
623  // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
624  return decodeOperand_SReg_32(Val);
625 }
626 
628  unsigned Val) const {
629  // SReg_32_XM0 is SReg_32 without EXEC_HI
630  return decodeOperand_SReg_32(Val);
631 }
632 
634  // table-gen generated disassembler doesn't care about operand types
635  // leaving only registry class so SSrc_32 operand turns into SReg_32
636  // and therefore we accept immediates and literals here as well
637  return decodeSrcOp(OPW32, Val);
638 }
639 
641  return decodeSrcOp(OPW64, Val);
642 }
643 
645  return decodeSrcOp(OPW64, Val);
646 }
647 
649  return decodeSrcOp(OPW128, Val);
650 }
651 
653  return decodeDstOp(OPW256, Val);
654 }
655 
657  return decodeDstOp(OPW512, Val);
658 }
659 
661  // For now all literal constants are supposed to be unsigned integer
662  // ToDo: deal with signed/unsigned 64-bit integer constants
663  // ToDo: deal with float/double constants
664  if (!HasLiteral) {
665  if (Bytes.size() < 4) {
666  return errOperand(0, "cannot read literal, inst bytes left " +
667  Twine(Bytes.size()));
668  }
669  HasLiteral = true;
670  Literal = eatBytes<uint32_t>(Bytes);
671  }
672  return MCOperand::createImm(Literal);
673 }
674 
676  using namespace AMDGPU::EncValues;
677 
680  (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
681  (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
682  // Cast prevents negative overflow.
683 }
684 
685 static int64_t getInlineImmVal32(unsigned Imm) {
686  switch (Imm) {
687  case 240:
688  return FloatToBits(0.5f);
689  case 241:
690  return FloatToBits(-0.5f);
691  case 242:
692  return FloatToBits(1.0f);
693  case 243:
694  return FloatToBits(-1.0f);
695  case 244:
696  return FloatToBits(2.0f);
697  case 245:
698  return FloatToBits(-2.0f);
699  case 246:
700  return FloatToBits(4.0f);
701  case 247:
702  return FloatToBits(-4.0f);
703  case 248: // 1 / (2 * PI)
704  return 0x3e22f983;
705  default:
706  llvm_unreachable("invalid fp inline imm");
707  }
708 }
709 
710 static int64_t getInlineImmVal64(unsigned Imm) {
711  switch (Imm) {
712  case 240:
713  return DoubleToBits(0.5);
714  case 241:
715  return DoubleToBits(-0.5);
716  case 242:
717  return DoubleToBits(1.0);
718  case 243:
719  return DoubleToBits(-1.0);
720  case 244:
721  return DoubleToBits(2.0);
722  case 245:
723  return DoubleToBits(-2.0);
724  case 246:
725  return DoubleToBits(4.0);
726  case 247:
727  return DoubleToBits(-4.0);
728  case 248: // 1 / (2 * PI)
729  return 0x3fc45f306dc9c882;
730  default:
731  llvm_unreachable("invalid fp inline imm");
732  }
733 }
734 
735 static int64_t getInlineImmVal16(unsigned Imm) {
736  switch (Imm) {
737  case 240:
738  return 0x3800;
739  case 241:
740  return 0xB800;
741  case 242:
742  return 0x3C00;
743  case 243:
744  return 0xBC00;
745  case 244:
746  return 0x4000;
747  case 245:
748  return 0xC000;
749  case 246:
750  return 0x4400;
751  case 247:
752  return 0xC400;
753  case 248: // 1 / (2 * PI)
754  return 0x3118;
755  default:
756  llvm_unreachable("invalid fp inline imm");
757  }
758 }
759 
763 
764  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
765  switch (Width) {
766  case OPW32:
768  case OPW64:
770  case OPW16:
771  case OPWV216:
773  default:
774  llvm_unreachable("implement me");
775  }
776 }
777 
778 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
779  using namespace AMDGPU;
780 
781  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
782  switch (Width) {
783  default: // fall
784  case OPW32:
785  case OPW16:
786  case OPWV216:
787  return VGPR_32RegClassID;
788  case OPW64: return VReg_64RegClassID;
789  case OPW128: return VReg_128RegClassID;
790  }
791 }
792 
793 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
794  using namespace AMDGPU;
795 
796  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
797  switch (Width) {
798  default: // fall
799  case OPW32:
800  case OPW16:
801  case OPWV216:
802  return SGPR_32RegClassID;
803  case OPW64: return SGPR_64RegClassID;
804  case OPW128: return SGPR_128RegClassID;
805  case OPW256: return SGPR_256RegClassID;
806  case OPW512: return SGPR_512RegClassID;
807  }
808 }
809 
810 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
811  using namespace AMDGPU;
812 
813  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
814  switch (Width) {
815  default: // fall
816  case OPW32:
817  case OPW16:
818  case OPWV216:
819  return TTMP_32RegClassID;
820  case OPW64: return TTMP_64RegClassID;
821  case OPW128: return TTMP_128RegClassID;
822  case OPW256: return TTMP_256RegClassID;
823  case OPW512: return TTMP_512RegClassID;
824  }
825 }
826 
827 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
828  using namespace AMDGPU::EncValues;
829 
830  unsigned TTmpMin =
832  unsigned TTmpMax =
834 
835  return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
836 }
837 
838 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
839  using namespace AMDGPU::EncValues;
840 
841  assert(Val < 512); // enum9
842 
843  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
844  return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
845  }
846  if (Val <= SGPR_MAX) {
847  assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
848  return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
849  }
850 
851  int TTmpIdx = getTTmpIdx(Val);
852  if (TTmpIdx >= 0) {
853  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
854  }
855 
856  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
857  return decodeIntImmed(Val);
858 
859  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
860  return decodeFPImmed(Width, Val);
861 
862  if (Val == LITERAL_CONST)
863  return decodeLiteralConstant();
864 
865  switch (Width) {
866  case OPW32:
867  case OPW16:
868  case OPWV216:
869  return decodeSpecialReg32(Val);
870  case OPW64:
871  return decodeSpecialReg64(Val);
872  default:
873  llvm_unreachable("unexpected immediate type");
874  }
875 }
876 
877 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
878  using namespace AMDGPU::EncValues;
879 
880  assert(Val < 128);
881  assert(Width == OPW256 || Width == OPW512);
882 
883  if (Val <= SGPR_MAX) {
884  assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
885  return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
886  }
887 
888  int TTmpIdx = getTTmpIdx(Val);
889  if (TTmpIdx >= 0) {
890  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
891  }
892 
893  llvm_unreachable("unknown dst register");
894 }
895 
897  using namespace AMDGPU;
898 
899  switch (Val) {
900  case 102: return createRegOperand(FLAT_SCR_LO);
901  case 103: return createRegOperand(FLAT_SCR_HI);
902  case 104: return createRegOperand(XNACK_MASK_LO);
903  case 105: return createRegOperand(XNACK_MASK_HI);
904  case 106: return createRegOperand(VCC_LO);
905  case 107: return createRegOperand(VCC_HI);
906  case 108: return createRegOperand(TBA_LO);
907  case 109: return createRegOperand(TBA_HI);
908  case 110: return createRegOperand(TMA_LO);
909  case 111: return createRegOperand(TMA_HI);
910  case 124: return createRegOperand(M0);
911  case 125: return createRegOperand(SGPR_NULL);
912  case 126: return createRegOperand(EXEC_LO);
913  case 127: return createRegOperand(EXEC_HI);
914  case 235: return createRegOperand(SRC_SHARED_BASE);
915  case 236: return createRegOperand(SRC_SHARED_LIMIT);
916  case 237: return createRegOperand(SRC_PRIVATE_BASE);
917  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
918  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
919  // ToDo: no support for vccz register
920  case 251: break;
921  // ToDo: no support for execz register
922  case 252: break;
923  case 253: return createRegOperand(SCC);
924  case 254: return createRegOperand(LDS_DIRECT);
925  default: break;
926  }
927  return errOperand(Val, "unknown operand encoding " + Twine(Val));
928 }
929 
931  using namespace AMDGPU;
932 
933  switch (Val) {
934  case 102: return createRegOperand(FLAT_SCR);
935  case 104: return createRegOperand(XNACK_MASK);
936  case 106: return createRegOperand(VCC);
937  case 108: return createRegOperand(TBA);
938  case 110: return createRegOperand(TMA);
939  case 126: return createRegOperand(EXEC);
940  case 235: return createRegOperand(SRC_SHARED_BASE);
941  case 236: return createRegOperand(SRC_SHARED_LIMIT);
942  case 237: return createRegOperand(SRC_PRIVATE_BASE);
943  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
944  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
945  default: break;
946  }
947  return errOperand(Val, "unknown operand encoding " + Twine(Val));
948 }
949 
951  const unsigned Val) const {
952  using namespace AMDGPU::SDWA;
953  using namespace AMDGPU::EncValues;
954 
955  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
956  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
957  // XXX: cast to int is needed to avoid stupid warning:
958  // compare with unsigned is always true
959  if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
961  return createRegOperand(getVgprClassId(Width),
963  }
964  if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
967  return createSRegOperand(getSgprClassId(Width),
969  }
970  if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
972  return createSRegOperand(getTtmpClassId(Width),
974  }
975 
976  const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
977 
978  if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
979  return decodeIntImmed(SVal);
980 
981  if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
982  return decodeFPImmed(Width, SVal);
983 
984  return decodeSpecialReg32(SVal);
985  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
986  return createRegOperand(getVgprClassId(Width), Val);
987  }
988  llvm_unreachable("unsupported target");
989 }
990 
992  return decodeSDWASrc(OPW16, Val);
993 }
994 
996  return decodeSDWASrc(OPW32, Val);
997 }
998 
1000  using namespace AMDGPU::SDWA;
1001 
1002  assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1003  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1004  "SDWAVopcDst should be present only on GFX9+");
1005 
1008 
1009  int TTmpIdx = getTTmpIdx(Val);
1010  if (TTmpIdx >= 0) {
1011  return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
1012  } else if (Val > SGPR_MAX) {
1013  return decodeSpecialReg64(Val);
1014  } else {
1015  return createSRegOperand(getSgprClassId(OPW64), Val);
1016  }
1017  } else {
1018  return createRegOperand(AMDGPU::VCC);
1019  }
1020 }
1021 
1023  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1024 }
1025 
1027  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1028 }
1029 
1031  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1032 }
1033 
1034 //===----------------------------------------------------------------------===//
1035 // AMDGPUSymbolizer
1036 //===----------------------------------------------------------------------===//
1037 
1038 // Try to find symbol name for specified label
1040  raw_ostream &/*cStream*/, int64_t Value,
1041  uint64_t /*Address*/, bool IsBranch,
1042  uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1043  using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
1044  using SectionSymbolsTy = std::vector<SymbolInfoTy>;
1045 
1046  if (!IsBranch) {
1047  return false;
1048  }
1049 
1050  auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1051  if (!Symbols)
1052  return false;
1053 
1054  auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1055  [Value](const SymbolInfoTy& Val) {
1056  return std::get<0>(Val) == static_cast<uint64_t>(Value)
1057  && std::get<2>(Val) == ELF::STT_NOTYPE;
1058  });
1059  if (Result != Symbols->end()) {
1060  auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
1061  const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1063  return true;
1064  }
1065  return false;
1066 }
1067 
1069  int64_t Value,
1070  uint64_t Address) {
1071  llvm_unreachable("unimplemented");
1072 }
1073 
1074 //===----------------------------------------------------------------------===//
1075 // Initialization
1076 //===----------------------------------------------------------------------===//
1077 
1079  LLVMOpInfoCallback /*GetOpInfo*/,
1080  LLVMSymbolLookupCallback /*SymbolLookUp*/,
1081  void *DisInfo,
1082  MCContext *Ctx,
1083  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1084  return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1085 }
1086 
1088  const MCSubtargetInfo &STI,
1089  MCContext &Ctx) {
1090  return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1091 }
1092 
1098 }
MCOperand createRegOperand(unsigned int RegId) const
static int64_t getInlineImmVal16(unsigned Imm)
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
iterator begin()
Definition: MCInst.h:192
Target & getTheGCNTarget()
The target for GCN GPUs.
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
bool hasPackedD16(const MCSubtargetInfo &STI)
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:833
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
#define DECODE_OPERAND_REG(RegClass)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_VS_128(unsigned Val) const
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
MCOperand decodeOperand_SReg_512(unsigned Val) const
Superclass for all disassemblers.
raw_ostream * CommentStream
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
const char * getRegClassName(unsigned RegClassID) const
bool isReg() const
Definition: MCInst.h:57
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeLiteralConstant() const
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const FeatureBitset & getFeatureBits() const
MCOperand decodeSDWAVopcDst(unsigned Val) const
void erase(iterator I)
Definition: MCInst.h:189
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
TargetRegisterInfo interface that is implemented by all hw codegen targets.
static int64_t getInlineImmVal32(unsigned Imm)
Context object for machine code objects.
Definition: MCContext.h:62
DecodeStatus convertSDWAInst(MCInst &MI) const
const MCSubtargetInfo & STI
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
MCOperand decodeSDWASrc32(unsigned Val) const
#define T
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:197
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:600
int64_t getImm() const
Definition: MCInst.h:75
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned const MachineRegisterInfo * MRI
MCOperand decodeOperand_VReg_128(unsigned Val) const
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:38
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
DecodeStatus convertMIMGInst(MCInst &MI) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
unsigned getNumOperands() const
Definition: MCInst.h:181
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static int64_t getInlineImmVal64(unsigned Imm)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const T * data() const
Definition: ArrayRef.h:145
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
#define SGPR_MAX
MCOperand decodeSDWASrc16(unsigned Val) const
void setOpcode(unsigned Op)
Definition: MCInst.h:170
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:519
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
MCContext & getContext() const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:590
static MCOperand decodeIntImmed(unsigned Imm)
#define DECODE_SDWA(DecName)
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:178
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Provides AMDGPU specific target descriptions.
void LLVMInitializeAMDGPUDisassembler()
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
This file contains declaration for AMDGPU ISA disassembler.
MCOperand decodeOperand_VSrc16(unsigned Val) const
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
uint32_t Size
Definition: Profile.cpp:46
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
MCOperand decodeOperand_SReg_64(unsigned Val) const
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
MCOperand decodeOperand_VReg_96(unsigned Val) const
LLVM Value Representation.
Definition: Value.h:72
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeSpecialReg64(unsigned Val) const
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
bool isValid() const
Definition: MCInst.h:56
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getOpcode() const
Definition: MCInst.h:171
MCOperand decodeSpecialReg32(unsigned Val) const
int getTTmpIdx(unsigned Val) const
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.