LLVM  9.0.0svn
AMDGPUDisassembler.h
Go to the documentation of this file.
1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This file contains declaration for AMDGPU ISA disassembler
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInstrInfo.h"
24 
25 #include <algorithm>
26 #include <cstdint>
27 #include <memory>
28 
29 namespace llvm {
30 
31 class MCInst;
32 class MCOperand;
33 class MCSubtargetInfo;
34 class Twine;
35 
36 //===----------------------------------------------------------------------===//
37 // AMDGPUDisassembler
38 //===----------------------------------------------------------------------===//
39 
41 private:
42  std::unique_ptr<MCInstrInfo const> const MCII;
43  const MCRegisterInfo &MRI;
44  mutable ArrayRef<uint8_t> Bytes;
45  mutable uint32_t Literal;
46  mutable bool HasLiteral;
47 
48 public:
50  MCInstrInfo const *MCII) :
51  MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()) {}
52 
53  ~AMDGPUDisassembler() override = default;
54 
56  ArrayRef<uint8_t> Bytes, uint64_t Address,
57  raw_ostream &WS, raw_ostream &CS) const override;
58 
59  const char* getRegClassName(unsigned RegClassID) const;
60 
61  MCOperand createRegOperand(unsigned int RegId) const;
62  MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
63  MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
64 
65  MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
66 
67  DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
68  uint64_t Address) const;
69 
72 
73  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
74  MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
75 
76  MCOperand decodeOperand_VS_32(unsigned Val) const;
77  MCOperand decodeOperand_VS_64(unsigned Val) const;
78  MCOperand decodeOperand_VS_128(unsigned Val) const;
79  MCOperand decodeOperand_VSrc16(unsigned Val) const;
80  MCOperand decodeOperand_VSrcV216(unsigned Val) const;
81 
82  MCOperand decodeOperand_VReg_64(unsigned Val) const;
83  MCOperand decodeOperand_VReg_96(unsigned Val) const;
84  MCOperand decodeOperand_VReg_128(unsigned Val) const;
85 
86  MCOperand decodeOperand_SReg_32(unsigned Val) const;
87  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
88  MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
89  MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
90  MCOperand decodeOperand_SReg_64(unsigned Val) const;
91  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
92  MCOperand decodeOperand_SReg_128(unsigned Val) const;
93  MCOperand decodeOperand_SReg_256(unsigned Val) const;
94  MCOperand decodeOperand_SReg_512(unsigned Val) const;
95 
96  enum OpWidthTy {
106  };
107 
108  unsigned getVgprClassId(const OpWidthTy Width) const;
109  unsigned getSgprClassId(const OpWidthTy Width) const;
110  unsigned getTtmpClassId(const OpWidthTy Width) const;
111 
112  static MCOperand decodeIntImmed(unsigned Imm);
113  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
115 
116  MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
117  MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
118  MCOperand decodeSpecialReg32(unsigned Val) const;
119  MCOperand decodeSpecialReg64(unsigned Val) const;
120 
121  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
122  MCOperand decodeSDWASrc16(unsigned Val) const;
123  MCOperand decodeSDWASrc32(unsigned Val) const;
124  MCOperand decodeSDWAVopcDst(unsigned Val) const;
125 
126  int getTTmpIdx(unsigned Val) const;
127 
128  bool isVI() const;
129  bool isGFX9() const;
130  };
131 
132 //===----------------------------------------------------------------------===//
133 // AMDGPUSymbolizer
134 //===----------------------------------------------------------------------===//
135 
137 private:
138  void *DisInfo;
139 
140 public:
141  AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
142  void *disInfo)
143  : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
144 
145  bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
146  int64_t Value, uint64_t Address,
147  bool IsBranch, uint64_t Offset,
148  uint64_t InstSize) override;
149 
151  int64_t Value,
152  uint64_t Address) override;
153 };
154 
155 } // end namespace llvm
156 
157 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
MCOperand createRegOperand(unsigned int RegId) const
~AMDGPUDisassembler() override=default
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_VS_128(unsigned Val) const
MCOperand decodeOperand_SReg_512(unsigned Val) const
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeLiteralConstant() const
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: BitVector.h:937
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
MCOperand decodeSDWAVopcDst(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Context object for machine code objects.
Definition: MCContext.h:62
DecodeStatus convertSDWAInst(MCInst &MI) const
const MCSubtargetInfo & STI
MCOperand decodeSDWASrc32(unsigned Val) const
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
unsigned getVgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_VReg_128(unsigned Val) const
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:38
DecodeStatus convertMIMGInst(MCInst &MI) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCOperand decodeSDWASrc16(unsigned Val) const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
static MCOperand decodeIntImmed(unsigned Imm)
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
MCOperand decodeOperand_VSrc16(unsigned Val) const
Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
uint32_t Size
Definition: Profile.cpp:46
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
MCOperand decodeOperand_SReg_64(unsigned Val) const
MCOperand decodeOperand_VReg_96(unsigned Val) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
LLVM Value Representation.
Definition: Value.h:72
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeSpecialReg64(unsigned Val) const
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
MCOperand decodeSpecialReg32(unsigned Val) const
int getTTmpIdx(unsigned Val) const
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34