15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H 33 class MCSubtargetInfo;
42 std::unique_ptr<MCInstrInfo const>
const MCII;
44 const unsigned TargetMaxInstBytes;
47 mutable bool HasLiteral;
67 uint64_t Address)
const;
161 bool IsBranch, uint64_t
Offset,
162 uint64_t InstSize)
override;
166 uint64_t Address)
override;
171 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H MCOperand createRegOperand(unsigned int RegId) const
~AMDGPUDisassembler() override=default
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
This class represents lattice values for constants.
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_VS_128(unsigned Val) const
MCOperand decodeOperand_SReg_512(unsigned Val) const
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeLiteralConstant() const
MCOperand decodeOperand_AReg_128(unsigned Val) const
MCOperand decodeOperand_SReg_128(unsigned Val) const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
MCOperand decodeSDWAVopcDst(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeOperand_AReg_512(unsigned Val) const
Context object for machine code objects.
DecodeStatus convertSDWAInst(MCInst &MI) const
MCOperand decodeOperand_AReg_1024(unsigned Val) const
const MCSubtargetInfo & STI
MCOperand decodeSDWASrc32(unsigned Val) const
MCOperand decodeOperand_VReg_256(unsigned Val) const
Instances of this class represent a single low-level machine instruction.
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCOperand decodeOperand_AV_64(unsigned Val) const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
unsigned getVgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_VReg_128(unsigned Val) const
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
Symbolize and annotate disassembled instructions.
DecodeStatus convertMIMGInst(MCInst &MI) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Interface to description of machine instruction set.
MCOperand decodeOperand_VReg_512(unsigned Val) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc16(unsigned Val) const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
static MCOperand decodeIntImmed(unsigned Imm)
MCOperand decodeOperand_AGPR_32(unsigned Val) const
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
MCOperand decodeOperand_AV_32(unsigned Val) const
MCOperand decodeOperand_VSrc16(unsigned Val) const
Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
MCOperand decodeOperand_SReg_64(unsigned Val) const
MCOperand decodeOperand_VReg_96(unsigned Val) const
LLVM Value Representation.
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeSpecialReg64(unsigned Val) const
This class implements an extremely fast bulk output stream that can only output to a stream...
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
MCOperand decodeSpecialReg32(unsigned Val) const
int getTTmpIdx(unsigned Val) const
Instances of this class represent operands of the MCInst class.