LLVM 19.0.0git
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This file implements the targeting of the Machinelegalizer class for AMDGPU. More...
#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUTargetMachine.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "amdgpu-legalinfo" |
Variables | |
static cl::opt< bool > | EnableNewLegality ("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden) |
static constexpr unsigned | MaxRegisterSize = 1024 |
static const LLT | S1 = LLT::scalar(1) |
static const LLT | S8 = LLT::scalar(8) |
static const LLT | S16 = LLT::scalar(16) |
static const LLT | S32 = LLT::scalar(32) |
static const LLT | S64 = LLT::scalar(64) |
static const LLT | S96 = LLT::scalar(96) |
static const LLT | S128 = LLT::scalar(128) |
static const LLT | S160 = LLT::scalar(160) |
static const LLT | S224 = LLT::scalar(224) |
static const LLT | S256 = LLT::scalar(256) |
static const LLT | S512 = LLT::scalar(512) |
static const LLT | MaxScalar = LLT::scalar(MaxRegisterSize) |
static const LLT | V2S8 = LLT::fixed_vector(2, 8) |
static const LLT | V2S16 = LLT::fixed_vector(2, 16) |
static const LLT | V4S16 = LLT::fixed_vector(4, 16) |
static const LLT | V6S16 = LLT::fixed_vector(6, 16) |
static const LLT | V8S16 = LLT::fixed_vector(8, 16) |
static const LLT | V10S16 = LLT::fixed_vector(10, 16) |
static const LLT | V12S16 = LLT::fixed_vector(12, 16) |
static const LLT | V16S16 = LLT::fixed_vector(16, 16) |
static const LLT | V2S32 = LLT::fixed_vector(2, 32) |
static const LLT | V3S32 = LLT::fixed_vector(3, 32) |
static const LLT | V4S32 = LLT::fixed_vector(4, 32) |
static const LLT | V5S32 = LLT::fixed_vector(5, 32) |
static const LLT | V6S32 = LLT::fixed_vector(6, 32) |
static const LLT | V7S32 = LLT::fixed_vector(7, 32) |
static const LLT | V8S32 = LLT::fixed_vector(8, 32) |
static const LLT | V9S32 = LLT::fixed_vector(9, 32) |
static const LLT | V10S32 = LLT::fixed_vector(10, 32) |
static const LLT | V11S32 = LLT::fixed_vector(11, 32) |
static const LLT | V12S32 = LLT::fixed_vector(12, 32) |
static const LLT | V16S32 = LLT::fixed_vector(16, 32) |
static const LLT | V32S32 = LLT::fixed_vector(32, 32) |
static const LLT | V2S64 = LLT::fixed_vector(2, 64) |
static const LLT | V3S64 = LLT::fixed_vector(3, 64) |
static const LLT | V4S64 = LLT::fixed_vector(4, 64) |
static const LLT | V5S64 = LLT::fixed_vector(5, 64) |
static const LLT | V6S64 = LLT::fixed_vector(6, 64) |
static const LLT | V7S64 = LLT::fixed_vector(7, 64) |
static const LLT | V8S64 = LLT::fixed_vector(8, 64) |
static const LLT | V16S64 = LLT::fixed_vector(16, 64) |
static const LLT | V2S128 = LLT::fixed_vector(2, 128) |
static const LLT | V4S128 = LLT::fixed_vector(4, 128) |
static std::initializer_list< LLT > | AllScalarTypes |
static std::initializer_list< LLT > | AllS16Vectors |
static std::initializer_list< LLT > | AllS32Vectors |
static std::initializer_list< LLT > | AllS64Vectors |
static constexpr unsigned | SPDenormModeBitField |
static constexpr unsigned | FPEnvModeBitField |
static constexpr unsigned | FPEnvTrapBitField |
This file implements the targeting of the Machinelegalizer class for AMDGPU.
Definition in file AMDGPULegalizerInfo.cpp.
#define DEBUG_TYPE "amdgpu-legalinfo" |
Definition at line 37 of file AMDGPULegalizerInfo.cpp.
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Definition at line 3209 of file AMDGPULegalizerInfo.cpp.
References llvm::MachineInstr::FmAfn, llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and Options.
Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().
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Definition at line 188 of file AMDGPULegalizerInfo.cpp.
References getBitcastRegisterType().
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Definition at line 195 of file AMDGPULegalizerInfo.cpp.
References assert(), llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.
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Definition at line 5741 of file AMDGPULegalizerInfo.cpp.
References B, and llvm::Format.
Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad().
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Definition at line 639 of file AMDGPULegalizerInfo.cpp.
References B, castBufferRsrcToV4I32(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), Idx, MI, and llvm::MachineOperand::setReg().
Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), and llvm::AMDGPULegalizerInfo::legalizeStore().
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Mutates IR (typicaly a load instruction) to use a <4 x s32> as the initial type of the operand idx
and then to transform it to a p8
via bitcasts and inttoptr.
In addition, handle vectors of p8. Returns the new type.
Definition at line 579 of file AMDGPULegalizerInfo.cpp.
References B, getBufferRsrcRegisterType(), getBufferRsrcScalarType(), llvm::MachineOperand::getReg(), hasBufferRsrcWorkaround(), I, Idx, MI, MRI, S32, llvm::LLT::scalar(), and llvm::MachineOperand::setReg().
Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().
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Cast a buffer resource (an address space 8 pointer) into a 4xi32, which is the form in which the value must be in order to be passed to the low-level representations used for MUBUF/MTBUF intrinsics.
This is a hack, which is needed in order to account for the fact that we can't define a register class for s128 without breaking SelectionDAG.
Definition at line 620 of file AMDGPULegalizerInfo.cpp.
References B, getBufferRsrcRegisterType(), getBufferRsrcScalarType(), I, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::LLT::scalar().
Referenced by castBufferRsrcArgToV4I32(), and llvm::AMDGPULegalizerInfo::fixStoreSourceType().
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Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg.
Definition at line 6124 of file AMDGPULegalizerInfo.cpp.
References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S32, llvm::LLT::scalar(), and llvm::SmallVectorBase< Size_T >::size().
Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().
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Definition at line 272 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and llvm::LLT::scalar().
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
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Definition at line 4463 of file AMDGPULegalizerInfo.cpp.
References B, S32, and llvm::LLT::scalar().
Referenced by llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl().
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Definition at line 2452 of file AMDGPULegalizerInfo.cpp.
References B, llvm::Hi, S32, and llvm::LLT::scalar().
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Definition at line 110 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getElementType(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::scalarOrVector(), and Size.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
Definition at line 176 of file AMDGPULegalizerInfo.cpp.
References llvm::ElementCount::getFixed(), llvm::LLT::getSizeInBits(), llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), and Size.
Referenced by bitcastToRegisterType(), and llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().
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Definition at line 5903 of file AMDGPULegalizerInfo.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPULegalizerInfo::legalizeBufferAtomic().
Definition at line 169 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::fixed_vector(), llvm::LLT::getElementCount(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::LLT::isVector(), and llvm::LLT::scalar().
Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().
Definition at line 162 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getElementCount(), llvm::LLT::isVector(), llvm::LLT::scalar(), and llvm::LLT::vector().
Referenced by castBufferRsrcFromV4I32(), and castBufferRsrcToV4I32().
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Definition at line 5358 of file AMDGPULegalizerInfo.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic().
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Definition at line 3294 of file AMDGPULegalizerInfo.cpp.
References B, llvm::FMul, X, and Y.
Definition at line 63 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits(), llvm::Log2_32_Ceil(), and llvm::LLT::scalar().
Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().
Definition at line 56 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), and llvm::Log2_32_Ceil().
Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().
Definition at line 471 of file AMDGPULegalizerInfo.cpp.
References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::LLT::getAddressSpace(), llvm::LLT::getElementType(), hasBufferRsrcWorkaround(), llvm::LLT::isPointer(), and llvm::LLT::isVector().
Referenced by castBufferRsrcArgToV4I32(), castBufferRsrcFromV4I32(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), hasBufferRsrcWorkaround(), isLoadStoreLegal(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeSBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeStore(), and loadStoreBitcastWorkaround().
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Definition at line 264 of file AMDGPULegalizerInfo.cpp.
References llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), and isRegisterType().
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Return true if the value is a known valid address, such that a null check is not necessary.
Definition at line 2238 of file AMDGPULegalizerInfo.cpp.
References llvm::ConstantInt::getSExtValue(), MRI, and TM.
Referenced by llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().
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Definition at line 505 of file AMDGPULegalizerInfo.cpp.
References hasBufferRsrcWorkaround(), isLoadStoreSizeLegal(), isRegisterType(), loadStoreBitcastWorkaround(), and llvm::LegalityQuery::Types.
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Definition at line 398 of file AMDGPULegalizerInfo.cpp.
References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), assert(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), maxSizeForAddrSpace(), llvm::LegalityQuery::MMODescrs, llvm::LegalityQuery::Opcode, RegSize, Size, and llvm::LegalityQuery::Types.
Referenced by isLoadStoreLegal().
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Definition at line 4149 of file AMDGPULegalizerInfo.cpp.
References llvm::getIConstantVRegSExtVal(), MI, and MRI.
Referenced by llvm::MCAsmParserExtension::ParseDirectiveCGProfile(), and verifyCFIntrinsic().
Definition at line 344 of file AMDGPULegalizerInfo.cpp.
References AllS16Vectors, AllS32Vectors, AllS64Vectors, AllScalarTypes, llvm::LLT::changeElementType(), llvm::LLT::getScalarSizeInBits(), llvm::is_contained(), llvm::LLT::isPointerOrPointerVector(), and llvm::LLT::scalar().
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().
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Definition at line 352 of file AMDGPULegalizerInfo.cpp.
References isRegisterClassType().
Definition at line 226 of file AMDGPULegalizerInfo.cpp.
References MaxRegisterSize, and Size.
Referenced by isRegisterType(), and shouldBitcastLoadStoreType().
Definition at line 243 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterVectorType(), and llvm::LLT::isVector().
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), isIllegalRegisterType(), isLoadStoreLegal(), isRegisterType(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), and shouldBitcastLoadStoreType().
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Definition at line 255 of file AMDGPULegalizerInfo.cpp.
References isRegisterType().
Definition at line 230 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits().
Referenced by shouldBitcastLoadStoreType().
Definition at line 235 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), and llvm::LLT::getSizeInBits().
Referenced by isRegisterType().
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Definition at line 72 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
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Definition at line 360 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits(), and llvm::LLT::isVector().
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Definition at line 93 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getNumElements(), llvm::LLT::getScalarType(), and llvm::LLT::getSizeInBits().
Definition at line 485 of file AMDGPULegalizerInfo.cpp.
References EnableNewLegality, llvm::LLT::getScalarSizeInBits(), llvm::LLT::getSizeInBits(), hasBufferRsrcWorkaround(), llvm::LLT::isPointerVector(), llvm::LLT::isVector(), and Size.
Referenced by isLoadStoreLegal(), and shouldBitcastLoadStoreType().
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Definition at line 371 of file AMDGPULegalizerInfo.cpp.
References llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::AMDGPUAS::LOCAL_ADDRESS, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Referenced by isLoadStoreSizeLegal(), and shouldWidenLoad().
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Definition at line 141 of file AMDGPULegalizerInfo.cpp.
References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::LLT::getSizeInBits(), and MaxRegisterSize.
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Definition at line 124 of file AMDGPULegalizerInfo.cpp.
References assert(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), and Size.
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Definition at line 3216 of file AMDGPULegalizerInfo.cpp.
References llvm::MachineFunction::getDenormalMode(), llvm::MachineFunction::getRegInfo(), llvm::APFloatBase::IEEEsingle(), llvm::DenormalMode::Input, llvm::DenormalMode::PreserveSign, and valueIsKnownNeverF32Denorm().
Referenced by llvm::AMDGPULegalizerInfo::getScaledLogInput(), llvm::AMDGPULegalizerInfo::legalizeFExp2(), llvm::AMDGPULegalizerInfo::legalizeFExpUnsafe(), and llvm::AMDGPULegalizerInfo::legalizeFSQRTF32().
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Definition at line 219 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getNumElements(), and llvm::LLT::isVector().
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Definition at line 101 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), and llvm::LLT::getNumElements().
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
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Turn a set of s16 typed registers in AddrRegs
into a dword sized vector with s16 typed elements.
Definition at line 6063 of file AMDGPULegalizerInfo.cpp.
References assert(), B, llvm::LLT::fixed_vector(), llvm::SrcOp::getReg(), I, Intr, MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S16, llvm::LLT::scalar(), and V2S16.
Referenced by llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().
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Definition at line 4305 of file AMDGPULegalizerInfo.cpp.
References B, llvm::CallingConv::C, and MI.
Referenced by llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic().
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Return true if a load or store of the type should be lowered with a bitcast to a different type.
Definition at line 513 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), isRegisterSize(), isRegisterType(), isRegisterVectorElementType(), llvm::LLT::isVector(), loadStoreBitcastWorkaround(), and Size.
Referenced by llvm::AMDGPULegalizerInfo::legalizeSBufferLoad().
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Definition at line 566 of file AMDGPULegalizerInfo.cpp.
References llvm::LegalityQuery::MMODescrs, shouldWidenLoad(), and llvm::LegalityQuery::Types.
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Return true if we should legalize a load by widening an odd sized memory access up to the alignment.
Note this case when the memory access itself changes, not the size of the result register.
Definition at line 532 of file AMDGPULegalizerInfo.cpp.
References llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::CallingConv::Fast, llvm::LLT::getSizeInBits(), llvm::isPowerOf2_32(), maxSizeForAddrSpace(), llvm::MachineMemOperand::MOLoad, and llvm::NextPowerOf2().
Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad(), and shouldWidenLoad().
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Definition at line 86 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits().
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Definition at line 3724 of file AMDGPULegalizerInfo.cpp.
References llvm::getOpcodeDef(), and MRI.
Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().
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Definition at line 4854 of file AMDGPULegalizerInfo.cpp.
References B, llvm::Enable, FP_DENORM_FLUSH_NONE, and SPDenormModeBitField.
Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32().
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Return true if it's known that Src
can never be an f32 denormal value.
Definition at line 3180 of file AMDGPULegalizerInfo.cpp.
References DefMI, getIntrinsicID(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), MRI, and llvm::LLT::scalar().
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Definition at line 205 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.
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Definition at line 212 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), and Size.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
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Definition at line 4158 of file AMDGPULegalizerInfo.cpp.
References llvm::MachineBasicBlock::end(), llvm::MachineFunction::end(), llvm::eraseInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), isNot(), MI, MRI, and UseMI.
Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsic().
Definition at line 3016 of file AMDGPULegalizerInfo.cpp.
References llvm::LLT::changeElementCount(), llvm::ElementCount::getFixed(), llvm::LLT::getNumElements(), llvm::LLT::getSizeInBits(), llvm::LLT::isVector(), llvm::PowerOf2Ceil(), and llvm::LLT::scalar().
Referenced by llvm::AMDGPULegalizerInfo::legalizeLoad().
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Definition at line 333 of file AMDGPULegalizerInfo.cpp.
Referenced by isRegisterClassType().
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Definition at line 336 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().
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Definition at line 340 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and isRegisterClassType().
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Definition at line 330 of file AMDGPULegalizerInfo.cpp.
Referenced by isRegisterClassType().
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Referenced by loadStoreBitcastWorkaround().
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Definition at line 6956 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), and llvm::AMDGPULegalizerInfo::legalizeSetFPEnv().
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Definition at line 6959 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), and llvm::AMDGPULegalizerInfo::legalizeSetFPEnv().
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Definition at line 53 of file AMDGPULegalizerInfo.cpp.
Referenced by isRegisterSize(), and moreElementsToNextExistingRegClass().
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Definition at line 293 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
Definition at line 282 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::BinaryOperator::BinaryOperator(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::StringSwitch< T, R >::Cases(), llvm::StringSwitch< T, R >::CasesLower(), llvm::BinaryOperator::Create(), llvm::CmpInst::Create(), llvm::SelectInst::Create(), CreateAdd(), CreateMul(), CreateNeg(), llvm::CmpInst::CreateWithCopiedFlags(), llvm::PMDataManager::dumpPassInfo(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), foldShuffleOfUnaryOps(), llvm::DILocation::getMergedLocation(), gsiRecordCmp(), INITIALIZE_PASS(), llvm::isEqual(), llvm::MipsCCState::isF128SoftLibCall(), llvm::MipsMCExpr::isGpOff(), isMemOPCandidate(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF32(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC_F64_TO_F16(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), matchBinaryPermuteShuffle(), llvm::CombinerHelper::matchCommuteShift(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performVectorAddSubExtCombine(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), runImpl(), llvm::set_difference(), llvm::set_intersect(), llvm::set_intersection(), llvm::set_intersection_impl(), llvm::set_is_subset(), llvm::set_subtract(), llvm::set_union(), simplifyLoopInst(), and llvm::GISelCSEInfo::verify().
Definition at line 288 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
Definition at line 284 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), llvm::AMDGPURegisterBankInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), llvm::AMDGPULegalizerInfo::legalizeBuildVector(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV16(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::LegalizerHelper::lowerFPTRUNC(), packImage16bitOpsToDwords(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().
Definition at line 289 of file AMDGPULegalizerInfo.cpp.
Definition at line 290 of file AMDGPULegalizerInfo.cpp.
Definition at line 291 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
Definition at line 285 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::SITargetLowering::allocateSpecialEntryInputVGPRs(), llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::AMDGPULegalizerInfo::buildAbsGlobalAddress(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), castBufferRsrcFromV4I32(), convertImageAddrToPacked(), emitReciprocalU64(), extractF64Exponent(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPURegisterBankInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), llvm::AMDGPULegalizerInfo::legalizeBuildVector(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV16(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeMul(), llvm::AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(), llvm::AMDGPULegalizerInfo::legalizeSetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::AMDGPULegalizerInfo::legalizeWaveID(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC_F64_TO_F16(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::AMDGPUCallLowering::passSpecialInputs(), llvm::PPCLegalizerInfo::PPCLegalizerInfo(), reinsertVectorIndexAdd(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), llvm::AMDGPURegisterBankInfo::splitBufferOffsets(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), and unpackV2S16ToS32().
Definition at line 292 of file AMDGPULegalizerInfo.cpp.
Definition at line 286 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPULegalizerInfo::buildMultiply(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeSetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(), llvm::LegalizerHelper::lowerFPTOSI(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerFPTRUNC(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().
Definition at line 283 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::StringSwitch< T, R >::Cases(), and llvm::PPCLegalizerInfo::PPCLegalizerInfo().
Definition at line 287 of file AMDGPULegalizerInfo.cpp.
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staticconstexpr |
Definition at line 4849 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::legalizeFDIV32(), and toggleSPDenormMode().
Definition at line 300 of file AMDGPULegalizerInfo.cpp.
Definition at line 312 of file AMDGPULegalizerInfo.cpp.
Definition at line 313 of file AMDGPULegalizerInfo.cpp.
Definition at line 301 of file AMDGPULegalizerInfo.cpp.
Definition at line 314 of file AMDGPULegalizerInfo.cpp.
Definition at line 302 of file AMDGPULegalizerInfo.cpp.
Definition at line 315 of file AMDGPULegalizerInfo.cpp.
Definition at line 325 of file AMDGPULegalizerInfo.cpp.
Definition at line 327 of file AMDGPULegalizerInfo.cpp.
Definition at line 296 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), and packImage16bitOpsToDwords().
Definition at line 304 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
Definition at line 318 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().
Definition at line 295 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo().
Definition at line 316 of file AMDGPULegalizerInfo.cpp.
Definition at line 305 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().
Definition at line 319 of file AMDGPULegalizerInfo.cpp.
Definition at line 328 of file AMDGPULegalizerInfo.cpp.
Definition at line 297 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo(), and llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic().
Definition at line 306 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().
Definition at line 320 of file AMDGPULegalizerInfo.cpp.
Definition at line 307 of file AMDGPULegalizerInfo.cpp.
Definition at line 321 of file AMDGPULegalizerInfo.cpp.
Definition at line 298 of file AMDGPULegalizerInfo.cpp.
Definition at line 308 of file AMDGPULegalizerInfo.cpp.
Definition at line 322 of file AMDGPULegalizerInfo.cpp.
Definition at line 309 of file AMDGPULegalizerInfo.cpp.
Definition at line 323 of file AMDGPULegalizerInfo.cpp.
Definition at line 299 of file AMDGPULegalizerInfo.cpp.
Referenced by llvm::PPCLegalizerInfo::PPCLegalizerInfo().
Definition at line 310 of file AMDGPULegalizerInfo.cpp.
Definition at line 324 of file AMDGPULegalizerInfo.cpp.
Definition at line 311 of file AMDGPULegalizerInfo.cpp.