LLVM  12.0.0git
Macros | Functions | Variables
AMDGPULegalizerInfo.cpp File Reference

This file implements the targeting of the Machinelegalizer class for AMDGPU. More...

#include "AMDGPULegalizerInfo.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
Include dependency graph for AMDGPULegalizerInfo.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "amdgpu-legalinfo"
 

Functions

static LLT getPow2VectorType (LLT Ty)
 
static LLT getPow2ScalarType (LLT Ty)
 
static LegalityPredicate isSmallOddVector (unsigned TypeIdx)
 
static LegalityPredicate isWideVec16 (unsigned TypeIdx)
 
static LegalizeMutation oneMoreElement (unsigned TypeIdx)
 
static LegalizeMutation fewerEltsToSize64Vector (unsigned TypeIdx)
 
static LegalizeMutation moreEltsToNext32Bit (unsigned TypeIdx)
 
static LegalizeMutation bitcastToRegisterType (unsigned TypeIdx)
 
static LegalityPredicate vectorSmallerThan (unsigned TypeIdx, unsigned Size)
 
static LegalityPredicate vectorWiderThan (unsigned TypeIdx, unsigned Size)
 
static LegalityPredicate numElementsNotEven (unsigned TypeIdx)
 
static bool isRegisterSize (unsigned Size)
 
static bool isRegisterVectorElementType (LLT EltTy)
 
static bool isRegisterVectorType (LLT Ty)
 
static bool isRegisterType (LLT Ty)
 
static LegalityPredicate isRegisterType (unsigned TypeIdx)
 
static LegalityPredicate elementTypeIsLegal (unsigned TypeIdx)
 
static LegalityPredicate isWideScalarTruncStore (unsigned TypeIdx)
 
static unsigned maxSizeForAddrSpace (const GCNSubtarget &ST, unsigned AS, bool IsLoad)
 
static bool isLoadStoreSizeLegal (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
 
static bool loadStoreBitcastWorkaround (const LLT Ty)
 
static bool isLoadStoreLegal (const GCNSubtarget &ST, const LegalityQuery &Query, unsigned Opcode)
 
static MachineInstrBuilder extractF64Exponent (unsigned Hi, MachineIRBuilder &B)
 
static Register stripAnySourceMods (Register OrigSrc, MachineRegisterInfo &MRI)
 
static MachineInstrverifyCFIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr *&Br, MachineBasicBlock *&UncondBrTarget)
 
static std::pair< Register, RegisteremitReciprocalU64 (MachineIRBuilder &B, Register Val)
 
static void toggleSPDenormMode (bool Enable, MachineIRBuilder &B, const GCNSubtarget &ST, AMDGPU::SIModeRegisterDefaults Mode)
 
static unsigned getBufferAtomicPseudo (Intrinsic::ID IntrID)
 
static void packImageA16AddressToDwords (MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, int AddrIdx, int DimIdx, int EndIdx, int NumGradients)
 Turn a set of s16 typed registers in A16AddrRegs into a dword sized vector with s16 typed elements. More...
 
static void convertImageAddrToPacked (MachineIRBuilder &B, MachineInstr &MI, int DimIdx, int NumVAddrs)
 Convert from separate vaddr components to a single vector address register, and replace the remaining operands with $noreg. More...
 

Variables

static cl::opt< boolEnableNewLegality ("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)
 
static constexpr unsigned MaxRegisterSize = 1024
 

Detailed Description

This file implements the targeting of the Machinelegalizer class for AMDGPU.

Todo:
This should be generated by TableGen.

Definition in file AMDGPULegalizerInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-legalinfo"

Definition at line 31 of file AMDGPULegalizerInfo.cpp.

Function Documentation

◆ bitcastToRegisterType()

static LegalizeMutation bitcastToRegisterType ( unsigned  TypeIdx)
static

◆ convertImageAddrToPacked()

static void convertImageAddrToPacked ( MachineIRBuilder B,
MachineInstr MI,
int  DimIdx,
int  NumVAddrs 
)
static

◆ elementTypeIsLegal()

static LegalityPredicate elementTypeIsLegal ( unsigned  TypeIdx)
static

◆ emitReciprocalU64()

static std::pair<Register, Register> emitReciprocalU64 ( MachineIRBuilder B,
Register  Val 
)
static

◆ extractF64Exponent()

static MachineInstrBuilder extractF64Exponent ( unsigned  Hi,
MachineIRBuilder B 
)
static

◆ fewerEltsToSize64Vector()

static LegalizeMutation fewerEltsToSize64Vector ( unsigned  TypeIdx)
static

◆ getBufferAtomicPseudo()

static unsigned getBufferAtomicPseudo ( Intrinsic::ID  IntrID)
static

◆ getPow2ScalarType()

static LLT getPow2ScalarType ( LLT  Ty)
static

◆ getPow2VectorType()

static LLT getPow2VectorType ( LLT  Ty)
static

◆ isLoadStoreLegal()

static bool isLoadStoreLegal ( const GCNSubtarget ST,
const LegalityQuery Query,
unsigned  Opcode 
)
static

◆ isLoadStoreSizeLegal()

static bool isLoadStoreSizeLegal ( const GCNSubtarget ST,
const LegalityQuery Query,
unsigned  Opcode 
)
static

◆ isRegisterSize()

static bool isRegisterSize ( unsigned  Size)
static

◆ isRegisterType() [1/2]

static bool isRegisterType ( LLT  Ty)
static

◆ isRegisterType() [2/2]

static LegalityPredicate isRegisterType ( unsigned  TypeIdx)
static

Definition at line 184 of file AMDGPULegalizerInfo.cpp.

References isRegisterType().

◆ isRegisterVectorElementType()

static bool isRegisterVectorElementType ( LLT  EltTy)
static

◆ isRegisterVectorType()

static bool isRegisterVectorType ( LLT  Ty)
static

◆ isSmallOddVector()

static LegalityPredicate isSmallOddVector ( unsigned  TypeIdx)
static

◆ isWideScalarTruncStore()

static LegalityPredicate isWideScalarTruncStore ( unsigned  TypeIdx)
static

◆ isWideVec16()

static LegalityPredicate isWideVec16 ( unsigned  TypeIdx)
static

◆ loadStoreBitcastWorkaround()

static bool loadStoreBitcastWorkaround ( const LLT  Ty)
static

◆ maxSizeForAddrSpace()

static unsigned maxSizeForAddrSpace ( const GCNSubtarget ST,
unsigned  AS,
bool  IsLoad 
)
static

◆ moreEltsToNext32Bit()

static LegalizeMutation moreEltsToNext32Bit ( unsigned  TypeIdx)
static

◆ numElementsNotEven()

static LegalityPredicate numElementsNotEven ( unsigned  TypeIdx)
static

◆ oneMoreElement()

static LegalizeMutation oneMoreElement ( unsigned  TypeIdx)
static

◆ packImageA16AddressToDwords()

static void packImageA16AddressToDwords ( MachineIRBuilder B,
MachineInstr MI,
SmallVectorImpl< Register > &  PackedAddrs,
int  AddrIdx,
int  DimIdx,
int  EndIdx,
int  NumGradients 
)
static

◆ stripAnySourceMods()

static Register stripAnySourceMods ( Register  OrigSrc,
MachineRegisterInfo MRI 
)
static

Definition at line 2281 of file AMDGPULegalizerInfo.cpp.

References llvm::getOpcodeDef().

Referenced by llvm::AMDGPULegalizerInfo::legalizeFFloor().

◆ toggleSPDenormMode()

static void toggleSPDenormMode ( bool  Enable,
MachineIRBuilder B,
const GCNSubtarget ST,
AMDGPU::SIModeRegisterDefaults  Mode 
)
static

◆ vectorSmallerThan()

static LegalityPredicate vectorSmallerThan ( unsigned  TypeIdx,
unsigned  Size 
)
static

◆ vectorWiderThan()

static LegalityPredicate vectorWiderThan ( unsigned  TypeIdx,
unsigned  Size 
)
static

◆ verifyCFIntrinsic()

static MachineInstr* verifyCFIntrinsic ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineInstr *&  Br,
MachineBasicBlock *&  UncondBrTarget 
)
static

Variable Documentation

◆ EnableNewLegality

cl::opt<bool> EnableNewLegality("amdgpu-global-isel-new-legality", cl::desc("Use GlobalISel desired legality, rather than try to use" "rules compatible with selection patterns"), cl::init(false), cl::ReallyHidden)
static

◆ MaxRegisterSize

constexpr unsigned MaxRegisterSize = 1024
static