LLVM  10.0.0svn
AMDGPULegalizerInfo.h
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1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
19 
20 namespace llvm {
21 
22 class GCNTargetMachine;
23 class LLVMContext;
24 class GCNSubtarget;
25 
26 /// This class provides the information for the target register banks.
28  const GCNSubtarget &ST;
29 
30 public:
32  const GCNTargetMachine &TM);
33 
35  MachineIRBuilder &MIRBuilder,
36  GISelChangeObserver &Observer) const override;
37 
38  Register getSegmentAperture(unsigned AddrSpace,
40  MachineIRBuilder &MIRBuilder) const;
41 
43  MachineIRBuilder &MIRBuilder) const;
45  MachineIRBuilder &MIRBuilder) const;
47  MachineIRBuilder &MIRBuilder) const;
49  MachineIRBuilder &MIRBuilder) const;
51  MachineIRBuilder &MIRBuilder, bool Signed) const;
53  MachineIRBuilder &MIRBuilder) const;
55  MachineIRBuilder &MIRBuilder) const;
57  MachineIRBuilder &MIRBuilder) const;
58 
60  Register Reg, LLT Ty) const;
61 
63  const ArgDescriptor *Arg) const;
67 
69  MachineIRBuilder &B) const;
70 
72  MachineIRBuilder &B) const;
74  MachineIRBuilder &MIRBuilder) const override;
75 
76 };
77 } // End llvm namespace.
78 #endif
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg) const
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
bool legalizeFDIVFast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, bool Signed) const
Abstract class that contains various methods for clients to notify about changes. ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Helper class to build MachineInstr.
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const override
Return true if MI is either legal or has been legalized and false if not legal.
This class provides the information for the target register banks.
bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, GISelChangeObserver &Observer) const override
IRTranslator LLVM IR MI
Register getLiveInRegister(MachineRegisterInfo &MRI, Register Reg, LLT Ty) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const