LLVM  10.0.0svn
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1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
19 #include "SIInstrInfo.h"
21 namespace llvm {
23 class GCNTargetMachine;
24 class LLVMContext;
25 class GCNSubtarget;
27 /// This class provides the information for the target register banks.
29  const GCNSubtarget &ST;
31 public:
33  const GCNTargetMachine &TM);
37  GISelChangeObserver &Observer) const override;
39  Register getSegmentAperture(unsigned AddrSpace,
41  MachineIRBuilder &B) const;
44  MachineIRBuilder &B) const;
46  MachineIRBuilder &B) const;
48  MachineIRBuilder &B) const;
50  MachineIRBuilder &B) const;
52  MachineIRBuilder &B, bool Signed) const;
54  MachineIRBuilder &B) const;
56  MachineIRBuilder &B) const;
58  MachineIRBuilder &B) const;
60  MachineIRBuilder &B) const;
63  Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
64  unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
67  MachineIRBuilder &B) const;
70  GISelChangeObserver &Observer) const;
73  MachineIRBuilder &B) const;
76  Register Reg, LLT Ty) const;
79  const ArgDescriptor *Arg) const;
85  MachineIRBuilder &B) const;
87  MachineIRBuilder &B) const;
89  MachineIRBuilder &B) const;
92  MachineIRBuilder &B) const;
94  MachineIRBuilder &B, unsigned AddrSpace) const;
97  Register Reg) const;
99  MachineIRBuilder &B, bool IsFormat) const;
101  MachineIRBuilder &B) const override;
103 };
104 } // End llvm namespace.
105 #endif
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const override
Return true if MI is either legal or has been legalized and false if not legal.
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer) const override
unsigned Reg
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer) const
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
Handle register layout difference for f16 images for some subtargets.
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Abstract class that contains various methods for clients to notify about changes. ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, unsigned Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
Helper class to build MachineInstr.
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
This class provides the information for the target register banks.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Interface definition for SIInstrInfo.
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
IRTranslator LLVM IR MI
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Register getLiveInRegister(MachineRegisterInfo &MRI, Register Reg, LLT Ty) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19