LLVM  8.0.0svn
AMDGPUMCInstLower.cpp
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1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12 //
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #include "AMDGPUAsmPrinter.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
21 #include "R600AsmPrinter.h"
22 #include "SIInstrInfo.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/MC/MCCodeEmitter.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
33 #include "llvm/MC/MCStreamer.h"
35 #include "llvm/Support/Format.h"
36 #include <algorithm>
37 
38 using namespace llvm;
39 
40 namespace {
41 
42 class AMDGPUMCInstLower {
43  MCContext &Ctx;
44  const TargetSubtargetInfo &ST;
45  const AsmPrinter &AP;
46 
47  const MCExpr *getLongBranchBlockExpr(const MachineBasicBlock &SrcBB,
48  const MachineOperand &MO) const;
49 
50 public:
51  AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST,
52  const AsmPrinter &AP);
53 
54  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
55 
56  /// Lower a MachineInstr to an MCInst
57  void lower(const MachineInstr *MI, MCInst &OutMI) const;
58 
59 };
60 
61 class R600MCInstLower : public AMDGPUMCInstLower {
62 public:
63  R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
64  const AsmPrinter &AP);
65 
66  /// Lower a MachineInstr to an MCInst
67  void lower(const MachineInstr *MI, MCInst &OutMI) const;
68 };
69 
70 
71 } // End anonymous namespace
72 
73 #include "AMDGPUGenMCPseudoLowering.inc"
74 
75 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
76  const TargetSubtargetInfo &st,
77  const AsmPrinter &ap):
78  Ctx(ctx), ST(st), AP(ap) { }
79 
80 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
81  switch (MOFlags) {
82  default:
94  }
95 }
96 
97 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
98  const MachineBasicBlock &SrcBB,
99  const MachineOperand &MO) const {
100  const MCExpr *DestBBSym
101  = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
102  const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
103 
104  assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
105  ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
106 
107  // s_getpc_b64 returns the address of next instruction.
108  const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
109  SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
110 
112  return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
113 
115  return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
116 }
117 
118 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
119  MCOperand &MCOp) const {
120  switch (MO.getType()) {
121  default:
122  llvm_unreachable("unknown operand type");
124  MCOp = MCOperand::createImm(MO.getImm());
125  return true;
128  return true;
130  if (MO.getTargetFlags() != 0) {
131  MCOp = MCOperand::createExpr(
132  getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
133  } else {
134  MCOp = MCOperand::createExpr(
136  }
137 
138  return true;
139  }
141  const GlobalValue *GV = MO.getGlobal();
143  AP.getNameWithPrefix(SymbolName, GV);
144  MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
145  const MCExpr *SymExpr =
147  const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
148  MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
149  MCOp = MCOperand::createExpr(Expr);
150  return true;
151  }
153  MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
154  Sym->setExternal(true);
155  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
156  MCOp = MCOperand::createExpr(Expr);
157  return true;
158  }
160  // Regmasks are like implicit defs.
161  return false;
162  }
163 }
164 
165 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
166  unsigned Opcode = MI->getOpcode();
167  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
168 
169  // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
170  // need to select it to the subtarget specific version, and there's no way to
171  // do that with a single pseudo source operation.
172  if (Opcode == AMDGPU::S_SETPC_B64_return)
173  Opcode = AMDGPU::S_SETPC_B64;
174  else if (Opcode == AMDGPU::SI_CALL) {
175  // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
176  // called function (which we need to remove here).
177  OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
178  MCOperand Dest, Src;
179  lowerOperand(MI->getOperand(0), Dest);
180  lowerOperand(MI->getOperand(1), Src);
181  OutMI.addOperand(Dest);
182  OutMI.addOperand(Src);
183  return;
184  } else if (Opcode == AMDGPU::SI_TCRETURN) {
185  // TODO: How to use branch immediate and avoid register+add?
186  Opcode = AMDGPU::S_SETPC_B64;
187  }
188 
189  int MCOpcode = TII->pseudoToMCOpcode(Opcode);
190  if (MCOpcode == -1) {
192  C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
193  "a target-specific version: " + Twine(MI->getOpcode()));
194  }
195 
196  OutMI.setOpcode(MCOpcode);
197 
198  for (const MachineOperand &MO : MI->explicit_operands()) {
199  MCOperand MCOp;
200  lowerOperand(MO, MCOp);
201  OutMI.addOperand(MCOp);
202  }
203 }
204 
206  MCOperand &MCOp) const {
207  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
208  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
209  return MCInstLowering.lowerOperand(MO, MCOp);
210 }
211 
213  const Constant *CV,
215  // TargetMachine does not support llvm-style cast. Use C++-style cast.
216  // This is safe since TM is always of type AMDGPUTargetMachine or its
217  // derived class.
218  auto &AT = static_cast<const AMDGPUTargetMachine&>(TM);
219  auto *CE = dyn_cast<ConstantExpr>(CV);
220 
221  // Lower null pointers in private and local address space.
222  // Clang generates addrspacecast for null pointers in private and local
223  // address space, which needs to be lowered.
224  if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
225  auto Op = CE->getOperand(0);
226  auto SrcAddr = Op->getType()->getPointerAddressSpace();
227  if (Op->isNullValue() && AT.getNullPointerValue(SrcAddr) == 0) {
228  auto DstAddr = CE->getType()->getPointerAddressSpace();
229  return MCConstantExpr::create(AT.getNullPointerValue(DstAddr),
230  OutContext);
231  }
232  }
233  return nullptr;
234 }
235 
237  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
238  return E;
239  return AsmPrinter::lowerConstant(CV);
240 }
241 
244  return;
245 
246  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
247  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
248 
249  StringRef Err;
250  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
252  C.emitError("Illegal instruction detected: " + Err);
253  MI->print(errs());
254  }
255 
256  if (MI->isBundle()) {
257  const MachineBasicBlock *MBB = MI->getParent();
259  while (I != MBB->instr_end() && I->isInsideBundle()) {
260  EmitInstruction(&*I);
261  ++I;
262  }
263  } else {
264  // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
265  // placeholder terminator instructions and should only be printed as
266  // comments.
267  if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
268  if (isVerbose()) {
269  SmallVector<char, 16> BBStr;
270  raw_svector_ostream Str(BBStr);
271 
272  const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
273  const MCSymbolRefExpr *Expr
275  Expr->print(Str, MAI);
276  OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
277  }
278 
279  return;
280  }
281 
282  if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
283  if (isVerbose())
284  OutStreamer->emitRawComment(" return to shader part epilog");
285  return;
286  }
287 
288  if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
289  if (isVerbose())
290  OutStreamer->emitRawComment(" wave barrier");
291  return;
292  }
293 
294  if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
295  if (isVerbose())
296  OutStreamer->emitRawComment(" divergent unreachable");
297  return;
298  }
299 
300  MCInst TmpInst;
301  MCInstLowering.lower(MI, TmpInst);
302  EmitToStreamer(*OutStreamer, TmpInst);
303 
304 #ifdef EXPENSIVE_CHECKS
305  // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
306  // work correctly for the generic CPU).
307  //
308  // The isPseudo check really shouldn't be here, but unfortunately there are
309  // some negative lit tests that depend on being able to continue through
310  // here even when pseudo instructions haven't been lowered.
311  if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU())) {
313  SmallVector<char, 16> CodeBytes;
314  raw_svector_ostream CodeStream(CodeBytes);
315 
316  std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
318  InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
319 
320  assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
321  }
322 #endif
323 
324  if (STI.dumpCode()) {
325  // Disassemble instruction/operands to text.
326  DisasmLines.resize(DisasmLines.size() + 1);
327  std::string &DisasmLine = DisasmLines.back();
328  raw_string_ostream DisasmStream(DisasmLine);
329 
330  AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
331  *STI.getInstrInfo(),
332  *STI.getRegisterInfo());
333  InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
334 
335  // Disassemble instruction/operands to hex representation.
337  SmallVector<char, 16> CodeBytes;
338  raw_svector_ostream CodeStream(CodeBytes);
339 
340  auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
341  MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
342  InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
344  HexLines.resize(HexLines.size() + 1);
345  std::string &HexLine = HexLines.back();
346  raw_string_ostream HexStream(HexLine);
347 
348  for (size_t i = 0; i < CodeBytes.size(); i += 4) {
349  unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
350  HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
351  }
352 
353  DisasmStream.flush();
354  DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
355  }
356  }
357 }
358 
359 R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
360  const AsmPrinter &AP) :
361  AMDGPUMCInstLower(Ctx, ST, AP) { }
362 
363 void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
364  OutMI.setOpcode(MI->getOpcode());
365  for (const MachineOperand &MO : MI->explicit_operands()) {
366  MCOperand MCOp;
367  lowerOperand(MO, MCOp);
368  OutMI.addOperand(MCOp);
369  }
370 }
371 
373  const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
374  R600MCInstLower MCInstLowering(OutContext, STI, *this);
375 
376  StringRef Err;
377  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
379  C.emitError("Illegal instruction detected: " + Err);
380  MI->print(errs());
381  }
382 
383  if (MI->isBundle()) {
384  const MachineBasicBlock *MBB = MI->getParent();
386  while (I != MBB->instr_end() && I->isInsideBundle()) {
387  EmitInstruction(&*I);
388  ++I;
389  }
390  } else {
391  MCInst TmpInst;
392  MCInstLowering.lower(MI, TmpInst);
393  EmitToStreamer(*OutStreamer, TmpInst);
394  }
395 }
396 
398  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
399  return E;
400  return AsmPrinter::lowerConstant(CV);
401 }
unsigned getTargetFlags() const
uint64_t CallInst * C
void EmitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
AMDGPU specific subclass of TargetSubtarget.
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:465
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI)
tblgen&#39;erated driver function for lowering simple MI->MC pseudo instructions.
unsigned getReg() const
getReg - Returns the register number.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
const SIInstrInfo * getInstrInfo() const override
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:510
MachineBasicBlock reference.
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
Mask of preserved registers.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
void setExternal(bool Value) const
Definition: MCSymbol.h:394
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Name of external global symbol.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:166
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
const char * getSymbolName() const
Context object for machine code objects.
Definition: MCContext.h:63
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:885
void EmitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
bool isBundle() const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
Streaming object file generation interface.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:460
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:199
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
bool dumpCode() const
Address of a global value.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:42
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:619
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const GlobalValue * getGlobal() const
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:81
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
const R600InstrInfo * getInstrInfo() const override
self_iterator getIterator()
Definition: ilist_node.h:82
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
The AMDGPU TargetMachine interface definition for hw codgen targets.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
size_t size() const
Definition: SmallVector.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)
Iterator for intrusive lists based on ilist_node.
std::vector< std::string > HexLines
void setOpcode(unsigned Op)
Definition: MCInst.h:173
virtual const MCExpr * lowerConstant(const Constant *CV)
Lower the specified LLVM Constant to an MCExpr.
R600 Assembly printer class.
MachineOperand class - Representation of each machine instruction operand.
static const MCExpr * lowerAddrSpaceCast(const TargetMachine &TM, const Constant *CV, MCContext &OutContext)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:229
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
std::vector< std::string > DisasmLines
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Interface definition for SIInstrInfo.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
AMDGPU Assembly printer class.
Generic base class for all target subtargets.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:483
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:295
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Wrapper for MCInstLowering.lowerOperand() for the tblgen&#39;erated pseudo lowering.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
const SIRegisterInfo * getRegisterInfo() const override