LLVM  9.0.0svn
AMDGPUMacroFusion.cpp
Go to the documentation of this file.
1 //===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file contains the AMDGPU implementation of the DAG scheduling
10 /// mutation to pair instructions back to back.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUMacroFusion.h"
15 #include "AMDGPUSubtarget.h"
16 #include "SIInstrInfo.h"
18 
20 
21 using namespace llvm;
22 
23 namespace {
24 
25 /// Check if the instr pair, FirstMI and SecondMI, should be fused
26 /// together. Given SecondMI, when FirstMI is unspecified, then check if
27 /// SecondMI may be part of a fused pair at all.
28 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
29  const TargetSubtargetInfo &TSI,
30  const MachineInstr *FirstMI,
31  const MachineInstr &SecondMI) {
32  const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_);
33 
34  switch (SecondMI.getOpcode()) {
35  case AMDGPU::V_ADDC_U32_e64:
36  case AMDGPU::V_SUBB_U32_e64:
37  case AMDGPU::V_CNDMASK_B32_e64: {
38  // Try to cluster defs of condition registers to their uses. This improves
39  // the chance VCC will be available which will allow shrinking to VOP2
40  // encodings.
41  if (!FirstMI)
42  return true;
43 
44  const MachineBasicBlock &MBB = *FirstMI->getParent();
45  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
47  const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
48  AMDGPU::OpName::src2);
49  return FirstMI->definesRegister(Src2->getReg(), TRI);
50  }
51  default:
52  return false;
53  }
54 
55  return false;
56 }
57 
58 } // end namespace
59 
60 
61 namespace llvm {
62 
63 std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () {
65 }
66 
67 } // end namespace llvm
AMDGPU specific subclass of TargetSubtarget.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned const TargetRegisterInfo * TRI
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
TargetInstrInfo - Interface to description of machine instruction set.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
MachineOperand class - Representation of each machine instruction operand.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Register getReg() const
getReg - Returns the register number.