LLVM  7.0.0svn
AMDGPUMacroFusion.cpp
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1 //===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file contains the AMDGPU implementation of the DAG scheduling
11 /// mutation to pair instructions back to back.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUMacroFusion.h"
16 #include "AMDGPUSubtarget.h"
17 #include "SIInstrInfo.h"
19 
21 
22 using namespace llvm;
23 
24 namespace {
25 
26 /// Check if the instr pair, FirstMI and SecondMI, should be fused
27 /// together. Given SecondMI, when FirstMI is unspecified, then check if
28 /// SecondMI may be part of a fused pair at all.
29 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
30  const TargetSubtargetInfo &TSI,
31  const MachineInstr *FirstMI,
32  const MachineInstr &SecondMI) {
33  const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_);
34 
35  switch (SecondMI.getOpcode()) {
36  case AMDGPU::V_ADDC_U32_e64:
37  case AMDGPU::V_SUBB_U32_e64:
38  case AMDGPU::V_CNDMASK_B32_e64: {
39  // Try to cluster defs of condition registers to their uses. This improves
40  // the chance VCC will be available which will allow shrinking to VOP2
41  // encodings.
42  if (!FirstMI)
43  return true;
44 
45  const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
46  AMDGPU::OpName::src2);
47  return FirstMI->definesRegister(Src2->getReg());
48  }
49  default:
50  return false;
51  }
52 
53  return false;
54 }
55 
56 } // end namespace
57 
58 
59 namespace llvm {
60 
61 std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () {
63 }
64 
65 } // end namespace llvm
AMDGPU specific subclass of TargetSubtarget.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getReg() const
getReg - Returns the register number.
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
TargetInstrInfo - Interface to description of machine instruction set.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:995
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
MachineOperand class - Representation of each machine instruction operand.
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:60
Interface definition for SIInstrInfo.