LLVM  6.0.0svn
AMDGPURegisterBankInfo.cpp
Go to the documentation of this file.
1 //===- AMDGPURegisterBankInfo.cpp -------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the RegisterBankInfo class for
11 /// AMDGPU.
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPURegisterBankInfo.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "SIRegisterInfo.h"
22 #include "llvm/IR/Constants.h"
23 
24 #define GET_TARGET_REGBANK_IMPL
25 #include "AMDGPUGenRegisterBank.inc"
26 
27 // This file will be TableGen'ed at some point.
28 #include "AMDGPUGenRegisterBankInfo.def"
29 
30 using namespace llvm;
31 
34  TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
35 
36  // HACK: Until this is fully tablegen'd
37  static bool AlreadyInit = false;
38  if (AlreadyInit)
39  return;
40 
41  AlreadyInit = true;
42 
44  (void)RBSGPR;
45  assert(&RBSGPR == &AMDGPU::SGPRRegBank);
46 
48  (void)RBVGPR;
49  assert(&RBVGPR == &AMDGPU::VGPRRegBank);
50 
51 }
52 
54  const RegisterBank &B,
55  unsigned Size) const {
56  return RegisterBankInfo::copyCost(A, B, Size);
57 }
58 
60  const TargetRegisterClass &RC) const {
61 
62  if (TRI->isSGPRClass(&RC))
64 
66 }
67 
70  const MachineInstr &MI) const {
71 
72  const MachineFunction &MF = *MI.getParent()->getParent();
73  const MachineRegisterInfo &MRI = MF.getRegInfo();
74 
75  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
76 
77  InstructionMappings AltMappings;
78  switch (MI.getOpcode()) {
79  case TargetOpcode::G_LOAD: {
80  // FIXME: Should we be hard coding the size for these mappings?
81  const InstructionMapping &SSMapping = getInstructionMapping(
82  1, 1, getOperandsMapping(
85  2); // Num Operands
86  AltMappings.push_back(&SSMapping);
87 
88  const InstructionMapping &VVMapping = getInstructionMapping(
89  2, 1, getOperandsMapping(
92  2); // Num Operands
93  AltMappings.push_back(&VVMapping);
94 
95  // FIXME: Should this be the pointer-size (64-bits) or the size of the
96  // register that will hold the bufffer resourc (128-bits).
97  const InstructionMapping &VSMapping = getInstructionMapping(
98  3, 1, getOperandsMapping(
101  2); // Num Operands
102  AltMappings.push_back(&VSMapping);
103 
104  return AltMappings;
105 
106  }
107  default:
108  break;
109  }
111 }
112 
113 void AMDGPURegisterBankInfo::applyMappingImpl(
114  const OperandsMapper &OpdMapper) const {
115  return applyDefaultMapping(OpdMapper);
116 }
117 
118 static bool isInstrUniform(const MachineInstr &MI) {
119  if (!MI.hasOneMemOperand())
120  return false;
121 
122  const MachineMemOperand *MMO = *MI.memoperands_begin();
123  return AMDGPU::isUniformMMO(MMO);
124 }
125 
127 AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
128 
129  const MachineFunction &MF = *MI.getParent()->getParent();
130  const MachineRegisterInfo &MRI = MF.getRegInfo();
132  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
133  unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
134 
135  const ValueMapping *ValMapping;
136  const ValueMapping *PtrMapping;
137 
138  if (isInstrUniform(MI)) {
139  // We have a uniform instruction so we want to use an SMRD load
141  PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize);
142  } else {
144  // FIXME: What would happen if we used SGPRRegBankID here?
145  PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize);
146  }
147 
148  OpdsMapping[0] = ValMapping;
149  OpdsMapping[1] = PtrMapping;
151  1, 1, getOperandsMapping(OpdsMapping), MI.getNumOperands());
152  return Mapping;
153 
154  // FIXME: Do we want to add a mapping for FLAT load, or should we just
155  // handle that during instruction selection?
156 }
157 
161 
162  if (Mapping.isValid())
163  return Mapping;
164 
165  const MachineFunction &MF = *MI.getParent()->getParent();
166  const MachineRegisterInfo &MRI = MF.getRegInfo();
168 
169  bool IsComplete = true;
170  switch (MI.getOpcode()) {
171  default:
172  IsComplete = false;
173  break;
174  case AMDGPU::G_CONSTANT: {
175  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
176  OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
177  break;
178  }
179  case AMDGPU::G_GEP: {
180  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
181  if (!MI.getOperand(i).isReg())
182  continue;
183 
184  unsigned Size = MRI.getType(MI.getOperand(i).getReg()).getSizeInBits();
185  OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
186  }
187  break;
188  }
189  case AMDGPU::G_STORE: {
190  assert(MI.getOperand(0).isReg());
191  unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
192  // FIXME: We need to specify a different reg bank once scalar stores
193  // are supported.
194  const ValueMapping *ValMapping =
196  // FIXME: Depending on the type of store, the pointer could be in
197  // the SGPR Reg bank.
198  // FIXME: Pointer size should be based on the address space.
199  const ValueMapping *PtrMapping =
201 
202  OpdsMapping[0] = ValMapping;
203  OpdsMapping[1] = PtrMapping;
204  break;
205  }
206 
207  case AMDGPU::G_LOAD:
208  return getInstrMappingForLoad(MI);
209  }
210 
211  if (!IsComplete) {
212  unsigned BankID = AMDGPU::SGPRRegBankID;
213 
214  unsigned Size = 0;
215  for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx) {
216  // If the operand is not a register default to the size of the previous
217  // operand.
218  // FIXME: Can't we pull the types from the MachineInstr rather than the
219  // operands.
220  if (MI.getOperand(Idx).isReg())
221  Size = getSizeInBits(MI.getOperand(Idx).getReg(), MRI, *TRI);
222  OpdsMapping.push_back(AMDGPU::getValueMapping(BankID, Size));
223  }
224  }
225  return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
226  MI.getNumOperands());
227 }
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Interface definition for SIRegisterInfo.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getReg() const
getReg - Returns the register number.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
A description of a memory reference used in the backend.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
bool isSGPRClass(const TargetRegisterClass *RC) const
static bool isInstrUniform(const MachineInstr &MI)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:404
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isValid() const
Check whether this object is valid.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:389
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
bool isUniformMMO(const MachineMemOperand *MMO)
This class provides the information for the target register banks.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Helper struct that represents how a value is mapped through different register banks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295