LLVM  9.0.0svn
AMDGPURegisterBankInfo.h
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1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 
17 
18 #define GET_REGBANK_DECLARATIONS
19 #include "AMDGPUGenRegisterBank.inc"
20 #undef GET_REGBANK_DECLARATIONS
21 
22 namespace llvm {
23 
24 class LLT;
25 class MachineIRBuilder;
26 class SIRegisterInfo;
27 class TargetRegisterInfo;
28 
29 /// This class provides the information for the target register banks.
31 
32 protected:
33 
34 #define GET_TARGET_REGBANK_CLASS
35 #include "AMDGPUGenRegisterBank.inc"
36 };
38  const SIRegisterInfo *TRI;
39 
40  void executeInWaterfallLoop(MachineInstr &MI,
42  ArrayRef<unsigned> OpIndices) const;
43 
44  /// See RegisterBankInfo::applyMapping.
45  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
46 
48  getInstrMappingForLoad(const MachineInstr &MI) const;
49 
50  unsigned getRegBankID(unsigned Reg, const MachineRegisterInfo &MRI,
51  const TargetRegisterInfo &TRI,
52  unsigned Default = AMDGPU::VGPRRegBankID) const;
53 
54  /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
55  /// Regs. This appropriately sets the regbank of the new registers.
56  void split64BitValueForMapping(MachineIRBuilder &B,
58  LLT HalfTy,
59  unsigned Reg) const;
60 
61  bool isSALUMapping(const MachineInstr &MI) const;
62  const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
63  const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
64  const InstructionMapping &getDefaultMappingAllVGPR(
65  const MachineInstr &MI) const;
66 public:
68 
69  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
70  unsigned Size) const override;
71 
72  unsigned getBreakDownCost(const ValueMapping &ValMapping,
73  const RegisterBank *CurBank = nullptr) const override;
74 
75  const RegisterBank &
76  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
77 
79  getInstrAlternativeMappings(const MachineInstr &MI) const override;
80 
81  const InstructionMapping &
82  getInstrMapping(const MachineInstr &MI) const override;
83 };
84 } // End llvm namespace.
85 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned Reg
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
Helper class to build MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
uint32_t Size
Definition: Profile.cpp:46
This class provides the information for the target register banks.
IRTranslator LLVM IR MI
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.