LLVM  7.0.0svn
AMDGPURegisterBankInfo.h
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1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
16 
18 
19 #define GET_REGBANK_DECLARATIONS
20 #include "AMDGPUGenRegisterBank.inc"
21 #undef GET_REGBANK_DECLARATIONS
22 
23 namespace llvm {
24 
25 class SIRegisterInfo;
26 class TargetRegisterInfo;
27 
28 /// This class provides the information for the target register banks.
30 
31 protected:
32 
33 #define GET_TARGET_REGBANK_CLASS
34 #include "AMDGPUGenRegisterBank.inc"
35 };
37  const SIRegisterInfo *TRI;
38 
39  /// See RegisterBankInfo::applyMapping.
40  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
41 
43  getInstrMappingForLoad(const MachineInstr &MI) const;
44 
45  unsigned getRegBankID(unsigned Reg, const MachineRegisterInfo &MRI,
46  const TargetRegisterInfo &TRI,
47  unsigned Default = AMDGPU::VGPRRegBankID) const;
48 
49  bool isSALUMapping(const MachineInstr &MI) const;
50  const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
51  const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
52 public:
54 
55  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
56  unsigned Size) const override;
57 
58  const RegisterBank &
59  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
60 
62  getInstrAlternativeMappings(const MachineInstr &MI) const override;
63 
64  const InstructionMapping &
65  getInstrMapping(const MachineInstr &MI) const override;
66 };
67 } // End llvm namespace.
68 #endif
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned Reg
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
This class implements the register bank concept.
Definition: RegisterBank.h:29
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
This class provides the information for the target register banks.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
IRTranslator LLVM IR MI
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.