LLVM  7.0.0svn
AMDGPURegisterInfo.cpp
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1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPURegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "SIRegisterInfo.h"
18 
19 using namespace llvm;
20 
22 
23 //===----------------------------------------------------------------------===//
24 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
25 // they are not supported at this time.
26 //===----------------------------------------------------------------------===//
27 
28 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
29  static const unsigned SubRegs[] = {
30  AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
31  AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
32  AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
33  AMDGPU::sub15
34  };
35 
36  assert(Channel < array_lengthof(SubRegs));
37  return SubRegs[Channel];
38 }
39 
40 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
41  MCRegAliasIterator R(Reg, this, true);
42 
43  for (; R.isValid(); ++R)
44  Reserved.set(*R);
45 }
46 
47 #define GET_REGINFO_TARGET_DESC
48 #include "AMDGPUGenRegisterInfo.inc"
49 
50 // Forced to be here by one .inc
52  const MachineFunction *MF) const {
54  switch (CC) {
55  case CallingConv::C:
56  case CallingConv::Fast:
57  case CallingConv::Cold:
58  return CSR_AMDGPU_HighRegs_SaveList;
59  default: {
60  // Dummy to not crash RegisterClassInfo.
61  static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
62  return &NoCalleeSavedReg;
63  }
64  }
65 }
66 
67 const MCPhysReg *
69  return nullptr;
70 }
71 
73  CallingConv::ID CC) const {
74  switch (CC) {
75  case CallingConv::C:
76  case CallingConv::Fast:
77  case CallingConv::Cold:
78  return CSR_AMDGPU_HighRegs_RegMask;
79  default:
80  return nullptr;
81  }
82 }
83 
85  return AMDGPU::NoRegister;
86 }
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector & set()
Definition: BitVector.h:398
Interface definition for SIRegisterInfo.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned getSubRegFromChannel(unsigned Channel) const
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo interface that is implemented by all hw codegen targets.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getFrameRegister(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
The AMDGPU TargetMachine interface definition for hw codgen targets.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:721
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void reserveRegisterTuples(BitVector &, unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())