LLVM  7.0.0svn
AMDGPURegisterInfo.cpp
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1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Parent TargetRegisterInfo class common to all hw codegen targets.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPURegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "SIMachineFunctionInfo.h"
18 #include "SIRegisterInfo.h"
20 
21 using namespace llvm;
22 
24 
25 //===----------------------------------------------------------------------===//
26 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
27 // they are not supported at this time.
28 //===----------------------------------------------------------------------===//
29 
30 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
31  static const unsigned SubRegs[] = {
32  AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
33  AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
34  AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
35  AMDGPU::sub15
36  };
37 
38  assert(Channel < array_lengthof(SubRegs));
39  return SubRegs[Channel];
40 }
41 
42 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
43  MCRegAliasIterator R(Reg, this, true);
44 
45  for (; R.isValid(); ++R)
46  Reserved.set(*R);
47 }
48 
49 #define GET_REGINFO_TARGET_DESC
50 #include "AMDGPUGenRegisterInfo.inc"
51 
52 // Forced to be here by one .inc
54  const MachineFunction *MF) const {
56  switch (CC) {
57  case CallingConv::C:
58  case CallingConv::Fast:
59  case CallingConv::Cold:
60  return CSR_AMDGPU_HighRegs_SaveList;
61  default: {
62  // Dummy to not crash RegisterClassInfo.
63  static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
64  return &NoCalleeSavedReg;
65  }
66  }
67 }
68 
69 const MCPhysReg *
71  return nullptr;
72 }
73 
75  CallingConv::ID CC) const {
76  switch (CC) {
77  case CallingConv::C:
78  case CallingConv::Fast:
79  case CallingConv::Cold:
80  return CSR_AMDGPU_HighRegs_RegMask;
81  default:
82  return nullptr;
83  }
84 }
85 
87  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
88  return FuncInfo->getFrameOffsetReg();
89 }
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector & set()
Definition: BitVector.h:398
Interface definition for SIRegisterInfo.
static unsigned getSubRegFromChannel(unsigned Channel)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned Reg
TargetRegisterInfo interface that is implemented by all hw codegen targets.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getFrameRegister(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The AMDGPU TargetMachine interface definition for hw codgen targets.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
Provides AMDGPU specific target descriptions.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
void reserveRegisterTuples(BitVector &, unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())