LLVM  9.0.0svn
AMDGPUTargetStreamer.cpp
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1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AMDGPU specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AMDGPUTargetStreamer.h"
14 #include "AMDGPU.h"
15 #include "SIDefines.h"
16 #include "Utils/AMDGPUBaseInfo.h"
18 #include "llvm/ADT/Twine.h"
20 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/Metadata.h"
25 #include "llvm/IR/Module.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCSectionELF.h"
32 
33 namespace llvm {
34 #include "AMDGPUPTNote.h"
35 }
36 
37 using namespace llvm;
38 using namespace llvm::AMDGPU;
39 using namespace llvm::AMDGPU::HSAMD;
40 
41 //===----------------------------------------------------------------------===//
42 // AMDGPUTargetStreamer
43 //===----------------------------------------------------------------------===//
44 
46  HSAMD::Metadata HSAMetadata;
47  if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
48  return false;
49 
50  return EmitHSAMetadata(HSAMetadata);
51 }
52 
54  std::shared_ptr<msgpack::Node> HSAMetadataRoot;
55  yaml::Input YIn(HSAMetadataString);
56  YIn >> HSAMetadataRoot;
57  if (YIn.error())
58  return false;
59  return EmitHSAMetadata(HSAMetadataRoot, false);
60 }
61 
63  AMDGPU::GPUKind AK;
64 
65  switch (ElfMach) {
66  case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
67  case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
68  case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
69  case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
70  case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
71  case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
72  case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
73  case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
77  case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
78  case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
81  case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
98  case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
99  }
100 
101  StringRef GPUName = getArchNameAMDGCN(AK);
102  if (GPUName != "")
103  return GPUName;
104  return getArchNameR600(AK);
105 }
106 
109  if (AK == AMDGPU::GPUKind::GK_NONE)
110  AK = parseArchR600(GPU);
111 
112  switch (AK) {
145  case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
146  }
147 
148  llvm_unreachable("unknown GPU");
149 }
150 
151 //===----------------------------------------------------------------------===//
152 // AMDGPUTargetAsmStreamer
153 //===----------------------------------------------------------------------===//
154 
157  : AMDGPUTargetStreamer(S), OS(OS) { }
158 
160  OS << "\t.amdgcn_target \"" << Target << "\"\n";
161 }
162 
164  uint32_t Major, uint32_t Minor) {
165  OS << "\t.hsa_code_object_version " <<
166  Twine(Major) << "," << Twine(Minor) << '\n';
167 }
168 
169 void
171  uint32_t Minor,
172  uint32_t Stepping,
173  StringRef VendorName,
174  StringRef ArchName) {
175  OS << "\t.hsa_code_object_isa " <<
176  Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
177  ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
178 
179 }
180 
181 void
183  OS << "\t.amd_kernel_code_t\n";
184  dumpAmdKernelCode(&Header, OS, "\t\t");
185  OS << "\t.end_amd_kernel_code_t\n";
186 }
187 
189  unsigned Type) {
190  switch (Type) {
191  default: llvm_unreachable("Invalid AMDGPU symbol type");
193  OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
194  break;
195  }
196 }
197 
199  OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n";
200  return true;
201 }
202 
204  const AMDGPU::HSAMD::Metadata &HSAMetadata) {
205  std::string HSAMetadataString;
206  if (HSAMD::toString(HSAMetadata, HSAMetadataString))
207  return false;
208 
209  OS << '\t' << AssemblerDirectiveBegin << '\n';
210  OS << HSAMetadataString << '\n';
211  OS << '\t' << AssemblerDirectiveEnd << '\n';
212  return true;
213 }
214 
216  std::shared_ptr<msgpack::Node> &HSAMetadataRoot, bool Strict) {
218  if (!Verifier.verify(*HSAMetadataRoot))
219  return false;
220 
221  std::string HSAMetadataString;
222  raw_string_ostream StrOS(HSAMetadataString);
223  yaml::Output YOut(StrOS);
224  YOut << HSAMetadataRoot;
225 
226  OS << '\t' << V3::AssemblerDirectiveBegin << '\n';
227  OS << StrOS.str() << '\n';
228  OS << '\t' << V3::AssemblerDirectiveEnd << '\n';
229  return true;
230 }
231 
233  const PALMD::Metadata &PALMetadata) {
234  std::string PALMetadataString;
235  if (PALMD::toString(PALMetadata, PALMetadataString))
236  return false;
237 
238  OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
239  return true;
240 }
241 
243  const MCSubtargetInfo &STI, StringRef KernelName,
244  const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
245  bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
246  IsaVersion IVersion = getIsaVersion(STI.getCPU());
247 
248  OS << "\t.amdhsa_kernel " << KernelName << '\n';
249 
250 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
251  STREAM << "\t\t" << DIRECTIVE << " " \
252  << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
253 
254  OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
255  << '\n';
256  OS << "\t\t.amdhsa_private_segment_fixed_size "
257  << KD.private_segment_fixed_size << '\n';
258 
259  PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
260  kernel_code_properties,
261  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
262  PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
263  kernel_code_properties,
264  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
265  PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
266  kernel_code_properties,
267  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
268  PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
269  kernel_code_properties,
270  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
271  PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
272  kernel_code_properties,
273  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
274  PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
275  kernel_code_properties,
276  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
277  PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
278  kernel_code_properties,
279  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
280  PRINT_FIELD(
281  OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
282  compute_pgm_rsrc2,
283  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
284  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
285  compute_pgm_rsrc2,
286  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
287  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
288  compute_pgm_rsrc2,
289  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
290  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
291  compute_pgm_rsrc2,
292  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
293  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
294  compute_pgm_rsrc2,
295  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
296  PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
297  compute_pgm_rsrc2,
298  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
299 
300  // These directives are required.
301  OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
302  OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
303 
304  if (!ReserveVCC)
305  OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
306  if (IVersion.Major >= 7 && !ReserveFlatScr)
307  OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
308  if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
309  OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
310 
311  PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
312  compute_pgm_rsrc1,
313  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
314  PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
315  compute_pgm_rsrc1,
316  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
317  PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
318  compute_pgm_rsrc1,
319  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
320  PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
321  compute_pgm_rsrc1,
322  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
323  PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
324  compute_pgm_rsrc1,
325  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
326  PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
327  compute_pgm_rsrc1,
328  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
329  if (IVersion.Major >= 9)
330  PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
331  compute_pgm_rsrc1,
332  amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
333  PRINT_FIELD(
334  OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
335  compute_pgm_rsrc2,
336  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
337  PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
338  compute_pgm_rsrc2,
339  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
340  PRINT_FIELD(
341  OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
342  compute_pgm_rsrc2,
343  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
344  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
345  compute_pgm_rsrc2,
346  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
347  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
348  compute_pgm_rsrc2,
349  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
350  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
351  compute_pgm_rsrc2,
352  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
353  PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
354  compute_pgm_rsrc2,
355  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
356 #undef PRINT_FIELD
357 
358  OS << "\t.end_amdhsa_kernel\n";
359 }
360 
361 //===----------------------------------------------------------------------===//
362 // AMDGPUTargetELFStreamer
363 //===----------------------------------------------------------------------===//
364 
366  MCStreamer &S, const MCSubtargetInfo &STI)
367  : AMDGPUTargetStreamer(S), Streamer(S) {
369  unsigned EFlags = MCA.getELFHeaderEFlags();
370 
371  EFlags &= ~ELF::EF_AMDGPU_MACH;
372  EFlags |= getElfMach(STI.getCPU());
373 
374  EFlags &= ~ELF::EF_AMDGPU_XNACK;
375  if (AMDGPU::hasXNACK(STI))
376  EFlags |= ELF::EF_AMDGPU_XNACK;
377 
378  EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC;
379  if (AMDGPU::hasSRAMECC(STI))
380  EFlags |= ELF::EF_AMDGPU_SRAM_ECC;
381 
382  MCA.setELFHeaderEFlags(EFlags);
383 }
384 
386  return static_cast<MCELFStreamer &>(Streamer);
387 }
388 
389 void AMDGPUTargetELFStreamer::EmitNote(
390  StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
391  function_ref<void(MCELFStreamer &)> EmitDesc) {
392  auto &S = getStreamer();
393  auto &Context = S.getContext();
394 
395  auto NameSZ = Name.size() + 1;
396 
397  S.PushSection();
398  S.SwitchSection(Context.getELFSection(
400  S.EmitIntValue(NameSZ, 4); // namesz
401  S.EmitValue(DescSZ, 4); // descz
402  S.EmitIntValue(NoteType, 4); // type
403  S.EmitBytes(Name); // name
404  S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
405  EmitDesc(S); // desc
406  S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
407  S.PopSection();
408 }
409 
411 
413  uint32_t Major, uint32_t Minor) {
414 
417  OS.EmitIntValue(Major, 4);
418  OS.EmitIntValue(Minor, 4);
419  });
420 }
421 
422 void
424  uint32_t Minor,
425  uint32_t Stepping,
426  StringRef VendorName,
427  StringRef ArchName) {
428  uint16_t VendorNameSize = VendorName.size() + 1;
429  uint16_t ArchNameSize = ArchName.size() + 1;
430 
431  unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
432  sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
433  VendorNameSize + ArchNameSize;
434 
437  OS.EmitIntValue(VendorNameSize, 2);
438  OS.EmitIntValue(ArchNameSize, 2);
439  OS.EmitIntValue(Major, 4);
440  OS.EmitIntValue(Minor, 4);
441  OS.EmitIntValue(Stepping, 4);
442  OS.EmitBytes(VendorName);
443  OS.EmitIntValue(0, 1); // NULL terminate VendorName
444  OS.EmitBytes(ArchName);
445  OS.EmitIntValue(0, 1); // NULL terminte ArchName
446  });
447 }
448 
449 void
451 
452  MCStreamer &OS = getStreamer();
453  OS.PushSection();
454  OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header)));
455  OS.PopSection();
456 }
457 
459  unsigned Type) {
460  MCSymbolELF *Symbol = cast<MCSymbolELF>(
461  getStreamer().getContext().getOrCreateSymbol(SymbolName));
462  Symbol->setType(Type);
463 }
464 
466  // Create two labels to mark the beginning and end of the desc field
467  // and a MCExpr to calculate the size of the desc field.
468  auto &Context = getContext();
469  auto *DescBegin = Context.createTempSymbol();
470  auto *DescEnd = Context.createTempSymbol();
471  auto *DescSZ = MCBinaryExpr::createSub(
474 
476  [&](MCELFStreamer &OS) {
477  OS.EmitLabel(DescBegin);
478  OS.EmitBytes(IsaVersionString);
479  OS.EmitLabel(DescEnd);
480  });
481  return true;
482 }
483 
485  std::shared_ptr<msgpack::Node> &HSAMetadataRoot, bool Strict) {
487  if (!Verifier.verify(*HSAMetadataRoot))
488  return false;
489 
490  std::string HSAMetadataString;
491  raw_string_ostream StrOS(HSAMetadataString);
492  msgpack::Writer MPWriter(StrOS);
493  HSAMetadataRoot->write(MPWriter);
494 
495  // Create two labels to mark the beginning and end of the desc field
496  // and a MCExpr to calculate the size of the desc field.
497  auto &Context = getContext();
498  auto *DescBegin = Context.createTempSymbol();
499  auto *DescEnd = Context.createTempSymbol();
500  auto *DescSZ = MCBinaryExpr::createSub(
503 
505  [&](MCELFStreamer &OS) {
506  OS.EmitLabel(DescBegin);
507  OS.EmitBytes(StrOS.str());
508  OS.EmitLabel(DescEnd);
509  });
510  return true;
511 }
512 
514  const AMDGPU::HSAMD::Metadata &HSAMetadata) {
515  std::string HSAMetadataString;
516  if (HSAMD::toString(HSAMetadata, HSAMetadataString))
517  return false;
518 
519  // Create two labels to mark the beginning and end of the desc field
520  // and a MCExpr to calculate the size of the desc field.
521  auto &Context = getContext();
522  auto *DescBegin = Context.createTempSymbol();
523  auto *DescEnd = Context.createTempSymbol();
524  auto *DescSZ = MCBinaryExpr::createSub(
527 
529  [&](MCELFStreamer &OS) {
530  OS.EmitLabel(DescBegin);
531  OS.EmitBytes(HSAMetadataString);
532  OS.EmitLabel(DescEnd);
533  });
534  return true;
535 }
536 
538  const PALMD::Metadata &PALMetadata) {
539  EmitNote(ElfNote::NoteNameV2,
540  MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t),
541  getContext()),
543  for (auto I : PALMetadata)
544  OS.EmitIntValue(I, sizeof(uint32_t));
545  });
546  return true;
547 }
548 
550  const MCSubtargetInfo &STI, StringRef KernelName,
551  const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
552  uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
553  bool ReserveXNACK) {
554  auto &Streamer = getStreamer();
555  auto &Context = Streamer.getContext();
556 
557  MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
558  Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
559  KernelDescriptorSymbol->setBinding(ELF::STB_GLOBAL);
560  KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
561  KernelDescriptorSymbol->setSize(
562  MCConstantExpr::create(sizeof(KernelDescriptor), Context));
563 
564  MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
565  Context.getOrCreateSymbol(Twine(KernelName)));
566  KernelCodeSymbol->setBinding(ELF::STB_LOCAL);
567 
568  Streamer.EmitLabel(KernelDescriptorSymbol);
569  Streamer.EmitBytes(StringRef(
570  (const char*)&(KernelDescriptor),
571  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset)));
572  // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
573  // expression being created is:
574  // (start of kernel code) - (start of kernel descriptor)
575  // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
578  KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
580  KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
581  Context),
582  sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
583  Streamer.EmitBytes(StringRef(
584  (const char*)&(KernelDescriptor) +
585  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) +
586  sizeof(KernelDescriptor.kernel_code_entry_byte_offset),
587  sizeof(KernelDescriptor) -
588  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) -
589  sizeof(KernelDescriptor.kernel_code_entry_byte_offset)));
590 }
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:255
In-memory representation of HSA metadata.
void EmitBytes(StringRef Data) override
Emit the bytes in Data into the output.
LLVMContext & Context
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
StringRef getArchNameR600(GPUKind AK)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) override
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
This file contains the declarations for metadata subclasses.
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:116
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString)
Instruction set architecture version.
Definition: TargetParser.h:131
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:367
bool EmitHSAMetadata(std::shared_ptr< msgpack::Node > &HSAMetadata, bool Strict) override
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
MCContext & getContext() const
Definition: MCStreamer.h:250
Verifier for AMDGPU HSA metadata.
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
AMD Kernel Code Object (amd_kernel_code_t).
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Writes MessagePack objects to an output stream, one at a time.
Definition: MsgPackWriter.h:40
static StringRef getArchNameFromElfMach(unsigned ElfMach)
StringRef getArchNameAMDGCN(GPUKind AK)
std::error_code fromString(std::string String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:123
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:154
This is a data structure for representing MessagePack "documents", with methods to go to and from Mes...
bool hasSRAMECC(const MCSubtargetInfo &STI)
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:26
Streaming machine code generation interface.
Definition: MCStreamer.h:188
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:80
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:22
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
static unsigned getElfMach(StringRef GPU)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
GPUKind parseArchAMDGCN(StringRef CPU)
MCAssembler & getAssembler()
#define offsetof(TYPE, MEMBER)
bool verify(msgpack::Node &HSAMetadataRoot)
Verify given HSA metadata.
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirective[]
PAL metadata assembler directive.
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:254
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:94
IsaVersion getIsaVersion(StringRef GPU)
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Enums and constants for AMDGPU PT_NOTE sections.
std::string toString(WasmSymbolType type)
Definition: Wasm.cpp:11
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) override
MCContext & getContext() const
Module.h This file contains the declarations for the Module class.
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
MCStreamer & Streamer
Definition: MCStreamer.h:85
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:41
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:25
void EmitDirectiveAMDGCNTarget(StringRef Target) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
StringRef getCPU() const
Target - Wrapper for Target specific information.
bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override
bool EmitISAVersion(StringRef IsaVersionString) override
void EmitDirectiveAMDGCNTarget(StringRef Target) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:122
bool hasXNACK(const MCSubtargetInfo &STI)
verify safepoint Safepoint IR Verifier
bool EmitISAVersion(StringRef IsaVersionString) override
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc()) override
Emit a label for Symbol into the current section.
bool EmitHSAMetadata(std::shared_ptr< msgpack::Node > &HSAMetadata, bool Strict) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:376
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:346
const char SectionName[]
Definition: AMDGPUPTNote.h:23
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
GPUKind parseArchR600(StringRef CPU)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
std::vector< uint32_t > Metadata
PAL metadata represented as a vector.