LLVM  8.0.0svn
AMDGPUTargetStreamer.cpp
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1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AMDGPU specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUTargetStreamer.h"
15 #include "AMDGPU.h"
16 #include "SIDefines.h"
17 #include "Utils/AMDGPUBaseInfo.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/Metadata.h"
24 #include "llvm/IR/Module.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCSectionELF.h"
31 
32 namespace llvm {
33 #include "AMDGPUPTNote.h"
34 }
35 
36 using namespace llvm;
37 using namespace llvm::AMDGPU;
38 
39 //===----------------------------------------------------------------------===//
40 // AMDGPUTargetStreamer
41 //===----------------------------------------------------------------------===//
42 
44  HSAMD::Metadata HSAMetadata;
45  if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
46  return false;
47 
48  return EmitHSAMetadata(HSAMetadata);
49 }
50 
52  AMDGPU::GPUKind AK;
53 
54  switch (ElfMach) {
55  case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
56  case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
57  case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
58  case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
59  case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
60  case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
61  case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
62  case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
66  case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
67  case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
70  case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
86  case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
87  }
88 
89  StringRef GPUName = getArchNameAMDGCN(AK);
90  if (GPUName != "")
91  return GPUName;
92  return getArchNameR600(AK);
93 }
94 
97  if (AK == AMDGPU::GPUKind::GK_NONE)
98  AK = parseArchR600(GPU);
99 
100  switch (AK) {
132  case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
133  }
134 
135  llvm_unreachable("unknown GPU");
136 }
137 
138 //===----------------------------------------------------------------------===//
139 // AMDGPUTargetAsmStreamer
140 //===----------------------------------------------------------------------===//
141 
144  : AMDGPUTargetStreamer(S), OS(OS) { }
145 
147  OS << "\t.amdgcn_target \"" << Target << "\"\n";
148 }
149 
151  uint32_t Major, uint32_t Minor) {
152  OS << "\t.hsa_code_object_version " <<
153  Twine(Major) << "," << Twine(Minor) << '\n';
154 }
155 
156 void
158  uint32_t Minor,
159  uint32_t Stepping,
160  StringRef VendorName,
161  StringRef ArchName) {
162  OS << "\t.hsa_code_object_isa " <<
163  Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
164  ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
165 
166 }
167 
168 void
170  OS << "\t.amd_kernel_code_t\n";
171  dumpAmdKernelCode(&Header, OS, "\t\t");
172  OS << "\t.end_amd_kernel_code_t\n";
173 }
174 
176  unsigned Type) {
177  switch (Type) {
178  default: llvm_unreachable("Invalid AMDGPU symbol type");
180  OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
181  break;
182  }
183 }
184 
186  OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n";
187  return true;
188 }
189 
191  const AMDGPU::HSAMD::Metadata &HSAMetadata) {
192  std::string HSAMetadataString;
193  if (HSAMD::toString(HSAMetadata, HSAMetadataString))
194  return false;
195 
196  OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
197  OS << HSAMetadataString << '\n';
198  OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
199  return true;
200 }
201 
203  const PALMD::Metadata &PALMetadata) {
204  std::string PALMetadataString;
205  if (PALMD::toString(PALMetadata, PALMetadataString))
206  return false;
207 
208  OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
209  return true;
210 }
211 
213  const MCSubtargetInfo &STI, StringRef KernelName,
214  const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
215  bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
216  IsaVersion IVersion = getIsaVersion(STI.getCPU());
217 
218  OS << "\t.amdhsa_kernel " << KernelName << '\n';
219 
220 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
221  STREAM << "\t\t" << DIRECTIVE << " " \
222  << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
223 
224  OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
225  << '\n';
226  OS << "\t\t.amdhsa_private_segment_fixed_size "
227  << KD.private_segment_fixed_size << '\n';
228 
229  PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
230  kernel_code_properties,
231  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
232  PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
233  kernel_code_properties,
234  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
235  PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
236  kernel_code_properties,
237  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
238  PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
239  kernel_code_properties,
240  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
241  PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
242  kernel_code_properties,
243  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
244  PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
245  kernel_code_properties,
246  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
247  PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
248  kernel_code_properties,
249  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
250  PRINT_FIELD(
251  OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
252  compute_pgm_rsrc2,
253  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
254  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
255  compute_pgm_rsrc2,
256  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
257  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
258  compute_pgm_rsrc2,
259  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
260  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
261  compute_pgm_rsrc2,
262  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
263  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
264  compute_pgm_rsrc2,
265  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
266  PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
267  compute_pgm_rsrc2,
268  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
269 
270  // These directives are required.
271  OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
272  OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
273 
274  if (!ReserveVCC)
275  OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
276  if (IVersion.Major >= 7 && !ReserveFlatScr)
277  OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
278  if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
279  OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
280 
281  PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
282  compute_pgm_rsrc1,
283  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
284  PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
285  compute_pgm_rsrc1,
286  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
287  PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
288  compute_pgm_rsrc1,
289  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
290  PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
291  compute_pgm_rsrc1,
292  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
293  PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
294  compute_pgm_rsrc1,
295  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
296  PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
297  compute_pgm_rsrc1,
298  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
299  if (IVersion.Major >= 9)
300  PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
301  compute_pgm_rsrc1,
302  amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
303  PRINT_FIELD(
304  OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
305  compute_pgm_rsrc2,
306  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
307  PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
308  compute_pgm_rsrc2,
309  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
310  PRINT_FIELD(
311  OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
312  compute_pgm_rsrc2,
313  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
314  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
315  compute_pgm_rsrc2,
316  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
317  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
318  compute_pgm_rsrc2,
319  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
320  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
321  compute_pgm_rsrc2,
322  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
323  PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
324  compute_pgm_rsrc2,
325  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
326 #undef PRINT_FIELD
327 
328  OS << "\t.end_amdhsa_kernel\n";
329 }
330 
331 //===----------------------------------------------------------------------===//
332 // AMDGPUTargetELFStreamer
333 //===----------------------------------------------------------------------===//
334 
336  MCStreamer &S, const MCSubtargetInfo &STI)
337  : AMDGPUTargetStreamer(S), Streamer(S) {
339  unsigned EFlags = MCA.getELFHeaderEFlags();
340 
341  EFlags &= ~ELF::EF_AMDGPU_MACH;
342  EFlags |= getElfMach(STI.getCPU());
343 
344  EFlags &= ~ELF::EF_AMDGPU_XNACK;
345  if (AMDGPU::hasXNACK(STI))
346  EFlags |= ELF::EF_AMDGPU_XNACK;
347 
348  MCA.setELFHeaderEFlags(EFlags);
349 }
350 
352  return static_cast<MCELFStreamer &>(Streamer);
353 }
354 
355 void AMDGPUTargetELFStreamer::EmitAMDGPUNote(
356  const MCExpr *DescSZ, unsigned NoteType,
357  function_ref<void(MCELFStreamer &)> EmitDesc) {
358  auto &S = getStreamer();
359  auto &Context = S.getContext();
360 
361  auto NameSZ = sizeof(ElfNote::NoteName);
362 
363  S.PushSection();
364  S.SwitchSection(Context.getELFSection(
366  S.EmitIntValue(NameSZ, 4); // namesz
367  S.EmitValue(DescSZ, 4); // descz
368  S.EmitIntValue(NoteType, 4); // type
369  S.EmitBytes(StringRef(ElfNote::NoteName, NameSZ)); // name
370  S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
371  EmitDesc(S); // desc
372  S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
373  S.PopSection();
374 }
375 
377 
379  uint32_t Major, uint32_t Minor) {
380 
381  EmitAMDGPUNote(
384  [&](MCELFStreamer &OS){
385  OS.EmitIntValue(Major, 4);
386  OS.EmitIntValue(Minor, 4);
387  }
388  );
389 }
390 
391 void
393  uint32_t Minor,
394  uint32_t Stepping,
395  StringRef VendorName,
396  StringRef ArchName) {
397  uint16_t VendorNameSize = VendorName.size() + 1;
398  uint16_t ArchNameSize = ArchName.size() + 1;
399 
400  unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
401  sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
402  VendorNameSize + ArchNameSize;
403 
404  EmitAMDGPUNote(
407  [&](MCELFStreamer &OS) {
408  OS.EmitIntValue(VendorNameSize, 2);
409  OS.EmitIntValue(ArchNameSize, 2);
410  OS.EmitIntValue(Major, 4);
411  OS.EmitIntValue(Minor, 4);
412  OS.EmitIntValue(Stepping, 4);
413  OS.EmitBytes(VendorName);
414  OS.EmitIntValue(0, 1); // NULL terminate VendorName
415  OS.EmitBytes(ArchName);
416  OS.EmitIntValue(0, 1); // NULL terminte ArchName
417  }
418  );
419 }
420 
421 void
423 
424  MCStreamer &OS = getStreamer();
425  OS.PushSection();
426  OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header)));
427  OS.PopSection();
428 }
429 
431  unsigned Type) {
432  MCSymbolELF *Symbol = cast<MCSymbolELF>(
433  getStreamer().getContext().getOrCreateSymbol(SymbolName));
434  Symbol->setType(Type);
435 }
436 
438  // Create two labels to mark the beginning and end of the desc field
439  // and a MCExpr to calculate the size of the desc field.
440  auto &Context = getContext();
441  auto *DescBegin = Context.createTempSymbol();
442  auto *DescEnd = Context.createTempSymbol();
443  auto *DescSZ = MCBinaryExpr::createSub(
446 
447  EmitAMDGPUNote(
448  DescSZ,
450  [&](MCELFStreamer &OS) {
451  OS.EmitLabel(DescBegin);
452  OS.EmitBytes(IsaVersionString);
453  OS.EmitLabel(DescEnd);
454  }
455  );
456  return true;
457 }
458 
460  const AMDGPU::HSAMD::Metadata &HSAMetadata) {
461  std::string HSAMetadataString;
462  if (HSAMD::toString(HSAMetadata, HSAMetadataString))
463  return false;
464 
465  // Create two labels to mark the beginning and end of the desc field
466  // and a MCExpr to calculate the size of the desc field.
467  auto &Context = getContext();
468  auto *DescBegin = Context.createTempSymbol();
469  auto *DescEnd = Context.createTempSymbol();
470  auto *DescSZ = MCBinaryExpr::createSub(
473 
474  EmitAMDGPUNote(
475  DescSZ,
477  [&](MCELFStreamer &OS) {
478  OS.EmitLabel(DescBegin);
479  OS.EmitBytes(HSAMetadataString);
480  OS.EmitLabel(DescEnd);
481  }
482  );
483  return true;
484 }
485 
487  const PALMD::Metadata &PALMetadata) {
488  EmitAMDGPUNote(
489  MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t), getContext()),
491  [&](MCELFStreamer &OS){
492  for (auto I : PALMetadata)
493  OS.EmitIntValue(I, sizeof(uint32_t));
494  }
495  );
496  return true;
497 }
498 
500  const MCSubtargetInfo &STI, StringRef KernelName,
501  const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
502  uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
503  bool ReserveXNACK) {
504  auto &Streamer = getStreamer();
505  auto &Context = Streamer.getContext();
506 
507  MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
508  Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
509  KernelDescriptorSymbol->setBinding(ELF::STB_GLOBAL);
510  KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
511  KernelDescriptorSymbol->setSize(
512  MCConstantExpr::create(sizeof(KernelDescriptor), Context));
513 
514  MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
515  Context.getOrCreateSymbol(Twine(KernelName)));
516  KernelCodeSymbol->setBinding(ELF::STB_LOCAL);
517 
518  Streamer.EmitLabel(KernelDescriptorSymbol);
519  Streamer.EmitBytes(StringRef(
520  (const char*)&(KernelDescriptor),
521  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset)));
522  // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
523  // expression being created is:
524  // (start of kernel code) - (start of kernel descriptor)
525  // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
528  KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
530  KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
531  Context),
532  sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
533  Streamer.EmitBytes(StringRef(
534  (const char*)&(KernelDescriptor) +
535  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) +
536  sizeof(KernelDescriptor.kernel_code_entry_byte_offset),
537  sizeof(KernelDescriptor) -
538  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) -
539  sizeof(KernelDescriptor.kernel_code_entry_byte_offset)));
540 }
bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:253
In-memory representation of HSA metadata.
void EmitBytes(StringRef Data) override
Emit the bytes in Data into the output.
LLVMContext & Context
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
StringRef getArchNameR600(GPUKind AK)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) override
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:977
This file contains the declarations for metadata subclasses.
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:107
Instruction set architecture version.
Definition: TargetParser.h:326
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:362
void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
MCContext & getContext() const
Definition: MCStreamer.h:253
virtual bool EmitHSAMetadata(StringRef HSAMetadataString)
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
AMD Kernel Code Object (amd_kernel_code_t).
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
static StringRef getArchNameFromElfMach(unsigned ElfMach)
bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override
StringRef getArchNameAMDGCN(GPUKind AK)
std::error_code fromString(std::string String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:545
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:112
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:143
Streaming machine code generation interface.
Definition: MCStreamer.h:183
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:276
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:23
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
static unsigned getElfMach(StringRef GPU)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
GPUKind parseArchAMDGCN(StringRef CPU)
MCAssembler & getAssembler()
#define offsetof(TYPE, MEMBER)
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirective[]
PAL metadata assembler directive.
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:252
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:95
const char NoteName[]
Definition: AMDGPUPTNote.h:26
IsaVersion getIsaVersion(StringRef GPU)
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Enums and constants for AMDGPU PT_NOTE sections.
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) override
MCContext & getContext() const
Module.h This file contains the declarations for the Module class.
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
MCStreamer & Streamer
Definition: MCStreamer.h:85
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:42
void EmitDirectiveAMDGCNTarget(StringRef Target) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
StringRef getCPU() const
Target - Wrapper for Target specific information.
bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override
bool EmitISAVersion(StringRef IsaVersionString) override
void EmitDirectiveAMDGCNTarget(StringRef Target) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
bool hasXNACK(const MCSubtargetInfo &STI)
bool EmitISAVersion(StringRef IsaVersionString) override
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc()) override
Emit a label for Symbol into the current section.
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:371
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:328
const char SectionName[]
Definition: AMDGPUPTNote.h:24
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
GPUKind parseArchR600(StringRef CPU)
std::string toString(wasm::WasmSymbolType type)
Definition: Wasm.cpp:12
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
std::vector< uint32_t > Metadata
PAL metadata represented as a vector.