LLVM  8.0.0svn
AMDGPUTargetStreamer.cpp
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1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AMDGPU specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUTargetStreamer.h"
15 #include "AMDGPU.h"
16 #include "SIDefines.h"
17 #include "Utils/AMDGPUBaseInfo.h"
19 #include "llvm/ADT/Twine.h"
21 #include "llvm/BinaryFormat/ELF.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/Metadata.h"
26 #include "llvm/IR/Module.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCSectionELF.h"
33 
34 namespace llvm {
35 #include "AMDGPUPTNote.h"
36 }
37 
38 using namespace llvm;
39 using namespace llvm::AMDGPU;
40 using namespace llvm::AMDGPU::HSAMD;
41 
42 //===----------------------------------------------------------------------===//
43 // AMDGPUTargetStreamer
44 //===----------------------------------------------------------------------===//
45 
47  HSAMD::Metadata HSAMetadata;
48  if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
49  return false;
50 
51  return EmitHSAMetadata(HSAMetadata);
52 }
53 
55  std::shared_ptr<msgpack::Node> HSAMetadataRoot;
56  yaml::Input YIn(HSAMetadataString);
57  YIn >> HSAMetadataRoot;
58  if (YIn.error())
59  return false;
60  return EmitHSAMetadata(HSAMetadataRoot, false);
61 }
62 
64  AMDGPU::GPUKind AK;
65 
66  switch (ElfMach) {
67  case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
68  case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
69  case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
70  case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
71  case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
72  case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
73  case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
74  case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
78  case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
79  case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
82  case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
99  case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
100  }
101 
102  StringRef GPUName = getArchNameAMDGCN(AK);
103  if (GPUName != "")
104  return GPUName;
105  return getArchNameR600(AK);
106 }
107 
110  if (AK == AMDGPU::GPUKind::GK_NONE)
111  AK = parseArchR600(GPU);
112 
113  switch (AK) {
146  case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
147  }
148 
149  llvm_unreachable("unknown GPU");
150 }
151 
152 //===----------------------------------------------------------------------===//
153 // AMDGPUTargetAsmStreamer
154 //===----------------------------------------------------------------------===//
155 
158  : AMDGPUTargetStreamer(S), OS(OS) { }
159 
161  OS << "\t.amdgcn_target \"" << Target << "\"\n";
162 }
163 
165  uint32_t Major, uint32_t Minor) {
166  OS << "\t.hsa_code_object_version " <<
167  Twine(Major) << "," << Twine(Minor) << '\n';
168 }
169 
170 void
172  uint32_t Minor,
173  uint32_t Stepping,
174  StringRef VendorName,
175  StringRef ArchName) {
176  OS << "\t.hsa_code_object_isa " <<
177  Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
178  ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
179 
180 }
181 
182 void
184  OS << "\t.amd_kernel_code_t\n";
185  dumpAmdKernelCode(&Header, OS, "\t\t");
186  OS << "\t.end_amd_kernel_code_t\n";
187 }
188 
190  unsigned Type) {
191  switch (Type) {
192  default: llvm_unreachable("Invalid AMDGPU symbol type");
194  OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
195  break;
196  }
197 }
198 
200  OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n";
201  return true;
202 }
203 
205  const AMDGPU::HSAMD::Metadata &HSAMetadata) {
206  std::string HSAMetadataString;
207  if (HSAMD::toString(HSAMetadata, HSAMetadataString))
208  return false;
209 
210  OS << '\t' << AssemblerDirectiveBegin << '\n';
211  OS << HSAMetadataString << '\n';
212  OS << '\t' << AssemblerDirectiveEnd << '\n';
213  return true;
214 }
215 
217  std::shared_ptr<msgpack::Node> &HSAMetadataRoot, bool Strict) {
219  if (!Verifier.verify(*HSAMetadataRoot))
220  return false;
221 
222  std::string HSAMetadataString;
223  raw_string_ostream StrOS(HSAMetadataString);
224  yaml::Output YOut(StrOS);
225  YOut << HSAMetadataRoot;
226 
227  OS << '\t' << V3::AssemblerDirectiveBegin << '\n';
228  OS << StrOS.str() << '\n';
229  OS << '\t' << V3::AssemblerDirectiveEnd << '\n';
230  return true;
231 }
232 
234  const PALMD::Metadata &PALMetadata) {
235  std::string PALMetadataString;
236  if (PALMD::toString(PALMetadata, PALMetadataString))
237  return false;
238 
239  OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
240  return true;
241 }
242 
244  const MCSubtargetInfo &STI, StringRef KernelName,
245  const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
246  bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
247  IsaVersion IVersion = getIsaVersion(STI.getCPU());
248 
249  OS << "\t.amdhsa_kernel " << KernelName << '\n';
250 
251 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
252  STREAM << "\t\t" << DIRECTIVE << " " \
253  << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
254 
255  OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
256  << '\n';
257  OS << "\t\t.amdhsa_private_segment_fixed_size "
258  << KD.private_segment_fixed_size << '\n';
259 
260  PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
261  kernel_code_properties,
262  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
263  PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
264  kernel_code_properties,
265  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
266  PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
267  kernel_code_properties,
268  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
269  PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
270  kernel_code_properties,
271  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
272  PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
273  kernel_code_properties,
274  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
275  PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
276  kernel_code_properties,
277  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
278  PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
279  kernel_code_properties,
280  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
281  PRINT_FIELD(
282  OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
283  compute_pgm_rsrc2,
284  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
285  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
286  compute_pgm_rsrc2,
287  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
288  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
289  compute_pgm_rsrc2,
290  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
291  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
292  compute_pgm_rsrc2,
293  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
294  PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
295  compute_pgm_rsrc2,
296  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
297  PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
298  compute_pgm_rsrc2,
299  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
300 
301  // These directives are required.
302  OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
303  OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
304 
305  if (!ReserveVCC)
306  OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
307  if (IVersion.Major >= 7 && !ReserveFlatScr)
308  OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
309  if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
310  OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
311 
312  PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
313  compute_pgm_rsrc1,
314  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
315  PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
316  compute_pgm_rsrc1,
317  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
318  PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
319  compute_pgm_rsrc1,
320  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
321  PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
322  compute_pgm_rsrc1,
323  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
324  PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
325  compute_pgm_rsrc1,
326  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
327  PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
328  compute_pgm_rsrc1,
329  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
330  if (IVersion.Major >= 9)
331  PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
332  compute_pgm_rsrc1,
333  amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
334  PRINT_FIELD(
335  OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
336  compute_pgm_rsrc2,
337  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
338  PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
339  compute_pgm_rsrc2,
340  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
341  PRINT_FIELD(
342  OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
343  compute_pgm_rsrc2,
344  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
345  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
346  compute_pgm_rsrc2,
347  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
348  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
349  compute_pgm_rsrc2,
350  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
351  PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
352  compute_pgm_rsrc2,
353  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
354  PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
355  compute_pgm_rsrc2,
356  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
357 #undef PRINT_FIELD
358 
359  OS << "\t.end_amdhsa_kernel\n";
360 }
361 
362 //===----------------------------------------------------------------------===//
363 // AMDGPUTargetELFStreamer
364 //===----------------------------------------------------------------------===//
365 
367  MCStreamer &S, const MCSubtargetInfo &STI)
368  : AMDGPUTargetStreamer(S), Streamer(S) {
370  unsigned EFlags = MCA.getELFHeaderEFlags();
371 
372  EFlags &= ~ELF::EF_AMDGPU_MACH;
373  EFlags |= getElfMach(STI.getCPU());
374 
375  EFlags &= ~ELF::EF_AMDGPU_XNACK;
376  if (AMDGPU::hasXNACK(STI))
377  EFlags |= ELF::EF_AMDGPU_XNACK;
378 
379  EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC;
380  if (AMDGPU::hasSRAMECC(STI))
381  EFlags |= ELF::EF_AMDGPU_SRAM_ECC;
382 
383  MCA.setELFHeaderEFlags(EFlags);
384 }
385 
387  return static_cast<MCELFStreamer &>(Streamer);
388 }
389 
390 void AMDGPUTargetELFStreamer::EmitNote(
391  StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
392  function_ref<void(MCELFStreamer &)> EmitDesc) {
393  auto &S = getStreamer();
394  auto &Context = S.getContext();
395 
396  auto NameSZ = Name.size() + 1;
397 
398  S.PushSection();
399  S.SwitchSection(Context.getELFSection(
401  S.EmitIntValue(NameSZ, 4); // namesz
402  S.EmitValue(DescSZ, 4); // descz
403  S.EmitIntValue(NoteType, 4); // type
404  S.EmitBytes(Name); // name
405  S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
406  EmitDesc(S); // desc
407  S.EmitValueToAlignment(4, 0, 1, 0); // padding 0
408  S.PopSection();
409 }
410 
412 
414  uint32_t Major, uint32_t Minor) {
415 
418  OS.EmitIntValue(Major, 4);
419  OS.EmitIntValue(Minor, 4);
420  });
421 }
422 
423 void
425  uint32_t Minor,
426  uint32_t Stepping,
427  StringRef VendorName,
428  StringRef ArchName) {
429  uint16_t VendorNameSize = VendorName.size() + 1;
430  uint16_t ArchNameSize = ArchName.size() + 1;
431 
432  unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
433  sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
434  VendorNameSize + ArchNameSize;
435 
438  OS.EmitIntValue(VendorNameSize, 2);
439  OS.EmitIntValue(ArchNameSize, 2);
440  OS.EmitIntValue(Major, 4);
441  OS.EmitIntValue(Minor, 4);
442  OS.EmitIntValue(Stepping, 4);
443  OS.EmitBytes(VendorName);
444  OS.EmitIntValue(0, 1); // NULL terminate VendorName
445  OS.EmitBytes(ArchName);
446  OS.EmitIntValue(0, 1); // NULL terminte ArchName
447  });
448 }
449 
450 void
452 
453  MCStreamer &OS = getStreamer();
454  OS.PushSection();
455  OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header)));
456  OS.PopSection();
457 }
458 
460  unsigned Type) {
461  MCSymbolELF *Symbol = cast<MCSymbolELF>(
462  getStreamer().getContext().getOrCreateSymbol(SymbolName));
463  Symbol->setType(Type);
464 }
465 
467  // Create two labels to mark the beginning and end of the desc field
468  // and a MCExpr to calculate the size of the desc field.
469  auto &Context = getContext();
470  auto *DescBegin = Context.createTempSymbol();
471  auto *DescEnd = Context.createTempSymbol();
472  auto *DescSZ = MCBinaryExpr::createSub(
475 
477  [&](MCELFStreamer &OS) {
478  OS.EmitLabel(DescBegin);
479  OS.EmitBytes(IsaVersionString);
480  OS.EmitLabel(DescEnd);
481  });
482  return true;
483 }
484 
486  std::shared_ptr<msgpack::Node> &HSAMetadataRoot, bool Strict) {
488  if (!Verifier.verify(*HSAMetadataRoot))
489  return false;
490 
491  std::string HSAMetadataString;
492  raw_string_ostream StrOS(HSAMetadataString);
493  msgpack::Writer MPWriter(StrOS);
494  HSAMetadataRoot->write(MPWriter);
495 
496  // Create two labels to mark the beginning and end of the desc field
497  // and a MCExpr to calculate the size of the desc field.
498  auto &Context = getContext();
499  auto *DescBegin = Context.createTempSymbol();
500  auto *DescEnd = Context.createTempSymbol();
501  auto *DescSZ = MCBinaryExpr::createSub(
504 
506  [&](MCELFStreamer &OS) {
507  OS.EmitLabel(DescBegin);
508  OS.EmitBytes(StrOS.str());
509  OS.EmitLabel(DescEnd);
510  });
511  return true;
512 }
513 
515  const AMDGPU::HSAMD::Metadata &HSAMetadata) {
516  std::string HSAMetadataString;
517  if (HSAMD::toString(HSAMetadata, HSAMetadataString))
518  return false;
519 
520  // Create two labels to mark the beginning and end of the desc field
521  // and a MCExpr to calculate the size of the desc field.
522  auto &Context = getContext();
523  auto *DescBegin = Context.createTempSymbol();
524  auto *DescEnd = Context.createTempSymbol();
525  auto *DescSZ = MCBinaryExpr::createSub(
528 
530  [&](MCELFStreamer &OS) {
531  OS.EmitLabel(DescBegin);
532  OS.EmitBytes(HSAMetadataString);
533  OS.EmitLabel(DescEnd);
534  });
535  return true;
536 }
537 
539  const PALMD::Metadata &PALMetadata) {
540  EmitNote(ElfNote::NoteNameV2,
541  MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t),
542  getContext()),
544  for (auto I : PALMetadata)
545  OS.EmitIntValue(I, sizeof(uint32_t));
546  });
547  return true;
548 }
549 
551  const MCSubtargetInfo &STI, StringRef KernelName,
552  const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
553  uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
554  bool ReserveXNACK) {
555  auto &Streamer = getStreamer();
556  auto &Context = Streamer.getContext();
557 
558  MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
559  Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
560  KernelDescriptorSymbol->setBinding(ELF::STB_GLOBAL);
561  KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
562  KernelDescriptorSymbol->setSize(
563  MCConstantExpr::create(sizeof(KernelDescriptor), Context));
564 
565  MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
566  Context.getOrCreateSymbol(Twine(KernelName)));
567  KernelCodeSymbol->setBinding(ELF::STB_LOCAL);
568 
569  Streamer.EmitLabel(KernelDescriptorSymbol);
570  Streamer.EmitBytes(StringRef(
571  (const char*)&(KernelDescriptor),
572  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset)));
573  // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
574  // expression being created is:
575  // (start of kernel code) - (start of kernel descriptor)
576  // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
579  KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
581  KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
582  Context),
583  sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
584  Streamer.EmitBytes(StringRef(
585  (const char*)&(KernelDescriptor) +
586  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) +
587  sizeof(KernelDescriptor.kernel_code_entry_byte_offset),
588  sizeof(KernelDescriptor) -
589  offsetof(amdhsa::kernel_descriptor_t, kernel_code_entry_byte_offset) -
590  sizeof(KernelDescriptor.kernel_code_entry_byte_offset)));
591 }
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:256
In-memory representation of HSA metadata.
void EmitBytes(StringRef Data) override
Emit the bytes in Data into the output.
LLVMContext & Context
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:323
StringRef getArchNameR600(GPUKind AK)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) override
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
This file contains the declarations for metadata subclasses.
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:111
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString)
Instruction set architecture version.
Definition: TargetParser.h:132
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:368
bool EmitHSAMetadata(std::shared_ptr< msgpack::Node > &HSAMetadata, bool Strict) override
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
MCContext & getContext() const
Definition: MCStreamer.h:251
Verifier for AMDGPU HSA metadata.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
AMD Kernel Code Object (amd_kernel_code_t).
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Writes MessagePack objects to an output stream, one at a time.
Definition: MsgPackWriter.h:41
static StringRef getArchNameFromElfMach(unsigned ElfMach)
StringRef getArchNameAMDGCN(GPUKind AK)
std::error_code fromString(std::string String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:546
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:124
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:155
This is a data structure for representing MessagePack "documents", with methods to go to and from Mes...
bool hasSRAMECC(const MCSubtargetInfo &STI)
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
Streaming machine code generation interface.
Definition: MCStreamer.h:189
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:81
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:23
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
static unsigned getElfMach(StringRef GPU)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
GPUKind parseArchAMDGCN(StringRef CPU)
MCAssembler & getAssembler()
#define offsetof(TYPE, MEMBER)
bool verify(msgpack::Node &HSAMetadataRoot)
Verify given HSA metadata.
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirective[]
PAL metadata assembler directive.
unsigned getELFHeaderEFlags() const
ELF e_header flags.
Definition: MCAssembler.h:255
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:499
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:95
IsaVersion getIsaVersion(StringRef GPU)
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
Enums and constants for AMDGPU PT_NOTE sections.
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) override
MCContext & getContext() const
Module.h This file contains the declarations for the Module class.
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
MCStreamer & Streamer
Definition: MCStreamer.h:86
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:42
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
void EmitDirectiveAMDGCNTarget(StringRef Target) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
StringRef getCPU() const
Target - Wrapper for Target specific information.
bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override
bool EmitISAVersion(StringRef IsaVersionString) override
void EmitDirectiveAMDGCNTarget(StringRef Target) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
bool hasXNACK(const MCSubtargetInfo &STI)
verify safepoint Safepoint IR Verifier
bool EmitISAVersion(StringRef IsaVersionString) override
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc()) override
Emit a label for Symbol into the current section.
bool EmitHSAMetadata(std::shared_ptr< msgpack::Node > &HSAMetadata, bool Strict) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:483
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:377
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:340
const char SectionName[]
Definition: AMDGPUPTNote.h:24
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
GPUKind parseArchR600(StringRef CPU)
std::string toString(wasm::WasmSymbolType type)
Definition: Wasm.cpp:12
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
std::vector< uint32_t > Metadata
PAL metadata represented as a vector.