LLVM  6.0.0svn
ARCBranchFinalize.cpp
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1 //===- ARCBranchFinalize.cpp - ARC conditional branches ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass takes existing conditional branches and expands them into longer
11 // range conditional branches.
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "arc-branch-finalize"
15 
16 #include "ARCInstrInfo.h"
17 #include "ARCTargetMachine.h"
18 #include "MCTargetDesc/ARCInfo.h"
22 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Support/Debug.h"
25 #include <vector>
26 
27 using namespace llvm;
28 
29 namespace llvm {
30 
33 
34 } // end namespace llvm
35 
36 namespace {
37 
38 class ARCBranchFinalize : public MachineFunctionPass {
39 public:
40  static char ID;
41 
42  ARCBranchFinalize() : MachineFunctionPass(ID) {
44  }
45 
46  StringRef getPassName() const override {
47  return "ARC Branch Finalization Pass";
48  }
49 
50  bool runOnMachineFunction(MachineFunction &MF) override;
51  void replaceWithBRcc(MachineInstr *MI) const;
52  void replaceWithCmpBcc(MachineInstr *MI) const;
53 
54 private:
55  const ARCInstrInfo *TII{nullptr};
56 };
57 
58 char ARCBranchFinalize::ID = 0;
59 
60 } // end anonymous namespace
61 
62 INITIALIZE_PASS_BEGIN(ARCBranchFinalize, "arc-branch-finalize",
63  "ARC finalize branches", false, false)
65 INITIALIZE_PASS_END(ARCBranchFinalize, "arc-branch-finalize",
66  "ARC finalize branches", false, false)
67 
68 // BRcc has 6 supported condition codes, which differ from the 16
69 // condition codes supported in the predicated instructions:
70 // EQ -- 000
71 // NE -- 001
72 // LT -- 010
73 // GE -- 011
74 // LO -- 100
75 // HS -- 101
76 static unsigned getCCForBRcc(unsigned CC) {
77  switch (CC) {
78  case ARCCC::EQ:
79  return 0;
80  case ARCCC::NE:
81  return 1;
82  case ARCCC::LT:
83  return 2;
84  case ARCCC::GE:
85  return 3;
86  case ARCCC::LO:
87  return 4;
88  case ARCCC::HS:
89  return 5;
90  default:
91  return -1U;
92  }
93 }
94 
95 static bool isBRccPseudo(MachineInstr *MI) {
96  return !(MI->getOpcode() != ARC::BRcc_rr_p &&
97  MI->getOpcode() != ARC::BRcc_ru6_p);
98 }
99 
100 static unsigned getBRccForPseudo(MachineInstr *MI) {
101  assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction.");
102  if (MI->getOpcode() == ARC::BRcc_rr_p)
103  return ARC::BRcc_rr;
104  return ARC::BRcc_ru6;
105 }
106 
107 static unsigned getCmpForPseudo(MachineInstr *MI) {
108  assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction.");
109  if (MI->getOpcode() == ARC::BRcc_rr_p)
110  return ARC::CMP_rr;
111  return ARC::CMP_ru6;
112 }
113 
114 void ARCBranchFinalize::replaceWithBRcc(MachineInstr *MI) const {
115  DEBUG(dbgs() << "Replacing pseudo branch with BRcc\n");
116  unsigned CC = getCCForBRcc(MI->getOperand(3).getImm());
117  if (CC != -1U) {
118  BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
119  TII->get(getBRccForPseudo(MI)))
120  .addMBB(MI->getOperand(0).getMBB())
121  .addReg(MI->getOperand(1).getReg())
122  .add(MI->getOperand(2))
123  .addImm(getCCForBRcc(MI->getOperand(3).getImm()));
124  MI->eraseFromParent();
125  } else {
126  replaceWithCmpBcc(MI);
127  }
128 }
129 
130 void ARCBranchFinalize::replaceWithCmpBcc(MachineInstr *MI) const {
131  DEBUG(dbgs() << "Branch: " << *MI << "\n");
132  DEBUG(dbgs() << "Replacing pseudo branch with Cmp + Bcc\n");
133  BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
134  TII->get(getCmpForPseudo(MI)))
135  .addReg(MI->getOperand(1).getReg())
136  .add(MI->getOperand(2));
137  BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc))
138  .addMBB(MI->getOperand(0).getMBB())
139  .addImm(MI->getOperand(3).getImm());
140  MI->eraseFromParent();
141 }
142 
143 bool ARCBranchFinalize::runOnMachineFunction(MachineFunction &MF) {
144  DEBUG(dbgs() << "Running ARC Branch Finalize on "
145  << MF.getFunction()->getName() << "\n");
146  std::vector<MachineInstr *> Branches;
147  bool Changed = false;
148  unsigned MaxSize = 0;
149  TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo();
150  std::map<MachineBasicBlock *, unsigned> BlockToPCMap;
151  std::vector<std::pair<MachineInstr *, unsigned>> BranchToPCList;
152  unsigned PC = 0;
153 
154  for (auto &MBB : MF) {
155  BlockToPCMap.insert(std::make_pair(&MBB, PC));
156  for (auto &MI : MBB) {
157  unsigned Size = TII->getInstSizeInBytes(MI);
158  if (Size > 8 || Size == 0) {
159  DEBUG(dbgs() << "Unknown (or size 0) size for: " << MI << "\n");
160  } else {
161  MaxSize += Size;
162  }
163  if (MI.isBranch()) {
164  Branches.push_back(&MI);
165  BranchToPCList.emplace_back(&MI, PC);
166  }
167  PC += Size;
168  }
169  }
170  for (auto P : BranchToPCList) {
171  if (isBRccPseudo(P.first))
172  isInt<9>(MaxSize) ? replaceWithBRcc(P.first) : replaceWithCmpBcc(P.first);
173  }
174 
175  DEBUG(dbgs() << "Estimated function size for " << MF.getFunction()->getName()
176  << ": " << MaxSize << "\n");
177 
178  return Changed;
179 }
180 
182  return new ARCBranchFinalize();
183 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
MachineBasicBlock * getMBB() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
arc branch finalize
arc branch ARC finalize branches
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
unsigned getReg() const
getReg - Returns the register number.
void initializeARCBranchFinalizePass(PassRegistry &Registry)
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:45
static bool isBRccPseudo(MachineInstr *MI)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
arc branch ARC finalize static false unsigned getCCForBRcc(unsigned CC)
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:482
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
INITIALIZE_PASS_BEGIN(ARCBranchFinalize, "arc-branch-finalize", "ARC finalize branches", false, false) INITIALIZE_PASS_END(ARCBranchFinalize
static unsigned getBRccForPseudo(MachineInstr *MI)
FunctionPass * createARCBranchFinalizePass()
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
objc arc
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
static unsigned getCmpForPseudo(MachineInstr *MI)
Representation of each machine instruction.
Definition: MachineInstr.h:59
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:220
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...