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ARMBaseInfo.h
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1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
18 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
19 
20 #include "ARMMCTargetDesc.h"
22 
23 namespace llvm {
24 
25 // Enums corresponding to ARM condition codes
26 namespace ARMCC {
27  // The CondCodes constants map directly to the 4-bit encoding of the
28  // condition field for predicated instructions.
29  enum CondCodes { // Meaning (integer) Meaning (floating-point)
30  EQ, // Equal Equal
31  NE, // Not equal Not equal, or unordered
32  HS, // Carry set >, ==, or unordered
33  LO, // Carry clear Less than
34  MI, // Minus, negative Less than
35  PL, // Plus, positive or zero >, ==, or unordered
36  VS, // Overflow Unordered
37  VC, // No overflow Not unordered
38  HI, // Unsigned higher Greater than, or unordered
39  LS, // Unsigned lower or same Less than or equal
40  GE, // Greater than or equal Greater than or equal
41  LT, // Less than Less than, or unordered
42  GT, // Greater than Greater than
43  LE, // Less than or equal <, ==, or unordered
44  AL // Always (unconditional) Always (unconditional)
45  };
46 
48  switch (CC) {
49  default: llvm_unreachable("Unknown condition code");
50  case EQ: return NE;
51  case NE: return EQ;
52  case HS: return LO;
53  case LO: return HS;
54  case MI: return PL;
55  case PL: return MI;
56  case VS: return VC;
57  case VC: return VS;
58  case HI: return LS;
59  case LS: return HI;
60  case GE: return LT;
61  case LT: return GE;
62  case GT: return LE;
63  case LE: return GT;
64  }
65  }
66 } // namespace ARMCC
67 
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
69  switch (CC) {
70  case ARMCC::EQ: return "eq";
71  case ARMCC::NE: return "ne";
72  case ARMCC::HS: return "hs";
73  case ARMCC::LO: return "lo";
74  case ARMCC::MI: return "mi";
75  case ARMCC::PL: return "pl";
76  case ARMCC::VS: return "vs";
77  case ARMCC::VC: return "vc";
78  case ARMCC::HI: return "hi";
79  case ARMCC::LS: return "ls";
80  case ARMCC::GE: return "ge";
81  case ARMCC::LT: return "lt";
82  case ARMCC::GT: return "gt";
83  case ARMCC::LE: return "le";
84  case ARMCC::AL: return "al";
85  }
86  llvm_unreachable("Unknown condition code");
87 }
88 
89 namespace ARM_PROC {
90  enum IMod {
91  IE = 2,
92  ID = 3
93  };
94 
95  enum IFlags {
96  F = 1,
97  I = 2,
98  A = 4
99  };
100 
101  inline static const char *IFlagsToString(unsigned val) {
102  switch (val) {
103  default: llvm_unreachable("Unknown iflags operand");
104  case F: return "f";
105  case I: return "i";
106  case A: return "a";
107  }
108  }
109 
110  inline static const char *IModToString(unsigned val) {
111  switch (val) {
112  default: llvm_unreachable("Unknown imod operand");
113  case IE: return "ie";
114  case ID: return "id";
115  }
116  }
117 }
118 
119 namespace ARM_MB {
120  // The Memory Barrier Option constants map directly to the 4-bit encoding of
121  // the option field for memory barrier operations.
122  enum MemBOpt {
124  OSHLD = 1,
125  OSHST = 2,
126  OSH = 3,
128  NSHLD = 5,
129  NSHST = 6,
130  NSH = 7,
132  ISHLD = 9,
133  ISHST = 10,
134  ISH = 11,
136  LD = 13,
137  ST = 14,
138  SY = 15
139  };
140 
141  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
142  switch (val) {
143  default: llvm_unreachable("Unknown memory operation");
144  case SY: return "sy";
145  case ST: return "st";
146  case LD: return HasV8 ? "ld" : "#0xd";
147  case RESERVED_12: return "#0xc";
148  case ISH: return "ish";
149  case ISHST: return "ishst";
150  case ISHLD: return HasV8 ? "ishld" : "#0x9";
151  case RESERVED_8: return "#0x8";
152  case NSH: return "nsh";
153  case NSHST: return "nshst";
154  case NSHLD: return HasV8 ? "nshld" : "#0x5";
155  case RESERVED_4: return "#0x4";
156  case OSH: return "osh";
157  case OSHST: return "oshst";
158  case OSHLD: return HasV8 ? "oshld" : "#0x1";
159  case RESERVED_0: return "#0x0";
160  }
161  }
162 } // namespace ARM_MB
163 
164 namespace ARM_ISB {
181  SY = 15
182  };
183 
184  inline static const char *InstSyncBOptToString(unsigned val) {
185  switch (val) {
186  default:
187  llvm_unreachable("Unknown memory operation");
188  case RESERVED_0: return "#0x0";
189  case RESERVED_1: return "#0x1";
190  case RESERVED_2: return "#0x2";
191  case RESERVED_3: return "#0x3";
192  case RESERVED_4: return "#0x4";
193  case RESERVED_5: return "#0x5";
194  case RESERVED_6: return "#0x6";
195  case RESERVED_7: return "#0x7";
196  case RESERVED_8: return "#0x8";
197  case RESERVED_9: return "#0x9";
198  case RESERVED_10: return "#0xa";
199  case RESERVED_11: return "#0xb";
200  case RESERVED_12: return "#0xc";
201  case RESERVED_13: return "#0xd";
202  case RESERVED_14: return "#0xe";
203  case SY: return "sy";
204  }
205  }
206 } // namespace ARM_ISB
207 
208 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
209 ///
210 static inline bool isARMLowRegister(unsigned Reg) {
211  using namespace ARM;
212  switch (Reg) {
213  case R0: case R1: case R2: case R3:
214  case R4: case R5: case R6: case R7:
215  return true;
216  default:
217  return false;
218  }
219 }
220 
221 /// ARMII - This namespace holds all of the target specific flags that
222 /// instruction info tracks.
223 ///
224 namespace ARMII {
225 
226  /// ARM Index Modes
227  enum IndexMode {
232  };
233 
234  /// ARM Addressing Modes
235  enum AddrMode {
246  AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
250  AddrModeT2_pc = 14, // +/- i12 for pc relative data
251  AddrModeT2_i8s4 = 15, // i8 * 4
253  };
254 
255  inline static const char *AddrModeToString(AddrMode addrmode) {
256  switch (addrmode) {
257  case AddrModeNone: return "AddrModeNone";
258  case AddrMode1: return "AddrMode1";
259  case AddrMode2: return "AddrMode2";
260  case AddrMode3: return "AddrMode3";
261  case AddrMode4: return "AddrMode4";
262  case AddrMode5: return "AddrMode5";
263  case AddrMode6: return "AddrMode6";
264  case AddrModeT1_1: return "AddrModeT1_1";
265  case AddrModeT1_2: return "AddrModeT1_2";
266  case AddrModeT1_4: return "AddrModeT1_4";
267  case AddrModeT1_s: return "AddrModeT1_s";
268  case AddrModeT2_i12: return "AddrModeT2_i12";
269  case AddrModeT2_i8: return "AddrModeT2_i8";
270  case AddrModeT2_so: return "AddrModeT2_so";
271  case AddrModeT2_pc: return "AddrModeT2_pc";
272  case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
273  case AddrMode_i12: return "AddrMode_i12";
274  }
275  }
276 
277  /// Target Operand Flag enum.
278  enum TOF {
279  //===------------------------------------------------------------------===//
280  // ARM Specific MachineOperand flags.
281 
283 
284  /// MO_LO16 - On a symbol operand, this represents a relocation containing
285  /// lower 16 bit of the address. Used only via movw instruction.
286  MO_LO16 = 0x1,
287 
288  /// MO_HI16 - On a symbol operand, this represents a relocation containing
289  /// higher 16 bit of the address. Used only via movt instruction.
290  MO_HI16 = 0x2,
291 
292  /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
293  /// just that part of the flag set.
295 
296  /// MO_SBREL - On a symbol operand, this represents a static base relative
297  /// relocation. Used in movw and movt instructions.
298  MO_SBREL = 0x10,
299 
300  /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
301  /// to the symbol is for an import stub. This is used for DLL import
302  /// storage class indication on Windows.
303  MO_DLLIMPORT = 0x20,
304 
305  /// MO_SECREL - On a symbol operand this indicates that the immediate is
306  /// the offset from beginning of section.
307  ///
308  /// This is the TLS offset for the COFF/Windows TLS mechanism.
309  MO_SECREL = 0x40,
310 
311  /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
312  /// represents a symbol which, if indirect, will get special Darwin mangling
313  /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
314  /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
315  /// example).
316  MO_NONLAZY = 0x80,
317 
318  // It's undefined behaviour if an enum overflows the range between its
319  // smallest and largest values, but since these are |ed together, it can
320  // happen. Put a sentinel in (values of this enum are stored as "unsigned
321  // char").
323  };
324 
325  enum {
326  //===------------------------------------------------------------------===//
327  // Instruction Flags.
328 
329  //===------------------------------------------------------------------===//
330  // This four-bit field describes the addressing mode used.
331  AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
332 
333  // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
334  // and store ops only. Generic "updating" flag is used for ld/st multiple.
335  // The index mode enums are declared in ARMBaseInfo.h
338 
339  //===------------------------------------------------------------------===//
340  // Instruction encoding formats.
341  //
343  FormMask = 0x3f << FormShift,
344 
345  // Pseudo instructions
346  Pseudo = 0 << FormShift,
347 
348  // Multiply instructions
350 
351  // Branch instructions
352  BrFrm = 2 << FormShift,
354 
355  // Data Processing instructions
356  DPFrm = 4 << FormShift,
358 
359  // Load and Store
360  LdFrm = 6 << FormShift,
361  StFrm = 7 << FormShift,
365 
367 
368  // Miscellaneous arithmetic instructions
370  SatFrm = 13 << FormShift,
371 
372  // Extend instructions
373  ExtFrm = 14 << FormShift,
374 
375  // VFP formats
386 
387  // Thumb format
389 
390  // Miscelleaneous format
392 
393  // NEON formats
409 
410  //===------------------------------------------------------------------===//
411  // Misc flags.
412 
413  // UnaryDP - Indicates this is a unary data processing instruction, i.e.
414  // it doesn't have a Rn operand.
415  UnaryDP = 1 << 13,
416 
417  // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
418  // a 16-bit Thumb instruction if certain conditions are met.
419  Xform16Bit = 1 << 14,
420 
421  // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
422  // instruction. Used by the parser to determine whether to require the 'S'
423  // suffix on the mnemonic (when not in an IT block) or preclude it (when
424  // in an IT block).
426 
427  //===------------------------------------------------------------------===//
428  // Code domain.
435 
436  //===------------------------------------------------------------------===//
437  // Field shifts - such shifts are used to set field while generating
438  // machine instructions.
439  //
440  // FIXME: This list will need adjusting/fixing as the MC code emitter
441  // takes shape and the ARMCodeEmitter.cpp bits go away.
443 
464  };
465 
466 } // end namespace ARMII
467 
468 } // end namespace llvm;
469 
470 #endif
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:303
#define R4(n)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
TOF
Target Operand Flag enum.
Definition: ARMBaseInfo.h:278
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:227
#define R2(n)
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
Definition: ARMBaseInfo.h:298
Reg
All possible values of the reg field in the ModR/M byte.
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: ARMBaseInfo.h:309
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:184
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:286
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:68
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:110
#define R6(n)
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:141
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:101
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:210
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:47
#define I(x, y, z)
Definition: MD5.cpp:58
MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects just that part of the flag set...
Definition: ARMBaseInfo.h:294
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:316
static const char * AddrModeToString(AddrMode addrmode)
Definition: ARMBaseInfo.h:255
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:290