LLVM  6.0.0svn
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ARMBaseInstrInfo.h File Reference
#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/Target/TargetInstrInfo.h"
#include <array>
#include <cstdint>
#include "ARMGenInstrInfo.inc"
Include dependency graph for ARMBaseInstrInfo.h:
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Classes

class  llvm::ARMBaseInstrInfo
 

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define GET_INSTRINFO_HEADER
 

Functions

static std::array< MachineOperand, 2 > llvm::predOps (ARMCC::CondCodes Pred, unsigned PredReg=0)
 Get the operands corresponding to the given Pred value. More...
 
static MachineOperand llvm::condCodeOp (unsigned CCReg=0)
 Get the operand corresponding to the conditional code result. More...
 
static MachineOperand llvm::t1CondCodeOp (bool isDead=false)
 Get the operand corresponding to the conditional code result for Thumb1. More...
 
static bool llvm::isUncondBranchOpcode (int Opc)
 
static bool llvm::isCondBranchOpcode (int Opc)
 
static bool llvm::isJumpTableBranchOpcode (int Opc)
 
static bool llvm::isIndirectBranchOpcode (int Opc)
 
static bool llvm::isPopOpcode (int Opc)
 
static bool llvm::isPushOpcode (int Opc)
 
ARMCC::CondCodes llvm::getInstrPredicate (const MachineInstr &MI, unsigned &PredReg)
 getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL. More...
 
unsigned llvm::getMatchingCondBranchOpcode (unsigned Opc)
 
unsigned llvm::canFoldARMInstrIntoMOVCC (unsigned Reg, MachineInstr *&MI, const MachineRegisterInfo &MRI)
 Determine if MI can be folded into an ARM MOVCC instruction, and return the opcode of the SSA instruction representing the conditional MI. More...
 
unsigned llvm::convertAddSubFlagsOpcode (unsigned OldOpc)
 Map pseudo instructions that imply an 'S' bit onto real opcodes. More...
 
void llvm::emitARMRegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
 emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea destreg = basereg + immediate in ARM / Thumb2 code. More...
 
void llvm::emitT2RegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
 
void llvm::emitThumbRegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
 emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immediate in Thumb code. More...
 
bool llvm::tryFoldSPUpdateIntoPushPop (const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
 Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the stack by an additional NumBytes. More...
 
bool llvm::rewriteARMFrameIndex (MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
 rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP. More...
 
bool llvm::rewriteT2FrameIndex (MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
 

Macro Definition Documentation

◆ GET_INSTRINFO_HEADER

#define GET_INSTRINFO_HEADER

Definition at line 28 of file ARMBaseInstrInfo.h.