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ARMBaseInstrInfo.h
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
16 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
25 #include <array>
26 #include <cstdint>
27 
28 #define GET_INSTRINFO_HEADER
29 #include "ARMGenInstrInfo.inc"
30 
31 namespace llvm {
32 
33 class ARMBaseRegisterInfo;
34 class ARMSubtarget;
35 
37  const ARMSubtarget &Subtarget;
38 
39 protected:
40  // Can be only subclassed.
41  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
42 
44  unsigned LoadImmOpc, unsigned LoadOpc) const;
45 
46  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
47  /// and \p DefIdx.
48  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
49  /// the list is modeled as <Reg:SubReg, SubIdx>.
50  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
51  /// two elements:
52  /// - %1:sub1, sub0
53  /// - %2<:0>, sub1
54  ///
55  /// \returns true if it is possible to build such an input sequence
56  /// with the pair \p MI, \p DefIdx. False otherwise.
57  ///
58  /// \pre MI.isRegSequenceLike().
60  const MachineInstr &MI, unsigned DefIdx,
61  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
62 
63  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
64  /// and \p DefIdx.
65  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
66  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
67  /// - %1:sub1, sub0
68  ///
69  /// \returns true if it is possible to build such an input sequence
70  /// with the pair \p MI, \p DefIdx. False otherwise.
71  ///
72  /// \pre MI.isExtractSubregLike().
73  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
74  RegSubRegPairAndIdx &InputReg) const override;
75 
76  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
77  /// and \p DefIdx.
78  /// \p [out] BaseReg and \p [out] InsertedReg contain
79  /// the equivalent inputs of INSERT_SUBREG.
80  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
81  /// - BaseReg: %0:sub0
82  /// - InsertedReg: %1:sub1, sub3
83  ///
84  /// \returns true if it is possible to build such an input sequence
85  /// with the pair \p MI, \p DefIdx. False otherwise.
86  ///
87  /// \pre MI.isInsertSubregLike().
88  bool
89  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90  RegSubRegPair &BaseReg,
91  RegSubRegPairAndIdx &InsertedReg) const override;
92 
93  /// Commutes the operands in the given instruction.
94  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
95  ///
96  /// Do not call this method for a non-commutable instruction or for
97  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
98  /// Even though the instruction is commutable, the method may still
99  /// fail to commute the operands, null pointer is returned in such cases.
101  unsigned OpIdx1,
102  unsigned OpIdx2) const override;
103 
104 public:
105  // Return whether the target has an explicit NOP encoding.
106  bool hasNOP() const;
107 
108  // Return the non-pre/post incrementing version of 'Opc'. Return 0
109  // if there is not such an opcode.
110  virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
111 
113  MachineInstr &MI,
114  LiveVariables *LV) const override;
115 
116  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
117  const ARMSubtarget &getSubtarget() const { return Subtarget; }
118 
121  const ScheduleDAG *DAG) const override;
122 
125  const ScheduleDAG *DAG) const override;
126 
127  // Branch analysis.
129  MachineBasicBlock *&FBB,
131  bool AllowModify = false) const override;
132  unsigned removeBranch(MachineBasicBlock &MBB,
133  int *BytesRemoved = nullptr) const override;
136  const DebugLoc &DL,
137  int *BytesAdded = nullptr) const override;
138 
139  bool
141 
142  // Predication support.
143  bool isPredicated(const MachineInstr &MI) const override;
144 
146  int PIdx = MI.findFirstPredOperandIdx();
147  return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
148  : ARMCC::AL;
149  }
150 
152  ArrayRef<MachineOperand> Pred) const override;
153 
155  ArrayRef<MachineOperand> Pred2) const override;
156 
158  std::vector<MachineOperand> &Pred) const override;
159 
160  bool isPredicable(const MachineInstr &MI) const override;
161 
162  // CPSR defined in instruction
163  static bool isCPSRDefined(const MachineInstr &MI);
164  bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
165  bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
166 
167  // Load, scaled register offset
168  bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
169  // Load, scaled register offset, not plus LSL2
170  bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
171  // Minus reg for ldstso addr mode
172  bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
173  // Scaled register offset in address mode 2
174  bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
175  // Load multiple, base reg in list
176  bool isLDMBaseRegInList(const MachineInstr &MI) const;
177  // get LDM variable defs size
178  unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
179 
180  /// GetInstSize - Returns the size of the specified MachineInstr.
181  ///
182  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
183 
184  unsigned isLoadFromStackSlot(const MachineInstr &MI,
185  int &FrameIndex) const override;
186  unsigned isStoreToStackSlot(const MachineInstr &MI,
187  int &FrameIndex) const override;
188  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
189  int &FrameIndex) const override;
190  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
191  int &FrameIndex) const override;
192 
194  unsigned SrcReg, bool KillSrc,
195  const ARMSubtarget &Subtarget) const;
197  unsigned DestReg, bool KillSrc,
198  const ARMSubtarget &Subtarget) const;
199 
201  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
202  bool KillSrc) const override;
203 
206  unsigned SrcReg, bool isKill, int FrameIndex,
207  const TargetRegisterClass *RC,
208  const TargetRegisterInfo *TRI) const override;
209 
212  unsigned DestReg, int FrameIndex,
213  const TargetRegisterClass *RC,
214  const TargetRegisterInfo *TRI) const override;
215 
216  bool expandPostRAPseudo(MachineInstr &MI) const override;
217 
218  bool shouldSink(const MachineInstr &MI) const override;
219 
221  unsigned DestReg, unsigned SubIdx,
222  const MachineInstr &Orig,
223  const TargetRegisterInfo &TRI) const override;
224 
225  MachineInstr &
227  const MachineInstr &Orig) const override;
228 
229  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
230  unsigned SubIdx, unsigned State,
231  const TargetRegisterInfo *TRI) const;
232 
233  bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
234  const MachineRegisterInfo *MRI) const override;
235 
236  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
237  /// determine if two loads are loading from the same base address. It should
238  /// only return true if the base pointers are the same and the only
239  /// differences between the two addresses is the offset. It also returns the
240  /// offsets by reference.
241  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
242  int64_t &Offset2) const override;
243 
244  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
245  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
246  /// should be scheduled togther. On some targets if two loads are loading from
247  /// addresses in the same cache line, it's better if they are scheduled
248  /// together. This function takes two integers that represent the load offsets
249  /// from the common base address. It returns true if it decides it's desirable
250  /// to schedule the two loads together. "NumLoads" is the number of loads that
251  /// have already been scheduled after Load1.
252  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
253  int64_t Offset1, int64_t Offset2,
254  unsigned NumLoads) const override;
255 
256  bool isSchedulingBoundary(const MachineInstr &MI,
257  const MachineBasicBlock *MBB,
258  const MachineFunction &MF) const override;
259 
261  unsigned NumCycles, unsigned ExtraPredCycles,
262  BranchProbability Probability) const override;
263 
264  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
265  unsigned ExtraT, MachineBasicBlock &FMBB,
266  unsigned NumF, unsigned ExtraF,
267  BranchProbability Probability) const override;
268 
269  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
270  BranchProbability Probability) const override {
271  return NumCycles == 1;
272  }
273 
275  MachineBasicBlock &FMBB) const override;
276 
277  /// analyzeCompare - For a comparison instruction, return the source registers
278  /// in SrcReg and SrcReg2 if having two register operands, and the value it
279  /// compares against in CmpValue. Return true if the comparison instruction
280  /// can be analyzed.
281  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
282  unsigned &SrcReg2, int &CmpMask,
283  int &CmpValue) const override;
284 
285  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
286  /// that we can remove a "comparison with zero"; Remove a redundant CMP
287  /// instruction if the flags can be updated in the same way by an earlier
288  /// instruction such as SUB.
289  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
290  unsigned SrcReg2, int CmpMask, int CmpValue,
291  const MachineRegisterInfo *MRI) const override;
292 
293  bool analyzeSelect(const MachineInstr &MI,
294  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
295  unsigned &FalseOp, bool &Optimizable) const override;
296 
299  bool) const override;
300 
301  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
302  /// instruction, try to fold the immediate into the use instruction.
303  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
304  MachineRegisterInfo *MRI) const override;
305 
306  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
307  const MachineInstr &MI) const override;
308 
309  int getOperandLatency(const InstrItineraryData *ItinData,
310  const MachineInstr &DefMI, unsigned DefIdx,
311  const MachineInstr &UseMI,
312  unsigned UseIdx) const override;
313  int getOperandLatency(const InstrItineraryData *ItinData,
314  SDNode *DefNode, unsigned DefIdx,
315  SDNode *UseNode, unsigned UseIdx) const override;
316 
317  /// VFP/NEON execution domains.
318  std::pair<uint16_t, uint16_t>
319  getExecutionDomain(const MachineInstr &MI) const override;
320  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
321 
322  unsigned
323  getPartialRegUpdateClearance(const MachineInstr &, unsigned,
324  const TargetRegisterInfo *) const override;
325  void breakPartialRegDependency(MachineInstr &, unsigned,
326  const TargetRegisterInfo *TRI) const override;
327 
328  /// Get the number of addresses by LDM or VLDM or zero for unknown.
329  unsigned getNumLDMAddresses(const MachineInstr &MI) const;
330 
331 private:
332  unsigned getInstBundleLength(const MachineInstr &MI) const;
333 
334  int getVLDMDefCycle(const InstrItineraryData *ItinData,
335  const MCInstrDesc &DefMCID,
336  unsigned DefClass,
337  unsigned DefIdx, unsigned DefAlign) const;
338  int getLDMDefCycle(const InstrItineraryData *ItinData,
339  const MCInstrDesc &DefMCID,
340  unsigned DefClass,
341  unsigned DefIdx, unsigned DefAlign) const;
342  int getVSTMUseCycle(const InstrItineraryData *ItinData,
343  const MCInstrDesc &UseMCID,
344  unsigned UseClass,
345  unsigned UseIdx, unsigned UseAlign) const;
346  int getSTMUseCycle(const InstrItineraryData *ItinData,
347  const MCInstrDesc &UseMCID,
348  unsigned UseClass,
349  unsigned UseIdx, unsigned UseAlign) const;
350  int getOperandLatency(const InstrItineraryData *ItinData,
351  const MCInstrDesc &DefMCID,
352  unsigned DefIdx, unsigned DefAlign,
353  const MCInstrDesc &UseMCID,
354  unsigned UseIdx, unsigned UseAlign) const;
355 
356  int getOperandLatencyImpl(const InstrItineraryData *ItinData,
357  const MachineInstr &DefMI, unsigned DefIdx,
358  const MCInstrDesc &DefMCID, unsigned DefAdj,
359  const MachineOperand &DefMO, unsigned Reg,
360  const MachineInstr &UseMI, unsigned UseIdx,
361  const MCInstrDesc &UseMCID, unsigned UseAdj) const;
362 
363  unsigned getPredicationCost(const MachineInstr &MI) const override;
364 
365  unsigned getInstrLatency(const InstrItineraryData *ItinData,
366  const MachineInstr &MI,
367  unsigned *PredCost = nullptr) const override;
368 
369  int getInstrLatency(const InstrItineraryData *ItinData,
370  SDNode *Node) const override;
371 
372  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
373  const MachineRegisterInfo *MRI,
374  const MachineInstr &DefMI, unsigned DefIdx,
375  const MachineInstr &UseMI,
376  unsigned UseIdx) const override;
377  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
378  const MachineInstr &DefMI,
379  unsigned DefIdx) const override;
380 
381  /// verifyInstruction - Perform target specific instruction verification.
382  bool verifyInstruction(const MachineInstr &MI,
383  StringRef &ErrInfo) const override;
384 
385  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
386 
387  void expandMEMCPY(MachineBasicBlock::iterator) const;
388 
389 private:
390  /// Modeling special VFP / NEON fp MLA / MLS hazards.
391 
392  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
393  /// MLx table.
394  DenseMap<unsigned, unsigned> MLxEntryMap;
395 
396  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
397  /// stalls when scheduled together with fp MLA / MLS opcodes.
398  SmallSet<unsigned, 16> MLxHazardOpcodes;
399 
400 public:
401  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
402  /// instruction.
403  bool isFpMLxInstruction(unsigned Opcode) const {
404  return MLxEntryMap.count(Opcode);
405  }
406 
407  /// isFpMLxInstruction - This version also returns the multiply opcode and the
408  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
409  /// the MLX instructions with an extra lane operand.
410  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
411  unsigned &AddSubOpc, bool &NegAcc,
412  bool &HasLane) const;
413 
414  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
415  /// will cause stalls when scheduled after (within 4-cycle window) a fp
416  /// MLA / MLS instruction.
417  bool canCauseFpMLxStall(unsigned Opcode) const {
418  return MLxHazardOpcodes.count(Opcode);
419  }
420 
421  /// Returns true if the instruction has a shift by immediate that can be
422  /// executed in one cycle less.
423  bool isSwiftFastImmShift(const MachineInstr *MI) const;
424 
425  /// Returns predicate register associated with the given frame instruction.
426  unsigned getFramePred(const MachineInstr &MI) const {
427  assert(isFrameInstr(MI));
428  // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
429  // - argument declared in the pattern:
430  // 0 - frame size
431  // 1 - arg of CALLSEQ_START/CALLSEQ_END
432  // 2 - predicate code (like ARMCC::AL)
433  // - added by predOps:
434  // 3 - predicate reg
435  return MI.getOperand(3).getReg();
436  }
437 };
438 
439 /// Get the operands corresponding to the given \p Pred value. By default, the
440 /// predicate register is assumed to be 0 (no register), but you can pass in a
441 /// \p PredReg if that is not the case.
442 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
443  unsigned PredReg = 0) {
444  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
445  MachineOperand::CreateReg(PredReg, false)}};
446 }
447 
448 /// Get the operand corresponding to the conditional code result. By default,
449 /// this is 0 (no register).
450 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
451  return MachineOperand::CreateReg(CCReg, false);
452 }
453 
454 /// Get the operand corresponding to the conditional code result for Thumb1.
455 /// This operand will always refer to CPSR and it will have the Define flag set.
456 /// You can optionally set the Dead flag by means of \p isDead.
457 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
458  return MachineOperand::CreateReg(ARM::CPSR,
459  /*Define*/ true, /*Implicit*/ false,
460  /*Kill*/ false, isDead);
461 }
462 
463 static inline
464 bool isUncondBranchOpcode(int Opc) {
465  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
466 }
467 
468 static inline
469 bool isCondBranchOpcode(int Opc) {
470  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
471 }
472 
473 static inline bool isJumpTableBranchOpcode(int Opc) {
474  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
475  Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
476  Opc == ARM::t2BR_JT;
477 }
478 
479 static inline
480 bool isIndirectBranchOpcode(int Opc) {
481  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
482 }
483 
484 static inline bool isPopOpcode(int Opc) {
485  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
486  Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
487  Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
488 }
489 
490 static inline bool isPushOpcode(int Opc) {
491  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
492  Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
493 }
494 
495 /// getInstrPredicate - If instruction is predicated, returns its predicate
496 /// condition, otherwise returns AL. It also returns the condition code
497 /// register by reference.
498 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
499 
500 unsigned getMatchingCondBranchOpcode(unsigned Opc);
501 
502 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
503 /// opcode of the SSA instruction representing the conditional MI.
504 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
505  MachineInstr *&MI,
506  const MachineRegisterInfo &MRI);
507 
508 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
509 /// the instruction is encoded with an 'S' bit is determined by the optional
510 /// CPSR def operand.
511 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
512 
513 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
514 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
515 /// code.
518  const DebugLoc &dl, unsigned DestReg,
519  unsigned BaseReg, int NumBytes,
520  ARMCC::CondCodes Pred, unsigned PredReg,
521  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
522 
525  const DebugLoc &dl, unsigned DestReg,
526  unsigned BaseReg, int NumBytes,
527  ARMCC::CondCodes Pred, unsigned PredReg,
528  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
531  const DebugLoc &dl, unsigned DestReg,
532  unsigned BaseReg, int NumBytes,
533  const TargetInstrInfo &TII,
534  const ARMBaseRegisterInfo &MRI,
535  unsigned MIFlags = 0);
536 
537 /// Tries to add registers to the reglist of a given base-updating
538 /// push/pop instruction to adjust the stack by an additional
539 /// NumBytes. This can save a few bytes per function in code-size, but
540 /// obviously generates more memory traffic. As such, it only takes
541 /// effect in functions being optimised for size.
542 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
543  MachineFunction &MF, MachineInstr *MI,
544  unsigned NumBytes);
545 
546 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
547 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
548 /// offset could not be handled directly in MI, and return the left-over
549 /// portion by reference.
550 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
551  unsigned FrameReg, int &Offset,
552  const ARMBaseInstrInfo &TII);
553 
554 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
555  unsigned FrameReg, int &Offset,
556  const ARMBaseInstrInfo &TII);
557 
558 } // end namespace llvm
559 
560 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isPredicated(const MachineInstr &MI) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
static bool isCPSRDefined(const MachineInstr &MI)
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP...
Reg
All possible values of the reg field in the ModR/M byte.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - &#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immedia...
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
const ARMSubtarget & getSubtarget() const
unsigned getMatchingCondBranchOpcode(unsigned Opc)
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
TargetInstrInfo - Interface to description of machine instruction set.
static bool isCondBranchOpcode(int Opc)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
MachineInstrBuilder & UseMI
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
static bool isJumpTableBranchOpcode(int Opc)
bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an &#39;S&#39; bit onto real opcodes.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
static bool isIndirectBranchOpcode(int Opc)
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Iterator for intrusive lists based on ilist_node.
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
unsigned getLDMVariableDefsSize(const MachineInstr &MI) const
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
MachineOperand class - Representation of each machine instruction operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
A pair composed of a register and a sub-register index.
MachineInstrBuilder MachineInstrBuilder & DefMI
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
int64_t getImm() const
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool) const override
unsigned canFoldARMInstrIntoMOVCC(unsigned Reg, MachineInstr *&MI, const MachineRegisterInfo &MRI)
Determine if MI can be folded into an ARM MOVCC instruction, and return the opcode of the SSA instruc...
ARMBaseInstrInfo(const ARMSubtarget &STI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
static bool isPopOpcode(int Opc)
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
bool isLDMBaseRegInList(const MachineInstr &MI) const
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:141
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool shouldSink(const MachineInstr &MI) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
IRTranslator LLVM IR MI
bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
A pair composed of a pair of a register and a sub-register index, and another sub-register index...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65