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ARMBaseInstrInfo.h
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
24 #include <array>
25 #include <cstdint>
26 
27 #define GET_INSTRINFO_HEADER
28 #include "ARMGenInstrInfo.inc"
29 
30 namespace llvm {
31 
32 class ARMBaseRegisterInfo;
33 class ARMSubtarget;
34 
36  const ARMSubtarget &Subtarget;
37 
38 protected:
39  // Can be only subclassed.
40  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
41 
43  unsigned LoadImmOpc, unsigned LoadOpc) const;
44 
45  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
46  /// and \p DefIdx.
47  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
48  /// the list is modeled as <Reg:SubReg, SubIdx>.
49  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
50  /// two elements:
51  /// - %1:sub1, sub0
52  /// - %2<:0>, sub1
53  ///
54  /// \returns true if it is possible to build such an input sequence
55  /// with the pair \p MI, \p DefIdx. False otherwise.
56  ///
57  /// \pre MI.isRegSequenceLike().
59  const MachineInstr &MI, unsigned DefIdx,
60  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
61 
62  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
63  /// and \p DefIdx.
64  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
65  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
66  /// - %1:sub1, sub0
67  ///
68  /// \returns true if it is possible to build such an input sequence
69  /// with the pair \p MI, \p DefIdx. False otherwise.
70  ///
71  /// \pre MI.isExtractSubregLike().
72  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
73  RegSubRegPairAndIdx &InputReg) const override;
74 
75  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
76  /// and \p DefIdx.
77  /// \p [out] BaseReg and \p [out] InsertedReg contain
78  /// the equivalent inputs of INSERT_SUBREG.
79  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
80  /// - BaseReg: %0:sub0
81  /// - InsertedReg: %1:sub1, sub3
82  ///
83  /// \returns true if it is possible to build such an input sequence
84  /// with the pair \p MI, \p DefIdx. False otherwise.
85  ///
86  /// \pre MI.isInsertSubregLike().
87  bool
88  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
89  RegSubRegPair &BaseReg,
90  RegSubRegPairAndIdx &InsertedReg) const override;
91 
92  /// Commutes the operands in the given instruction.
93  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
94  ///
95  /// Do not call this method for a non-commutable instruction or for
96  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
97  /// Even though the instruction is commutable, the method may still
98  /// fail to commute the operands, null pointer is returned in such cases.
100  unsigned OpIdx1,
101  unsigned OpIdx2) const override;
102 
103  /// If the specific machine instruction is a instruction that moves/copies
104  /// value from one register to another register return true along with
105  /// @Source machine operand and @Destination machine operand.
106  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
107  const MachineOperand *&Destination) const override;
108 
109 public:
110  // Return whether the target has an explicit NOP encoding.
111  bool hasNOP() const;
112 
113  // Return the non-pre/post incrementing version of 'Opc'. Return 0
114  // if there is not such an opcode.
115  virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
116 
118  MachineInstr &MI,
119  LiveVariables *LV) const override;
120 
121  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
122  const ARMSubtarget &getSubtarget() const { return Subtarget; }
123 
126  const ScheduleDAG *DAG) const override;
127 
130  const ScheduleDAG *DAG) const override;
131 
132  // Branch analysis.
134  MachineBasicBlock *&FBB,
136  bool AllowModify = false) const override;
137  unsigned removeBranch(MachineBasicBlock &MBB,
138  int *BytesRemoved = nullptr) const override;
141  const DebugLoc &DL,
142  int *BytesAdded = nullptr) const override;
143 
144  bool
146 
147  // Predication support.
148  bool isPredicated(const MachineInstr &MI) const override;
149 
151  int PIdx = MI.findFirstPredOperandIdx();
152  return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
153  : ARMCC::AL;
154  }
155 
157  ArrayRef<MachineOperand> Pred) const override;
158 
160  ArrayRef<MachineOperand> Pred2) const override;
161 
163  std::vector<MachineOperand> &Pred) const override;
164 
165  bool isPredicable(const MachineInstr &MI) const override;
166 
167  // CPSR defined in instruction
168  static bool isCPSRDefined(const MachineInstr &MI);
169  bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
170  bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
171 
172  // Load, scaled register offset
173  bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
174  // Load, scaled register offset, not plus LSL2
175  bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
176  // Minus reg for ldstso addr mode
177  bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
178  // Scaled register offset in address mode 2
179  bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
180  // Load multiple, base reg in list
181  bool isLDMBaseRegInList(const MachineInstr &MI) const;
182  // get LDM variable defs size
183  unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
184 
185  /// GetInstSize - Returns the size of the specified MachineInstr.
186  ///
187  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188 
189  unsigned isLoadFromStackSlot(const MachineInstr &MI,
190  int &FrameIndex) const override;
191  unsigned isStoreToStackSlot(const MachineInstr &MI,
192  int &FrameIndex) const override;
193  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
194  int &FrameIndex) const override;
195  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
196  int &FrameIndex) const override;
197 
199  unsigned SrcReg, bool KillSrc,
200  const ARMSubtarget &Subtarget) const;
202  unsigned DestReg, bool KillSrc,
203  const ARMSubtarget &Subtarget) const;
204 
206  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
207  bool KillSrc) const override;
208 
211  unsigned SrcReg, bool isKill, int FrameIndex,
212  const TargetRegisterClass *RC,
213  const TargetRegisterInfo *TRI) const override;
214 
217  unsigned DestReg, int FrameIndex,
218  const TargetRegisterClass *RC,
219  const TargetRegisterInfo *TRI) const override;
220 
221  bool expandPostRAPseudo(MachineInstr &MI) const override;
222 
223  bool shouldSink(const MachineInstr &MI) const override;
224 
226  unsigned DestReg, unsigned SubIdx,
227  const MachineInstr &Orig,
228  const TargetRegisterInfo &TRI) const override;
229 
230  MachineInstr &
232  const MachineInstr &Orig) const override;
233 
234  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
235  unsigned SubIdx, unsigned State,
236  const TargetRegisterInfo *TRI) const;
237 
238  bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
239  const MachineRegisterInfo *MRI) const override;
240 
241  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
242  /// determine if two loads are loading from the same base address. It should
243  /// only return true if the base pointers are the same and the only
244  /// differences between the two addresses is the offset. It also returns the
245  /// offsets by reference.
246  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
247  int64_t &Offset2) const override;
248 
249  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
250  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
251  /// should be scheduled togther. On some targets if two loads are loading from
252  /// addresses in the same cache line, it's better if they are scheduled
253  /// together. This function takes two integers that represent the load offsets
254  /// from the common base address. It returns true if it decides it's desirable
255  /// to schedule the two loads together. "NumLoads" is the number of loads that
256  /// have already been scheduled after Load1.
257  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
258  int64_t Offset1, int64_t Offset2,
259  unsigned NumLoads) const override;
260 
261  bool isSchedulingBoundary(const MachineInstr &MI,
262  const MachineBasicBlock *MBB,
263  const MachineFunction &MF) const override;
264 
266  unsigned NumCycles, unsigned ExtraPredCycles,
267  BranchProbability Probability) const override;
268 
269  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
270  unsigned ExtraT, MachineBasicBlock &FMBB,
271  unsigned NumF, unsigned ExtraF,
272  BranchProbability Probability) const override;
273 
274  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
275  BranchProbability Probability) const override {
276  return NumCycles == 1;
277  }
278 
280  MachineBasicBlock &FMBB) const override;
281 
282  /// analyzeCompare - For a comparison instruction, return the source registers
283  /// in SrcReg and SrcReg2 if having two register operands, and the value it
284  /// compares against in CmpValue. Return true if the comparison instruction
285  /// can be analyzed.
286  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
287  unsigned &SrcReg2, int &CmpMask,
288  int &CmpValue) const override;
289 
290  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
291  /// that we can remove a "comparison with zero"; Remove a redundant CMP
292  /// instruction if the flags can be updated in the same way by an earlier
293  /// instruction such as SUB.
294  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
295  unsigned SrcReg2, int CmpMask, int CmpValue,
296  const MachineRegisterInfo *MRI) const override;
297 
298  bool analyzeSelect(const MachineInstr &MI,
299  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
300  unsigned &FalseOp, bool &Optimizable) const override;
301 
304  bool) const override;
305 
306  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
307  /// instruction, try to fold the immediate into the use instruction.
308  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
309  MachineRegisterInfo *MRI) const override;
310 
311  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
312  const MachineInstr &MI) const override;
313 
314  int getOperandLatency(const InstrItineraryData *ItinData,
315  const MachineInstr &DefMI, unsigned DefIdx,
316  const MachineInstr &UseMI,
317  unsigned UseIdx) const override;
318  int getOperandLatency(const InstrItineraryData *ItinData,
319  SDNode *DefNode, unsigned DefIdx,
320  SDNode *UseNode, unsigned UseIdx) const override;
321 
322  /// VFP/NEON execution domains.
323  std::pair<uint16_t, uint16_t>
324  getExecutionDomain(const MachineInstr &MI) const override;
325  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
326 
327  unsigned
328  getPartialRegUpdateClearance(const MachineInstr &, unsigned,
329  const TargetRegisterInfo *) const override;
330  void breakPartialRegDependency(MachineInstr &, unsigned,
331  const TargetRegisterInfo *TRI) const override;
332 
333  /// Get the number of addresses by LDM or VLDM or zero for unknown.
334  unsigned getNumLDMAddresses(const MachineInstr &MI) const;
335 
336  std::pair<unsigned, unsigned>
337  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
342 
343 private:
344  unsigned getInstBundleLength(const MachineInstr &MI) const;
345 
346  int getVLDMDefCycle(const InstrItineraryData *ItinData,
347  const MCInstrDesc &DefMCID,
348  unsigned DefClass,
349  unsigned DefIdx, unsigned DefAlign) const;
350  int getLDMDefCycle(const InstrItineraryData *ItinData,
351  const MCInstrDesc &DefMCID,
352  unsigned DefClass,
353  unsigned DefIdx, unsigned DefAlign) const;
354  int getVSTMUseCycle(const InstrItineraryData *ItinData,
355  const MCInstrDesc &UseMCID,
356  unsigned UseClass,
357  unsigned UseIdx, unsigned UseAlign) const;
358  int getSTMUseCycle(const InstrItineraryData *ItinData,
359  const MCInstrDesc &UseMCID,
360  unsigned UseClass,
361  unsigned UseIdx, unsigned UseAlign) const;
362  int getOperandLatency(const InstrItineraryData *ItinData,
363  const MCInstrDesc &DefMCID,
364  unsigned DefIdx, unsigned DefAlign,
365  const MCInstrDesc &UseMCID,
366  unsigned UseIdx, unsigned UseAlign) const;
367 
368  int getOperandLatencyImpl(const InstrItineraryData *ItinData,
369  const MachineInstr &DefMI, unsigned DefIdx,
370  const MCInstrDesc &DefMCID, unsigned DefAdj,
371  const MachineOperand &DefMO, unsigned Reg,
372  const MachineInstr &UseMI, unsigned UseIdx,
373  const MCInstrDesc &UseMCID, unsigned UseAdj) const;
374 
375  unsigned getPredicationCost(const MachineInstr &MI) const override;
376 
377  unsigned getInstrLatency(const InstrItineraryData *ItinData,
378  const MachineInstr &MI,
379  unsigned *PredCost = nullptr) const override;
380 
381  int getInstrLatency(const InstrItineraryData *ItinData,
382  SDNode *Node) const override;
383 
384  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
385  const MachineRegisterInfo *MRI,
386  const MachineInstr &DefMI, unsigned DefIdx,
387  const MachineInstr &UseMI,
388  unsigned UseIdx) const override;
389  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
390  const MachineInstr &DefMI,
391  unsigned DefIdx) const override;
392 
393  /// verifyInstruction - Perform target specific instruction verification.
394  bool verifyInstruction(const MachineInstr &MI,
395  StringRef &ErrInfo) const override;
396 
397  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
398 
399  void expandMEMCPY(MachineBasicBlock::iterator) const;
400 
401  /// Identify instructions that can be folded into a MOVCC instruction, and
402  /// return the defining instruction.
403  MachineInstr *canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI,
404  const TargetInstrInfo *TII) const;
405 
406 private:
407  /// Modeling special VFP / NEON fp MLA / MLS hazards.
408 
409  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
410  /// MLx table.
411  DenseMap<unsigned, unsigned> MLxEntryMap;
412 
413  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
414  /// stalls when scheduled together with fp MLA / MLS opcodes.
415  SmallSet<unsigned, 16> MLxHazardOpcodes;
416 
417 public:
418  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
419  /// instruction.
420  bool isFpMLxInstruction(unsigned Opcode) const {
421  return MLxEntryMap.count(Opcode);
422  }
423 
424  /// isFpMLxInstruction - This version also returns the multiply opcode and the
425  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
426  /// the MLX instructions with an extra lane operand.
427  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
428  unsigned &AddSubOpc, bool &NegAcc,
429  bool &HasLane) const;
430 
431  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
432  /// will cause stalls when scheduled after (within 4-cycle window) a fp
433  /// MLA / MLS instruction.
434  bool canCauseFpMLxStall(unsigned Opcode) const {
435  return MLxHazardOpcodes.count(Opcode);
436  }
437 
438  /// Returns true if the instruction has a shift by immediate that can be
439  /// executed in one cycle less.
440  bool isSwiftFastImmShift(const MachineInstr *MI) const;
441 
442  /// Returns predicate register associated with the given frame instruction.
443  unsigned getFramePred(const MachineInstr &MI) const {
444  assert(isFrameInstr(MI));
445  // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
446  // - argument declared in the pattern:
447  // 0 - frame size
448  // 1 - arg of CALLSEQ_START/CALLSEQ_END
449  // 2 - predicate code (like ARMCC::AL)
450  // - added by predOps:
451  // 3 - predicate reg
452  return MI.getOperand(3).getReg();
453  }
454 };
455 
456 /// Get the operands corresponding to the given \p Pred value. By default, the
457 /// predicate register is assumed to be 0 (no register), but you can pass in a
458 /// \p PredReg if that is not the case.
459 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
460  unsigned PredReg = 0) {
461  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462  MachineOperand::CreateReg(PredReg, false)}};
463 }
464 
465 /// Get the operand corresponding to the conditional code result. By default,
466 /// this is 0 (no register).
467 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468  return MachineOperand::CreateReg(CCReg, false);
469 }
470 
471 /// Get the operand corresponding to the conditional code result for Thumb1.
472 /// This operand will always refer to CPSR and it will have the Define flag set.
473 /// You can optionally set the Dead flag by means of \p isDead.
474 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
475  return MachineOperand::CreateReg(ARM::CPSR,
476  /*Define*/ true, /*Implicit*/ false,
477  /*Kill*/ false, isDead);
478 }
479 
480 static inline
481 bool isUncondBranchOpcode(int Opc) {
482  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
483 }
484 
485 static inline bool isVPTOpcode(int Opc) {
486  return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
487  Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
488  Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
489  Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
490  Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
491  Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
492  Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
493  Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
494  Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
495  Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
496  Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
497  Opc == ARM::MVE_VPST;
498 }
499 
500 static inline
501 bool isCondBranchOpcode(int Opc) {
502  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
503 }
504 
505 static inline bool isJumpTableBranchOpcode(int Opc) {
506  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
507  Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
508  Opc == ARM::t2BR_JT;
509 }
510 
511 static inline
512 bool isIndirectBranchOpcode(int Opc) {
513  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
514 }
515 
516 static inline bool isPopOpcode(int Opc) {
517  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
518  Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
519  Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
520 }
521 
522 static inline bool isPushOpcode(int Opc) {
523  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
524  Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
525 }
526 
527 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
528 /// number is legal in generic instructions like CDP. The answer can
529 /// vary with the subtarget.
530 static inline bool isValidCoprocessorNumber(unsigned Num,
531  const FeatureBitset& featureBits) {
532  // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
533  if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
534  return false;
535 
536  // Armv7 disallows 101x (CP10 and CP11), which clash with VFP/NEON.
537  if (featureBits[ARM::HasV7Ops] && (Num & 0xE) == 0xA)
538  return false;
539 
540  // Armv8.1-M also disallows 100x (CP8,CP9) and 111x (CP14,CP15)
541  // which clash with MVE.
542  if (featureBits[ARM::HasV8_1MMainlineOps] &&
543  ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
544  return false;
545 
546  return true;
547 }
548 
549 /// getInstrPredicate - If instruction is predicated, returns its predicate
550 /// condition, otherwise returns AL. It also returns the condition code
551 /// register by reference.
552 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
553 
554 unsigned getMatchingCondBranchOpcode(unsigned Opc);
555 
556 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
557 /// the instruction is encoded with an 'S' bit is determined by the optional
558 /// CPSR def operand.
559 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
560 
561 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
562 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
563 /// code.
566  const DebugLoc &dl, unsigned DestReg,
567  unsigned BaseReg, int NumBytes,
568  ARMCC::CondCodes Pred, unsigned PredReg,
569  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
570 
573  const DebugLoc &dl, unsigned DestReg,
574  unsigned BaseReg, int NumBytes,
575  ARMCC::CondCodes Pred, unsigned PredReg,
576  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
579  const DebugLoc &dl, unsigned DestReg,
580  unsigned BaseReg, int NumBytes,
581  const TargetInstrInfo &TII,
582  const ARMBaseRegisterInfo &MRI,
583  unsigned MIFlags = 0);
584 
585 /// Tries to add registers to the reglist of a given base-updating
586 /// push/pop instruction to adjust the stack by an additional
587 /// NumBytes. This can save a few bytes per function in code-size, but
588 /// obviously generates more memory traffic. As such, it only takes
589 /// effect in functions being optimised for size.
590 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
591  MachineFunction &MF, MachineInstr *MI,
592  unsigned NumBytes);
593 
594 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
595 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
596 /// offset could not be handled directly in MI, and return the left-over
597 /// portion by reference.
598 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
599  unsigned FrameReg, int &Offset,
600  const ARMBaseInstrInfo &TII);
601 
602 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
603  unsigned FrameReg, int &Offset,
604  const ARMBaseInstrInfo &TII);
605 
606 /// Return true if Reg is defd between From and To
609  const TargetRegisterInfo *TRI);
610 
611 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
612 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
614  const TargetRegisterInfo *TRI);
615 
617 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg);
618 
619 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
620 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
621  unsigned Inactive);
622 
623 } // end namespace llvm
624 
625 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned Reg
bool isPredicated(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
static bool isCPSRDefined(const MachineInstr &MI)
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg)
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
static bool isVPTOpcode(int Opc)
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access &#39;Offset&#39; bytes from the FP...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - &#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immedia...
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const ARMSubtarget & getSubtarget() const
unsigned getMatchingCondBranchOpcode(unsigned Opc)
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
BasicBlockListType::iterator iterator
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
TargetInstrInfo - Interface to description of machine instruction set.
static bool isCondBranchOpcode(int Opc)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
MachineInstrBuilder & UseMI
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
static bool isJumpTableBranchOpcode(int Opc)
bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an &#39;S&#39; bit onto real opcodes.
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
static bool isIndirectBranchOpcode(int Opc)
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
unsigned getLDMVariableDefsSize(const MachineInstr &MI) const
BlockVerifier::State From
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
MachineOperand class - Representation of each machine instruction operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
A pair composed of a register and a sub-register index.
MachineInstrBuilder MachineInstrBuilder & DefMI
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
int64_t getImm() const
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
ARMBaseInstrInfo(const ARMSubtarget &STI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
static bool isPopOpcode(int Opc)
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
bool isLDMBaseRegInList(const MachineInstr &MI) const
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:171
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool shouldSink(const MachineInstr &MI) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
IRTranslator LLVM IR MI
bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Register getReg() const
getReg - Returns the register number.
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164