LLVM  8.0.0svn
ARMConstantIslandPass.cpp
Go to the documentation of this file.
1 //===- ARMConstantIslandPass.cpp - ARM constant islands -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "ARM.h"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBasicBlockInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
22 #include "Thumb2InstrInfo.h"
23 #include "Utils/ARMBaseInfo.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
38 #include "llvm/Config/llvm-config.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DebugLoc.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Pass.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Format.h"
50 #include <algorithm>
51 #include <cassert>
52 #include <cstdint>
53 #include <iterator>
54 #include <utility>
55 #include <vector>
56 
57 using namespace llvm;
58 
59 #define DEBUG_TYPE "arm-cp-islands"
60 
61 #define ARM_CP_ISLANDS_OPT_NAME \
62  "ARM constant island placement and branch shortening pass"
63 STATISTIC(NumCPEs, "Number of constpool entries");
64 STATISTIC(NumSplit, "Number of uncond branches inserted");
65 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
66 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
67 STATISTIC(NumTBs, "Number of table branches generated");
68 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
69 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
70 STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
71 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
72 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
73 
74 static cl::opt<bool>
75 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
76  cl::desc("Adjust basic block layout to better use TB[BH]"));
77 
78 static cl::opt<unsigned>
79 CPMaxIteration("arm-constant-island-max-iteration", cl::Hidden, cl::init(30),
80  cl::desc("The max number of iteration for converge"));
81 
83  "arm-synthesize-thumb-1-tbb", cl::Hidden, cl::init(true),
84  cl::desc("Use compressed jump tables in Thumb-1 by synthesizing an "
85  "equivalent to the TBB/TBH instructions"));
86 
87 namespace {
88 
89  /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
90  /// requires constant pool entries to be scattered among the instructions
91  /// inside a function. To do this, it completely ignores the normal LLVM
92  /// constant pool; instead, it places constants wherever it feels like with
93  /// special instructions.
94  ///
95  /// The terminology used in this pass includes:
96  /// Islands - Clumps of constants placed in the function.
97  /// Water - Potential places where an island could be formed.
98  /// CPE - A constant pool entry that has been placed somewhere, which
99  /// tracks a list of users.
100  class ARMConstantIslands : public MachineFunctionPass {
101  std::vector<BasicBlockInfo> BBInfo;
102 
103  /// WaterList - A sorted list of basic blocks where islands could be placed
104  /// (i.e. blocks that don't fall through to the following block, due
105  /// to a return, unreachable, or unconditional branch).
106  std::vector<MachineBasicBlock*> WaterList;
107 
108  /// NewWaterList - The subset of WaterList that was created since the
109  /// previous iteration by inserting unconditional branches.
110  SmallSet<MachineBasicBlock*, 4> NewWaterList;
111 
112  using water_iterator = std::vector<MachineBasicBlock *>::iterator;
113 
114  /// CPUser - One user of a constant pool, keeping the machine instruction
115  /// pointer, the constant pool being referenced, and the max displacement
116  /// allowed from the instruction to the CP. The HighWaterMark records the
117  /// highest basic block where a new CPEntry can be placed. To ensure this
118  /// pass terminates, the CP entries are initially placed at the end of the
119  /// function and then move monotonically to lower addresses. The
120  /// exception to this rule is when the current CP entry for a particular
121  /// CPUser is out of range, but there is another CP entry for the same
122  /// constant value in range. We want to use the existing in-range CP
123  /// entry, but if it later moves out of range, the search for new water
124  /// should resume where it left off. The HighWaterMark is used to record
125  /// that point.
126  struct CPUser {
127  MachineInstr *MI;
128  MachineInstr *CPEMI;
129  MachineBasicBlock *HighWaterMark;
130  unsigned MaxDisp;
131  bool NegOk;
132  bool IsSoImm;
133  bool KnownAlignment = false;
134 
135  CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
136  bool neg, bool soimm)
137  : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
138  HighWaterMark = CPEMI->getParent();
139  }
140 
141  /// getMaxDisp - Returns the maximum displacement supported by MI.
142  /// Correct for unknown alignment.
143  /// Conservatively subtract 2 bytes to handle weird alignment effects.
144  unsigned getMaxDisp() const {
145  return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
146  }
147  };
148 
149  /// CPUsers - Keep track of all of the machine instructions that use various
150  /// constant pools and their max displacement.
151  std::vector<CPUser> CPUsers;
152 
153  /// CPEntry - One per constant pool entry, keeping the machine instruction
154  /// pointer, the constpool index, and the number of CPUser's which
155  /// reference this entry.
156  struct CPEntry {
157  MachineInstr *CPEMI;
158  unsigned CPI;
159  unsigned RefCount;
160 
161  CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
162  : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
163  };
164 
165  /// CPEntries - Keep track of all of the constant pool entry machine
166  /// instructions. For each original constpool index (i.e. those that existed
167  /// upon entry to this pass), it keeps a vector of entries. Original
168  /// elements are cloned as we go along; the clones are put in the vector of
169  /// the original element, but have distinct CPIs.
170  ///
171  /// The first half of CPEntries contains generic constants, the second half
172  /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
173  /// which vector it will be in here.
174  std::vector<std::vector<CPEntry>> CPEntries;
175 
176  /// Maps a JT index to the offset in CPEntries containing copies of that
177  /// table. The equivalent map for a CONSTPOOL_ENTRY is the identity.
178  DenseMap<int, int> JumpTableEntryIndices;
179 
180  /// Maps a JT index to the LEA that actually uses the index to calculate its
181  /// base address.
182  DenseMap<int, int> JumpTableUserIndices;
183 
184  /// ImmBranch - One per immediate branch, keeping the machine instruction
185  /// pointer, conditional or unconditional, the max displacement,
186  /// and (if isCond is true) the corresponding unconditional branch
187  /// opcode.
188  struct ImmBranch {
189  MachineInstr *MI;
190  unsigned MaxDisp : 31;
191  bool isCond : 1;
192  unsigned UncondBr;
193 
194  ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, unsigned ubr)
195  : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
196  };
197 
198  /// ImmBranches - Keep track of all the immediate branch instructions.
199  std::vector<ImmBranch> ImmBranches;
200 
201  /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
203 
204  /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
205  SmallVector<MachineInstr*, 4> T2JumpTables;
206 
207  /// HasFarJump - True if any far jump instruction has been emitted during
208  /// the branch fix up pass.
209  bool HasFarJump;
210 
211  MachineFunction *MF;
212  MachineConstantPool *MCP;
213  const ARMBaseInstrInfo *TII;
214  const ARMSubtarget *STI;
215  ARMFunctionInfo *AFI;
216  bool isThumb;
217  bool isThumb1;
218  bool isThumb2;
219  bool isPositionIndependentOrROPI;
220 
221  public:
222  static char ID;
223 
224  ARMConstantIslands() : MachineFunctionPass(ID) {}
225 
226  bool runOnMachineFunction(MachineFunction &MF) override;
227 
228  MachineFunctionProperties getRequiredProperties() const override {
231  }
232 
233  StringRef getPassName() const override {
235  }
236 
237  private:
238  void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
239  void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
241  CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
242  unsigned getCPELogAlign(const MachineInstr *CPEMI);
243  void scanFunctionJumpTables();
244  void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
245  MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
246  void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
247  void adjustBBOffsetsAfter(MachineBasicBlock *BB);
248  bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
249  unsigned getCombinedIndex(const MachineInstr *CPEMI);
250  int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
251  bool findAvailableWater(CPUser&U, unsigned UserOffset,
252  water_iterator &WaterIter, bool CloserWater);
253  void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
254  MachineBasicBlock *&NewMBB);
255  bool handleConstantPoolUser(unsigned CPUserIndex, bool CloserWater);
256  void removeDeadCPEMI(MachineInstr *CPEMI);
257  bool removeUnusedCPEntries();
258  bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
259  MachineInstr *CPEMI, unsigned Disp, bool NegOk,
260  bool DoDump = false);
261  bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
262  CPUser &U, unsigned &Growth);
263  bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
264  bool fixupImmediateBr(ImmBranch &Br);
265  bool fixupConditionalBr(ImmBranch &Br);
266  bool fixupUnconditionalBr(ImmBranch &Br);
267  bool undoLRSpillRestore();
268  bool optimizeThumb2Instructions();
269  bool optimizeThumb2Branches();
270  bool reorderThumb2JumpTables();
271  bool preserveBaseRegister(MachineInstr *JumpMI, MachineInstr *LEAMI,
272  unsigned &DeadSize, bool &CanDeleteLEA,
273  bool &BaseRegKill);
274  bool optimizeThumb2JumpTables();
275  MachineBasicBlock *adjustJTTargetBlockForward(MachineBasicBlock *BB,
276  MachineBasicBlock *JTBB);
277 
278  unsigned getOffsetOf(MachineInstr *MI) const;
279  unsigned getUserOffset(CPUser&) const;
280  void dumpBBs();
281  void verify();
282 
283  bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
284  unsigned Disp, bool NegativeOK, bool IsSoImm = false);
285  bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
286  const CPUser &U) {
287  return isOffsetInRange(UserOffset, TrialOffset,
288  U.getMaxDisp(), U.NegOk, U.IsSoImm);
289  }
290  };
291 
292 } // end anonymous namespace
293 
294 char ARMConstantIslands::ID = 0;
295 
296 /// verify - check BBOffsets, BBSizes, alignment of islands
298 #ifndef NDEBUG
299  assert(std::is_sorted(MF->begin(), MF->end(),
300  [this](const MachineBasicBlock &LHS,
301  const MachineBasicBlock &RHS) {
302  return BBInfo[LHS.getNumber()].postOffset() <
303  BBInfo[RHS.getNumber()].postOffset();
304  }));
305  LLVM_DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
306  for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
307  CPUser &U = CPUsers[i];
308  unsigned UserOffset = getUserOffset(U);
309  // Verify offset using the real max displacement without the safety
310  // adjustment.
311  if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getMaxDisp()+2, U.NegOk,
312  /* DoDump = */ true)) {
313  LLVM_DEBUG(dbgs() << "OK\n");
314  continue;
315  }
316  LLVM_DEBUG(dbgs() << "Out of range.\n");
317  dumpBBs();
318  LLVM_DEBUG(MF->dump());
319  llvm_unreachable("Constant pool entry out of range!");
320  }
321 #endif
322 }
323 
324 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
325 /// print block size and offset information - debugging
326 LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
327  LLVM_DEBUG({
328  for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
329  const BasicBlockInfo &BBI = BBInfo[J];
330  dbgs() << format("%08x %bb.%u\t", BBI.Offset, J)
331  << " kb=" << unsigned(BBI.KnownBits)
332  << " ua=" << unsigned(BBI.Unalign)
333  << " pa=" << unsigned(BBI.PostAlign)
334  << format(" size=%#x\n", BBInfo[J].Size);
335  }
336  });
337 }
338 #endif
339 
340 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
341  MF = &mf;
342  MCP = mf.getConstantPool();
343 
344  LLVM_DEBUG(dbgs() << "***** ARMConstantIslands: "
345  << MCP->getConstants().size() << " CP entries, aligned to "
346  << MCP->getConstantPoolAlignment() << " bytes *****\n");
347 
348  STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
349  TII = STI->getInstrInfo();
350  isPositionIndependentOrROPI =
351  STI->getTargetLowering()->isPositionIndependent() || STI->isROPI();
352  AFI = MF->getInfo<ARMFunctionInfo>();
353 
354  isThumb = AFI->isThumbFunction();
355  isThumb1 = AFI->isThumb1OnlyFunction();
356  isThumb2 = AFI->isThumb2Function();
357 
358  HasFarJump = false;
359  bool GenerateTBB = isThumb2 || (isThumb1 && SynthesizeThumb1TBB);
360 
361  // This pass invalidates liveness information when it splits basic blocks.
363 
364  // Renumber all of the machine basic blocks in the function, guaranteeing that
365  // the numbers agree with the position of the block in the function.
366  MF->RenumberBlocks();
367 
368  // Try to reorder and otherwise adjust the block layout to make good use
369  // of the TB[BH] instructions.
370  bool MadeChange = false;
371  if (GenerateTBB && AdjustJumpTableBlocks) {
372  scanFunctionJumpTables();
373  MadeChange |= reorderThumb2JumpTables();
374  // Data is out of date, so clear it. It'll be re-computed later.
375  T2JumpTables.clear();
376  // Blocks may have shifted around. Keep the numbering up to date.
377  MF->RenumberBlocks();
378  }
379 
380  // Perform the initial placement of the constant pool entries. To start with,
381  // we put them all at the end of the function.
382  std::vector<MachineInstr*> CPEMIs;
383  if (!MCP->isEmpty())
384  doInitialConstPlacement(CPEMIs);
385 
386  if (MF->getJumpTableInfo())
387  doInitialJumpTablePlacement(CPEMIs);
388 
389  /// The next UID to take is the first unused one.
390  AFI->initPICLabelUId(CPEMIs.size());
391 
392  // Do the initial scan of the function, building up information about the
393  // sizes of each block, the location of all the water, and finding all of the
394  // constant pool users.
395  initializeFunctionInfo(CPEMIs);
396  CPEMIs.clear();
397  LLVM_DEBUG(dumpBBs());
398 
399  // Functions with jump tables need an alignment of 4 because they use the ADR
400  // instruction, which aligns the PC to 4 bytes before adding an offset.
401  if (!T2JumpTables.empty())
402  MF->ensureAlignment(2);
403 
404  /// Remove dead constant pool entries.
405  MadeChange |= removeUnusedCPEntries();
406 
407  // Iteratively place constant pool entries and fix up branches until there
408  // is no change.
409  unsigned NoCPIters = 0, NoBRIters = 0;
410  while (true) {
411  LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
412  bool CPChange = false;
413  for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
414  // For most inputs, it converges in no more than 5 iterations.
415  // If it doesn't end in 10, the input may have huge BB or many CPEs.
416  // In this case, we will try different heuristics.
417  CPChange |= handleConstantPoolUser(i, NoCPIters >= CPMaxIteration / 2);
418  if (CPChange && ++NoCPIters > CPMaxIteration)
419  report_fatal_error("Constant Island pass failed to converge!");
420  LLVM_DEBUG(dumpBBs());
421 
422  // Clear NewWaterList now. If we split a block for branches, it should
423  // appear as "new water" for the next iteration of constant pool placement.
424  NewWaterList.clear();
425 
426  LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
427  bool BRChange = false;
428  for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
429  BRChange |= fixupImmediateBr(ImmBranches[i]);
430  if (BRChange && ++NoBRIters > 30)
431  report_fatal_error("Branch Fix Up pass failed to converge!");
432  LLVM_DEBUG(dumpBBs());
433 
434  if (!CPChange && !BRChange)
435  break;
436  MadeChange = true;
437  }
438 
439  // Shrink 32-bit Thumb2 load and store instructions.
440  if (isThumb2 && !STI->prefers32BitThumb())
441  MadeChange |= optimizeThumb2Instructions();
442 
443  // Shrink 32-bit branch instructions.
444  if (isThumb && STI->hasV8MBaselineOps())
445  MadeChange |= optimizeThumb2Branches();
446 
447  // Optimize jump tables using TBB / TBH.
448  if (GenerateTBB && !STI->genExecuteOnly())
449  MadeChange |= optimizeThumb2JumpTables();
450 
451  // After a while, this might be made debug-only, but it is not expensive.
452  verify();
453 
454  // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
455  // undo the spill / restore of LR if possible.
456  if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
457  MadeChange |= undoLRSpillRestore();
458 
459  // Save the mapping between original and cloned constpool entries.
460  for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
461  for (unsigned j = 0, je = CPEntries[i].size(); j != je; ++j) {
462  const CPEntry & CPE = CPEntries[i][j];
463  if (CPE.CPEMI && CPE.CPEMI->getOperand(1).isCPI())
464  AFI->recordCPEClone(i, CPE.CPI);
465  }
466  }
467 
468  LLVM_DEBUG(dbgs() << '\n'; dumpBBs());
469 
470  BBInfo.clear();
471  WaterList.clear();
472  CPUsers.clear();
473  CPEntries.clear();
474  JumpTableEntryIndices.clear();
475  JumpTableUserIndices.clear();
476  ImmBranches.clear();
477  PushPopMIs.clear();
478  T2JumpTables.clear();
479 
480  return MadeChange;
481 }
482 
483 /// Perform the initial placement of the regular constant pool entries.
484 /// To start with, we put them all at the end of the function.
485 void
486 ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
487  // Create the basic block to hold the CPE's.
489  MF->push_back(BB);
490 
491  // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
492  unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
493 
494  // Mark the basic block as required by the const-pool.
495  BB->setAlignment(MaxAlign);
496 
497  // The function needs to be as aligned as the basic blocks. The linker may
498  // move functions around based on their alignment.
499  MF->ensureAlignment(BB->getAlignment());
500 
501  // Order the entries in BB by descending alignment. That ensures correct
502  // alignment of all entries as long as BB is sufficiently aligned. Keep
503  // track of the insertion point for each alignment. We are going to bucket
504  // sort the entries as they are created.
505  SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
506 
507  // Add all of the constants from the constant pool to the end block, use an
508  // identity mapping of CPI's to CPE's.
509  const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
510 
511  const DataLayout &TD = MF->getDataLayout();
512  for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
513  unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
514  unsigned Align = CPs[i].getAlignment();
515  assert(isPowerOf2_32(Align) && "Invalid alignment");
516  // Verify that all constant pool entries are a multiple of their alignment.
517  // If not, we would have to pad them out so that instructions stay aligned.
518  assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!");
519 
520  // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
521  unsigned LogAlign = Log2_32(Align);
522  MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
523  MachineInstr *CPEMI =
524  BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
525  .addImm(i).addConstantPoolIndex(i).addImm(Size);
526  CPEMIs.push_back(CPEMI);
527 
528  // Ensure that future entries with higher alignment get inserted before
529  // CPEMI. This is bucket sort with iterators.
530  for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
531  if (InsPoint[a] == InsAt)
532  InsPoint[a] = CPEMI;
533 
534  // Add a new CPEntry, but no corresponding CPUser yet.
535  CPEntries.emplace_back(1, CPEntry(CPEMI, i));
536  ++NumCPEs;
537  LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
538  << Size << ", align = " << Align << '\n');
539  }
540  LLVM_DEBUG(BB->dump());
541 }
542 
543 /// Do initial placement of the jump tables. Because Thumb2's TBB and TBH
544 /// instructions can be made more efficient if the jump table immediately
545 /// follows the instruction, it's best to place them immediately next to their
546 /// jumps to begin with. In almost all cases they'll never be moved from that
547 /// position.
548 void ARMConstantIslands::doInitialJumpTablePlacement(
549  std::vector<MachineInstr *> &CPEMIs) {
550  unsigned i = CPEntries.size();
551  auto MJTI = MF->getJumpTableInfo();
552  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
553 
554  MachineBasicBlock *LastCorrectlyNumberedBB = nullptr;
555  for (MachineBasicBlock &MBB : *MF) {
556  auto MI = MBB.getLastNonDebugInstr();
557  if (MI == MBB.end())
558  continue;
559 
560  unsigned JTOpcode;
561  switch (MI->getOpcode()) {
562  default:
563  continue;
564  case ARM::BR_JTadd:
565  case ARM::BR_JTr:
566  case ARM::tBR_JTr:
567  case ARM::BR_JTm_i12:
568  case ARM::BR_JTm_rs:
569  JTOpcode = ARM::JUMPTABLE_ADDRS;
570  break;
571  case ARM::t2BR_JT:
572  JTOpcode = ARM::JUMPTABLE_INSTS;
573  break;
574  case ARM::tTBB_JT:
575  case ARM::t2TBB_JT:
576  JTOpcode = ARM::JUMPTABLE_TBB;
577  break;
578  case ARM::tTBH_JT:
579  case ARM::t2TBH_JT:
580  JTOpcode = ARM::JUMPTABLE_TBH;
581  break;
582  }
583 
584  unsigned NumOps = MI->getDesc().getNumOperands();
585  MachineOperand JTOp =
586  MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
587  unsigned JTI = JTOp.getIndex();
588  unsigned Size = JT[JTI].MBBs.size() * sizeof(uint32_t);
589  MachineBasicBlock *JumpTableBB = MF->CreateMachineBasicBlock();
590  MF->insert(std::next(MachineFunction::iterator(MBB)), JumpTableBB);
591  MachineInstr *CPEMI = BuildMI(*JumpTableBB, JumpTableBB->begin(),
592  DebugLoc(), TII->get(JTOpcode))
593  .addImm(i++)
594  .addJumpTableIndex(JTI)
595  .addImm(Size);
596  CPEMIs.push_back(CPEMI);
597  CPEntries.emplace_back(1, CPEntry(CPEMI, JTI));
598  JumpTableEntryIndices.insert(std::make_pair(JTI, CPEntries.size() - 1));
599  if (!LastCorrectlyNumberedBB)
600  LastCorrectlyNumberedBB = &MBB;
601  }
602 
603  // If we did anything then we need to renumber the subsequent blocks.
604  if (LastCorrectlyNumberedBB)
605  MF->RenumberBlocks(LastCorrectlyNumberedBB);
606 }
607 
608 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
609 /// into the block immediately after it.
611  // Get the next machine basic block in the function.
613  // Can't fall off end of function.
614  if (std::next(MBBI) == MBB->getParent()->end())
615  return false;
616 
617  MachineBasicBlock *NextBB = &*std::next(MBBI);
618  if (!MBB->isSuccessor(NextBB))
619  return false;
620 
621  // Try to analyze the end of the block. A potential fallthrough may already
622  // have an unconditional branch for whatever reason.
623  MachineBasicBlock *TBB, *FBB;
625  bool TooDifficult = TII->analyzeBranch(*MBB, TBB, FBB, Cond);
626  return TooDifficult || FBB == nullptr;
627 }
628 
629 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
630 /// look up the corresponding CPEntry.
631 ARMConstantIslands::CPEntry *
632 ARMConstantIslands::findConstPoolEntry(unsigned CPI,
633  const MachineInstr *CPEMI) {
634  std::vector<CPEntry> &CPEs = CPEntries[CPI];
635  // Number of entries per constpool index should be small, just do a
636  // linear search.
637  for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
638  if (CPEs[i].CPEMI == CPEMI)
639  return &CPEs[i];
640  }
641  return nullptr;
642 }
643 
644 /// getCPELogAlign - Returns the required alignment of the constant pool entry
645 /// represented by CPEMI. Alignment is measured in log2(bytes) units.
646 unsigned ARMConstantIslands::getCPELogAlign(const MachineInstr *CPEMI) {
647  switch (CPEMI->getOpcode()) {
648  case ARM::CONSTPOOL_ENTRY:
649  break;
650  case ARM::JUMPTABLE_TBB:
651  return isThumb1 ? 2 : 0;
652  case ARM::JUMPTABLE_TBH:
653  return isThumb1 ? 2 : 1;
654  case ARM::JUMPTABLE_INSTS:
655  return 1;
656  case ARM::JUMPTABLE_ADDRS:
657  return 2;
658  default:
659  llvm_unreachable("unknown constpool entry kind");
660  }
661 
662  unsigned CPI = getCombinedIndex(CPEMI);
663  assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
664  unsigned Align = MCP->getConstants()[CPI].getAlignment();
665  assert(isPowerOf2_32(Align) && "Invalid CPE alignment");
666  return Log2_32(Align);
667 }
668 
669 /// scanFunctionJumpTables - Do a scan of the function, building up
670 /// information about the sizes of each block and the locations of all
671 /// the jump tables.
672 void ARMConstantIslands::scanFunctionJumpTables() {
673  for (MachineBasicBlock &MBB : *MF) {
674  for (MachineInstr &I : MBB)
675  if (I.isBranch() &&
676  (I.getOpcode() == ARM::t2BR_JT || I.getOpcode() == ARM::tBR_JTr))
677  T2JumpTables.push_back(&I);
678  }
679 }
680 
681 /// initializeFunctionInfo - Do the initial scan of the function, building up
682 /// information about the sizes of each block, the location of all the water,
683 /// and finding all of the constant pool users.
684 void ARMConstantIslands::
685 initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
686 
687  BBInfo = computeAllBlockSizes(MF);
688 
689  // The known bits of the entry block offset are determined by the function
690  // alignment.
691  BBInfo.front().KnownBits = MF->getAlignment();
692 
693  // Compute block offsets and known bits.
694  adjustBBOffsetsAfter(&MF->front());
695 
696  // Now go back through the instructions and build up our data structures.
697  for (MachineBasicBlock &MBB : *MF) {
698  // If this block doesn't fall through into the next MBB, then this is
699  // 'water' that a constant pool island could be placed.
700  if (!BBHasFallthrough(&MBB))
701  WaterList.push_back(&MBB);
702 
703  for (MachineInstr &I : MBB) {
704  if (I.isDebugInstr())
705  continue;
706 
707  unsigned Opc = I.getOpcode();
708  if (I.isBranch()) {
709  bool isCond = false;
710  unsigned Bits = 0;
711  unsigned Scale = 1;
712  int UOpc = Opc;
713  switch (Opc) {
714  default:
715  continue; // Ignore other JT branches
716  case ARM::t2BR_JT:
717  case ARM::tBR_JTr:
718  T2JumpTables.push_back(&I);
719  continue; // Does not get an entry in ImmBranches
720  case ARM::Bcc:
721  isCond = true;
722  UOpc = ARM::B;
724  case ARM::B:
725  Bits = 24;
726  Scale = 4;
727  break;
728  case ARM::tBcc:
729  isCond = true;
730  UOpc = ARM::tB;
731  Bits = 8;
732  Scale = 2;
733  break;
734  case ARM::tB:
735  Bits = 11;
736  Scale = 2;
737  break;
738  case ARM::t2Bcc:
739  isCond = true;
740  UOpc = ARM::t2B;
741  Bits = 20;
742  Scale = 2;
743  break;
744  case ARM::t2B:
745  Bits = 24;
746  Scale = 2;
747  break;
748  }
749 
750  // Record this immediate branch.
751  unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
752  ImmBranches.push_back(ImmBranch(&I, MaxOffs, isCond, UOpc));
753  }
754 
755  if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
756  PushPopMIs.push_back(&I);
757 
758  if (Opc == ARM::CONSTPOOL_ENTRY || Opc == ARM::JUMPTABLE_ADDRS ||
759  Opc == ARM::JUMPTABLE_INSTS || Opc == ARM::JUMPTABLE_TBB ||
760  Opc == ARM::JUMPTABLE_TBH)
761  continue;
762 
763  // Scan the instructions for constant pool operands.
764  for (unsigned op = 0, e = I.getNumOperands(); op != e; ++op)
765  if (I.getOperand(op).isCPI() || I.getOperand(op).isJTI()) {
766  // We found one. The addressing mode tells us the max displacement
767  // from the PC that this instruction permits.
768 
769  // Basic size info comes from the TSFlags field.
770  unsigned Bits = 0;
771  unsigned Scale = 1;
772  bool NegOk = false;
773  bool IsSoImm = false;
774 
775  switch (Opc) {
776  default:
777  llvm_unreachable("Unknown addressing mode for CP reference!");
778 
779  // Taking the address of a CP entry.
780  case ARM::LEApcrel:
781  case ARM::LEApcrelJT:
782  // This takes a SoImm, which is 8 bit immediate rotated. We'll
783  // pretend the maximum offset is 255 * 4. Since each instruction
784  // 4 byte wide, this is always correct. We'll check for other
785  // displacements that fits in a SoImm as well.
786  Bits = 8;
787  Scale = 4;
788  NegOk = true;
789  IsSoImm = true;
790  break;
791  case ARM::t2LEApcrel:
792  case ARM::t2LEApcrelJT:
793  Bits = 12;
794  NegOk = true;
795  break;
796  case ARM::tLEApcrel:
797  case ARM::tLEApcrelJT:
798  Bits = 8;
799  Scale = 4;
800  break;
801 
802  case ARM::LDRBi12:
803  case ARM::LDRi12:
804  case ARM::LDRcp:
805  case ARM::t2LDRpci:
806  case ARM::t2LDRHpci:
807  case ARM::t2LDRBpci:
808  Bits = 12; // +-offset_12
809  NegOk = true;
810  break;
811 
812  case ARM::tLDRpci:
813  Bits = 8;
814  Scale = 4; // +(offset_8*4)
815  break;
816 
817  case ARM::VLDRD:
818  case ARM::VLDRS:
819  Bits = 8;
820  Scale = 4; // +-(offset_8*4)
821  NegOk = true;
822  break;
823  case ARM::VLDRH:
824  Bits = 8;
825  Scale = 2; // +-(offset_8*2)
826  NegOk = true;
827  break;
828 
829  case ARM::tLDRHi:
830  Bits = 5;
831  Scale = 2; // +(offset_5*2)
832  break;
833  }
834 
835  // Remember that this is a user of a CP entry.
836  unsigned CPI = I.getOperand(op).getIndex();
837  if (I.getOperand(op).isJTI()) {
838  JumpTableUserIndices.insert(std::make_pair(CPI, CPUsers.size()));
839  CPI = JumpTableEntryIndices[CPI];
840  }
841 
842  MachineInstr *CPEMI = CPEMIs[CPI];
843  unsigned MaxOffs = ((1 << Bits)-1) * Scale;
844  CPUsers.push_back(CPUser(&I, CPEMI, MaxOffs, NegOk, IsSoImm));
845 
846  // Increment corresponding CPEntry reference count.
847  CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
848  assert(CPE && "Cannot find a corresponding CPEntry!");
849  CPE->RefCount++;
850 
851  // Instructions can only use one CP entry, don't bother scanning the
852  // rest of the operands.
853  break;
854  }
855  }
856  }
857 }
858 
859 /// getOffsetOf - Return the current offset of the specified machine instruction
860 /// from the start of the function. This offset changes as stuff is moved
861 /// around inside the function.
862 unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const {
863  MachineBasicBlock *MBB = MI->getParent();
864 
865  // The offset is composed of two things: the sum of the sizes of all MBB's
866  // before this instruction's block, and the offset from the start of the block
867  // it is in.
868  unsigned Offset = BBInfo[MBB->getNumber()].Offset;
869 
870  // Sum instructions before MI in MBB.
871  for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
872  assert(I != MBB->end() && "Didn't find MI in its own basic block?");
873  Offset += TII->getInstSizeInBytes(*I);
874  }
875  return Offset;
876 }
877 
878 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
879 /// ID.
880 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
881  const MachineBasicBlock *RHS) {
882  return LHS->getNumber() < RHS->getNumber();
883 }
884 
885 /// updateForInsertedWaterBlock - When a block is newly inserted into the
886 /// machine function, it upsets all of the block numbers. Renumber the blocks
887 /// and update the arrays that parallel this numbering.
888 void ARMConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
889  // Renumber the MBB's to keep them consecutive.
890  NewBB->getParent()->RenumberBlocks(NewBB);
891 
892  // Insert an entry into BBInfo to align it properly with the (newly
893  // renumbered) block numbers.
894  BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
895 
896  // Next, update WaterList. Specifically, we need to add NewMBB as having
897  // available water after it.
898  water_iterator IP =
899  std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
901  WaterList.insert(IP, NewBB);
902 }
903 
904 /// Split the basic block containing MI into two blocks, which are joined by
905 /// an unconditional branch. Update data structures and renumber blocks to
906 /// account for this change and returns the newly created block.
907 MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
908  MachineBasicBlock *OrigBB = MI->getParent();
909 
910  // Create a new MBB for the code after the OrigBB.
911  MachineBasicBlock *NewBB =
912  MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
913  MachineFunction::iterator MBBI = ++OrigBB->getIterator();
914  MF->insert(MBBI, NewBB);
915 
916  // Splice the instructions starting with MI over to NewBB.
917  NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
918 
919  // Add an unconditional branch from OrigBB to NewBB.
920  // Note the new unconditional branch is not being recorded.
921  // There doesn't seem to be meaningful DebugInfo available; this doesn't
922  // correspond to anything in the source.
923  unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
924  if (!isThumb)
925  BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
926  else
927  BuildMI(OrigBB, DebugLoc(), TII->get(Opc))
928  .addMBB(NewBB)
929  .add(predOps(ARMCC::AL));
930  ++NumSplit;
931 
932  // Update the CFG. All succs of OrigBB are now succs of NewBB.
933  NewBB->transferSuccessors(OrigBB);
934 
935  // OrigBB branches to NewBB.
936  OrigBB->addSuccessor(NewBB);
937 
938  // Update internal data structures to account for the newly inserted MBB.
939  // This is almost the same as updateForInsertedWaterBlock, except that
940  // the Water goes after OrigBB, not NewBB.
941  MF->RenumberBlocks(NewBB);
942 
943  // Insert an entry into BBInfo to align it properly with the (newly
944  // renumbered) block numbers.
945  BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
946 
947  // Next, update WaterList. Specifically, we need to add OrigMBB as having
948  // available water after it (but not if it's already there, which happens
949  // when splitting before a conditional branch that is followed by an
950  // unconditional branch - in that case we want to insert NewBB).
951  water_iterator IP =
952  std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
954  MachineBasicBlock* WaterBB = *IP;
955  if (WaterBB == OrigBB)
956  WaterList.insert(std::next(IP), NewBB);
957  else
958  WaterList.insert(IP, OrigBB);
959  NewWaterList.insert(OrigBB);
960 
961  // Figure out how large the OrigBB is. As the first half of the original
962  // block, it cannot contain a tablejump. The size includes
963  // the new jump we added. (It should be possible to do this without
964  // recounting everything, but it's very confusing, and this is rarely
965  // executed.)
966  computeBlockSize(MF, OrigBB, BBInfo[OrigBB->getNumber()]);
967 
968  // Figure out how large the NewMBB is. As the second half of the original
969  // block, it may contain a tablejump.
970  computeBlockSize(MF, NewBB, BBInfo[NewBB->getNumber()]);
971 
972  // All BBOffsets following these blocks must be modified.
973  adjustBBOffsetsAfter(OrigBB);
974 
975  return NewBB;
976 }
977 
978 /// getUserOffset - Compute the offset of U.MI as seen by the hardware
979 /// displacement computation. Update U.KnownAlignment to match its current
980 /// basic block location.
981 unsigned ARMConstantIslands::getUserOffset(CPUser &U) const {
982  unsigned UserOffset = getOffsetOf(U.MI);
983  const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
984  unsigned KnownBits = BBI.internalKnownBits();
985 
986  // The value read from PC is offset from the actual instruction address.
987  UserOffset += (isThumb ? 4 : 8);
988 
989  // Because of inline assembly, we may not know the alignment (mod 4) of U.MI.
990  // Make sure U.getMaxDisp() returns a constrained range.
991  U.KnownAlignment = (KnownBits >= 2);
992 
993  // On Thumb, offsets==2 mod 4 are rounded down by the hardware for
994  // purposes of the displacement computation; compensate for that here.
995  // For unknown alignments, getMaxDisp() constrains the range instead.
996  if (isThumb && U.KnownAlignment)
997  UserOffset &= ~3u;
998 
999  return UserOffset;
1000 }
1001 
1002 /// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
1003 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
1004 /// constant pool entry).
1005 /// UserOffset is computed by getUserOffset above to include PC adjustments. If
1006 /// the mod 4 alignment of UserOffset is not known, the uncertainty must be
1007 /// subtracted from MaxDisp instead. CPUser::getMaxDisp() does that.
1008 bool ARMConstantIslands::isOffsetInRange(unsigned UserOffset,
1009  unsigned TrialOffset, unsigned MaxDisp,
1010  bool NegativeOK, bool IsSoImm) {
1011  if (UserOffset <= TrialOffset) {
1012  // User before the Trial.
1013  if (TrialOffset - UserOffset <= MaxDisp)
1014  return true;
1015  // FIXME: Make use full range of soimm values.
1016  } else if (NegativeOK) {
1017  if (UserOffset - TrialOffset <= MaxDisp)
1018  return true;
1019  // FIXME: Make use full range of soimm values.
1020  }
1021  return false;
1022 }
1023 
1024 /// isWaterInRange - Returns true if a CPE placed after the specified
1025 /// Water (a basic block) will be in range for the specific MI.
1026 ///
1027 /// Compute how much the function will grow by inserting a CPE after Water.
1028 bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
1029  MachineBasicBlock* Water, CPUser &U,
1030  unsigned &Growth) {
1031  unsigned CPELogAlign = getCPELogAlign(U.CPEMI);
1032  unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
1033  unsigned NextBlockOffset, NextBlockAlignment;
1034  MachineFunction::const_iterator NextBlock = Water->getIterator();
1035  if (++NextBlock == MF->end()) {
1036  NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
1037  NextBlockAlignment = 0;
1038  } else {
1039  NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
1040  NextBlockAlignment = NextBlock->getAlignment();
1041  }
1042  unsigned Size = U.CPEMI->getOperand(2).getImm();
1043  unsigned CPEEnd = CPEOffset + Size;
1044 
1045  // The CPE may be able to hide in the alignment padding before the next
1046  // block. It may also cause more padding to be required if it is more aligned
1047  // that the next block.
1048  if (CPEEnd > NextBlockOffset) {
1049  Growth = CPEEnd - NextBlockOffset;
1050  // Compute the padding that would go at the end of the CPE to align the next
1051  // block.
1052  Growth += OffsetToAlignment(CPEEnd, 1ULL << NextBlockAlignment);
1053 
1054  // If the CPE is to be inserted before the instruction, that will raise
1055  // the offset of the instruction. Also account for unknown alignment padding
1056  // in blocks between CPE and the user.
1057  if (CPEOffset < UserOffset)
1058  UserOffset += Growth + UnknownPadding(MF->getAlignment(), CPELogAlign);
1059  } else
1060  // CPE fits in existing padding.
1061  Growth = 0;
1062 
1063  return isOffsetInRange(UserOffset, CPEOffset, U);
1064 }
1065 
1066 /// isCPEntryInRange - Returns true if the distance between specific MI and
1067 /// specific ConstPool entry instruction can fit in MI's displacement field.
1068 bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
1069  MachineInstr *CPEMI, unsigned MaxDisp,
1070  bool NegOk, bool DoDump) {
1071  unsigned CPEOffset = getOffsetOf(CPEMI);
1072 
1073  if (DoDump) {
1074  LLVM_DEBUG({
1075  unsigned Block = MI->getParent()->getNumber();
1076  const BasicBlockInfo &BBI = BBInfo[Block];
1077  dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1078  << " max delta=" << MaxDisp
1079  << format(" insn address=%#x", UserOffset) << " in "
1080  << printMBBReference(*MI->getParent()) << ": "
1081  << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1082  << format("CPE address=%#x offset=%+d: ", CPEOffset,
1083  int(CPEOffset - UserOffset));
1084  });
1085  }
1086 
1087  return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
1088 }
1089 
1090 #ifndef NDEBUG
1091 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
1092 /// unconditionally branches to its only successor.
1094  if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
1095  return false;
1096 
1097  MachineBasicBlock *Succ = *MBB->succ_begin();
1098  MachineBasicBlock *Pred = *MBB->pred_begin();
1099  MachineInstr *PredMI = &Pred->back();
1100  if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
1101  || PredMI->getOpcode() == ARM::t2B)
1102  return PredMI->getOperand(0).getMBB() == Succ;
1103  return false;
1104 }
1105 #endif // NDEBUG
1106 
1107 void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
1108  unsigned BBNum = BB->getNumber();
1109  for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
1110  // Get the offset and known bits at the end of the layout predecessor.
1111  // Include the alignment of the current block.
1112  unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
1113  unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
1114  unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
1115 
1116  // This is where block i begins. Stop if the offset is already correct,
1117  // and we have updated 2 blocks. This is the maximum number of blocks
1118  // changed before calling this function.
1119  if (i > BBNum + 2 &&
1120  BBInfo[i].Offset == Offset &&
1121  BBInfo[i].KnownBits == KnownBits)
1122  break;
1123 
1124  BBInfo[i].Offset = Offset;
1125  BBInfo[i].KnownBits = KnownBits;
1126  }
1127 }
1128 
1129 /// decrementCPEReferenceCount - find the constant pool entry with index CPI
1130 /// and instruction CPEMI, and decrement its refcount. If the refcount
1131 /// becomes 0 remove the entry and instruction. Returns true if we removed
1132 /// the entry, false if we didn't.
1133 bool ARMConstantIslands::decrementCPEReferenceCount(unsigned CPI,
1134  MachineInstr *CPEMI) {
1135  // Find the old entry. Eliminate it if it is no longer used.
1136  CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
1137  assert(CPE && "Unexpected!");
1138  if (--CPE->RefCount == 0) {
1139  removeDeadCPEMI(CPEMI);
1140  CPE->CPEMI = nullptr;
1141  --NumCPEs;
1142  return true;
1143  }
1144  return false;
1145 }
1146 
1147 unsigned ARMConstantIslands::getCombinedIndex(const MachineInstr *CPEMI) {
1148  if (CPEMI->getOperand(1).isCPI())
1149  return CPEMI->getOperand(1).getIndex();
1150 
1151  return JumpTableEntryIndices[CPEMI->getOperand(1).getIndex()];
1152 }
1153 
1154 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
1155 /// if not, see if an in-range clone of the CPE is in range, and if so,
1156 /// change the data structures so the user references the clone. Returns:
1157 /// 0 = no existing entry found
1158 /// 1 = entry found, and there were no code insertions or deletions
1159 /// 2 = entry found, and there were code insertions or deletions
1160 int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
1161  MachineInstr *UserMI = U.MI;
1162  MachineInstr *CPEMI = U.CPEMI;
1163 
1164  // Check to see if the CPE is already in-range.
1165  if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk,
1166  true)) {
1167  LLVM_DEBUG(dbgs() << "In range\n");
1168  return 1;
1169  }
1170 
1171  // No. Look for previously created clones of the CPE that are in range.
1172  unsigned CPI = getCombinedIndex(CPEMI);
1173  std::vector<CPEntry> &CPEs = CPEntries[CPI];
1174  for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
1175  // We already tried this one
1176  if (CPEs[i].CPEMI == CPEMI)
1177  continue;
1178  // Removing CPEs can leave empty entries, skip
1179  if (CPEs[i].CPEMI == nullptr)
1180  continue;
1181  if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
1182  U.NegOk)) {
1183  LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
1184  << CPEs[i].CPI << "\n");
1185  // Point the CPUser node to the replacement
1186  U.CPEMI = CPEs[i].CPEMI;
1187  // Change the CPI in the instruction operand to refer to the clone.
1188  for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
1189  if (UserMI->getOperand(j).isCPI()) {
1190  UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1191  break;
1192  }
1193  // Adjust the refcount of the clone...
1194  CPEs[i].RefCount++;
1195  // ...and the original. If we didn't remove the old entry, none of the
1196  // addresses changed, so we don't need another pass.
1197  return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
1198  }
1199  }
1200  return 0;
1201 }
1202 
1203 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1204 /// the specific unconditional branch instruction.
1205 static inline unsigned getUnconditionalBrDisp(int Opc) {
1206  switch (Opc) {
1207  case ARM::tB:
1208  return ((1<<10)-1)*2;
1209  case ARM::t2B:
1210  return ((1<<23)-1)*2;
1211  default:
1212  break;
1213  }
1214 
1215  return ((1<<23)-1)*4;
1216 }
1217 
1218 /// findAvailableWater - Look for an existing entry in the WaterList in which
1219 /// we can place the CPE referenced from U so it's within range of U's MI.
1220 /// Returns true if found, false if not. If it returns true, WaterIter
1221 /// is set to the WaterList entry. For Thumb, prefer water that will not
1222 /// introduce padding to water that will. To ensure that this pass
1223 /// terminates, the CPE location for a particular CPUser is only allowed to
1224 /// move to a lower address, so search backward from the end of the list and
1225 /// prefer the first water that is in range.
1226 bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
1227  water_iterator &WaterIter,
1228  bool CloserWater) {
1229  if (WaterList.empty())
1230  return false;
1231 
1232  unsigned BestGrowth = ~0u;
1233  // The nearest water without splitting the UserBB is right after it.
1234  // If the distance is still large (we have a big BB), then we need to split it
1235  // if we don't converge after certain iterations. This helps the following
1236  // situation to converge:
1237  // BB0:
1238  // Big BB
1239  // BB1:
1240  // Constant Pool
1241  // When a CP access is out of range, BB0 may be used as water. However,
1242  // inserting islands between BB0 and BB1 makes other accesses out of range.
1243  MachineBasicBlock *UserBB = U.MI->getParent();
1244  unsigned MinNoSplitDisp =
1245  BBInfo[UserBB->getNumber()].postOffset(getCPELogAlign(U.CPEMI));
1246  if (CloserWater && MinNoSplitDisp > U.getMaxDisp() / 2)
1247  return false;
1248  for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
1249  --IP) {
1250  MachineBasicBlock* WaterBB = *IP;
1251  // Check if water is in range and is either at a lower address than the
1252  // current "high water mark" or a new water block that was created since
1253  // the previous iteration by inserting an unconditional branch. In the
1254  // latter case, we want to allow resetting the high water mark back to
1255  // this new water since we haven't seen it before. Inserting branches
1256  // should be relatively uncommon and when it does happen, we want to be
1257  // sure to take advantage of it for all the CPEs near that block, so that
1258  // we don't insert more branches than necessary.
1259  // When CloserWater is true, we try to find the lowest address after (or
1260  // equal to) user MI's BB no matter of padding growth.
1261  unsigned Growth;
1262  if (isWaterInRange(UserOffset, WaterBB, U, Growth) &&
1263  (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1264  NewWaterList.count(WaterBB) || WaterBB == U.MI->getParent()) &&
1265  Growth < BestGrowth) {
1266  // This is the least amount of required padding seen so far.
1267  BestGrowth = Growth;
1268  WaterIter = IP;
1269  LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
1270  << " Growth=" << Growth << '\n');
1271 
1272  if (CloserWater && WaterBB == U.MI->getParent())
1273  return true;
1274  // Keep looking unless it is perfect and we're not looking for the lowest
1275  // possible address.
1276  if (!CloserWater && BestGrowth == 0)
1277  return true;
1278  }
1279  if (IP == B)
1280  break;
1281  }
1282  return BestGrowth != ~0u;
1283 }
1284 
1285 /// createNewWater - No existing WaterList entry will work for
1286 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1287 /// block is used if in range, and the conditional branch munged so control
1288 /// flow is correct. Otherwise the block is split to create a hole with an
1289 /// unconditional branch around it. In either case NewMBB is set to a
1290 /// block following which the new island can be inserted (the WaterList
1291 /// is not adjusted).
1292 void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
1293  unsigned UserOffset,
1294  MachineBasicBlock *&NewMBB) {
1295  CPUser &U = CPUsers[CPUserIndex];
1296  MachineInstr *UserMI = U.MI;
1297  MachineInstr *CPEMI = U.CPEMI;
1298  unsigned CPELogAlign = getCPELogAlign(CPEMI);
1299  MachineBasicBlock *UserMBB = UserMI->getParent();
1300  const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
1301 
1302  // If the block does not end in an unconditional branch already, and if the
1303  // end of the block is within range, make new water there. (The addition
1304  // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1305  // Thumb2, 2 on Thumb1.
1306  if (BBHasFallthrough(UserMBB)) {
1307  // Size of branch to insert.
1308  unsigned Delta = isThumb1 ? 2 : 4;
1309  // Compute the offset where the CPE will begin.
1310  unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta;
1311 
1312  if (isOffsetInRange(UserOffset, CPEOffset, U)) {
1313  LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
1314  << format(", expected CPE offset %#x\n", CPEOffset));
1315  NewMBB = &*++UserMBB->getIterator();
1316  // Add an unconditional branch from UserMBB to fallthrough block. Record
1317  // it for branch lengthening; this new branch will not get out of range,
1318  // but if the preceding conditional branch is out of range, the targets
1319  // will be exchanged, and the altered branch may be out of range, so the
1320  // machinery has to know about it.
1321  int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1322  if (!isThumb)
1323  BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1324  else
1325  BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr))
1326  .addMBB(NewMBB)
1327  .add(predOps(ARMCC::AL));
1328  unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1329  ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1330  MaxDisp, false, UncondBr));
1331  computeBlockSize(MF, UserMBB, BBInfo[UserMBB->getNumber()]);
1332  adjustBBOffsetsAfter(UserMBB);
1333  return;
1334  }
1335  }
1336 
1337  // What a big block. Find a place within the block to split it. This is a
1338  // little tricky on Thumb1 since instructions are 2 bytes and constant pool
1339  // entries are 4 bytes: if instruction I references island CPE, and
1340  // instruction I+1 references CPE', it will not work well to put CPE as far
1341  // forward as possible, since then CPE' cannot immediately follow it (that
1342  // location is 2 bytes farther away from I+1 than CPE was from I) and we'd
1343  // need to create a new island. So, we make a first guess, then walk through
1344  // the instructions between the one currently being looked at and the
1345  // possible insertion point, and make sure any other instructions that
1346  // reference CPEs will be able to use the same island area; if not, we back
1347  // up the insertion point.
1348 
1349  // Try to split the block so it's fully aligned. Compute the latest split
1350  // point where we can add a 4-byte branch instruction, and then align to
1351  // LogAlign which is the largest possible alignment in the function.
1352  unsigned LogAlign = MF->getAlignment();
1353  assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
1354  unsigned KnownBits = UserBBI.internalKnownBits();
1355  unsigned UPad = UnknownPadding(LogAlign, KnownBits);
1356  unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
1357  LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
1358  BaseInsertOffset));
1359 
1360  // The 4 in the following is for the unconditional branch we'll be inserting
1361  // (allows for long branch on Thumb1). Alignment of the island is handled
1362  // inside isOffsetInRange.
1363  BaseInsertOffset -= 4;
1364 
1365  LLVM_DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
1366  << " la=" << LogAlign << " kb=" << KnownBits
1367  << " up=" << UPad << '\n');
1368 
1369  // This could point off the end of the block if we've already got constant
1370  // pool entries following this block; only the last one is in the water list.
1371  // Back past any possible branches (allow for a conditional and a maximally
1372  // long unconditional).
1373  if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
1374  // Ensure BaseInsertOffset is larger than the offset of the instruction
1375  // following UserMI so that the loop which searches for the split point
1376  // iterates at least once.
1377  BaseInsertOffset =
1378  std::max(UserBBI.postOffset() - UPad - 8,
1379  UserOffset + TII->getInstSizeInBytes(*UserMI) + 1);
1380  LLVM_DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
1381  }
1382  unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
1383  CPEMI->getOperand(2).getImm();
1384  MachineBasicBlock::iterator MI = UserMI;
1385  ++MI;
1386  unsigned CPUIndex = CPUserIndex+1;
1387  unsigned NumCPUsers = CPUsers.size();
1388  MachineInstr *LastIT = nullptr;
1389  for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
1390  Offset < BaseInsertOffset;
1391  Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
1392  assert(MI != UserMBB->end() && "Fell off end of block");
1393  if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
1394  CPUser &U = CPUsers[CPUIndex];
1395  if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
1396  // Shift intertion point by one unit of alignment so it is within reach.
1397  BaseInsertOffset -= 1u << LogAlign;
1398  EndInsertOffset -= 1u << LogAlign;
1399  }
1400  // This is overly conservative, as we don't account for CPEMIs being
1401  // reused within the block, but it doesn't matter much. Also assume CPEs
1402  // are added in order with alignment padding. We may eventually be able
1403  // to pack the aligned CPEs better.
1404  EndInsertOffset += U.CPEMI->getOperand(2).getImm();
1405  CPUIndex++;
1406  }
1407 
1408  // Remember the last IT instruction.
1409  if (MI->getOpcode() == ARM::t2IT)
1410  LastIT = &*MI;
1411  }
1412 
1413  --MI;
1414 
1415  // Avoid splitting an IT block.
1416  if (LastIT) {
1417  unsigned PredReg = 0;
1418  ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
1419  if (CC != ARMCC::AL)
1420  MI = LastIT;
1421  }
1422 
1423  // Avoid splitting a MOVW+MOVT pair with a relocation on Windows.
1424  // On Windows, this instruction pair is covered by one single
1425  // IMAGE_REL_ARM_MOV32T relocation which covers both instructions. If a
1426  // constant island is injected inbetween them, the relocation will clobber
1427  // the instruction and fail to update the MOVT instruction.
1428  // (These instructions are bundled up until right before the ConstantIslands
1429  // pass.)
1430  if (STI->isTargetWindows() && isThumb && MI->getOpcode() == ARM::t2MOVTi16 &&
1431  (MI->getOperand(2).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1432  ARMII::MO_HI16) {
1433  --MI;
1434  assert(MI->getOpcode() == ARM::t2MOVi16 &&
1435  (MI->getOperand(1).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1436  ARMII::MO_LO16);
1437  }
1438 
1439  // We really must not split an IT block.
1440  LLVM_DEBUG(unsigned PredReg; assert(
1441  !isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
1442 
1443  NewMBB = splitBlockBeforeInstr(&*MI);
1444 }
1445 
1446 /// handleConstantPoolUser - Analyze the specified user, checking to see if it
1447 /// is out-of-range. If so, pick up the constant pool value and move it some
1448 /// place in-range. Return true if we changed any addresses (thus must run
1449 /// another pass of branch lengthening), false otherwise.
1450 bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
1451  bool CloserWater) {
1452  CPUser &U = CPUsers[CPUserIndex];
1453  MachineInstr *UserMI = U.MI;
1454  MachineInstr *CPEMI = U.CPEMI;
1455  unsigned CPI = getCombinedIndex(CPEMI);
1456  unsigned Size = CPEMI->getOperand(2).getImm();
1457  // Compute this only once, it's expensive.
1458  unsigned UserOffset = getUserOffset(U);
1459 
1460  // See if the current entry is within range, or there is a clone of it
1461  // in range.
1462  int result = findInRangeCPEntry(U, UserOffset);
1463  if (result==1) return false;
1464  else if (result==2) return true;
1465 
1466  // No existing clone of this CPE is within range.
1467  // We will be generating a new clone. Get a UID for it.
1468  unsigned ID = AFI->createPICLabelUId();
1469 
1470  // Look for water where we can place this CPE.
1471  MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
1472  MachineBasicBlock *NewMBB;
1473  water_iterator IP;
1474  if (findAvailableWater(U, UserOffset, IP, CloserWater)) {
1475  LLVM_DEBUG(dbgs() << "Found water in range\n");
1476  MachineBasicBlock *WaterBB = *IP;
1477 
1478  // If the original WaterList entry was "new water" on this iteration,
1479  // propagate that to the new island. This is just keeping NewWaterList
1480  // updated to match the WaterList, which will be updated below.
1481  if (NewWaterList.erase(WaterBB))
1482  NewWaterList.insert(NewIsland);
1483 
1484  // The new CPE goes before the following block (NewMBB).
1485  NewMBB = &*++WaterBB->getIterator();
1486  } else {
1487  // No water found.
1488  LLVM_DEBUG(dbgs() << "No water found\n");
1489  createNewWater(CPUserIndex, UserOffset, NewMBB);
1490 
1491  // splitBlockBeforeInstr adds to WaterList, which is important when it is
1492  // called while handling branches so that the water will be seen on the
1493  // next iteration for constant pools, but in this context, we don't want
1494  // it. Check for this so it will be removed from the WaterList.
1495  // Also remove any entry from NewWaterList.
1496  MachineBasicBlock *WaterBB = &*--NewMBB->getIterator();
1497  IP = find(WaterList, WaterBB);
1498  if (IP != WaterList.end())
1499  NewWaterList.erase(WaterBB);
1500 
1501  // We are adding new water. Update NewWaterList.
1502  NewWaterList.insert(NewIsland);
1503  }
1504  // Always align the new block because CP entries can be smaller than 4
1505  // bytes. Be careful not to decrease the existing alignment, e.g. NewMBB may
1506  // be an already aligned constant pool block.
1507  const unsigned Align = isThumb ? 1 : 2;
1508  if (NewMBB->getAlignment() < Align)
1509  NewMBB->setAlignment(Align);
1510 
1511  // Remove the original WaterList entry; we want subsequent insertions in
1512  // this vicinity to go after the one we're about to insert. This
1513  // considerably reduces the number of times we have to move the same CPE
1514  // more than once and is also important to ensure the algorithm terminates.
1515  if (IP != WaterList.end())
1516  WaterList.erase(IP);
1517 
1518  // Okay, we know we can put an island before NewMBB now, do it!
1519  MF->insert(NewMBB->getIterator(), NewIsland);
1520 
1521  // Update internal data structures to account for the newly inserted MBB.
1522  updateForInsertedWaterBlock(NewIsland);
1523 
1524  // Now that we have an island to add the CPE to, clone the original CPE and
1525  // add it to the island.
1526  U.HighWaterMark = NewIsland;
1527  U.CPEMI = BuildMI(NewIsland, DebugLoc(), CPEMI->getDesc())
1528  .addImm(ID)
1529  .add(CPEMI->getOperand(1))
1530  .addImm(Size);
1531  CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1532  ++NumCPEs;
1533 
1534  // Decrement the old entry, and remove it if refcount becomes 0.
1535  decrementCPEReferenceCount(CPI, CPEMI);
1536 
1537  // Mark the basic block as aligned as required by the const-pool entry.
1538  NewIsland->setAlignment(getCPELogAlign(U.CPEMI));
1539 
1540  // Increase the size of the island block to account for the new entry.
1541  BBInfo[NewIsland->getNumber()].Size += Size;
1542  adjustBBOffsetsAfter(&*--NewIsland->getIterator());
1543 
1544  // Finally, change the CPI in the instruction operand to be ID.
1545  for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1546  if (UserMI->getOperand(i).isCPI()) {
1547  UserMI->getOperand(i).setIndex(ID);
1548  break;
1549  }
1550 
1551  LLVM_DEBUG(
1552  dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
1553  << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset));
1554 
1555  return true;
1556 }
1557 
1558 /// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update
1559 /// sizes and offsets of impacted basic blocks.
1560 void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
1561  MachineBasicBlock *CPEBB = CPEMI->getParent();
1562  unsigned Size = CPEMI->getOperand(2).getImm();
1563  CPEMI->eraseFromParent();
1564  BBInfo[CPEBB->getNumber()].Size -= Size;
1565  // All succeeding offsets have the current size value added in, fix this.
1566  if (CPEBB->empty()) {
1567  BBInfo[CPEBB->getNumber()].Size = 0;
1568 
1569  // This block no longer needs to be aligned.
1570  CPEBB->setAlignment(0);
1571  } else
1572  // Entries are sorted by descending alignment, so realign from the front.
1573  CPEBB->setAlignment(getCPELogAlign(&*CPEBB->begin()));
1574 
1575  adjustBBOffsetsAfter(CPEBB);
1576  // An island has only one predecessor BB and one successor BB. Check if
1577  // this BB's predecessor jumps directly to this BB's successor. This
1578  // shouldn't happen currently.
1579  assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1580  // FIXME: remove the empty blocks after all the work is done?
1581 }
1582 
1583 /// removeUnusedCPEntries - Remove constant pool entries whose refcounts
1584 /// are zero.
1585 bool ARMConstantIslands::removeUnusedCPEntries() {
1586  unsigned MadeChange = false;
1587  for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1588  std::vector<CPEntry> &CPEs = CPEntries[i];
1589  for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1590  if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1591  removeDeadCPEMI(CPEs[j].CPEMI);
1592  CPEs[j].CPEMI = nullptr;
1593  MadeChange = true;
1594  }
1595  }
1596  }
1597  return MadeChange;
1598 }
1599 
1600 /// isBBInRange - Returns true if the distance between specific MI and
1601 /// specific BB can fit in MI's displacement field.
1602 bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1603  unsigned MaxDisp) {
1604  unsigned PCAdj = isThumb ? 4 : 8;
1605  unsigned BrOffset = getOffsetOf(MI) + PCAdj;
1606  unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1607 
1608  LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
1609  << " from " << printMBBReference(*MI->getParent())
1610  << " max delta=" << MaxDisp << " from " << getOffsetOf(MI)
1611  << " to " << DestOffset << " offset "
1612  << int(DestOffset - BrOffset) << "\t" << *MI);
1613 
1614  if (BrOffset <= DestOffset) {
1615  // Branch before the Dest.
1616  if (DestOffset-BrOffset <= MaxDisp)
1617  return true;
1618  } else {
1619  if (BrOffset-DestOffset <= MaxDisp)
1620  return true;
1621  }
1622  return false;
1623 }
1624 
1625 /// fixupImmediateBr - Fix up an immediate branch whose destination is too far
1626 /// away to fit in its displacement field.
1627 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1628  MachineInstr *MI = Br.MI;
1629  MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1630 
1631  // Check to see if the DestBB is already in-range.
1632  if (isBBInRange(MI, DestBB, Br.MaxDisp))
1633  return false;
1634 
1635  if (!Br.isCond)
1636  return fixupUnconditionalBr(Br);
1637  return fixupConditionalBr(Br);
1638 }
1639 
1640 /// fixupUnconditionalBr - Fix up an unconditional branch whose destination is
1641 /// too far away to fit in its displacement field. If the LR register has been
1642 /// spilled in the epilogue, then we can use BL to implement a far jump.
1643 /// Otherwise, add an intermediate branch instruction to a branch.
1644 bool
1645 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
1646  MachineInstr *MI = Br.MI;
1647  MachineBasicBlock *MBB = MI->getParent();
1648  if (!isThumb1)
1649  llvm_unreachable("fixupUnconditionalBr is Thumb1 only!");
1650 
1651  // Use BL to implement far jump.
1652  Br.MaxDisp = (1 << 21) * 2;
1653  MI->setDesc(TII->get(ARM::tBfar));
1654  BBInfo[MBB->getNumber()].Size += 2;
1655  adjustBBOffsetsAfter(MBB);
1656  HasFarJump = true;
1657  ++NumUBrFixed;
1658 
1659  LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI);
1660 
1661  return true;
1662 }
1663 
1664 /// fixupConditionalBr - Fix up a conditional branch whose destination is too
1665 /// far away to fit in its displacement field. It is converted to an inverse
1666 /// conditional branch + an unconditional branch to the destination.
1667 bool
1668 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
1669  MachineInstr *MI = Br.MI;
1670  MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1671 
1672  // Add an unconditional branch to the destination and invert the branch
1673  // condition to jump over it:
1674  // blt L1
1675  // =>
1676  // bge L2
1677  // b L1
1678  // L2:
1680  CC = ARMCC::getOppositeCondition(CC);
1681  unsigned CCReg = MI->getOperand(2).getReg();
1682 
1683  // If the branch is at the end of its MBB and that has a fall-through block,
1684  // direct the updated conditional branch to the fall-through block. Otherwise,
1685  // split the MBB before the next instruction.
1686  MachineBasicBlock *MBB = MI->getParent();
1687  MachineInstr *BMI = &MBB->back();
1688  bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1689 
1690  ++NumCBrFixed;
1691  if (BMI != MI) {
1692  if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
1693  BMI->getOpcode() == Br.UncondBr) {
1694  // Last MI in the BB is an unconditional branch. Can we simply invert the
1695  // condition and swap destinations:
1696  // beq L1
1697  // b L2
1698  // =>
1699  // bne L2
1700  // b L1
1701  MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1702  if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
1703  LLVM_DEBUG(
1704  dbgs() << " Invert Bcc condition and swap its destination with "
1705  << *BMI);
1706  BMI->getOperand(0).setMBB(DestBB);
1707  MI->getOperand(0).setMBB(NewDest);
1708  MI->getOperand(1).setImm(CC);
1709  return true;
1710  }
1711  }
1712  }
1713 
1714  if (NeedSplit) {
1715  splitBlockBeforeInstr(MI);
1716  // No need for the branch to the next block. We're adding an unconditional
1717  // branch to the destination.
1718  int delta = TII->getInstSizeInBytes(MBB->back());
1719  BBInfo[MBB->getNumber()].Size -= delta;
1720  MBB->back().eraseFromParent();
1721 
1722  // The conditional successor will be swapped between the BBs after this, so
1723  // update CFG.
1724  MBB->addSuccessor(DestBB);
1725  std::next(MBB->getIterator())->removeSuccessor(DestBB);
1726 
1727  // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
1728  }
1729  MachineBasicBlock *NextBB = &*++MBB->getIterator();
1730 
1731  LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
1732  << " also invert condition and change dest. to "
1733  << printMBBReference(*NextBB) << "\n");
1734 
1735  // Insert a new conditional branch and a new unconditional branch.
1736  // Also update the ImmBranch as well as adding a new entry for the new branch.
1737  BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1738  .addMBB(NextBB).addImm(CC).addReg(CCReg);
1739  Br.MI = &MBB->back();
1740  BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
1741  if (isThumb)
1742  BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr))
1743  .addMBB(DestBB)
1744  .add(predOps(ARMCC::AL));
1745  else
1746  BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1747  BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
1748  unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1749  ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1750 
1751  // Remove the old conditional branch. It may or may not still be in MBB.
1752  BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
1753  MI->eraseFromParent();
1754  adjustBBOffsetsAfter(MBB);
1755  return true;
1756 }
1757 
1758 /// undoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1759 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1760 /// to do this if tBfar is not used.
1761 bool ARMConstantIslands::undoLRSpillRestore() {
1762  bool MadeChange = false;
1763  for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1764  MachineInstr *MI = PushPopMIs[i];
1765  // First two operands are predicates.
1766  if (MI->getOpcode() == ARM::tPOP_RET &&
1767  MI->getOperand(2).getReg() == ARM::PC &&
1768  MI->getNumExplicitOperands() == 3) {
1769  // Create the new insn and copy the predicate from the old.
1770  BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
1771  .add(MI->getOperand(0))
1772  .add(MI->getOperand(1));
1773  MI->eraseFromParent();
1774  MadeChange = true;
1775  } else if (MI->getOpcode() == ARM::tPUSH &&
1776  MI->getOperand(2).getReg() == ARM::LR &&
1777  MI->getNumExplicitOperands() == 3) {
1778  // Just remove the push.
1779  MI->eraseFromParent();
1780  MadeChange = true;
1781  }
1782  }
1783  return MadeChange;
1784 }
1785 
1786 bool ARMConstantIslands::optimizeThumb2Instructions() {
1787  bool MadeChange = false;
1788 
1789  // Shrink ADR and LDR from constantpool.
1790  for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1791  CPUser &U = CPUsers[i];
1792  unsigned Opcode = U.MI->getOpcode();
1793  unsigned NewOpc = 0;
1794  unsigned Scale = 1;
1795  unsigned Bits = 0;
1796  switch (Opcode) {
1797  default: break;
1798  case ARM::t2LEApcrel:
1799  if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1800  NewOpc = ARM::tLEApcrel;
1801  Bits = 8;
1802  Scale = 4;
1803  }
1804  break;
1805  case ARM::t2LDRpci:
1806  if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1807  NewOpc = ARM::tLDRpci;
1808  Bits = 8;
1809  Scale = 4;
1810  }
1811  break;
1812  }
1813 
1814  if (!NewOpc)
1815  continue;
1816 
1817  unsigned UserOffset = getUserOffset(U);
1818  unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1819 
1820  // Be conservative with inline asm.
1821  if (!U.KnownAlignment)
1822  MaxOffs -= 2;
1823 
1824  // FIXME: Check if offset is multiple of scale if scale is not 4.
1825  if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1826  LLVM_DEBUG(dbgs() << "Shrink: " << *U.MI);
1827  U.MI->setDesc(TII->get(NewOpc));
1828  MachineBasicBlock *MBB = U.MI->getParent();
1829  BBInfo[MBB->getNumber()].Size -= 2;
1830  adjustBBOffsetsAfter(MBB);
1831  ++NumT2CPShrunk;
1832  MadeChange = true;
1833  }
1834  }
1835 
1836  return MadeChange;
1837 }
1838 
1839 bool ARMConstantIslands::optimizeThumb2Branches() {
1840  bool MadeChange = false;
1841 
1842  // The order in which branches appear in ImmBranches is approximately their
1843  // order within the function body. By visiting later branches first, we reduce
1844  // the distance between earlier forward branches and their targets, making it
1845  // more likely that the cbn?z optimization, which can only apply to forward
1846  // branches, will succeed.
1847  for (unsigned i = ImmBranches.size(); i != 0; --i) {
1848  ImmBranch &Br = ImmBranches[i-1];
1849  unsigned Opcode = Br.MI->getOpcode();
1850  unsigned NewOpc = 0;
1851  unsigned Scale = 1;
1852  unsigned Bits = 0;
1853  switch (Opcode) {
1854  default: break;
1855  case ARM::t2B:
1856  NewOpc = ARM::tB;
1857  Bits = 11;
1858  Scale = 2;
1859  break;
1860  case ARM::t2Bcc:
1861  NewOpc = ARM::tBcc;
1862  Bits = 8;
1863  Scale = 2;
1864  break;
1865  }
1866  if (NewOpc) {
1867  unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1868  MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1869  if (isBBInRange(Br.MI, DestBB, MaxOffs)) {
1870  LLVM_DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1871  Br.MI->setDesc(TII->get(NewOpc));
1872  MachineBasicBlock *MBB = Br.MI->getParent();
1873  BBInfo[MBB->getNumber()].Size -= 2;
1874  adjustBBOffsetsAfter(MBB);
1875  ++NumT2BrShrunk;
1876  MadeChange = true;
1877  }
1878  }
1879 
1880  Opcode = Br.MI->getOpcode();
1881  if (Opcode != ARM::tBcc)
1882  continue;
1883 
1884  // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1885  // so this transformation is not safe.
1886  if (!Br.MI->killsRegister(ARM::CPSR))
1887  continue;
1888 
1889  NewOpc = 0;
1890  unsigned PredReg = 0;
1891  ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);
1892  if (Pred == ARMCC::EQ)
1893  NewOpc = ARM::tCBZ;
1894  else if (Pred == ARMCC::NE)
1895  NewOpc = ARM::tCBNZ;
1896  if (!NewOpc)
1897  continue;
1898  MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1899  // Check if the distance is within 126. Subtract starting offset by 2
1900  // because the cmp will be eliminated.
1901  unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;
1902  unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1903  if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
1904  MachineBasicBlock::iterator CmpMI = Br.MI;
1905  if (CmpMI != Br.MI->getParent()->begin()) {
1906  --CmpMI;
1907  if (CmpMI->getOpcode() == ARM::tCMPi8) {
1908  unsigned Reg = CmpMI->getOperand(0).getReg();
1909  Pred = getInstrPredicate(*CmpMI, PredReg);
1910  if (Pred == ARMCC::AL &&
1911  CmpMI->getOperand(1).getImm() == 0 &&
1912  isARMLowRegister(Reg)) {
1913  MachineBasicBlock *MBB = Br.MI->getParent();
1914  LLVM_DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);
1915  MachineInstr *NewBR =
1916  BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1917  .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
1918  CmpMI->eraseFromParent();
1919  Br.MI->eraseFromParent();
1920  Br.MI = NewBR;
1921  BBInfo[MBB->getNumber()].Size -= 2;
1922  adjustBBOffsetsAfter(MBB);
1923  ++NumCBZ;
1924  MadeChange = true;
1925  }
1926  }
1927  }
1928  }
1929  }
1930 
1931  return MadeChange;
1932 }
1933 
1934 static bool isSimpleIndexCalc(MachineInstr &I, unsigned EntryReg,
1935  unsigned BaseReg) {
1936  if (I.getOpcode() != ARM::t2ADDrs)
1937  return false;
1938 
1939  if (I.getOperand(0).getReg() != EntryReg)
1940  return false;
1941 
1942  if (I.getOperand(1).getReg() != BaseReg)
1943  return false;
1944 
1945  // FIXME: what about CC and IdxReg?
1946  return true;
1947 }
1948 
1949 /// While trying to form a TBB/TBH instruction, we may (if the table
1950 /// doesn't immediately follow the BR_JT) need access to the start of the
1951 /// jump-table. We know one instruction that produces such a register; this
1952 /// function works out whether that definition can be preserved to the BR_JT,
1953 /// possibly by removing an intervening addition (which is usually needed to
1954 /// calculate the actual entry to jump to).
1955 bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
1956  MachineInstr *LEAMI,
1957  unsigned &DeadSize,
1958  bool &CanDeleteLEA,
1959  bool &BaseRegKill) {
1960  if (JumpMI->getParent() != LEAMI->getParent())
1961  return false;
1962 
1963  // Now we hope that we have at least these instructions in the basic block:
1964  // BaseReg = t2LEA ...
1965  // [...]
1966  // EntryReg = t2ADDrs BaseReg, ...
1967  // [...]
1968  // t2BR_JT EntryReg
1969  //
1970  // We have to be very conservative about what we recognise here though. The
1971  // main perturbing factors to watch out for are:
1972  // + Spills at any point in the chain: not direct problems but we would
1973  // expect a blocking Def of the spilled register so in practice what we
1974  // can do is limited.
1975  // + EntryReg == BaseReg: this is the one situation we should allow a Def
1976  // of BaseReg, but only if the t2ADDrs can be removed.
1977  // + Some instruction other than t2ADDrs computing the entry. Not seen in
1978  // the wild, but we should be careful.
1979  unsigned EntryReg = JumpMI->getOperand(0).getReg();
1980  unsigned BaseReg = LEAMI->getOperand(0).getReg();
1981 
1982  CanDeleteLEA = true;
1983  BaseRegKill = false;
1984  MachineInstr *RemovableAdd = nullptr;
1986  for (++I; &*I != JumpMI; ++I) {
1987  if (isSimpleIndexCalc(*I, EntryReg, BaseReg)) {
1988  RemovableAdd = &*I;
1989  break;
1990  }
1991 
1992  for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
1993  const MachineOperand &MO = I->getOperand(K);
1994  if (!MO.isReg() || !MO.getReg())
1995  continue;
1996  if (MO.isDef() && MO.getReg() == BaseReg)
1997  return false;
1998  if (MO.isUse() && MO.getReg() == BaseReg) {
1999  BaseRegKill = BaseRegKill || MO.isKill();
2000  CanDeleteLEA = false;
2001  }
2002  }
2003  }
2004 
2005  if (!RemovableAdd)
2006  return true;
2007 
2008  // Check the add really is removable, and that nothing else in the block
2009  // clobbers BaseReg.
2010  for (++I; &*I != JumpMI; ++I) {
2011  for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
2012  const MachineOperand &MO = I->getOperand(K);
2013  if (!MO.isReg() || !MO.getReg())
2014  continue;
2015  if (MO.isDef() && MO.getReg() == BaseReg)
2016  return false;
2017  if (MO.isUse() && MO.getReg() == EntryReg)
2018  RemovableAdd = nullptr;
2019  }
2020  }
2021 
2022  if (RemovableAdd) {
2023  RemovableAdd->eraseFromParent();
2024  DeadSize += isThumb2 ? 4 : 2;
2025  } else if (BaseReg == EntryReg) {
2026  // The add wasn't removable, but clobbered the base for the TBB. So we can't
2027  // preserve it.
2028  return false;
2029  }
2030 
2031  // We reached the end of the block without seeing another definition of
2032  // BaseReg (except, possibly the t2ADDrs, which was removed). BaseReg can be
2033  // used in the TBB/TBH if necessary.
2034  return true;
2035 }
2036 
2037 /// Returns whether CPEMI is the first instruction in the block
2038 /// immediately following JTMI (assumed to be a TBB or TBH terminator). If so,
2039 /// we can switch the first register to PC and usually remove the address
2040 /// calculation that preceded it.
2041 static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI) {
2043  MachineFunction *MF = MBB->getParent();
2044  ++MBB;
2045 
2046  return MBB != MF->end() && MBB->begin() != MBB->end() &&
2047  &*MBB->begin() == CPEMI;
2048 }
2049 
2051  MachineInstr *JumpMI,
2052  unsigned &DeadSize) {
2053  // Remove a dead add between the LEA and JT, which used to compute EntryReg,
2054  // but the JT now uses PC. Finds the last ADD (if any) that def's EntryReg
2055  // and is not clobbered / used.
2056  MachineInstr *RemovableAdd = nullptr;
2057  unsigned EntryReg = JumpMI->getOperand(0).getReg();
2058 
2059  // Find the last ADD to set EntryReg
2061  for (++I; &*I != JumpMI; ++I) {
2062  if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2063  RemovableAdd = &*I;
2064  }
2065 
2066  if (!RemovableAdd)
2067  return;
2068 
2069  // Ensure EntryReg is not clobbered or used.
2070  MachineBasicBlock::iterator J(RemovableAdd);
2071  for (++J; &*J != JumpMI; ++J) {
2072  for (unsigned K = 0, E = J->getNumOperands(); K != E; ++K) {
2073  const MachineOperand &MO = J->getOperand(K);
2074  if (!MO.isReg() || !MO.getReg())
2075  continue;
2076  if (MO.isDef() && MO.getReg() == EntryReg)
2077  return;
2078  if (MO.isUse() && MO.getReg() == EntryReg)
2079  return;
2080  }
2081  }
2082 
2083  LLVM_DEBUG(dbgs() << "Removing Dead Add: " << *RemovableAdd);
2084  RemovableAdd->eraseFromParent();
2085  DeadSize += 4;
2086 }
2087 
2088 static bool registerDefinedBetween(unsigned Reg,
2091  const TargetRegisterInfo *TRI) {
2092  for (auto I = From; I != To; ++I)
2093  if (I->modifiesRegister(Reg, TRI))
2094  return true;
2095  return false;
2096 }
2097 
2098 /// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
2099 /// jumptables when it's possible.
2100 bool ARMConstantIslands::optimizeThumb2JumpTables() {
2101  bool MadeChange = false;
2102 
2103  // FIXME: After the tables are shrunk, can we get rid some of the
2104  // constantpool tables?
2105  MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2106  if (!MJTI) return false;
2107 
2108  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2109  for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
2110  MachineInstr *MI = T2JumpTables[i];
2111  const MCInstrDesc &MCID = MI->getDesc();
2112  unsigned NumOps = MCID.getNumOperands();
2113  unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2114  MachineOperand JTOP = MI->getOperand(JTOpIdx);
2115  unsigned JTI = JTOP.getIndex();
2116  assert(JTI < JT.size());
2117 
2118  bool ByteOk = true;
2119  bool HalfWordOk = true;
2120  unsigned JTOffset = getOffsetOf(MI) + 4;
2121  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2122  for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
2123  MachineBasicBlock *MBB = JTBBs[j];
2124  unsigned DstOffset = BBInfo[MBB->getNumber()].Offset;
2125  // Negative offset is not ok. FIXME: We should change BB layout to make
2126  // sure all the branches are forward.
2127  if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
2128  ByteOk = false;
2129  unsigned TBHLimit = ((1<<16)-1)*2;
2130  if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
2131  HalfWordOk = false;
2132  if (!ByteOk && !HalfWordOk)
2133  break;
2134  }
2135 
2136  if (!ByteOk && !HalfWordOk)
2137  continue;
2138 
2139  CPUser &User = CPUsers[JumpTableUserIndices[JTI]];
2140  MachineBasicBlock *MBB = MI->getParent();
2141  if (!MI->getOperand(0).isKill()) // FIXME: needed now?
2142  continue;
2143 
2144  unsigned DeadSize = 0;
2145  bool CanDeleteLEA = false;
2146  bool BaseRegKill = false;
2147 
2148  unsigned IdxReg = ~0U;
2149  bool IdxRegKill = true;
2150  if (isThumb2) {
2151  IdxReg = MI->getOperand(1).getReg();
2152  IdxRegKill = MI->getOperand(1).isKill();
2153 
2154  bool PreservedBaseReg =
2155  preserveBaseRegister(MI, User.MI, DeadSize, CanDeleteLEA, BaseRegKill);
2156  if (!jumpTableFollowsTB(MI, User.CPEMI) && !PreservedBaseReg)
2157  continue;
2158  } else {
2159  // We're in thumb-1 mode, so we must have something like:
2160  // %idx = tLSLri %idx, 2
2161  // %base = tLEApcrelJT
2162  // %t = tLDRr %base, %idx
2163  unsigned BaseReg = User.MI->getOperand(0).getReg();
2164 
2165  if (User.MI->getIterator() == User.MI->getParent()->begin())
2166  continue;
2167  MachineInstr *Shift = User.MI->getPrevNode();
2168  if (Shift->getOpcode() != ARM::tLSLri ||
2169  Shift->getOperand(3).getImm() != 2 ||
2170  !Shift->getOperand(2).isKill())
2171  continue;
2172  IdxReg = Shift->getOperand(2).getReg();
2173  unsigned ShiftedIdxReg = Shift->getOperand(0).getReg();
2174 
2175  // It's important that IdxReg is live until the actual TBB/TBH. Most of
2176  // the range is checked later, but the LEA might still clobber it and not
2177  // actually get removed.
2178  if (BaseReg == IdxReg && !jumpTableFollowsTB(MI, User.CPEMI))
2179  continue;
2180 
2181  MachineInstr *Load = User.MI->getNextNode();
2182  if (Load->getOpcode() != ARM::tLDRr)
2183  continue;
2184  if (Load->getOperand(1).getReg() != BaseReg ||
2185  Load->getOperand(2).getReg() != ShiftedIdxReg ||
2186  !Load->getOperand(2).isKill())
2187  continue;
2188 
2189  // If we're in PIC mode, there should be another ADD following.
2190  auto *TRI = STI->getRegisterInfo();
2191 
2192  // %base cannot be redefined after the load as it will appear before
2193  // TBB/TBH like:
2194  // %base =
2195  // %base =
2196  // tBB %base, %idx
2197  if (registerDefinedBetween(BaseReg, Load->getNextNode(), MBB->end(), TRI))
2198  continue;
2199 
2200  if (isPositionIndependentOrROPI) {
2201  MachineInstr *Add = Load->getNextNode();
2202  if (Add->getOpcode() != ARM::tADDrr ||
2203  Add->getOperand(2).getReg() != BaseReg ||
2204  Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
2205  !Add->getOperand(3).isKill())
2206  continue;
2207  if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2208  continue;
2209  if (registerDefinedBetween(IdxReg, Add->getNextNode(), MI, TRI))
2210  // IdxReg gets redefined in the middle of the sequence.
2211  continue;
2212  Add->eraseFromParent();
2213  DeadSize += 2;
2214  } else {
2215  if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
2216  continue;
2217  if (registerDefinedBetween(IdxReg, Load->getNextNode(), MI, TRI))
2218  // IdxReg gets redefined in the middle of the sequence.
2219  continue;
2220  }
2221 
2222  // Now safe to delete the load and lsl. The LEA will be removed later.
2223  CanDeleteLEA = true;
2224  Shift->eraseFromParent();
2225  Load->eraseFromParent();
2226  DeadSize += 4;
2227  }
2228 
2229  LLVM_DEBUG(dbgs() << "Shrink JT: " << *MI);
2230  MachineInstr *CPEMI = User.CPEMI;
2231  unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
2232  if (!isThumb2)
2233  Opc = ByteOk ? ARM::tTBB_JT : ARM::tTBH_JT;
2234 
2236  MachineInstr *NewJTMI =
2237  BuildMI(*MBB, MI_JT, MI->getDebugLoc(), TII->get(Opc))
2238  .addReg(User.MI->getOperand(0).getReg(),
2239  getKillRegState(BaseRegKill))
2240  .addReg(IdxReg, getKillRegState(IdxRegKill))
2241  .addJumpTableIndex(JTI, JTOP.getTargetFlags())
2242  .addImm(CPEMI->getOperand(0).getImm());
2243  LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI);
2244 
2245  unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH;
2246  CPEMI->setDesc(TII->get(JTOpc));
2247 
2248  if (jumpTableFollowsTB(MI, User.CPEMI)) {
2249  NewJTMI->getOperand(0).setReg(ARM::PC);
2250  NewJTMI->getOperand(0).setIsKill(false);
2251 
2252  if (CanDeleteLEA) {
2253  if (isThumb2)
2254  RemoveDeadAddBetweenLEAAndJT(User.MI, MI, DeadSize);
2255 
2256  User.MI->eraseFromParent();
2257  DeadSize += isThumb2 ? 4 : 2;
2258 
2259  // The LEA was eliminated, the TBB instruction becomes the only new user
2260  // of the jump table.
2261  User.MI = NewJTMI;
2262  User.MaxDisp = 4;
2263  User.NegOk = false;
2264  User.IsSoImm = false;
2265  User.KnownAlignment = false;
2266  } else {
2267  // The LEA couldn't be eliminated, so we must add another CPUser to
2268  // record the TBB or TBH use.
2269  int CPEntryIdx = JumpTableEntryIndices[JTI];
2270  auto &CPEs = CPEntries[CPEntryIdx];
2271  auto Entry =
2272  find_if(CPEs, [&](CPEntry &E) { return E.CPEMI == User.CPEMI; });
2273  ++Entry->RefCount;
2274  CPUsers.emplace_back(CPUser(NewJTMI, User.CPEMI, 4, false, false));
2275  }
2276  }
2277 
2278  unsigned NewSize = TII->getInstSizeInBytes(*NewJTMI);
2279  unsigned OrigSize = TII->getInstSizeInBytes(*MI);
2280  MI->eraseFromParent();
2281 
2282  int Delta = OrigSize - NewSize + DeadSize;
2283  BBInfo[MBB->getNumber()].Size -= Delta;
2284  adjustBBOffsetsAfter(MBB);
2285 
2286  ++NumTBs;
2287  MadeChange = true;
2288  }
2289 
2290  return MadeChange;
2291 }
2292 
2293 /// reorderThumb2JumpTables - Adjust the function's block layout to ensure that
2294 /// jump tables always branch forwards, since that's what tbb and tbh need.
2295 bool ARMConstantIslands::reorderThumb2JumpTables() {
2296  bool MadeChange = false;
2297 
2298  MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2299  if (!MJTI) return false;
2300 
2301  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2302  for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
2303  MachineInstr *MI = T2JumpTables[i];
2304  const MCInstrDesc &MCID = MI->getDesc();
2305  unsigned NumOps = MCID.getNumOperands();
2306  unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2307  MachineOperand JTOP = MI->getOperand(JTOpIdx);
2308  unsigned JTI = JTOP.getIndex();
2309  assert(JTI < JT.size());
2310 
2311  // We prefer if target blocks for the jump table come after the jump
2312  // instruction so we can use TB[BH]. Loop through the target blocks
2313  // and try to adjust them such that that's true.
2314  int JTNumber = MI->getParent()->getNumber();
2315  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2316  for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
2317  MachineBasicBlock *MBB = JTBBs[j];
2318  int DTNumber = MBB->getNumber();
2319 
2320  if (DTNumber < JTNumber) {
2321  // The destination precedes the switch. Try to move the block forward
2322  // so we have a positive offset.
2323  MachineBasicBlock *NewBB =
2324  adjustJTTargetBlockForward(MBB, MI->getParent());
2325  if (NewBB)
2326  MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
2327  MadeChange = true;
2328  }
2329  }
2330  }
2331 
2332  return MadeChange;
2333 }
2334 
2335 MachineBasicBlock *ARMConstantIslands::
2336 adjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB) {
2337  // If the destination block is terminated by an unconditional branch,
2338  // try to move it; otherwise, create a new block following the jump
2339  // table that branches back to the actual target. This is a very simple
2340  // heuristic. FIXME: We can definitely improve it.
2341  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
2345  MachineFunction::iterator OldPrior = std::prev(BBi);
2346 
2347  // If the block terminator isn't analyzable, don't try to move the block
2348  bool B = TII->analyzeBranch(*BB, TBB, FBB, Cond);
2349 
2350  // If the block ends in an unconditional branch, move it. The prior block
2351  // has to have an analyzable terminator for us to move this one. Be paranoid
2352  // and make sure we're not trying to move the entry block of the function.
2353  if (!B && Cond.empty() && BB != &MF->front() &&
2354  !TII->analyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
2355  BB->moveAfter(JTBB);
2356  OldPrior->updateTerminator();
2357  BB->updateTerminator();
2358  // Update numbering to account for the block being moved.
2359  MF->RenumberBlocks();
2360  ++NumJTMoved;
2361  return nullptr;
2362  }
2363 
2364  // Create a new MBB for the code after the jump BB.
2365  MachineBasicBlock *NewBB =
2366  MF->CreateMachineBasicBlock(JTBB->getBasicBlock());
2367  MachineFunction::iterator MBBI = ++JTBB->getIterator();
2368  MF->insert(MBBI, NewBB);
2369 
2370  // Add an unconditional branch from NewBB to BB.
2371  // There doesn't seem to be meaningful DebugInfo available; this doesn't
2372  // correspond directly to anything in the source.
2373  if (isThumb2)
2374  BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B))
2375  .addMBB(BB)
2376  .add(predOps(ARMCC::AL));
2377  else
2378  BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB))
2379  .addMBB(BB)
2380  .add(predOps(ARMCC::AL));
2381 
2382  // Update internal data structures to account for the newly inserted MBB.
2383  MF->RenumberBlocks(NewBB);
2384 
2385  // Update the CFG.
2386  NewBB->addSuccessor(BB);
2387  JTBB->replaceSuccessor(BB, NewBB);
2388 
2389  ++NumJTInserted;
2390  return NewBB;
2391 }
2392 
2393 /// createARMConstantIslandPass - returns an instance of the constpool
2394 /// island pass.
2396  return new ARMConstantIslands();
2397 }
2398 
2399 INITIALIZE_PASS(ARMConstantIslands, "arm-cp-islands", ARM_CP_ISLANDS_OPT_NAME,
2400  false, false)
void push_back(const T &Elt)
Definition: SmallVector.h:218
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
MachineBasicBlock * getMBB() const
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
bool isEmpty() const
isEmpty - Return true if this constant pool contains no constants.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void RenumberBlocks(MachineBasicBlock *MBBFrom=nullptr)
RenumberBlocks - This discards all of the MachineBasicBlock numbers and recomputes them...
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:687
unsigned Offset
Offset - Distance from the beginning of the function to the beginning of this basic block...
STATISTIC(NumFunctions, "Total number of functions")
void moveAfter(MachineBasicBlock *NewBefore)
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
#define op(i)
void dump() const
dump - Print the current MachineFunction to cerr, useful for debugger use.
void computeBlockSize(MachineFunction *MF, MachineBasicBlock *MBB, BasicBlockInfo &BBI)
bool erase(const T &V)
Definition: SmallSet.h:208
static bool isThumb(const MCSubtargetInfo &STI)
void setAlignment(unsigned Align)
Set alignment of the basic block.
bool ReplaceMBBInJumpTable(unsigned Idx, MachineBasicBlock *Old, MachineBasicBlock *New)
ReplaceMBBInJumpTable - If Old is a target of the jump tables, update the jump table to branch to New...
BasicBlockInfo - Information about the offset and size of a single basic block.
static bool CompareMBBNumbers(const MachineBasicBlock *LHS, const MachineBasicBlock *RHS)
CompareMBBNumbers - Little predicate function to sort the WaterList by MBB ID.
static bool isSimpleIndexCalc(MachineInstr &I, unsigned EntryReg, unsigned BaseReg)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:191
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:412
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void setIndex(int Idx)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
#define ARM_CP_ISLANDS_OPT_NAME
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
void clear()
Definition: SmallSet.h:219
static cl::opt< bool > SynthesizeThumb1TBB("arm-synthesize-thumb-1-tbb", cl::Hidden, cl::init(true), cl::desc("Use compressed jump tables in Thumb-1 by synthesizing an " "equivalent to the TBB/TBH instructions"))
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1138
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getKillRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define rc(i)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned getConstantPoolAlignment() const
getConstantPoolAlignment - Return the alignment required by the whole constant pool, of which the first element must be aligned.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned postOffset(unsigned LogAlign=0) const
Compute the offset immediately following this block.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
static bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
unsigned getAlignment() const
Return alignment of the basic block.
void ensureAlignment(unsigned A)
ensureAlignment - Make sure the function is at least 1 << A bytes aligned.
void setMBB(MachineBasicBlock *MBB)
static bool BBIsJumpedOver(MachineBasicBlock *MBB)
BBIsJumpedOver - Return true of the specified basic block&#39;s only predecessor unconditionally branches...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
void initPICLabelUId(unsigned UId)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
self_iterator getIterator()
Definition: ilist_node.h:82
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1070
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned internalKnownBits() const
Compute the number of known offset bits internally to this block.
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
static wasm::ValType getType(const TargetRegisterClass *RC)
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1063
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:241
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setIsKill(bool Val=true)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
const std::vector< MachineConstantPoolEntry > & getConstants() const
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1023
BlockVerifier::State From
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
unsigned UnknownPadding(unsigned LogAlign, unsigned KnownBits)
UnknownPadding - Return the worst case padding that could result from unknown offset bits...
MachineOperand class - Representation of each machine instruction operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
void updateTerminator()
Update the terminator instructions in block to account for changes to the layout. ...
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
APFloat neg(APFloat X)
Returns the negated value of the argument.
Definition: APFloat.h:1219
static cl::opt< bool > AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true), cl::desc("Adjust basic block layout to better use TB[BH]"))
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
int64_t getImm() const
unsigned pred_size() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
unsigned succ_size() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineFunctionProperties & set(Property P)
void recordCPEClone(unsigned CPIdx, unsigned CPCloneIdx)
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:161
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:49
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
uint8_t Unalign
Unalign - When non-zero, the block contains instructions (inline asm) of unknown size.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
static bool BBHasFallthrough(MachineBasicBlock *MBB)
BBHasFallthrough - Return true if the specified basic block can fallthrough into the block immediatel...
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects just that part of the flag set...
Definition: ARMBaseInfo.h:249
uint8_t KnownBits
KnownBits - The number of low bits in Offset that are known to be exact.
uint32_t Size
Definition: Profile.cpp:47
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
static unsigned getUnconditionalBrDisp(int Opc)
getUnconditionalBrDisp - Returns the maximum displacement that can fit in the specific unconditional ...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
static cl::opt< unsigned > CPMaxIteration("arm-constant-island-max-iteration", cl::Hidden, cl::init(30), cl::desc("The max number of iteration for converge"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI)
Returns whether CPEMI is the first instruction in the block immediately following JTMI (assumed to be...
void push_back(MachineBasicBlock *MBB)
uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
Definition: MathExtras.h:727
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
ppc ctr loops verify
static void RemoveDeadAddBetweenLEAAndJT(MachineInstr *LEAMI, MachineInstr *JumpMI, unsigned &DeadSize)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
uint8_t PostAlign
PostAlign - When non-zero, the block terminator contains a .align directive, so the end of the block ...
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:245
Properties which a MachineFunction may have at a given point in time.
std::vector< BasicBlockInfo > computeAllBlockSizes(MachineFunction *MF)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165