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ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
13 #include "Utils/ARMBaseInfo.h"
14 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/Compiler.h"
26 #include <algorithm>
27 #include <cassert>
28 #include <cstdint>
29 #include <vector>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "arm-disassembler"
34 
36 
37 namespace {
38 
39  // Handles the condition code status of instructions in IT blocks
40  class ITStatus
41  {
42  public:
43  // Returns the condition code for instruction in IT block
44  unsigned getITCC() {
45  unsigned CC = ARMCC::AL;
46  if (instrInITBlock())
47  CC = ITStates.back();
48  return CC;
49  }
50 
51  // Advances the IT block state to the next T or E
52  void advanceITState() {
53  ITStates.pop_back();
54  }
55 
56  // Returns true if the current instruction is in an IT block
57  bool instrInITBlock() {
58  return !ITStates.empty();
59  }
60 
61  // Returns true if current instruction is the last instruction in an IT block
62  bool instrLastInITBlock() {
63  return ITStates.size() == 1;
64  }
65 
66  // Called when decoding an IT instruction. Sets the IT state for the following
67  // instructions that for the IT block. Firstcond and Mask correspond to the
68  // fields in the IT instruction encoding.
69  void setITState(char Firstcond, char Mask) {
70  // (3 - the number of trailing zeros) is the number of then / else.
71  unsigned CondBit0 = Firstcond & 1;
72  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
73  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
74  assert(NumTZ <= 3 && "Invalid IT mask!");
75  // push condition codes onto the stack the correct order for the pops
76  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77  bool T = ((Mask >> Pos) & 1) == CondBit0;
78  if (T)
79  ITStates.push_back(CCBits);
80  else
81  ITStates.push_back(CCBits ^ 1);
82  }
83  ITStates.push_back(CCBits);
84  }
85 
86  private:
87  std::vector<unsigned char> ITStates;
88  };
89 
90 /// ARM disassembler for all ARM platforms.
91 class ARMDisassembler : public MCDisassembler {
92 public:
93  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94  MCDisassembler(STI, Ctx) {
95  }
96 
97  ~ARMDisassembler() override = default;
98 
99  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
100  ArrayRef<uint8_t> Bytes, uint64_t Address,
101  raw_ostream &VStream,
102  raw_ostream &CStream) const override;
103 };
104 
105 /// Thumb disassembler for all Thumb platforms.
106 class ThumbDisassembler : public MCDisassembler {
107 public:
108  ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
109  MCDisassembler(STI, Ctx) {
110  }
111 
112  ~ThumbDisassembler() override = default;
113 
114  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
115  ArrayRef<uint8_t> Bytes, uint64_t Address,
116  raw_ostream &VStream,
117  raw_ostream &CStream) const override;
118 
119 private:
120  mutable ITStatus ITBlock;
121 
122  DecodeStatus AddThumbPredicate(MCInst&) const;
123  void UpdateThumbVFPPredicate(MCInst&) const;
124 };
125 
126 } // end anonymous namespace
127 
128 static bool Check(DecodeStatus &Out, DecodeStatus In) {
129  switch (In) {
131  // Out stays the same.
132  return true;
134  Out = In;
135  return true;
137  Out = In;
138  return false;
139  }
140  llvm_unreachable("Invalid DecodeStatus!");
141 }
142 
143 // Forward declare these because the autogenerated code will reference them.
144 // Definitions are further down.
145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
146  uint64_t Address, const void *Decoder);
148  unsigned RegNo, uint64_t Address,
149  const void *Decoder);
151  unsigned RegNo, uint64_t Address,
152  const void *Decoder);
153 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154  uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156  uint64_t Address, const void *Decoder);
157 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
158  uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
160  uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
162  uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
164  uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
166  uint64_t Address, const void *Decoder);
168  unsigned RegNo,
169  uint64_t Address,
170  const void *Decoder);
171 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
172  uint64_t Address, const void *Decoder);
173 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
174  uint64_t Address, const void *Decoder);
176  unsigned RegNo, uint64_t Address,
177  const void *Decoder);
178 
179 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
180  uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
182  uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
184  uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
186  uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
188  uint64_t Address, const void *Decoder);
189 
190 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
191  uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
193  uint64_t Address, const void *Decoder);
195  unsigned Insn,
196  uint64_t Address,
197  const void *Decoder);
198 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
199  uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
201  uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
203  uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
205  uint64_t Address, const void *Decoder);
206 
208  unsigned Insn,
209  uint64_t Adddress,
210  const void *Decoder);
211 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
212  uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
214  uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
216  uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
218  uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
220  uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
222  uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
224  uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
226  uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
228  uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
230  uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
232  uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
234  uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
236  uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
238  uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
240  uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
242  uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
244  uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
246  uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
248  uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
250  uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
252  uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
254  uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
256  uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
258  uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
260  uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
262  uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
264  uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
266  uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
268  uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
270  uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
272  uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
274  uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
276  uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
278  uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
280  uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
282  uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
284  uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
286  uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
288  uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
290  uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
292  uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
294  uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
296  uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
298  uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
300  uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
302  uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
304  uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
306  uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
308  uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
310  uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
312  uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
314  uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
316  uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
318  uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
320  uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
322  uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
324  uint64_t Address, const void *Decoder);
325 
326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
327  uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
329  uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
331  uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
333  uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
335  uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
337  uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
339  uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
341  uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
343  uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
345  uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
347  uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
349  uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
351  uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
353  uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
355  uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
357  uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
359  uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
361  uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
363  uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
365  uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
367  uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
369  uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
371  uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
373  uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
375  uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
377  uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
379  uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
381  uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
383  uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
385  uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
387  uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
389  uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
391  uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
393  uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
395  uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
397  uint64_t Address, const void *Decoder);
398 
399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
400  uint64_t Address, const void *Decoder);
401 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
402  uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
404  uint64_t Address, const void *Decoder);
405 
406 #include "ARMGenDisassemblerTables.inc"
407 
409  const MCSubtargetInfo &STI,
410  MCContext &Ctx) {
411  return new ARMDisassembler(STI, Ctx);
412 }
413 
415  const MCSubtargetInfo &STI,
416  MCContext &Ctx) {
417  return new ThumbDisassembler(STI, Ctx);
418 }
419 
420 // Post-decoding checks
422  uint64_t Address, raw_ostream &OS,
423  raw_ostream &CS,
424  uint32_t Insn,
425  DecodeStatus Result) {
426  switch (MI.getOpcode()) {
427  case ARM::HVC: {
428  // HVC is undefined if condition = 0xf otherwise upredictable
429  // if condition != 0xe
430  uint32_t Cond = (Insn >> 28) & 0xF;
431  if (Cond == 0xF)
432  return MCDisassembler::Fail;
433  if (Cond != 0xE)
435  return Result;
436  }
437  default: return Result;
438  }
439 }
440 
441 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
442  ArrayRef<uint8_t> Bytes,
443  uint64_t Address, raw_ostream &OS,
444  raw_ostream &CS) const {
445  CommentStream = &CS;
446 
447  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
448  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
449  "mode!");
450 
451  // We want to read exactly 4 bytes of data.
452  if (Bytes.size() < 4) {
453  Size = 0;
454  return MCDisassembler::Fail;
455  }
456 
457  // Encoded as a small-endian 32-bit word in the stream.
458  uint32_t Insn =
459  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
460 
461  // Calling the auto-generated decoder function.
462  DecodeStatus Result =
463  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
464  if (Result != MCDisassembler::Fail) {
465  Size = 4;
466  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
467  }
468 
469  struct DecodeTable {
470  const uint8_t *P;
471  bool DecodePred;
472  };
473 
474  const DecodeTable Tables[] = {
475  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
476  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
477  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
478  {DecoderTablev8Crypto32, false},
479  };
480 
481  for (auto Table : Tables) {
482  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
483  if (Result != MCDisassembler::Fail) {
484  Size = 4;
485  // Add a fake predicate operand, because we share these instruction
486  // definitions with Thumb2 where these instructions are predicable.
487  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
488  return MCDisassembler::Fail;
489  return Result;
490  }
491  }
492 
493  Result =
494  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
495  if (Result != MCDisassembler::Fail) {
496  Size = 4;
497  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
498  }
499 
500  Size = 4;
501  return MCDisassembler::Fail;
502 }
503 
504 namespace llvm {
505 
506 extern const MCInstrDesc ARMInsts[];
507 
508 } // end namespace llvm
509 
510 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
511 /// immediate Value in the MCInst. The immediate Value has had any PC
512 /// adjustment made by the caller. If the instruction is a branch instruction
513 /// then isBranch is true, else false. If the getOpInfo() function was set as
514 /// part of the setupForSymbolicDisassembly() call then that function is called
515 /// to get any symbolic information at the Address for this instruction. If
516 /// that returns non-zero then the symbolic information it returns is used to
517 /// create an MCExpr and that is added as an operand to the MCInst. If
518 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
519 /// Value is done and if a symbol is found an MCExpr is created with that, else
520 /// an MCExpr with Value is created. This function returns true if it adds an
521 /// operand to the MCInst and false otherwise.
522 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
523  bool isBranch, uint64_t InstSize,
524  MCInst &MI, const void *Decoder) {
525  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
526  // FIXME: Does it make sense for value to be negative?
527  return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
528  /* Offset */ 0, InstSize);
529 }
530 
531 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
532 /// referenced by a load instruction with the base register that is the Pc.
533 /// These can often be values in a literal pool near the Address of the
534 /// instruction. The Address of the instruction and its immediate Value are
535 /// used as a possible literal pool entry. The SymbolLookUp call back will
536 /// return the name of a symbol referenced by the literal pool's entry if
537 /// the referenced address is that of a symbol. Or it will return a pointer to
538 /// a literal 'C' string if the referenced address of the literal pool's entry
539 /// is an address into a section with 'C' string literals.
541  const void *Decoder) {
542  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
543  Dis->tryAddingPcLoadReferenceComment(Value, Address);
544 }
545 
546 // Thumb1 instructions don't have explicit S bits. Rather, they
547 // implicitly set CPSR. Since it's not represented in the encoding, the
548 // auto-generated decoder won't inject the CPSR operand. We need to fix
549 // that as a post-pass.
550 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
551  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
552  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
553  MCInst::iterator I = MI.begin();
554  for (unsigned i = 0; i < NumOps; ++i, ++I) {
555  if (I == MI.end()) break;
556  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
557  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
558  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
559  return;
560  }
561  }
562 
563  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
564 }
565 
566 // Most Thumb instructions don't have explicit predicates in the
567 // encoding, but rather get their predicates from IT context. We need
568 // to fix up the predicate operands using this context information as a
569 // post-pass.
571 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
573 
574  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
575 
576  // A few instructions actually have predicates encoded in them. Don't
577  // try to overwrite it if we're seeing one of those.
578  switch (MI.getOpcode()) {
579  case ARM::tBcc:
580  case ARM::t2Bcc:
581  case ARM::tCBZ:
582  case ARM::tCBNZ:
583  case ARM::tCPS:
584  case ARM::t2CPS3p:
585  case ARM::t2CPS2p:
586  case ARM::t2CPS1p:
587  case ARM::tMOVSr:
588  case ARM::tSETEND:
589  // Some instructions (mostly conditional branches) are not
590  // allowed in IT blocks.
591  if (ITBlock.instrInITBlock())
592  S = SoftFail;
593  else
594  return Success;
595  break;
596  case ARM::t2HINT:
597  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
598  S = SoftFail;
599  break;
600  case ARM::tB:
601  case ARM::t2B:
602  case ARM::t2TBB:
603  case ARM::t2TBH:
604  // Some instructions (mostly unconditional branches) can
605  // only appears at the end of, or outside of, an IT.
606  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
607  S = SoftFail;
608  break;
609  default:
610  break;
611  }
612 
613  // If we're in an IT block, base the predicate on that. Otherwise,
614  // assume a predicate of AL.
615  unsigned CC;
616  CC = ITBlock.getITCC();
617  if (CC == 0xF)
618  CC = ARMCC::AL;
619  if (ITBlock.instrInITBlock())
620  ITBlock.advanceITState();
621 
622  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
623  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
624  MCInst::iterator I = MI.begin();
625  for (unsigned i = 0; i < NumOps; ++i, ++I) {
626  if (I == MI.end()) break;
627  if (OpInfo[i].isPredicate()) {
628  I = MI.insert(I, MCOperand::createImm(CC));
629  ++I;
630  if (CC == ARMCC::AL)
631  MI.insert(I, MCOperand::createReg(0));
632  else
633  MI.insert(I, MCOperand::createReg(ARM::CPSR));
634  return S;
635  }
636  }
637 
638  I = MI.insert(I, MCOperand::createImm(CC));
639  ++I;
640  if (CC == ARMCC::AL)
641  MI.insert(I, MCOperand::createReg(0));
642  else
643  MI.insert(I, MCOperand::createReg(ARM::CPSR));
644 
645  return S;
646 }
647 
648 // Thumb VFP instructions are a special case. Because we share their
649 // encodings between ARM and Thumb modes, and they are predicable in ARM
650 // mode, the auto-generated decoder will give them an (incorrect)
651 // predicate operand. We need to rewrite these operands based on the IT
652 // context as a post-pass.
653 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
654  unsigned CC;
655  CC = ITBlock.getITCC();
656  if (ITBlock.instrInITBlock())
657  ITBlock.advanceITState();
658 
659  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
660  MCInst::iterator I = MI.begin();
661  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
662  for (unsigned i = 0; i < NumOps; ++i, ++I) {
663  if (OpInfo[i].isPredicate() ) {
664  I->setImm(CC);
665  ++I;
666  if (CC == ARMCC::AL)
667  I->setReg(0);
668  else
669  I->setReg(ARM::CPSR);
670  return;
671  }
672  }
673 }
674 
675 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
676  ArrayRef<uint8_t> Bytes,
677  uint64_t Address,
678  raw_ostream &OS,
679  raw_ostream &CS) const {
680  CommentStream = &CS;
681 
682  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
683  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
684 
685  // We want to read exactly 2 bytes of data.
686  if (Bytes.size() < 2) {
687  Size = 0;
688  return MCDisassembler::Fail;
689  }
690 
691  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
692  DecodeStatus Result =
693  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
694  if (Result != MCDisassembler::Fail) {
695  Size = 2;
696  Check(Result, AddThumbPredicate(MI));
697  return Result;
698  }
699 
700  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
701  STI);
702  if (Result) {
703  Size = 2;
704  bool InITBlock = ITBlock.instrInITBlock();
705  Check(Result, AddThumbPredicate(MI));
706  AddThumb1SBit(MI, InITBlock);
707  return Result;
708  }
709 
710  Result =
711  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
712  if (Result != MCDisassembler::Fail) {
713  Size = 2;
714 
715  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
716  // the Thumb predicate.
717  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
718  Result = MCDisassembler::SoftFail;
719 
720  Check(Result, AddThumbPredicate(MI));
721 
722  // If we find an IT instruction, we need to parse its condition
723  // code and mask operands so that we can apply them correctly
724  // to the subsequent instructions.
725  if (MI.getOpcode() == ARM::t2IT) {
726 
727  unsigned Firstcond = MI.getOperand(0).getImm();
728  unsigned Mask = MI.getOperand(1).getImm();
729  ITBlock.setITState(Firstcond, Mask);
730  }
731 
732  return Result;
733  }
734 
735  // We want to read exactly 4 bytes of data.
736  if (Bytes.size() < 4) {
737  Size = 0;
738  return MCDisassembler::Fail;
739  }
740 
741  uint32_t Insn32 =
742  (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
743  Result =
744  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
745  if (Result != MCDisassembler::Fail) {
746  Size = 4;
747  bool InITBlock = ITBlock.instrInITBlock();
748  Check(Result, AddThumbPredicate(MI));
749  AddThumb1SBit(MI, InITBlock);
750  return Result;
751  }
752 
753  Result =
754  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
755  if (Result != MCDisassembler::Fail) {
756  Size = 4;
757  Check(Result, AddThumbPredicate(MI));
758  return Result;
759  }
760 
761  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
762  Result =
763  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
764  if (Result != MCDisassembler::Fail) {
765  Size = 4;
766  UpdateThumbVFPPredicate(MI);
767  return Result;
768  }
769  }
770 
771  Result =
772  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
773  if (Result != MCDisassembler::Fail) {
774  Size = 4;
775  return Result;
776  }
777 
778  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
779  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
780  STI);
781  if (Result != MCDisassembler::Fail) {
782  Size = 4;
783  Check(Result, AddThumbPredicate(MI));
784  return Result;
785  }
786  }
787 
788  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
789  uint32_t NEONLdStInsn = Insn32;
790  NEONLdStInsn &= 0xF0FFFFFF;
791  NEONLdStInsn |= 0x04000000;
792  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
793  Address, this, STI);
794  if (Result != MCDisassembler::Fail) {
795  Size = 4;
796  Check(Result, AddThumbPredicate(MI));
797  return Result;
798  }
799  }
800 
801  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
802  uint32_t NEONDataInsn = Insn32;
803  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
804  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
805  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
806  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
807  Address, this, STI);
808  if (Result != MCDisassembler::Fail) {
809  Size = 4;
810  Check(Result, AddThumbPredicate(MI));
811  return Result;
812  }
813 
814  uint32_t NEONCryptoInsn = Insn32;
815  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
816  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
817  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
818  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
819  Address, this, STI);
820  if (Result != MCDisassembler::Fail) {
821  Size = 4;
822  return Result;
823  }
824 
825  uint32_t NEONv8Insn = Insn32;
826  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
827  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
828  this, STI);
829  if (Result != MCDisassembler::Fail) {
830  Size = 4;
831  return Result;
832  }
833  }
834 
835  Result =
836  decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
837  if (Result != MCDisassembler::Fail) {
838  Size = 4;
839  Check(Result, AddThumbPredicate(MI));
840  return Result;
841  }
842 
843  Size = 0;
844  return MCDisassembler::Fail;
845 }
846 
847 extern "C" void LLVMInitializeARMDisassembler() {
856 }
857 
858 static const uint16_t GPRDecoderTable[] = {
859  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
860  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
861  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
862  ARM::R12, ARM::SP, ARM::LR, ARM::PC
863 };
864 
865 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
866  uint64_t Address, const void *Decoder) {
867  if (RegNo > 15)
868  return MCDisassembler::Fail;
869 
870  unsigned Register = GPRDecoderTable[RegNo];
871  Inst.addOperand(MCOperand::createReg(Register));
873 }
874 
875 static DecodeStatus
876 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
877  uint64_t Address, const void *Decoder) {
879 
880  if (RegNo == 15)
882 
883  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
884 
885  return S;
886 }
887 
888 static DecodeStatus
890  uint64_t Address, const void *Decoder) {
892 
893  if (RegNo == 15)
894  {
895  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
897  }
898 
899  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
900  return S;
901 }
902 
903 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
904  uint64_t Address, const void *Decoder) {
905  if (RegNo > 7)
906  return MCDisassembler::Fail;
907  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
908 }
909 
910 static const uint16_t GPRPairDecoderTable[] = {
911  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
912  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
913 };
914 
915 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
916  uint64_t Address, const void *Decoder) {
918 
919  if (RegNo > 13)
920  return MCDisassembler::Fail;
921 
922  if ((RegNo & 1) || RegNo == 0xe)
924 
925  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
926  Inst.addOperand(MCOperand::createReg(RegisterPair));
927  return S;
928 }
929 
930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
931  uint64_t Address, const void *Decoder) {
932  unsigned Register = 0;
933  switch (RegNo) {
934  case 0:
935  Register = ARM::R0;
936  break;
937  case 1:
938  Register = ARM::R1;
939  break;
940  case 2:
941  Register = ARM::R2;
942  break;
943  case 3:
944  Register = ARM::R3;
945  break;
946  case 9:
947  Register = ARM::R9;
948  break;
949  case 12:
950  Register = ARM::R12;
951  break;
952  default:
953  return MCDisassembler::Fail;
954  }
955 
956  Inst.addOperand(MCOperand::createReg(Register));
958 }
959 
960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
961  uint64_t Address, const void *Decoder) {
963 
964  const FeatureBitset &featureBits =
965  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
966 
967  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
969 
970  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
971  return S;
972 }
973 
974 static const uint16_t SPRDecoderTable[] = {
975  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
976  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
977  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
978  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
979  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
980  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
981  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
982  ARM::S28, ARM::S29, ARM::S30, ARM::S31
983 };
984 
985 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
986  uint64_t Address, const void *Decoder) {
987  if (RegNo > 31)
988  return MCDisassembler::Fail;
989 
990  unsigned Register = SPRDecoderTable[RegNo];
991  Inst.addOperand(MCOperand::createReg(Register));
993 }
994 
995 static const uint16_t DPRDecoderTable[] = {
996  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
997  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
998  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
999  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1000  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1001  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1002  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1003  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1004 };
1005 
1006 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1007  uint64_t Address, const void *Decoder) {
1008  const FeatureBitset &featureBits =
1009  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1010 
1011  bool hasD16 = featureBits[ARM::FeatureD16];
1012 
1013  if (RegNo > 31 || (hasD16 && RegNo > 15))
1014  return MCDisassembler::Fail;
1015 
1016  unsigned Register = DPRDecoderTable[RegNo];
1017  Inst.addOperand(MCOperand::createReg(Register));
1018  return MCDisassembler::Success;
1019 }
1020 
1021 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1022  uint64_t Address, const void *Decoder) {
1023  if (RegNo > 7)
1024  return MCDisassembler::Fail;
1025  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1026 }
1027 
1028 static DecodeStatus
1029 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1030  uint64_t Address, const void *Decoder) {
1031  if (RegNo > 15)
1032  return MCDisassembler::Fail;
1033  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1034 }
1035 
1036 static const uint16_t QPRDecoderTable[] = {
1037  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1038  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1039  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1040  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1041 };
1042 
1043 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1044  uint64_t Address, const void *Decoder) {
1045  if (RegNo > 31 || (RegNo & 1) != 0)
1046  return MCDisassembler::Fail;
1047  RegNo >>= 1;
1048 
1049  unsigned Register = QPRDecoderTable[RegNo];
1050  Inst.addOperand(MCOperand::createReg(Register));
1051  return MCDisassembler::Success;
1052 }
1053 
1054 static const uint16_t DPairDecoderTable[] = {
1055  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1056  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1057  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1058  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1059  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1060  ARM::Q15
1061 };
1062 
1063 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1064  uint64_t Address, const void *Decoder) {
1065  if (RegNo > 30)
1066  return MCDisassembler::Fail;
1067 
1068  unsigned Register = DPairDecoderTable[RegNo];
1069  Inst.addOperand(MCOperand::createReg(Register));
1070  return MCDisassembler::Success;
1071 }
1072 
1073 static const uint16_t DPairSpacedDecoderTable[] = {
1074  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1075  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1076  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1077  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1078  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1079  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1080  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1081  ARM::D28_D30, ARM::D29_D31
1082 };
1083 
1085  unsigned RegNo,
1086  uint64_t Address,
1087  const void *Decoder) {
1088  if (RegNo > 29)
1089  return MCDisassembler::Fail;
1090 
1091  unsigned Register = DPairSpacedDecoderTable[RegNo];
1092  Inst.addOperand(MCOperand::createReg(Register));
1093  return MCDisassembler::Success;
1094 }
1095 
1096 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1097  uint64_t Address, const void *Decoder) {
1098  if (Val == 0xF) return MCDisassembler::Fail;
1099  // AL predicate is not allowed on Thumb1 branches.
1100  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1101  return MCDisassembler::Fail;
1102  Inst.addOperand(MCOperand::createImm(Val));
1103  if (Val == ARMCC::AL) {
1105  } else
1106  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1107  return MCDisassembler::Success;
1108 }
1109 
1110 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1111  uint64_t Address, const void *Decoder) {
1112  if (Val)
1113  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1114  else
1116  return MCDisassembler::Success;
1117 }
1118 
1119 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1120  uint64_t Address, const void *Decoder) {
1122 
1123  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1124  unsigned type = fieldFromInstruction(Val, 5, 2);
1125  unsigned imm = fieldFromInstruction(Val, 7, 5);
1126 
1127  // Register-immediate
1128  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1129  return MCDisassembler::Fail;
1130 
1131  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1132  switch (type) {
1133  case 0:
1134  Shift = ARM_AM::lsl;
1135  break;
1136  case 1:
1137  Shift = ARM_AM::lsr;
1138  break;
1139  case 2:
1140  Shift = ARM_AM::asr;
1141  break;
1142  case 3:
1143  Shift = ARM_AM::ror;
1144  break;
1145  }
1146 
1147  if (Shift == ARM_AM::ror && imm == 0)
1148  Shift = ARM_AM::rrx;
1149 
1150  unsigned Op = Shift | (imm << 3);
1151  Inst.addOperand(MCOperand::createImm(Op));
1152 
1153  return S;
1154 }
1155 
1156 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1157  uint64_t Address, const void *Decoder) {
1159 
1160  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1161  unsigned type = fieldFromInstruction(Val, 5, 2);
1162  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1163 
1164  // Register-register
1165  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1166  return MCDisassembler::Fail;
1167  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1168  return MCDisassembler::Fail;
1169 
1170  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1171  switch (type) {
1172  case 0:
1173  Shift = ARM_AM::lsl;
1174  break;
1175  case 1:
1176  Shift = ARM_AM::lsr;
1177  break;
1178  case 2:
1179  Shift = ARM_AM::asr;
1180  break;
1181  case 3:
1182  Shift = ARM_AM::ror;
1183  break;
1184  }
1185 
1186  Inst.addOperand(MCOperand::createImm(Shift));
1187 
1188  return S;
1189 }
1190 
1191 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1192  uint64_t Address, const void *Decoder) {
1194 
1195  bool NeedDisjointWriteback = false;
1196  unsigned WritebackReg = 0;
1197  switch (Inst.getOpcode()) {
1198  default:
1199  break;
1200  case ARM::LDMIA_UPD:
1201  case ARM::LDMDB_UPD:
1202  case ARM::LDMIB_UPD:
1203  case ARM::LDMDA_UPD:
1204  case ARM::t2LDMIA_UPD:
1205  case ARM::t2LDMDB_UPD:
1206  case ARM::t2STMIA_UPD:
1207  case ARM::t2STMDB_UPD:
1208  NeedDisjointWriteback = true;
1209  WritebackReg = Inst.getOperand(0).getReg();
1210  break;
1211  }
1212 
1213  // Empty register lists are not allowed.
1214  if (Val == 0) return MCDisassembler::Fail;
1215  for (unsigned i = 0; i < 16; ++i) {
1216  if (Val & (1 << i)) {
1217  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1218  return MCDisassembler::Fail;
1219  // Writeback not allowed if Rn is in the target list.
1220  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1222  }
1223  }
1224 
1225  return S;
1226 }
1227 
1228 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1229  uint64_t Address, const void *Decoder) {
1231 
1232  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1233  unsigned regs = fieldFromInstruction(Val, 0, 8);
1234 
1235  // In case of unpredictable encoding, tweak the operands.
1236  if (regs == 0 || (Vd + regs) > 32) {
1237  regs = Vd + regs > 32 ? 32 - Vd : regs;
1238  regs = std::max( 1u, regs);
1240  }
1241 
1242  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1243  return MCDisassembler::Fail;
1244  for (unsigned i = 0; i < (regs - 1); ++i) {
1245  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1246  return MCDisassembler::Fail;
1247  }
1248 
1249  return S;
1250 }
1251 
1252 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1253  uint64_t Address, const void *Decoder) {
1255 
1256  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1257  unsigned regs = fieldFromInstruction(Val, 1, 7);
1258 
1259  // In case of unpredictable encoding, tweak the operands.
1260  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1261  regs = Vd + regs > 32 ? 32 - Vd : regs;
1262  regs = std::max( 1u, regs);
1263  regs = std::min(16u, regs);
1265  }
1266 
1267  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1268  return MCDisassembler::Fail;
1269  for (unsigned i = 0; i < (regs - 1); ++i) {
1270  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1271  return MCDisassembler::Fail;
1272  }
1273 
1274  return S;
1275 }
1276 
1277 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1278  uint64_t Address, const void *Decoder) {
1279  // This operand encodes a mask of contiguous zeros between a specified MSB
1280  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1281  // the mask of all bits LSB-and-lower, and then xor them to create
1282  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1283  // create the final mask.
1284  unsigned msb = fieldFromInstruction(Val, 5, 5);
1285  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1286 
1288  if (lsb > msb) {
1290  // The check above will cause the warning for the "potentially undefined
1291  // instruction encoding" but we can't build a bad MCOperand value here
1292  // with a lsb > msb or else printing the MCInst will cause a crash.
1293  lsb = msb;
1294  }
1295 
1296  uint32_t msb_mask = 0xFFFFFFFF;
1297  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1298  uint32_t lsb_mask = (1U << lsb) - 1;
1299 
1300  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1301  return S;
1302 }
1303 
1304 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1305  uint64_t Address, const void *Decoder) {
1307 
1308  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1309  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1310  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1311  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1312  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1313  unsigned U = fieldFromInstruction(Insn, 23, 1);
1314 
1315  switch (Inst.getOpcode()) {
1316  case ARM::LDC_OFFSET:
1317  case ARM::LDC_PRE:
1318  case ARM::LDC_POST:
1319  case ARM::LDC_OPTION:
1320  case ARM::LDCL_OFFSET:
1321  case ARM::LDCL_PRE:
1322  case ARM::LDCL_POST:
1323  case ARM::LDCL_OPTION:
1324  case ARM::STC_OFFSET:
1325  case ARM::STC_PRE:
1326  case ARM::STC_POST:
1327  case ARM::STC_OPTION:
1328  case ARM::STCL_OFFSET:
1329  case ARM::STCL_PRE:
1330  case ARM::STCL_POST:
1331  case ARM::STCL_OPTION:
1332  case ARM::t2LDC_OFFSET:
1333  case ARM::t2LDC_PRE:
1334  case ARM::t2LDC_POST:
1335  case ARM::t2LDC_OPTION:
1336  case ARM::t2LDCL_OFFSET:
1337  case ARM::t2LDCL_PRE:
1338  case ARM::t2LDCL_POST:
1339  case ARM::t2LDCL_OPTION:
1340  case ARM::t2STC_OFFSET:
1341  case ARM::t2STC_PRE:
1342  case ARM::t2STC_POST:
1343  case ARM::t2STC_OPTION:
1344  case ARM::t2STCL_OFFSET:
1345  case ARM::t2STCL_PRE:
1346  case ARM::t2STCL_POST:
1347  case ARM::t2STCL_OPTION:
1348  if (coproc == 0xA || coproc == 0xB)
1349  return MCDisassembler::Fail;
1350  break;
1351  default:
1352  break;
1353  }
1354 
1355  const FeatureBitset &featureBits =
1356  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1357  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1358  return MCDisassembler::Fail;
1359 
1360  Inst.addOperand(MCOperand::createImm(coproc));
1361  Inst.addOperand(MCOperand::createImm(CRd));
1362  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1363  return MCDisassembler::Fail;
1364 
1365  switch (Inst.getOpcode()) {
1366  case ARM::t2LDC2_OFFSET:
1367  case ARM::t2LDC2L_OFFSET:
1368  case ARM::t2LDC2_PRE:
1369  case ARM::t2LDC2L_PRE:
1370  case ARM::t2STC2_OFFSET:
1371  case ARM::t2STC2L_OFFSET:
1372  case ARM::t2STC2_PRE:
1373  case ARM::t2STC2L_PRE:
1374  case ARM::LDC2_OFFSET:
1375  case ARM::LDC2L_OFFSET:
1376  case ARM::LDC2_PRE:
1377  case ARM::LDC2L_PRE:
1378  case ARM::STC2_OFFSET:
1379  case ARM::STC2L_OFFSET:
1380  case ARM::STC2_PRE:
1381  case ARM::STC2L_PRE:
1382  case ARM::t2LDC_OFFSET:
1383  case ARM::t2LDCL_OFFSET:
1384  case ARM::t2LDC_PRE:
1385  case ARM::t2LDCL_PRE:
1386  case ARM::t2STC_OFFSET:
1387  case ARM::t2STCL_OFFSET:
1388  case ARM::t2STC_PRE:
1389  case ARM::t2STCL_PRE:
1390  case ARM::LDC_OFFSET:
1391  case ARM::LDCL_OFFSET:
1392  case ARM::LDC_PRE:
1393  case ARM::LDCL_PRE:
1394  case ARM::STC_OFFSET:
1395  case ARM::STCL_OFFSET:
1396  case ARM::STC_PRE:
1397  case ARM::STCL_PRE:
1398  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1399  Inst.addOperand(MCOperand::createImm(imm));
1400  break;
1401  case ARM::t2LDC2_POST:
1402  case ARM::t2LDC2L_POST:
1403  case ARM::t2STC2_POST:
1404  case ARM::t2STC2L_POST:
1405  case ARM::LDC2_POST:
1406  case ARM::LDC2L_POST:
1407  case ARM::STC2_POST:
1408  case ARM::STC2L_POST:
1409  case ARM::t2LDC_POST:
1410  case ARM::t2LDCL_POST:
1411  case ARM::t2STC_POST:
1412  case ARM::t2STCL_POST:
1413  case ARM::LDC_POST:
1414  case ARM::LDCL_POST:
1415  case ARM::STC_POST:
1416  case ARM::STCL_POST:
1417  imm |= U << 8;
1419  default:
1420  // The 'option' variant doesn't encode 'U' in the immediate since
1421  // the immediate is unsigned [0,255].
1422  Inst.addOperand(MCOperand::createImm(imm));
1423  break;
1424  }
1425 
1426  switch (Inst.getOpcode()) {
1427  case ARM::LDC_OFFSET:
1428  case ARM::LDC_PRE:
1429  case ARM::LDC_POST:
1430  case ARM::LDC_OPTION:
1431  case ARM::LDCL_OFFSET:
1432  case ARM::LDCL_PRE:
1433  case ARM::LDCL_POST:
1434  case ARM::LDCL_OPTION:
1435  case ARM::STC_OFFSET:
1436  case ARM::STC_PRE:
1437  case ARM::STC_POST:
1438  case ARM::STC_OPTION:
1439  case ARM::STCL_OFFSET:
1440  case ARM::STCL_PRE:
1441  case ARM::STCL_POST:
1442  case ARM::STCL_OPTION:
1443  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1444  return MCDisassembler::Fail;
1445  break;
1446  default:
1447  break;
1448  }
1449 
1450  return S;
1451 }
1452 
1453 static DecodeStatus
1455  uint64_t Address, const void *Decoder) {
1457 
1458  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1459  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1460  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1461  unsigned imm = fieldFromInstruction(Insn, 0, 12);
1462  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1463  unsigned reg = fieldFromInstruction(Insn, 25, 1);
1464  unsigned P = fieldFromInstruction(Insn, 24, 1);
1465  unsigned W = fieldFromInstruction(Insn, 21, 1);
1466 
1467  // On stores, the writeback operand precedes Rt.
1468  switch (Inst.getOpcode()) {
1469  case ARM::STR_POST_IMM:
1470  case ARM::STR_POST_REG:
1471  case ARM::STRB_POST_IMM:
1472  case ARM::STRB_POST_REG:
1473  case ARM::STRT_POST_REG:
1474  case ARM::STRT_POST_IMM:
1475  case ARM::STRBT_POST_REG:
1476  case ARM::STRBT_POST_IMM:
1477  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1478  return MCDisassembler::Fail;
1479  break;
1480  default:
1481  break;
1482  }
1483 
1484  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1485  return MCDisassembler::Fail;
1486 
1487  // On loads, the writeback operand comes after Rt.
1488  switch (Inst.getOpcode()) {
1489  case ARM::LDR_POST_IMM:
1490  case ARM::LDR_POST_REG:
1491  case ARM::LDRB_POST_IMM:
1492  case ARM::LDRB_POST_REG:
1493  case ARM::LDRBT_POST_REG:
1494  case ARM::LDRBT_POST_IMM:
1495  case ARM::LDRT_POST_REG:
1496  case ARM::LDRT_POST_IMM:
1497  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1498  return MCDisassembler::Fail;
1499  break;
1500  default:
1501  break;
1502  }
1503 
1504  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1505  return MCDisassembler::Fail;
1506 
1508  if (!fieldFromInstruction(Insn, 23, 1))
1509  Op = ARM_AM::sub;
1510 
1511  bool writeback = (P == 0) || (W == 1);
1512  unsigned idx_mode = 0;
1513  if (P && writeback)
1514  idx_mode = ARMII::IndexModePre;
1515  else if (!P && writeback)
1516  idx_mode = ARMII::IndexModePost;
1517 
1518  if (writeback && (Rn == 15 || Rn == Rt))
1519  S = MCDisassembler::SoftFail; // UNPREDICTABLE
1520 
1521  if (reg) {
1522  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1523  return MCDisassembler::Fail;
1525  switch( fieldFromInstruction(Insn, 5, 2)) {
1526  case 0:
1527  Opc = ARM_AM::lsl;
1528  break;
1529  case 1:
1530  Opc = ARM_AM::lsr;
1531  break;
1532  case 2:
1533  Opc = ARM_AM::asr;
1534  break;
1535  case 3:
1536  Opc = ARM_AM::ror;
1537  break;
1538  default:
1539  return MCDisassembler::Fail;
1540  }
1541  unsigned amt = fieldFromInstruction(Insn, 7, 5);
1542  if (Opc == ARM_AM::ror && amt == 0)
1543  Opc = ARM_AM::rrx;
1544  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1545 
1546  Inst.addOperand(MCOperand::createImm(imm));
1547  } else {
1549  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1550  Inst.addOperand(MCOperand::createImm(tmp));
1551  }
1552 
1553  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1554  return MCDisassembler::Fail;
1555 
1556  return S;
1557 }
1558 
1559 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1560  uint64_t Address, const void *Decoder) {
1562 
1563  unsigned Rn = fieldFromInstruction(Val, 13, 4);
1564  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1565  unsigned type = fieldFromInstruction(Val, 5, 2);
1566  unsigned imm = fieldFromInstruction(Val, 7, 5);
1567  unsigned U = fieldFromInstruction(Val, 12, 1);
1568 
1570  switch (type) {
1571  case 0:
1572  ShOp = ARM_AM::lsl;
1573  break;
1574  case 1:
1575  ShOp = ARM_AM::lsr;
1576  break;
1577  case 2:
1578  ShOp = ARM_AM::asr;
1579  break;
1580  case 3:
1581  ShOp = ARM_AM::ror;
1582  break;
1583  }
1584 
1585  if (ShOp == ARM_AM::ror && imm == 0)
1586  ShOp = ARM_AM::rrx;
1587 
1588  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1589  return MCDisassembler::Fail;
1590  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1591  return MCDisassembler::Fail;
1592  unsigned shift;
1593  if (U)
1594  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1595  else
1596  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1597  Inst.addOperand(MCOperand::createImm(shift));
1598 
1599  return S;
1600 }
1601 
1602 static DecodeStatus
1603 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1604  uint64_t Address, const void *Decoder) {
1606 
1607  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1608  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1609  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1610  unsigned type = fieldFromInstruction(Insn, 22, 1);
1611  unsigned imm = fieldFromInstruction(Insn, 8, 4);
1612  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1613  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1614  unsigned W = fieldFromInstruction(Insn, 21, 1);
1615  unsigned P = fieldFromInstruction(Insn, 24, 1);
1616  unsigned Rt2 = Rt + 1;
1617 
1618  bool writeback = (W == 1) | (P == 0);
1619 
1620  // For {LD,ST}RD, Rt must be even, else undefined.
1621  switch (Inst.getOpcode()) {
1622  case ARM::STRD:
1623  case ARM::STRD_PRE:
1624  case ARM::STRD_POST:
1625  case ARM::LDRD:
1626  case ARM::LDRD_PRE:
1627  case ARM::LDRD_POST:
1628  if (Rt & 0x1) S = MCDisassembler::SoftFail;
1629  break;
1630  default:
1631  break;
1632  }
1633  switch (Inst.getOpcode()) {
1634  case ARM::STRD:
1635  case ARM::STRD_PRE:
1636  case ARM::STRD_POST:
1637  if (P == 0 && W == 1)
1639 
1640  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1642  if (type && Rm == 15)
1644  if (Rt2 == 15)
1646  if (!type && fieldFromInstruction(Insn, 8, 4))
1648  break;
1649  case ARM::STRH:
1650  case ARM::STRH_PRE:
1651  case ARM::STRH_POST:
1652  if (Rt == 15)
1654  if (writeback && (Rn == 15 || Rn == Rt))
1656  if (!type && Rm == 15)
1658  break;
1659  case ARM::LDRD:
1660  case ARM::LDRD_PRE:
1661  case ARM::LDRD_POST:
1662  if (type && Rn == 15) {
1663  if (Rt2 == 15)
1665  break;
1666  }
1667  if (P == 0 && W == 1)
1669  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1671  if (!type && writeback && Rn == 15)
1673  if (writeback && (Rn == Rt || Rn == Rt2))
1675  break;
1676  case ARM::LDRH:
1677  case ARM::LDRH_PRE:
1678  case ARM::LDRH_POST:
1679  if (type && Rn == 15) {
1680  if (Rt == 15)
1682  break;
1683  }
1684  if (Rt == 15)
1686  if (!type && Rm == 15)
1688  if (!type && writeback && (Rn == 15 || Rn == Rt))
1690  break;
1691  case ARM::LDRSH:
1692  case ARM::LDRSH_PRE:
1693  case ARM::LDRSH_POST:
1694  case ARM::LDRSB:
1695  case ARM::LDRSB_PRE:
1696  case ARM::LDRSB_POST:
1697  if (type && Rn == 15) {
1698  if (Rt == 15)
1700  break;
1701  }
1702  if (type && (Rt == 15 || (writeback && Rn == Rt)))
1704  if (!type && (Rt == 15 || Rm == 15))
1706  if (!type && writeback && (Rn == 15 || Rn == Rt))
1708  break;
1709  default:
1710  break;
1711  }
1712 
1713  if (writeback) { // Writeback
1714  if (P)
1715  U |= ARMII::IndexModePre << 9;
1716  else
1717  U |= ARMII::IndexModePost << 9;
1718 
1719  // On stores, the writeback operand precedes Rt.
1720  switch (Inst.getOpcode()) {
1721  case ARM::STRD:
1722  case ARM::STRD_PRE:
1723  case ARM::STRD_POST:
1724  case ARM::STRH:
1725  case ARM::STRH_PRE:
1726  case ARM::STRH_POST:
1727  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1728  return MCDisassembler::Fail;
1729  break;
1730  default:
1731  break;
1732  }
1733  }
1734 
1735  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1736  return MCDisassembler::Fail;
1737  switch (Inst.getOpcode()) {
1738  case ARM::STRD:
1739  case ARM::STRD_PRE:
1740  case ARM::STRD_POST:
1741  case ARM::LDRD:
1742  case ARM::LDRD_PRE:
1743  case ARM::LDRD_POST:
1744  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1745  return MCDisassembler::Fail;
1746  break;
1747  default:
1748  break;
1749  }
1750 
1751  if (writeback) {
1752  // On loads, the writeback operand comes after Rt.
1753  switch (Inst.getOpcode()) {
1754  case ARM::LDRD:
1755  case ARM::LDRD_PRE:
1756  case ARM::LDRD_POST:
1757  case ARM::LDRH:
1758  case ARM::LDRH_PRE:
1759  case ARM::LDRH_POST:
1760  case ARM::LDRSH:
1761  case ARM::LDRSH_PRE:
1762  case ARM::LDRSH_POST:
1763  case ARM::LDRSB:
1764  case ARM::LDRSB_PRE:
1765  case ARM::LDRSB_POST:
1766  case ARM::LDRHTr:
1767  case ARM::LDRSBTr:
1768  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1769  return MCDisassembler::Fail;
1770  break;
1771  default:
1772  break;
1773  }
1774  }
1775 
1776  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1777  return MCDisassembler::Fail;
1778 
1779  if (type) {
1781  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1782  } else {
1783  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1784  return MCDisassembler::Fail;
1786  }
1787 
1788  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1789  return MCDisassembler::Fail;
1790 
1791  return S;
1792 }
1793 
1794 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1795  uint64_t Address, const void *Decoder) {
1797 
1798  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1799  unsigned mode = fieldFromInstruction(Insn, 23, 2);
1800 
1801  switch (mode) {
1802  case 0:
1803  mode = ARM_AM::da;
1804  break;
1805  case 1:
1806  mode = ARM_AM::ia;
1807  break;
1808  case 2:
1809  mode = ARM_AM::db;
1810  break;
1811  case 3:
1812  mode = ARM_AM::ib;
1813  break;
1814  }
1815 
1816  Inst.addOperand(MCOperand::createImm(mode));
1817  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1818  return MCDisassembler::Fail;
1819 
1820  return S;
1821 }
1822 
1823 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1824  uint64_t Address, const void *Decoder) {
1826 
1827  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1828  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1829  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1830  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1831 
1832  if (pred == 0xF)
1833  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1834 
1835  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1836  return MCDisassembler::Fail;
1837  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1838  return MCDisassembler::Fail;
1839  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1840  return MCDisassembler::Fail;
1841  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1842  return MCDisassembler::Fail;
1843  return S;
1844 }
1845 
1847  unsigned Insn,
1848  uint64_t Address, const void *Decoder) {
1850 
1851  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1852  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1853  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1854 
1855  if (pred == 0xF) {
1856  // Ambiguous with RFE and SRS
1857  switch (Inst.getOpcode()) {
1858  case ARM::LDMDA:
1859  Inst.setOpcode(ARM::RFEDA);
1860  break;
1861  case ARM::LDMDA_UPD:
1862  Inst.setOpcode(ARM::RFEDA_UPD);
1863  break;
1864  case ARM::LDMDB:
1865  Inst.setOpcode(ARM::RFEDB);
1866  break;
1867  case ARM::LDMDB_UPD:
1868  Inst.setOpcode(ARM::RFEDB_UPD);
1869  break;
1870  case ARM::LDMIA:
1871  Inst.setOpcode(ARM::RFEIA);
1872  break;
1873  case ARM::LDMIA_UPD:
1874  Inst.setOpcode(ARM::RFEIA_UPD);
1875  break;
1876  case ARM::LDMIB:
1877  Inst.setOpcode(ARM::RFEIB);
1878  break;
1879  case ARM::LDMIB_UPD:
1880  Inst.setOpcode(ARM::RFEIB_UPD);
1881  break;
1882  case ARM::STMDA:
1883  Inst.setOpcode(ARM::SRSDA);
1884  break;
1885  case ARM::STMDA_UPD:
1886  Inst.setOpcode(ARM::SRSDA_UPD);
1887  break;
1888  case ARM::STMDB:
1889  Inst.setOpcode(ARM::SRSDB);
1890  break;
1891  case ARM::STMDB_UPD:
1892  Inst.setOpcode(ARM::SRSDB_UPD);
1893  break;
1894  case ARM::STMIA:
1895  Inst.setOpcode(ARM::SRSIA);
1896  break;
1897  case ARM::STMIA_UPD:
1898  Inst.setOpcode(ARM::SRSIA_UPD);
1899  break;
1900  case ARM::STMIB:
1901  Inst.setOpcode(ARM::SRSIB);
1902  break;
1903  case ARM::STMIB_UPD:
1904  Inst.setOpcode(ARM::SRSIB_UPD);
1905  break;
1906  default:
1907  return MCDisassembler::Fail;
1908  }
1909 
1910  // For stores (which become SRS's, the only operand is the mode.
1911  if (fieldFromInstruction(Insn, 20, 1) == 0) {
1912  // Check SRS encoding constraints
1913  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1914  fieldFromInstruction(Insn, 20, 1) == 0))
1915  return MCDisassembler::Fail;
1916 
1917  Inst.addOperand(
1918  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1919  return S;
1920  }
1921 
1922  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1923  }
1924 
1925  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1926  return MCDisassembler::Fail;
1927  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1928  return MCDisassembler::Fail; // Tied
1929  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1930  return MCDisassembler::Fail;
1931  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1932  return MCDisassembler::Fail;
1933 
1934  return S;
1935 }
1936 
1937 // Check for UNPREDICTABLE predicated ESB instruction
1938 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1939  uint64_t Address, const void *Decoder) {
1940  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1941  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1942  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1943  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1944 
1946 
1947  Inst.addOperand(MCOperand::createImm(imm8));
1948 
1949  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1950  return MCDisassembler::Fail;
1951 
1952  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1953  // so all predicates should be allowed.
1954  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1956 
1957  return S;
1958 }
1959 
1960 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1961  uint64_t Address, const void *Decoder) {
1962  unsigned imod = fieldFromInstruction(Insn, 18, 2);
1963  unsigned M = fieldFromInstruction(Insn, 17, 1);
1964  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1965  unsigned mode = fieldFromInstruction(Insn, 0, 5);
1966 
1968 
1969  // This decoder is called from multiple location that do not check
1970  // the full encoding is valid before they do.
1971  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1972  fieldFromInstruction(Insn, 16, 1) != 0 ||
1973  fieldFromInstruction(Insn, 20, 8) != 0x10)
1974  return MCDisassembler::Fail;
1975 
1976  // imod == '01' --> UNPREDICTABLE
1977  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1978  // return failure here. The '01' imod value is unprintable, so there's
1979  // nothing useful we could do even if we returned UNPREDICTABLE.
1980 
1981  if (imod == 1) return MCDisassembler::Fail;
1982 
1983  if (imod && M) {
1984  Inst.setOpcode(ARM::CPS3p);
1985  Inst.addOperand(MCOperand::createImm(imod));
1986  Inst.addOperand(MCOperand::createImm(iflags));
1987  Inst.addOperand(MCOperand::createImm(mode));
1988  } else if (imod && !M) {
1989  Inst.setOpcode(ARM::CPS2p);
1990  Inst.addOperand(MCOperand::createImm(imod));
1991  Inst.addOperand(MCOperand::createImm(iflags));
1992  if (mode) S = MCDisassembler::SoftFail;
1993  } else if (!imod && M) {
1994  Inst.setOpcode(ARM::CPS1p);
1995  Inst.addOperand(MCOperand::createImm(mode));
1996  if (iflags) S = MCDisassembler::SoftFail;
1997  } else {
1998  // imod == '00' && M == '0' --> UNPREDICTABLE
1999  Inst.setOpcode(ARM::CPS1p);
2000  Inst.addOperand(MCOperand::createImm(mode));
2002  }
2003 
2004  return S;
2005 }
2006 
2007 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2008  uint64_t Address, const void *Decoder) {
2009  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2010  unsigned M = fieldFromInstruction(Insn, 8, 1);
2011  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2012  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2013 
2015 
2016  // imod == '01' --> UNPREDICTABLE
2017  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2018  // return failure here. The '01' imod value is unprintable, so there's
2019  // nothing useful we could do even if we returned UNPREDICTABLE.
2020 
2021  if (imod == 1) return MCDisassembler::Fail;
2022 
2023  if (imod && M) {
2024  Inst.setOpcode(ARM::t2CPS3p);
2025  Inst.addOperand(MCOperand::createImm(imod));
2026  Inst.addOperand(MCOperand::createImm(iflags));
2027  Inst.addOperand(MCOperand::createImm(mode));
2028  } else if (imod && !M) {
2029  Inst.setOpcode(ARM::t2CPS2p);
2030  Inst.addOperand(MCOperand::createImm(imod));
2031  Inst.addOperand(MCOperand::createImm(iflags));
2032  if (mode) S = MCDisassembler::SoftFail;
2033  } else if (!imod && M) {
2034  Inst.setOpcode(ARM::t2CPS1p);
2035  Inst.addOperand(MCOperand::createImm(mode));
2036  if (iflags) S = MCDisassembler::SoftFail;
2037  } else {
2038  // imod == '00' && M == '0' --> this is a HINT instruction
2039  int imm = fieldFromInstruction(Insn, 0, 8);
2040  // HINT are defined only for immediate in [0..4]
2041  if(imm > 4) return MCDisassembler::Fail;
2042  Inst.setOpcode(ARM::t2HINT);
2043  Inst.addOperand(MCOperand::createImm(imm));
2044  }
2045 
2046  return S;
2047 }
2048 
2049 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2050  uint64_t Address, const void *Decoder) {
2052 
2053  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2054  unsigned imm = 0;
2055 
2056  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2057  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2058  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2059  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2060 
2061  if (Inst.getOpcode() == ARM::t2MOVTi16)
2062  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2063  return MCDisassembler::Fail;
2064  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2065  return MCDisassembler::Fail;
2066 
2067  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2068  Inst.addOperand(MCOperand::createImm(imm));
2069 
2070  return S;
2071 }
2072 
2073 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2074  uint64_t Address, const void *Decoder) {
2076 
2077  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2078  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2079  unsigned imm = 0;
2080 
2081  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2082  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2083 
2084  if (Inst.getOpcode() == ARM::MOVTi16)
2085  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2086  return MCDisassembler::Fail;
2087 
2088  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2089  return MCDisassembler::Fail;
2090 
2091  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2092  Inst.addOperand(MCOperand::createImm(imm));
2093 
2094  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2095  return MCDisassembler::Fail;
2096 
2097  return S;
2098 }
2099 
2100 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2101  uint64_t Address, const void *Decoder) {
2103 
2104  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2105  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2106  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2107  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2108  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2109 
2110  if (pred == 0xF)
2111  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2112 
2113  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2114  return MCDisassembler::Fail;
2115  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2116  return MCDisassembler::Fail;
2117  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2118  return MCDisassembler::Fail;
2119  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2120  return MCDisassembler::Fail;
2121 
2122  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2123  return MCDisassembler::Fail;
2124 
2125  return S;
2126 }
2127 
2128 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2129  uint64_t Address, const void *Decoder) {
2131 
2132  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2133  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2134  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2135 
2136  if (Pred == 0xF)
2137  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2138 
2139  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2140  return MCDisassembler::Fail;
2141  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2142  return MCDisassembler::Fail;
2143  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2144  return MCDisassembler::Fail;
2145 
2146  return S;
2147 }
2148 
2149 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2150  uint64_t Address, const void *Decoder) {
2152 
2153  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2154 
2155  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2156  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2157 
2158  if (!FeatureBits[ARM::HasV8_1aOps] ||
2159  !FeatureBits[ARM::HasV8Ops])
2160  return MCDisassembler::Fail;
2161 
2162  // Decoder can be called from DecodeTST, which does not check the full
2163  // encoding is valid.
2164  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2165  fieldFromInstruction(Insn, 4,4) != 0)
2166  return MCDisassembler::Fail;
2167  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2168  fieldFromInstruction(Insn, 0,4) != 0)
2170 
2171  Inst.setOpcode(ARM::SETPAN);
2172  Inst.addOperand(MCOperand::createImm(Imm));
2173 
2174  return S;
2175 }
2176 
2178  uint64_t Address, const void *Decoder) {
2180 
2181  unsigned add = fieldFromInstruction(Val, 12, 1);
2182  unsigned imm = fieldFromInstruction(Val, 0, 12);
2183  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2184 
2185  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2186  return MCDisassembler::Fail;
2187 
2188  if (!add) imm *= -1;
2189  if (imm == 0 && !add) imm = INT32_MIN;
2190  Inst.addOperand(MCOperand::createImm(imm));
2191  if (Rn == 15)
2192  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2193 
2194  return S;
2195 }
2196 
2197 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2198  uint64_t Address, const void *Decoder) {
2200 
2201  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2202  // U == 1 to add imm, 0 to subtract it.
2203  unsigned U = fieldFromInstruction(Val, 8, 1);
2204  unsigned imm = fieldFromInstruction(Val, 0, 8);
2205 
2206  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2207  return MCDisassembler::Fail;
2208 
2209  if (U)
2211  else
2213 
2214  return S;
2215 }
2216 
2218  uint64_t Address, const void *Decoder) {
2220 
2221  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2222  // U == 1 to add imm, 0 to subtract it.
2223  unsigned U = fieldFromInstruction(Val, 8, 1);
2224  unsigned imm = fieldFromInstruction(Val, 0, 8);
2225 
2226  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2227  return MCDisassembler::Fail;
2228 
2229  if (U)
2231  else
2233 
2234  return S;
2235 }
2236 
2237 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2238  uint64_t Address, const void *Decoder) {
2239  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2240 }
2241 
2242 static DecodeStatus
2243 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2244  uint64_t Address, const void *Decoder) {
2246 
2247  // Note the J1 and J2 values are from the encoded instruction. So here
2248  // change them to I1 and I2 values via as documented:
2249  // I1 = NOT(J1 EOR S);
2250  // I2 = NOT(J2 EOR S);
2251  // and build the imm32 with one trailing zero as documented:
2252  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2253  unsigned S = fieldFromInstruction(Insn, 26, 1);
2254  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2255  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2256  unsigned I1 = !(J1 ^ S);
2257  unsigned I2 = !(J2 ^ S);
2258  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2259  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2260  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2261  int imm32 = SignExtend32<25>(tmp << 1);
2262  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2263  true, 4, Inst, Decoder))
2264  Inst.addOperand(MCOperand::createImm(imm32));
2265 
2266  return Status;
2267 }
2268 
2269 static DecodeStatus
2270 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2271  uint64_t Address, const void *Decoder) {
2273 
2274  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2275  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2276 
2277  if (pred == 0xF) {
2278  Inst.setOpcode(ARM::BLXi);
2279  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2280  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2281  true, 4, Inst, Decoder))
2282  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2283  return S;
2284  }
2285 
2286  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2287  true, 4, Inst, Decoder))
2288  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2289  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2290  return MCDisassembler::Fail;
2291 
2292  return S;
2293 }
2294 
2295 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2296  uint64_t Address, const void *Decoder) {
2298 
2299  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2300  unsigned align = fieldFromInstruction(Val, 4, 2);
2301 
2302  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2303  return MCDisassembler::Fail;
2304  if (!align)
2306  else
2307  Inst.addOperand(MCOperand::createImm(4 << align));
2308 
2309  return S;
2310 }
2311 
2312 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2313  uint64_t Address, const void *Decoder) {
2315 
2316  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2317  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2318  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2319  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2320  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2321  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2322 
2323  // First output register
2324  switch (Inst.getOpcode()) {
2325  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2326  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2327  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2328  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2329  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2330  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2331  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2332  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2333  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2334  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2335  return MCDisassembler::Fail;
2336  break;
2337  case ARM::VLD2b16:
2338  case ARM::VLD2b32:
2339  case ARM::VLD2b8:
2340  case ARM::VLD2b16wb_fixed:
2341  case ARM::VLD2b16wb_register:
2342  case ARM::VLD2b32wb_fixed:
2343  case ARM::VLD2b32wb_register:
2344  case ARM::VLD2b8wb_fixed:
2345  case ARM::VLD2b8wb_register:
2346  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2347  return MCDisassembler::Fail;
2348  break;
2349  default:
2350  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2351  return MCDisassembler::Fail;
2352  }
2353 
2354  // Second output register
2355  switch (Inst.getOpcode()) {
2356  case ARM::VLD3d8:
2357  case ARM::VLD3d16:
2358  case ARM::VLD3d32:
2359  case ARM::VLD3d8_UPD:
2360  case ARM::VLD3d16_UPD:
2361  case ARM::VLD3d32_UPD:
2362  case ARM::VLD4d8:
2363  case ARM::VLD4d16:
2364  case ARM::VLD4d32:
2365  case ARM::VLD4d8_UPD:
2366  case ARM::VLD4d16_UPD:
2367  case ARM::VLD4d32_UPD:
2368  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2369  return MCDisassembler::Fail;
2370  break;
2371  case ARM::VLD3q8:
2372  case ARM::VLD3q16:
2373  case ARM::VLD3q32:
2374  case ARM::VLD3q8_UPD:
2375  case ARM::VLD3q16_UPD:
2376  case ARM::VLD3q32_UPD:
2377  case ARM::VLD4q8:
2378  case ARM::VLD4q16:
2379  case ARM::VLD4q32:
2380  case ARM::VLD4q8_UPD:
2381  case ARM::VLD4q16_UPD:
2382  case ARM::VLD4q32_UPD:
2383  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2384  return MCDisassembler::Fail;
2385  default:
2386  break;
2387  }
2388 
2389  // Third output register
2390  switch(Inst.getOpcode()) {
2391  case ARM::VLD3d8:
2392  case ARM::VLD3d16:
2393  case ARM::VLD3d32:
2394  case ARM::VLD3d8_UPD:
2395  case ARM::VLD3d16_UPD:
2396  case ARM::VLD3d32_UPD:
2397  case ARM::VLD4d8:
2398  case ARM::VLD4d16:
2399  case ARM::VLD4d32:
2400  case ARM::VLD4d8_UPD:
2401  case ARM::VLD4d16_UPD:
2402  case ARM::VLD4d32_UPD:
2403  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2404  return MCDisassembler::Fail;
2405  break;
2406  case ARM::VLD3q8:
2407  case ARM::VLD3q16:
2408  case ARM::VLD3q32:
2409  case ARM::VLD3q8_UPD:
2410  case ARM::VLD3q16_UPD:
2411  case ARM::VLD3q32_UPD:
2412  case ARM::VLD4q8:
2413  case ARM::VLD4q16:
2414  case ARM::VLD4q32:
2415  case ARM::VLD4q8_UPD:
2416  case ARM::VLD4q16_UPD:
2417  case ARM::VLD4q32_UPD:
2418  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2419  return MCDisassembler::Fail;
2420  break;
2421  default:
2422  break;
2423  }
2424 
2425  // Fourth output register
2426  switch (Inst.getOpcode()) {
2427  case ARM::VLD4d8:
2428  case ARM::VLD4d16:
2429  case ARM::VLD4d32:
2430  case ARM::VLD4d8_UPD:
2431  case ARM::VLD4d16_UPD:
2432  case ARM::VLD4d32_UPD:
2433  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2434  return MCDisassembler::Fail;
2435  break;
2436  case ARM::VLD4q8:
2437  case ARM::VLD4q16:
2438  case ARM::VLD4q32:
2439  case ARM::VLD4q8_UPD:
2440  case ARM::VLD4q16_UPD:
2441  case ARM::VLD4q32_UPD:
2442  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2443  return MCDisassembler::Fail;
2444  break;
2445  default:
2446  break;
2447  }
2448 
2449  // Writeback operand
2450  switch (Inst.getOpcode()) {
2451  case ARM::VLD1d8wb_fixed:
2452  case ARM::VLD1d16wb_fixed:
2453  case ARM::VLD1d32wb_fixed:
2454  case ARM::VLD1d64wb_fixed:
2455  case ARM::VLD1d8wb_register:
2456  case ARM::VLD1d16wb_register:
2457  case ARM::VLD1d32wb_register:
2458  case ARM::VLD1d64wb_register:
2459  case ARM::VLD1q8wb_fixed:
2460  case ARM::VLD1q16wb_fixed:
2461  case ARM::VLD1q32wb_fixed:
2462  case ARM::VLD1q64wb_fixed:
2463  case ARM::VLD1q8wb_register:
2464  case ARM::VLD1q16wb_register:
2465  case ARM::VLD1q32wb_register:
2466  case ARM::VLD1q64wb_register:
2467  case ARM::VLD1d8Twb_fixed:
2468  case ARM::VLD1d8Twb_register:
2469  case ARM::VLD1d16Twb_fixed:
2470  case ARM::VLD1d16Twb_register:
2471  case ARM::VLD1d32Twb_fixed:
2472  case ARM::VLD1d32Twb_register:
2473  case ARM::VLD1d64Twb_fixed:
2474  case ARM::VLD1d64Twb_register:
2475  case ARM::VLD1d8Qwb_fixed:
2476  case ARM::VLD1d8Qwb_register:
2477  case ARM::VLD1d16Qwb_fixed:
2478  case ARM::VLD1d16Qwb_register:
2479  case ARM::VLD1d32Qwb_fixed:
2480  case ARM::VLD1d32Qwb_register:
2481  case ARM::VLD1d64Qwb_fixed:
2482  case ARM::VLD1d64Qwb_register:
2483  case ARM::VLD2d8wb_fixed:
2484  case ARM::VLD2d16wb_fixed:
2485  case ARM::VLD2d32wb_fixed:
2486  case ARM::VLD2q8wb_fixed:
2487  case ARM::VLD2q16wb_fixed:
2488  case ARM::VLD2q32wb_fixed:
2489  case ARM::VLD2d8wb_register:
2490  case ARM::VLD2d16wb_register:
2491  case ARM::VLD2d32wb_register:
2492  case ARM::VLD2q8wb_register:
2493  case ARM::VLD2q16wb_register:
2494  case ARM::VLD2q32wb_register:
2495  case ARM::VLD2b8wb_fixed:
2496  case ARM::VLD2b16wb_fixed:
2497  case ARM::VLD2b32wb_fixed:
2498  case ARM::VLD2b8wb_register:
2499  case ARM::VLD2b16wb_register:
2500  case ARM::VLD2b32wb_register:
2502  break;
2503  case ARM::VLD3d8_UPD:
2504  case ARM::VLD3d16_UPD:
2505  case ARM::VLD3d32_UPD:
2506  case ARM::VLD3q8_UPD:
2507  case ARM::VLD3q16_UPD:
2508  case ARM::VLD3q32_UPD:
2509  case ARM::VLD4d8_UPD:
2510  case ARM::VLD4d16_UPD:
2511  case ARM::VLD4d32_UPD:
2512  case ARM::VLD4q8_UPD:
2513  case ARM::VLD4q16_UPD:
2514  case ARM::VLD4q32_UPD:
2515  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2516  return MCDisassembler::Fail;
2517  break;
2518  default:
2519  break;
2520  }
2521 
2522  // AddrMode6 Base (register+alignment)
2523  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2524  return MCDisassembler::Fail;
2525 
2526  // AddrMode6 Offset (register)
2527  switch (Inst.getOpcode()) {
2528  default:
2529  // The below have been updated to have explicit am6offset split
2530  // between fixed and register offset. For those instructions not
2531  // yet updated, we need to add an additional reg0 operand for the
2532  // fixed variant.
2533  //
2534  // The fixed offset encodes as Rm == 0xd, so we check for that.
2535  if (Rm == 0xd) {
2537  break;
2538  }
2539  // Fall through to handle the register offset variant.
2541  case ARM::VLD1d8wb_fixed:
2542  case ARM::VLD1d16wb_fixed:
2543  case ARM::VLD1d32wb_fixed:
2544  case ARM::VLD1d64wb_fixed:
2545  case ARM::VLD1d8Twb_fixed:
2546  case ARM::VLD1d16Twb_fixed:
2547  case ARM::VLD1d32Twb_fixed:
2548  case ARM::VLD1d64Twb_fixed:
2549  case ARM::VLD1d8Qwb_fixed:
2550  case ARM::VLD1d16Qwb_fixed:
2551  case ARM::VLD1d32Qwb_fixed:
2552  case ARM::VLD1d64Qwb_fixed:
2553  case ARM::VLD1d8wb_register:
2554  case ARM::VLD1d16wb_register:
2555  case ARM::VLD1d32wb_register:
2556  case ARM::VLD1d64wb_register:
2557  case ARM::VLD1q8wb_fixed:
2558  case ARM::VLD1q16wb_fixed:
2559  case ARM::VLD1q32wb_fixed:
2560  case ARM::VLD1q64wb_fixed:
2561  case ARM::VLD1q8wb_register:
2562  case ARM::VLD1q16wb_register:
2563  case ARM::VLD1q32wb_register:
2564  case ARM::VLD1q64wb_register:
2565  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2566  // variant encodes Rm == 0xf. Anything else is a register offset post-
2567  // increment and we need to add the register operand to the instruction.
2568  if (Rm != 0xD && Rm != 0xF &&
2569  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2570  return MCDisassembler::Fail;
2571  break;
2572  case ARM::VLD2d8wb_fixed:
2573  case ARM::VLD2d16wb_fixed:
2574  case ARM::VLD2d32wb_fixed:
2575  case ARM::VLD2b8wb_fixed:
2576  case ARM::VLD2b16wb_fixed:
2577  case ARM::VLD2b32wb_fixed:
2578  case ARM::VLD2q8wb_fixed:
2579  case ARM::VLD2q16wb_fixed:
2580  case ARM::VLD2q32wb_fixed:
2581  break;
2582  }
2583 
2584  return S;
2585 }
2586 
2587 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2588  uint64_t Address, const void *Decoder) {
2589  unsigned type = fieldFromInstruction(Insn, 8, 4);
2590  unsigned align = fieldFromInstruction(Insn, 4, 2);
2591  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2592  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2593  if (type == 10 && align == 3) return MCDisassembler::Fail;
2594 
2595  unsigned load = fieldFromInstruction(Insn, 21, 1);
2596  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2597  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2598 }
2599 
2600 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2601  uint64_t Address, const void *Decoder) {
2602  unsigned size = fieldFromInstruction(Insn, 6, 2);
2603  if (size == 3) return MCDisassembler::Fail;
2604 
2605  unsigned type = fieldFromInstruction(Insn, 8, 4);
2606  unsigned align = fieldFromInstruction(Insn, 4, 2);
2607  if (type == 8 && align == 3) return MCDisassembler::Fail;
2608  if (type == 9 && align == 3) return MCDisassembler::Fail;
2609 
2610  unsigned load = fieldFromInstruction(Insn, 21, 1);
2611  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2612  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2613 }
2614 
2615 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2616  uint64_t Address, const void *Decoder) {
2617  unsigned size = fieldFromInstruction(Insn, 6, 2);
2618  if (size == 3) return MCDisassembler::Fail;
2619 
2620  unsigned align = fieldFromInstruction(Insn, 4, 2);
2621  if (align & 2) return MCDisassembler::Fail;
2622 
2623  unsigned load = fieldFromInstruction(Insn, 21, 1);
2624  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2625  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2626 }
2627 
2628 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2629  uint64_t Address, const void *Decoder) {
2630  unsigned size = fieldFromInstruction(Insn, 6, 2);
2631  if (size == 3) return MCDisassembler::Fail;
2632 
2633  unsigned load = fieldFromInstruction(Insn, 21, 1);
2634  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2635  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2636 }
2637 
2638 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2639  uint64_t Address, const void *Decoder) {
2641 
2642  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2643  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2644  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2645  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2646  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2647  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2648 
2649  // Writeback Operand
2650  switch (Inst.getOpcode()) {
2651  case ARM::VST1d8wb_fixed:
2652  case ARM::VST1d16wb_fixed:
2653  case ARM::VST1d32wb_fixed:
2654  case ARM::VST1d64wb_fixed:
2655  case ARM::VST1d8wb_register:
2656  case ARM::VST1d16wb_register:
2657  case ARM::VST1d32wb_register:
2658  case ARM::VST1d64wb_register:
2659  case ARM::VST1q8wb_fixed:
2660  case ARM::VST1q16wb_fixed:
2661  case ARM::VST1q32wb_fixed:
2662  case ARM::VST1q64wb_fixed:
2663  case ARM::VST1q8wb_register:
2664  case ARM::VST1q16wb_register:
2665  case ARM::VST1q32wb_register:
2666  case ARM::VST1q64wb_register:
2667  case ARM::VST1d8Twb_fixed:
2668  case ARM::VST1d16Twb_fixed:
2669  case ARM::VST1d32Twb_fixed:
2670  case ARM::VST1d64Twb_fixed:
2671  case ARM::VST1d8Twb_register:
2672  case ARM::VST1d16Twb_register:
2673  case ARM::VST1d32Twb_register:
2674  case ARM::VST1d64Twb_register:
2675  case ARM::VST1d8Qwb_fixed:
2676  case ARM::VST1d16Qwb_fixed:
2677  case ARM::VST1d32Qwb_fixed:
2678  case ARM::VST1d64Qwb_fixed:
2679  case ARM::VST1d8Qwb_register:
2680  case ARM::VST1d16Qwb_register:
2681  case ARM::VST1d32Qwb_register:
2682  case ARM::VST1d64Qwb_register:
2683  case ARM::VST2d8wb_fixed:
2684  case ARM::VST2d16wb_fixed:
2685  case ARM::VST2d32wb_fixed:
2686  case ARM::VST2d8wb_register:
2687  case ARM::VST2d16wb_register:
2688  case ARM::VST2d32wb_register:
2689  case ARM::VST2q8wb_fixed:
2690  case ARM::VST2q16wb_fixed:
2691  case ARM::VST2q32wb_fixed:
2692  case ARM::VST2q8wb_register:
2693  case ARM::VST2q16wb_register:
2694  case ARM::VST2q32wb_register:
2695  case ARM::VST2b8wb_fixed:
2696  case ARM::VST2b16wb_fixed:
2697  case ARM::VST2b32wb_fixed:
2698  case ARM::VST2b8wb_register:
2699  case ARM::VST2b16wb_register:
2700  case ARM::VST2b32wb_register:
2701  if (Rm == 0xF)
2702  return MCDisassembler::Fail;
2704  break;
2705  case ARM::VST3d8_UPD:
2706  case ARM::VST3d16_UPD:
2707  case ARM::VST3d32_UPD:
2708  case ARM::VST3q8_UPD:
2709  case ARM::VST3q16_UPD:
2710  case ARM::VST3q32_UPD:
2711  case ARM::VST4d8_UPD:
2712  case ARM::VST4d16_UPD:
2713  case ARM::VST4d32_UPD:
2714  case ARM::VST4q8_UPD:
2715  case ARM::VST4q16_UPD:
2716  case ARM::VST4q32_UPD:
2717  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2718  return MCDisassembler::Fail;
2719  break;
2720  default:
2721  break;
2722  }
2723 
2724  // AddrMode6 Base (register+alignment)
2725  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2726  return MCDisassembler::Fail;
2727 
2728  // AddrMode6 Offset (register)
2729  switch (Inst.getOpcode()) {
2730  default:
2731  if (Rm == 0xD)
2733  else if (Rm != 0xF) {
2734  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2735  return MCDisassembler::Fail;
2736  }
2737  break;
2738  case ARM::VST1d8wb_fixed:
2739  case ARM::VST1d16wb_fixed:
2740  case ARM::VST1d32wb_fixed:
2741  case ARM::VST1d64wb_fixed:
2742  case ARM::VST1q8wb_fixed:
2743  case ARM::VST1q16wb_fixed:
2744  case ARM::VST1q32wb_fixed:
2745  case ARM::VST1q64wb_fixed:
2746  case ARM::VST1d8Twb_fixed:
2747  case ARM::VST1d16Twb_fixed:
2748  case ARM::VST1d32Twb_fixed:
2749  case ARM::VST1d64Twb_fixed:
2750  case ARM::VST1d8Qwb_fixed:
2751  case ARM::VST1d16Qwb_fixed:
2752  case ARM::VST1d32Qwb_fixed:
2753  case ARM::VST1d64Qwb_fixed:
2754  case ARM::VST2d8wb_fixed:
2755  case ARM::VST2d16wb_fixed:
2756  case ARM::VST2d32wb_fixed:
2757  case ARM::VST2q8wb_fixed:
2758  case ARM::VST2q16wb_fixed:
2759  case ARM::VST2q32wb_fixed:
2760  case ARM::VST2b8wb_fixed:
2761  case ARM::VST2b16wb_fixed:
2762  case ARM::VST2b32wb_fixed:
2763  break;
2764  }
2765 
2766  // First input register
2767  switch (Inst.getOpcode()) {
2768  case ARM::VST1q16:
2769  case ARM::VST1q32:
2770  case ARM::VST1q64:
2771  case ARM::VST1q8:
2772  case ARM::VST1q16wb_fixed:
2773  case ARM::VST1q16wb_register:
2774  case ARM::VST1q32wb_fixed:
2775  case ARM::VST1q32wb_register:
2776  case ARM::VST1q64wb_fixed:
2777  case ARM::VST1q64wb_register:
2778  case ARM::VST1q8wb_fixed:
2779  case ARM::VST1q8wb_register:
2780  case ARM::VST2d16:
2781  case ARM::VST2d32:
2782  case ARM::VST2d8:
2783  case ARM::VST2d16wb_fixed:
2784  case ARM::VST2d16wb_register:
2785  case ARM::VST2d32wb_fixed:
2786  case ARM::VST2d32wb_register:
2787  case ARM::VST2d8wb_fixed:
2788  case ARM::VST2d8wb_register:
2789  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2790  return MCDisassembler::Fail;
2791  break;
2792  case ARM::VST2b16:
2793  case ARM::VST2b32:
2794  case ARM::VST2b8:
2795  case ARM::VST2b16wb_fixed:
2796  case ARM::VST2b16wb_register:
2797  case ARM::VST2b32wb_fixed:
2798  case ARM::VST2b32wb_register:
2799  case ARM::VST2b8wb_fixed:
2800  case ARM::VST2b8wb_register:
2801  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2802  return MCDisassembler::Fail;
2803  break;
2804  default:
2805  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2806  return MCDisassembler::Fail;
2807  }
2808 
2809  // Second input register
2810  switch (Inst.getOpcode()) {
2811  case ARM::VST3d8:
2812  case ARM::VST3d16:
2813  case ARM::VST3d32:
2814  case ARM::VST3d8_UPD:
2815  case ARM::VST3d16_UPD:
2816  case ARM::VST3d32_UPD:
2817  case ARM::VST4d8:
2818  case ARM::VST4d16:
2819  case ARM::VST4d32:
2820  case ARM::VST4d8_UPD:
2821  case ARM::VST4d16_UPD:
2822  case ARM::VST4d32_UPD:
2823  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2824  return MCDisassembler::Fail;
2825  break;
2826  case ARM::VST3q8:
2827  case ARM::VST3q16:
2828  case ARM::VST3q32:
2829  case ARM::VST3q8_UPD:
2830  case ARM::VST3q16_UPD:
2831  case ARM::VST3q32_UPD:
2832  case ARM::VST4q8:
2833  case ARM::VST4q16:
2834  case ARM::VST4q32:
2835  case ARM::VST4q8_UPD:
2836  case ARM::VST4q16_UPD:
2837  case ARM::VST4q32_UPD:
2838  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2839  return MCDisassembler::Fail;
2840  break;
2841  default:
2842  break;
2843  }
2844 
2845  // Third input register
2846  switch (Inst.getOpcode()) {
2847  case ARM::VST3d8:
2848  case ARM::VST3d16:
2849  case ARM::VST3d32:
2850  case ARM::VST3d8_UPD:
2851  case ARM::VST3d16_UPD:
2852  case ARM::VST3d32_UPD:
2853  case ARM::VST4d8:
2854  case ARM::VST4d16:
2855  case ARM::VST4d32:
2856  case ARM::VST4d8_UPD:
2857  case ARM::VST4d16_UPD:
2858  case ARM::VST4d32_UPD:
2859  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2860  return MCDisassembler::Fail;
2861  break;
2862  case ARM::VST3q8:
2863  case ARM::VST3q16:
2864  case ARM::VST3q32:
2865  case ARM::VST3q8_UPD:
2866  case ARM::VST3q16_UPD:
2867  case ARM::VST3q32_UPD:
2868  case ARM::VST4q8:
2869  case ARM::VST4q16:
2870  case ARM::VST4q32:
2871  case ARM::VST4q8_UPD:
2872  case ARM::VST4q16_UPD:
2873  case ARM::VST4q32_UPD:
2874  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2875  return MCDisassembler::Fail;
2876  break;
2877  default:
2878  break;
2879  }
2880 
2881  // Fourth input register
2882  switch (Inst.getOpcode()) {
2883  case ARM::VST4d8:
2884  case ARM::VST4d16:
2885  case ARM::VST4d32:
2886  case ARM::VST4d8_UPD:
2887  case ARM::VST4d16_UPD:
2888  case ARM::VST4d32_UPD:
2889  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2890  return MCDisassembler::Fail;
2891  break;
2892  case ARM::VST4q8:
2893  case ARM::VST4q16:
2894  case ARM::VST4q32:
2895  case ARM::VST4q8_UPD:
2896  case ARM::VST4q16_UPD:
2897  case ARM::VST4q32_UPD:
2898  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2899  return MCDisassembler::Fail;
2900  break;
2901  default:
2902  break;
2903  }
2904 
2905  return S;
2906 }
2907 
2908 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2909  uint64_t Address, const void *Decoder) {
2911 
2912  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2913  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2914  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2915  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2916  unsigned align = fieldFromInstruction(Insn, 4, 1);
2917  unsigned size = fieldFromInstruction(Insn, 6, 2);
2918 
2919  if (size == 0 && align == 1)
2920  return MCDisassembler::Fail;
2921  align *= (1 << size);
2922 
2923  switch (Inst.getOpcode()) {
2924  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2925  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2926  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2927  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2928  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2929  return MCDisassembler::Fail;
2930  break;
2931  default:
2932  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2933  return MCDisassembler::Fail;
2934  break;
2935  }
2936  if (Rm != 0xF) {
2937  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2938  return MCDisassembler::Fail;
2939  }
2940 
2941  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2942  return MCDisassembler::Fail;
2943  Inst.addOperand(MCOperand::createImm(align));
2944 
2945  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2946  // variant encodes Rm == 0xf. Anything else is a register offset post-
2947  // increment and we need to add the register operand to the instruction.
2948  if (Rm != 0xD && Rm != 0xF &&
2949  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2950  return MCDisassembler::Fail;
2951 
2952  return S;
2953 }
2954 
2955 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2956  uint64_t Address, const void *Decoder) {
2958 
2959  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2960  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2961  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2962  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2963  unsigned align = fieldFromInstruction(Insn, 4, 1);
2964  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2965  align *= 2*size;
2966 
2967  switch (Inst.getOpcode()) {
2968  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2969  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2970  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2971  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2972  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2973  return MCDisassembler::Fail;
2974  break;
2975  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2976  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2977  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2978  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2979  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2980  return MCDisassembler::Fail;
2981  break;
2982  default:
2983  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2984  return MCDisassembler::Fail;
2985  break;
2986  }
2987 
2988  if (Rm != 0xF)
2990 
2991  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2992  return MCDisassembler::Fail;
2993  Inst.addOperand(MCOperand::createImm(align));
2994 
2995  if (Rm != 0xD && Rm != 0xF) {
2996  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2997  return MCDisassembler::Fail;
2998  }
2999 
3000  return S;
3001 }
3002 
3003 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3004  uint64_t Address, const void *Decoder) {
3006 
3007  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3008  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3009  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3010  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3011  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3012 
3013  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3014  return MCDisassembler::Fail;
3015  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3016  return MCDisassembler::Fail;
3017  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3018  return MCDisassembler::Fail;
3019  if (Rm != 0xF) {
3020  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3021  return MCDisassembler::Fail;
3022  }
3023 
3024  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3025  return MCDisassembler::Fail;
3027 
3028  if (Rm == 0xD)
3030  else if (Rm != 0xF) {
3031  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3032  return MCDisassembler::Fail;
3033  }
3034 
3035  return S;
3036 }
3037 
3038 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3039  uint64_t Address, const void *Decoder) {
3041 
3042  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3043  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3044  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3045  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3046  unsigned size = fieldFromInstruction(Insn, 6, 2);
3047  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3048  unsigned align = fieldFromInstruction(Insn, 4, 1);
3049 
3050  if (size == 0x3) {
3051  if (align == 0)
3052  return MCDisassembler::Fail;
3053  align = 16;
3054  } else {
3055  if (size == 2) {
3056  align *= 8;
3057  } else {
3058  size = 1 << size;
3059  align *= 4*size;
3060  }
3061  }
3062 
3063  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3064  return MCDisassembler::Fail;
3065  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3066  return MCDisassembler::Fail;
3067  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3068  return MCDisassembler::Fail;
3069  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3070  return MCDisassembler::Fail;
3071  if (Rm != 0xF) {
3072  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3073  return MCDisassembler::Fail;
3074  }
3075 
3076  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3077  return MCDisassembler::Fail;
3078  Inst.addOperand(MCOperand::createImm(align));
3079 
3080  if (Rm == 0xD)
3082  else if (Rm != 0xF) {
3083  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3084  return MCDisassembler::Fail;
3085  }
3086 
3087  return S;
3088 }
3089 
3090 static DecodeStatus
3092  uint64_t Address, const void *Decoder) {
3094 
3095  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3096  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3097  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3098  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3099  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3100  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3101  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3102  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3103 
3104  if (Q) {
3105  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3106  return MCDisassembler::Fail;
3107  } else {
3108  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3109  return MCDisassembler::Fail;
3110  }
3111 
3112  Inst.addOperand(MCOperand::createImm(imm));
3113 
3114  switch (Inst.getOpcode()) {
3115  case ARM::VORRiv4i16:
3116  case ARM::VORRiv2i32:
3117  case ARM::VBICiv4i16:
3118  case ARM::VBICiv2i32:
3119  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3120  return MCDisassembler::Fail;
3121  break;
3122  case ARM::VORRiv8i16:
3123  case ARM::VORRiv4i32:
3124  case ARM::VBICiv8i16:
3125  case ARM::VBICiv4i32:
3126  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3127  return MCDisassembler::Fail;
3128  break;
3129  default:
3130  break;
3131  }
3132 
3133  return S;
3134 }
3135 
3136 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3137  uint64_t Address, const void *Decoder) {
3139 
3140  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3141  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3142  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3143  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3144  unsigned size = fieldFromInstruction(Insn, 18, 2);
3145 
3146  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3147  return MCDisassembler::Fail;
3148  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3149  return MCDisassembler::Fail;
3150  Inst.addOperand(MCOperand::createImm(8 << size));
3151 
3152  return S;
3153 }
3154 
3155 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3156  uint64_t Address, const void *Decoder) {
3157  Inst.addOperand(MCOperand::createImm(8 - Val));
3158  return MCDisassembler::Success;
3159 }
3160 
3161 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3162  uint64_t Address, const void *Decoder) {
3163  Inst.addOperand(MCOperand::createImm(16 - Val));
3164  return MCDisassembler::Success;
3165 }
3166 
3167 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3168  uint64_t Address, const void *Decoder) {
3169  Inst.addOperand(MCOperand::createImm(32 - Val));
3170  return MCDisassembler::Success;
3171 }
3172 
3173 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3174  uint64_t Address, const void *Decoder) {
3175  Inst.addOperand(MCOperand::createImm(64 - Val));
3176  return MCDisassembler::Success;
3177 }
3178 
3179 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3180  uint64_t Address, const void *Decoder) {
3182 
3183  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3184  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3185  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3186  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3187  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3188  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3189  unsigned op = fieldFromInstruction(Insn, 6, 1);
3190 
3191  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3192  return MCDisassembler::Fail;
3193  if (op) {
3194  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3195  return MCDisassembler::Fail; // Writeback
3196  }
3197 
3198  switch (Inst.getOpcode()) {
3199  case ARM::VTBL2:
3200  case ARM::VTBX2:
3201  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3202  return MCDisassembler::Fail;
3203  break;
3204  default:
3205  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3206  return MCDisassembler::Fail;
3207  }
3208 
3209  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3210  return MCDisassembler::Fail;
3211 
3212  return S;
3213 }
3214 
3215 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3216  uint64_t Address, const void *Decoder) {
3218 
3219  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3220  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3221 
3222  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3223  return MCDisassembler::Fail;
3224 
3225  switch(Inst.getOpcode()) {
3226  default:
3227  return MCDisassembler::Fail;
3228  case ARM::tADR:
3229  break; // tADR does not explicitly represent the PC as an operand.
3230  case ARM::tADDrSPi:
3231  Inst.addOperand(MCOperand::createReg(ARM::SP));
3232  break;
3233  }
3234 
3235  Inst.addOperand(MCOperand::createImm(imm));
3236  return S;
3237 }
3238 
3239 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3240  uint64_t Address, const void *Decoder) {
3241  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3242  true, 2, Inst, Decoder))
3243  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3244  return MCDisassembler::Success;
3245 }
3246 
3247 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3248  uint64_t Address, const void *Decoder) {
3249  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3250  true, 4, Inst, Decoder))
3251  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3252  return MCDisassembler::Success;
3253 }
3254 
3255 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3256  uint64_t Address, const void *Decoder) {
3257  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3258  true, 2, Inst, Decoder))
3259  Inst.addOperand(MCOperand::createImm(Val << 1));
3260  return MCDisassembler::Success;
3261 }
3262 
3263 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3264  uint64_t Address, const void *Decoder) {
3266 
3267  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3268  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3269 
3270  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3271  return MCDisassembler::Fail;
3272  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3273  return MCDisassembler::Fail;
3274 
3275  return S;
3276 }
3277 
3278 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3279  uint64_t Address, const void *Decoder) {
3281 
3282  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3283  unsigned imm = fieldFromInstruction(Val, 3, 5);
3284 
3285  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3286  return MCDisassembler::Fail;
3287  Inst.addOperand(MCOperand::createImm(imm));
3288 
3289  return S;
3290 }
3291 
3292 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3293  uint64_t Address, const void *Decoder) {
3294  unsigned imm = Val << 2;
3295 
3296  Inst.addOperand(MCOperand::createImm(imm));
3297  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3298 
3299  return MCDisassembler::Success;
3300 }
3301 
3302 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3303  uint64_t Address, const void *Decoder) {
3304  Inst.addOperand(MCOperand::createReg(ARM::SP));
3305  Inst.addOperand(MCOperand::createImm(Val));
3306 
3307  return MCDisassembler::Success;
3308 }
3309 
3310 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3311  uint64_t Address, const void *Decoder) {
3313 
3314  unsigned Rn = fieldFromInstruction(Val, 6, 4);
3315  unsigned Rm = fieldFromInstruction(Val, 2, 4);
3316  unsigned imm = fieldFromInstruction(Val, 0, 2);
3317 
3318  // Thumb stores cannot use PC as dest register.
3319  switch (Inst.getOpcode()) {
3320  case ARM::t2STRHs:
3321  case ARM::t2STRBs:
3322  case ARM::t2STRs:
3323  if (Rn == 15)
3324  return MCDisassembler::Fail;
3325  default:
3326  break;
3327  }
3328 
3329  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3330  return MCDisassembler::Fail;
3331  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3332  return MCDisassembler::Fail;
3333  Inst.addOperand(MCOperand::createImm(imm));
3334 
3335  return S;
3336 }
3337 
3338 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3339  uint64_t Address, const void *Decoder) {
3341 
3342  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3343  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3344 
3345  const FeatureBitset &featureBits =
3346  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3347 
3348  bool hasMP = featureBits[ARM::FeatureMP];
3349  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3350 
3351  if (Rn == 15) {
3352  switch (Inst.getOpcode()) {
3353  case ARM::t2LDRBs:
3354  Inst.setOpcode(ARM::t2LDRBpci);
3355  break;
3356  case ARM::t2LDRHs:
3357  Inst.setOpcode(ARM::t2LDRHpci);
3358  break;
3359  case ARM::t2LDRSHs:
3360  Inst.setOpcode(ARM::t2LDRSHpci);
3361  break;
3362  case ARM::t2LDRSBs:
3363  Inst.setOpcode(ARM::t2LDRSBpci);
3364  break;
3365  case ARM::t2LDRs:
3366  Inst.setOpcode(ARM::t2LDRpci);
3367  break;
3368  case ARM::t2PLDs:
3369  Inst.setOpcode(ARM::t2PLDpci);
3370  break;
3371  case ARM::t2PLIs:
3372  Inst.setOpcode(ARM::t2PLIpci);
3373  break;
3374  default:
3375  return MCDisassembler::Fail;
3376  }
3377 
3378  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3379  }
3380 
3381  if (Rt == 15) {
3382  switch (Inst.getOpcode()) {
3383  case ARM::t2LDRSHs:
3384  return MCDisassembler::Fail;
3385  case ARM::t2LDRHs:
3386  Inst.setOpcode(ARM::t2PLDWs);
3387  break;
3388  case ARM::t2LDRSBs:
3389  Inst.setOpcode(ARM::t2PLIs);
3390  default:
3391  break;
3392  }
3393  }
3394 
3395  switch (Inst.getOpcode()) {
3396  case ARM::t2PLDs:
3397  break;
3398  case ARM::t2PLIs:
3399  if (!hasV7Ops)
3400  return MCDisassembler::Fail;
3401  break;
3402  case ARM::t2PLDWs:
3403  if (!hasV7Ops || !hasMP)
3404  return MCDisassembler::Fail;
3405  break;
3406  default:
3407  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3408  return MCDisassembler::Fail;
3409  }
3410 
3411  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3412  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3413  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3414  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3415  return MCDisassembler::Fail;
3416 
3417  return S;
3418 }
3419 
3420 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3421  uint64_t Address, const void* Decoder) {
3423 
3424  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3425  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3426  unsigned U = fieldFromInstruction(Insn, 9, 1);
3427  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3428  imm |= (U << 8);
3429  imm |= (Rn << 9);
3430  unsigned add = fieldFromInstruction(Insn, 9, 1);
3431 
3432  const FeatureBitset &featureBits =
3433  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3434 
3435  bool hasMP = featureBits[ARM::FeatureMP];
3436  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3437 
3438  if (Rn == 15) {
3439  switch (Inst.getOpcode()) {
3440  case ARM::t2LDRi8:
3441  Inst.setOpcode(ARM::t2LDRpci);
3442  break;
3443  case ARM::t2LDRBi8:
3444  Inst.setOpcode(ARM::t2LDRBpci);
3445  break;
3446  case ARM::t2LDRSBi8:
3447  Inst.setOpcode(ARM::t2LDRSBpci);
3448  break;
3449  case ARM::t2LDRHi8:
3450  Inst.setOpcode(ARM::t2LDRHpci);
3451  break;
3452  case ARM::t2LDRSHi8:
3453  Inst.setOpcode(ARM::t2LDRSHpci);
3454  break;
3455  case ARM::t2PLDi8:
3456  Inst.setOpcode(ARM::t2PLDpci);
3457  break;
3458  case ARM::t2PLIi8:
3459  Inst.setOpcode(ARM::t2PLIpci);
3460  break;
3461  default:
3462  return MCDisassembler::Fail;
3463  }
3464  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3465  }
3466 
3467  if (Rt == 15) {
3468  switch (Inst.getOpcode()) {
3469  case ARM::t2LDRSHi8:
3470  return MCDisassembler::Fail;
3471  case ARM::t2LDRHi8:
3472  if (!add)
3473  Inst.setOpcode(ARM::t2PLDWi8);
3474  break;
3475  case ARM::t2LDRSBi8:
3476  Inst.setOpcode(ARM::t2PLIi8);
3477  break;
3478  default:
3479  break;
3480  }
3481  }
3482 
3483  switch (Inst.getOpcode()) {
3484  case ARM::t2PLDi8:
3485  break;
3486  case ARM::t2PLIi8:
3487  if (!hasV7Ops)
3488  return MCDisassembler::Fail;
3489  break;
3490  case ARM::t2PLDWi8:
3491  if (!hasV7Ops || !hasMP)
3492  return MCDisassembler::Fail;
3493  break;
3494  default:
3495  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3496  return MCDisassembler::Fail;
3497  }
3498 
3499  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3500  return MCDisassembler::Fail;
3501  return S;
3502 }
3503 
3504 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3505  uint64_t Address, const void* Decoder) {
3507 
3508  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3509  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3510  unsigned imm = fieldFromInstruction(Insn, 0, 12);
3511  imm |= (Rn << 13);
3512 
3513  const FeatureBitset &featureBits =
3514  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3515 
3516  bool hasMP = featureBits[ARM::FeatureMP];
3517  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3518 
3519  if (Rn == 15) {
3520  switch (Inst.getOpcode()) {
3521  case ARM::t2LDRi12:
3522  Inst.setOpcode(ARM::t2LDRpci);
3523  break;
3524  case ARM::t2LDRHi12:
3525  Inst.setOpcode(ARM::t2LDRHpci);
3526  break;
3527  case ARM::t2LDRSHi12:
3528  Inst.setOpcode(ARM::t2LDRSHpci);
3529  break;
3530  case ARM::t2LDRBi12:
3531  Inst.setOpcode(ARM::t2LDRBpci);
3532  break;
3533  case ARM::t2LDRSBi12:
3534  Inst.setOpcode(ARM::t2LDRSBpci);
3535  break;
3536  case ARM::t2PLDi12:
3537  Inst.setOpcode(ARM::t2PLDpci);
3538  break;
3539  case ARM::t2PLIi12:
3540  Inst.setOpcode(ARM::t2PLIpci);
3541  break;
3542  default:
3543  return MCDisassembler::Fail;
3544  }
3545  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3546  }
3547 
3548  if (Rt == 15) {
3549  switch (Inst.getOpcode()) {
3550  case ARM::t2LDRSHi12:
3551  return MCDisassembler::Fail;
3552  case ARM::t2LDRHi12:
3553  Inst.setOpcode(ARM::t2PLDWi12);
3554  break;
3555  case ARM::t2LDRSBi12:
3556  Inst.setOpcode(ARM::t2PLIi12);
3557  break;
3558  default:
3559  break;
3560  }
3561  }
3562 
3563  switch (Inst.getOpcode()) {
3564  case ARM::t2PLDi12:
3565  break;
3566  case ARM::t2PLIi12:
3567  if (!hasV7Ops)
3568  return MCDisassembler::Fail;
3569  break;
3570  case ARM::t2PLDWi12:
3571  if (!hasV7Ops || !hasMP)
3572  return MCDisassembler::Fail;
3573  break;
3574  default:
3575  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3576  return MCDisassembler::Fail;
3577  }
3578 
3579  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3580  return MCDisassembler::Fail;
3581  return S;
3582 }
3583 
3584 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3585  uint64_t Address, const void* Decoder) {
3587 
3588  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3589  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3590  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3591  imm |= (Rn << 9);
3592 
3593  if (Rn == 15) {
3594  switch (Inst.getOpcode()) {
3595  case ARM::t2LDRT:
3596  Inst.setOpcode(ARM::t2LDRpci);
3597  break;
3598  case ARM::t2LDRBT:
3599  Inst.setOpcode(ARM::t2LDRBpci);
3600  break;
3601  case ARM::t2LDRHT:
3602  Inst.setOpcode(ARM::t2LDRHpci);
3603  break;
3604  case ARM::t2LDRSBT:
3605  Inst.setOpcode(ARM::t2LDRSBpci);
3606  break;
3607  case ARM::t2LDRSHT:
3608  Inst.setOpcode(ARM::t2LDRSHpci);
3609  break;
3610  default:
3611  return MCDisassembler::Fail;
3612  }
3613  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3614  }
3615 
3616  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3617  return MCDisassembler::Fail;
3618  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3619  return MCDisassembler::Fail;
3620  return S;
3621 }
3622 
3623 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3624  uint64_t Address, const void* Decoder) {
3626 
3627  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3628  unsigned U = fieldFromInstruction(Insn, 23, 1);
3629  int imm = fieldFromInstruction(Insn, 0, 12);
3630 
3631  const FeatureBitset &featureBits =
3632  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3633 
3634  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3635 
3636  if (Rt == 15) {
3637  switch (Inst.getOpcode()) {
3638  case ARM::t2LDRBpci:
3639  case ARM::t2LDRHpci:
3640  Inst.setOpcode(ARM::t2PLDpci);
3641  break;
3642  case ARM::t2LDRSBpci:
3643  Inst.setOpcode(ARM::t2PLIpci);
3644  break;
3645  case ARM::t2LDRSHpci:
3646  return MCDisassembler::Fail;
3647  default:
3648  break;
3649  }
3650  }
3651 
3652  switch(Inst.getOpcode()) {
3653  case ARM::t2PLDpci:
3654  break;
3655  case ARM::t2PLIpci:
3656  if (!hasV7Ops)
3657  return MCDisassembler::Fail;
3658  break;
3659  default:
3660  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3661  return MCDisassembler::Fail;
3662  }
3663 
3664  if (!U) {
3665  // Special case for #-0.
3666  if (imm == 0)
3667  imm = INT32_MIN;
3668  else
3669  imm = -imm;
3670  }
3671  Inst.addOperand(MCOperand::createImm(imm));
3672 
3673  return S;
3674 }
3675 
3676 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3677  uint64_t Address, const void *Decoder) {
3678  if (Val == 0)
3679  Inst.addOperand(MCOperand::createImm(INT32_MIN));
3680  else {
3681  int imm = Val & 0xFF;
3682 
3683  if (!(Val & 0x100)) imm *= -1;
3684  Inst.addOperand(MCOperand::createImm(imm * 4));
3685  }
3686 
3687  return MCDisassembler::Success;
3688 }
3689 
3690 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3691  uint64_t Address, const void *Decoder) {
3693 
3694  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3695  unsigned imm = fieldFromInstruction(Val, 0, 9);
3696 
3697  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3698  return MCDisassembler::Fail;
3699  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3700  return MCDisassembler::Fail;
3701 
3702  return S;
3703 }
3704 
3706  uint64_t Address, const void *Decoder) {
3708 
3709  unsigned Rn = fieldFromInstruction(Val, 8, 4);
3710  unsigned imm = fieldFromInstruction(Val, 0, 8);
3711 
3712  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3713  return MCDisassembler::Fail;
3714 
3715  Inst.addOperand(MCOperand::createImm(imm));
3716 
3717  return S;
3718 }
3719 
3720 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3721  uint64_t Address, const void *Decoder) {
3722  int imm = Val & 0xFF;
3723  if (Val == 0)
3724  imm = INT32_MIN;
3725  else if (!(Val & 0x100))
3726  imm *= -1;
3727  Inst.addOperand(MCOperand::createImm(imm));
3728 
3729  return MCDisassembler::Success;
3730 }
3731 
3732 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3733  uint64_t Address, const void *Decoder) {
3735 
3736  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3737  unsigned imm = fieldFromInstruction(Val, 0, 9);
3738 
3739  // Thumb stores cannot use PC as dest register.
3740  switch (Inst.getOpcode()) {
3741  case ARM::t2STRT:
3742  case ARM::t2STRBT:
3743  case ARM::t2STRHT:
3744  case ARM::t2STRi8:
3745  case ARM::t2STRHi8:
3746  case ARM::t2STRBi8:
3747  if (Rn == 15)
3748  return MCDisassembler::Fail;
3749  break;
3750  default:
3751  break;
3752  }
3753 
3754  // Some instructions always use an additive offset.
3755  switch (Inst.getOpcode()) {
3756  case ARM::t2LDRT:
3757  case ARM::t2LDRBT:
3758  case ARM::t2LDRHT:
3759  case ARM::t2LDRSBT:
3760  case ARM::t2LDRSHT:
3761  case ARM::t2STRT:
3762  case ARM::t2STRBT:
3763  case ARM::t2STRHT:
3764  imm |= 0x100;
3765  break;
3766  default:
3767  break;
3768  }
3769 
3770  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3771  return MCDisassembler::Fail;
3772  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3773  return MCDisassembler::Fail;
3774 
3775  return S;
3776 }
3777 
3778 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3779  uint64_t Address, const void *Decoder) {
3781 
3782  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3783  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3784  unsigned addr = fieldFromInstruction(Insn, 0, 8);
3785  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3786  addr |= Rn << 9;
3787  unsigned load = fieldFromInstruction(Insn, 20, 1);
3788 
3789  if (Rn == 15) {
3790  switch (Inst.getOpcode()) {
3791  case ARM::t2LDR_PRE:
3792  case ARM::t2LDR_POST:
3793  Inst.setOpcode(ARM::t2LDRpci);
3794  break;
3795  case ARM::t2LDRB_PRE:
3796  case ARM::t2LDRB_POST:
3797  Inst.setOpcode(ARM::t2LDRBpci);
3798  break;
3799  case ARM::t2LDRH_PRE:
3800  case ARM::t2LDRH_POST:
3801  Inst.setOpcode(ARM::t2LDRHpci);
3802  break;
3803  case ARM::t2LDRSB_PRE:
3804  case ARM::t2LDRSB_POST:
3805  if (Rt == 15)
3806  Inst.setOpcode(ARM::t2PLIpci);
3807  else
3808  Inst.setOpcode(ARM::t2LDRSBpci);
3809  break;
3810  case ARM::t2LDRSH_PRE:
3811  case ARM::t2LDRSH_POST:
3812  Inst.setOpcode(ARM::t2LDRSHpci);
3813  break;
3814  default:
3815  return MCDisassembler::Fail;
3816  }
3817  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3818  }
3819 
3820  if (!load) {
3821  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3822  return MCDisassembler::Fail;
3823  }
3824 
3825  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3826  return MCDisassembler::Fail;
3827 
3828  if (load) {
3829  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3830  return MCDisassembler::Fail;
3831  }
3832 
3833  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3834  return MCDisassembler::Fail;
3835 
3836  return S;
3837 }
3838 
3839 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3840  uint64_t Address, const void *Decoder) {
3842 
3843  unsigned Rn = fieldFromInstruction(Val, 13, 4);
3844  unsigned imm = fieldFromInstruction(Val, 0, 12);
3845 
3846  // Thumb stores cannot use PC as dest register.
3847  switch (Inst.getOpcode()) {
3848  case ARM::t2STRi12:
3849  case ARM::t2STRBi12:
3850  case ARM::t2STRHi12:
3851  if (Rn == 15)
3852  return MCDisassembler::Fail;
3853  default:
3854  break;
3855  }
3856 
3857  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3858  return MCDisassembler::Fail;
3859  Inst.addOperand(MCOperand::createImm(imm));
3860 
3861  return S;
3862 }
3863 
3864 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3865  uint64_t Address, const void *Decoder) {
3866  unsigned imm = fieldFromInstruction(Insn, 0, 7);
3867 
3868  Inst.addOperand(MCOperand::createReg(ARM::SP));
3869  Inst.addOperand(MCOperand::createReg(ARM::SP));
3870  Inst.addOperand(MCOperand::createImm(imm));
3871 
3872  return MCDisassembler::Success;
3873 }
3874 
3875 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3876  uint64_t Address, const void *Decoder) {
3878 
3879  if (Inst.getOpcode() == ARM::tADDrSP) {
3880  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3881  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3882 
3883  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3884  return MCDisassembler::Fail;
3885  Inst.addOperand(MCOperand::createReg(ARM::SP));
3886  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3887  return MCDisassembler::Fail;
3888  } else if (Inst.getOpcode() == ARM::tADDspr) {
3889  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3890 
3891  Inst.addOperand(MCOperand::createReg(ARM::SP));
3892  Inst.addOperand(MCOperand::createReg(ARM::SP));
3893  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3894  return MCDisassembler::Fail;
3895  }
3896 
3897  return S;
3898 }
3899 
3900 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3901  uint64_t Address, const void *Decoder) {
3902  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3903  unsigned flags = fieldFromInstruction(Insn, 0, 3);
3904 
3905  Inst.addOperand(MCOperand::createImm(imod));
3906  Inst.addOperand(MCOperand::createImm(flags));
3907 
3908  return MCDisassembler::Success;
3909 }
3910 
3911 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3912  uint64_t Address, const void *Decoder) {
3914  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3915  unsigned add = fieldFromInstruction(Insn, 4, 1);
3916 
3917  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3918  return MCDisassembler::Fail;
3919  Inst.addOperand(MCOperand::createImm(add));
3920 
3921  return S;
3922 }
3923 
3924 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3925  uint64_t Address, const void *Decoder) {
3926  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3927  // Note only one trailing zero not two. Also the J1 and J2 values are from
3928  // the encoded instruction. So here change to I1 and I2 values via:
3929  // I1 = NOT(J1 EOR S);
3930  // I2 = NOT(J2 EOR S);
3931  // and build the imm32 with two trailing zeros as documented:
3932  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3933  unsigned S = (Val >> 23) & 1;
3934  unsigned J1 = (Val >> 22) & 1;
3935  unsigned J2 = (Val >> 21) & 1;
3936  unsigned I1 = !(J1 ^ S);
3937  unsigned I2 = !(J2 ^ S);
3938  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3939  int imm32 = SignExtend32<25>(tmp << 1);
3940 
3941  if (!tryAddingSymbolicOperand(Address,
3942  (Address & ~2u) + imm32 + 4,
3943  true, 4, Inst, Decoder))
3944  Inst.addOperand(MCOperand::createImm(imm32));
3945  return MCDisassembler::Success;
3946 }
3947 
3948 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3949  uint64_t Address, const void *Decoder) {
3950  if (Val == 0xA || Val == 0xB)
3951  return MCDisassembler::Fail;
3952 
3953  const FeatureBitset &featureBits =
3954  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3955 
3956  if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3957  return MCDisassembler::Fail;
3958 
3959  Inst.addOperand(MCOperand::createImm(Val));
3960  return MCDisassembler::Success;
3961 }
3962 
3963 static DecodeStatus
3964 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3965  uint64_t Address, const void *Decoder) {
3967 
3968  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3969  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3970 
3971  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3972  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3973  return MCDisassembler::Fail;
3974  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3975  return MCDisassembler::Fail;
3976  return S;
3977 }
3978 
3979 static DecodeStatus
3980 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3981  uint64_t Address, const void *Decoder) {
3983 
3984  unsigned pred = fieldFromInstruction(Insn, 22, 4);
3985  if (pred == 0xE || pred == 0xF) {
3986  unsigned opc = fieldFromInstruction(Insn, 4, 28);
3987  switch (opc) {
3988  default:
3989  return MCDisassembler::Fail;
3990  case 0xf3bf8f4:
3991  Inst.setOpcode(ARM::t2DSB);
3992  break;
3993  case 0xf3bf8f5:
3994  Inst.setOpcode(ARM::t2DMB);
3995  break;
3996  case 0xf3bf8f6:
3997  Inst.setOpcode(ARM::t2ISB);
3998  break;
3999  }
4000 
4001  unsigned imm = fieldFromInstruction(Insn, 0, 4);
4002  return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4003  }
4004 
4005  unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4006  brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4007  brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4008  brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4009  brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4010 
4011  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4012  return MCDisassembler::Fail;
4013  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4014  return MCDisassembler::Fail;
4015 
4016  return S;
4017 }
4018 
4019 // Decode a shifted immediate operand. These basically consist
4020 // of an 8-bit value, and a 4-bit directive that specifies either
4021 // a splat operation or a rotation.
4022 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4023  uint64_t Address, const void *Decoder) {
4024  unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4025  if (ctrl == 0) {
4026  unsigned byte = fieldFromInstruction(Val, 8, 2);
4027  unsigned imm = fieldFromInstruction(Val, 0, 8);
4028  switch (byte) {
4029  case 0:
4030  Inst.addOperand(MCOperand::createImm(imm));
4031  break;
4032  case 1:
4033  Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4034  break;
4035  case 2:
4036  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4037  break;
4038  case 3:
4039  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4040  (imm << 8) | imm));
4041  break;
4042  }
4043  } else {
4044  unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4045  unsigned rot = fieldFromInstruction(Val, 7, 5);
4046  unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4047  Inst.addOperand(MCOperand::createImm(imm));
4048  }
4049 
4050  return MCDisassembler::Success;
4051 }
4052 
4053 static DecodeStatus
4055  uint64_t Address, const void *Decoder) {
4056  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4057  true, 2, Inst, Decoder))
4058  Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4059  return MCDisassembler::Success;
4060 }
4061 
4063  uint64_t Address,
4064  const void *Decoder) {
4065  // Val is passed in as S:J1:J2:imm10:imm11
4066  // Note no trailing zero after imm11. Also the J1 and J2 values are from
4067  // the encoded instruction. So here change to I1 and I2 values via:
4068  // I1 = NOT(J1 EOR S);
4069  // I2 = NOT(J2 EOR S);
4070  // and build the imm32 with one trailing zero as documented:
4071  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4072  unsigned S = (Val >> 23) & 1;
4073  unsigned J1 = (Val >> 22) & 1;
4074  unsigned J2 = (Val >> 21) & 1;
4075  unsigned I1 = !(J1 ^ S);
4076  unsigned I2 = !(J2 ^ S);
4077  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4078  int imm32 = SignExtend32<25>(tmp << 1);
4079 
4080  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4081  true, 4, Inst, Decoder))
4082  Inst.addOperand(MCOperand::createImm(imm32));
4083  return MCDisassembler::Success;
4084 }
4085 
4086 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4087  uint64_t Address, const void *Decoder) {
4088  if (Val & ~0xf)
4089  return MCDisassembler::Fail;
4090 
4091  Inst.addOperand(MCOperand::createImm(Val));
4092  return MCDisassembler::Success;
4093 }
4094 
4096  uint64_t Address, const void *Decoder) {
4097  if (Val & ~0xf)
4098  return MCDisassembler::Fail;
4099 
4100  Inst.addOperand(MCOperand::createImm(Val));
4101  return MCDisassembler::Success;
4102 }
4103 
4104 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4105  uint64_t Address, const void *Decoder) {
4107  const FeatureBitset &FeatureBits =
4108  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4109 
4110  if (FeatureBits[ARM::FeatureMClass]) {
4111  unsigned ValLow = Val & 0xff;
4112 
4113  // Validate the SYSm value first.
4114  switch (ValLow) {
4115  case 0: // apsr
4116  case 1: // iapsr
4117  case 2: // eapsr
4118  case 3: // xpsr
4119  case 5: // ipsr
4120  case 6: // epsr
4121  case 7: // iepsr
4122  case 8: // msp
4123  case 9: // psp
4124  case 16: // primask
4125  case 20: // control
4126  break;
4127  case 17: // basepri
4128  case 18: // basepri_max
4129  case 19: // faultmask
4130  if (!(FeatureBits[ARM::HasV7Ops]))
4131  // Values basepri, basepri_max and faultmask are only valid for v7m.
4132  return MCDisassembler::Fail;
4133  break;
4134  case 0x8a: // msplim_ns
4135  case 0x8b: // psplim_ns
4136  case 0x91: // basepri_ns
4137  case 0x92: // basepri_max_ns
4138  case 0x93: // faultmask_ns
4139  if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4140  return MCDisassembler::Fail;
4142  case 10: // msplim
4143  case 11: // psplim
4144  case 0x88: // msp_ns
4145  case 0x89: // psp_ns
4146  case 0x90: // primask_ns
4147  case 0x94: // control_ns
4148  case 0x98: // sp_ns
4149  if (!(FeatureBits[ARM::Feature8MSecExt]))
4150  return MCDisassembler::Fail;
4151  break;
4152  default:
4153  return MCDisassembler::Fail;
4154  }
4155 
4156  if (Inst.getOpcode() == ARM::t2MSR_M) {
4157  unsigned Mask = fieldFromInstruction(Val, 10, 2);
4158  if (!(FeatureBits[ARM::HasV7Ops])) {
4159  // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4160  // unpredictable.
4161  if (Mask != 2)
4163  }
4164  else {
4165  // The ARMv7-M architecture stores an additional 2-bit mask value in
4166  // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4167  // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4168  // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4169  // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4170  // only if the processor includes the DSP extension.
4171  if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4172  (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4174  }
4175  }
4176  } else {
4177  // A/R class
4178  if (Val == 0)
4179  return MCDisassembler::Fail;
4180  }
4181  Inst.addOperand(MCOperand::createImm(Val));
4182  return S;
4183 }
4184 
4185 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4186  uint64_t Address, const void *Decoder) {
4187  unsigned R = fieldFromInstruction(Val, 5, 1);
4188  unsigned SysM = fieldFromInstruction(Val, 0, 5);
4189 
4190  // The table of encodings for these banked registers comes from B9.2.3 of the
4191  // ARM ARM. There are patterns, but nothing regular enough to make this logic
4192  // neater. So by fiat, these values are UNPREDICTABLE:
4193  if (!R) {
4194  if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4195  SysM == 0x1a || SysM == 0x1b)
4196  return MCDisassembler::SoftFail;
4197  } else {
4198  if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4199  SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4200  return MCDisassembler::SoftFail;
4201  }
4202 
4203  Inst.addOperand(MCOperand::createImm(Val));
4204  return MCDisassembler::Success;
4205 }
4206 
4207 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4208  uint64_t Address, const void *Decoder) {
4210 
4211  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4212  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4213  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4214 
4215  if (Rn == 0xF)
4217 
4218  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4219  return MCDisassembler::Fail;
4220  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4221  return MCDisassembler::Fail;
4222  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4223  return MCDisassembler::Fail;
4224 
4225  return S;
4226 }
4227 
4228 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4229  uint64_t Address,
4230  const void *Decoder) {
4232 
4233  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4234  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4235  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4236  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4237 
4238  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4239  return MCDisassembler::Fail;
4240 
4241  if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4243 
4244  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4245  return MCDisassembler::Fail;
4246  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4247  return MCDisassembler::Fail;
4248  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4249  return MCDisassembler::Fail;
4250 
4251  return S;
4252 }
4253 
4254 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4255  uint64_t Address, const void *Decoder) {
4257 
4258  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4259  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4260  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4261  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4262  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4263  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4264 
4265  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4266 
4267  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4268  return MCDisassembler::Fail;
4269  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4270  return MCDisassembler::Fail;
4271  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4272  return MCDisassembler::Fail;
4273  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4274  return MCDisassembler::Fail;
4275 
4276  return S;
4277 }
4278 
4279 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4280  uint64_t Address, const void *Decoder) {
4282 
4283  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4284  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4285  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4286  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4287  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4288  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4289  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4290 
4291  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4292  if (Rm == 0xF) S = MCDisassembler::SoftFail;
4293 
4294  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4295  return MCDisassembler::Fail;
4296  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4297  return MCDisassembler::Fail;
4298  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4299  return MCDisassembler::Fail;
4300  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4301  return MCDisassembler::Fail;
4302 
4303  return S;
4304 }
4305 
4306 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4307  uint64_t Address, const void *Decoder) {
4309 
4310  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4311  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4312  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4313  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4314  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4315  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4316 
4317  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4318 
4319  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4320  return MCDisassembler::Fail;
4321  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4322  return MCDisassembler::Fail;
4323  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4324  return MCDisassembler::Fail;
4325  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4326  return MCDisassembler::Fail;
4327 
4328  return S;
4329 }
4330 
4331 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4332  uint64_t Address, const void *Decoder) {
4334 
4335  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4336  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4337  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4338  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4339  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4340  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4341 
4342  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4343 
4344  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4345  return MCDisassembler::Fail;
4346  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4347  return MCDisassembler::Fail;
4348  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4349  return MCDisassembler::Fail;
4350  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4351  return MCDisassembler::Fail;
4352 
4353  return S;
4354 }
4355 
4356 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4357  uint64_t Address, const void *Decoder) {
4359 
4360  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4361  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4362  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4363  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4364  unsigned size = fieldFromInstruction(Insn, 10, 2);
4365 
4366  unsigned align = 0;
4367  unsigned index = 0;
4368  switch (size) {
4369  default:
4370  return MCDisassembler::Fail;
4371  case 0:
4372  if (fieldFromInstruction(Insn, 4, 1))
4373  return MCDisassembler::Fail; // UNDEFINED
4374  index = fieldFromInstruction(Insn, 5, 3);
4375  break;
4376  case 1:
4377  if (fieldFromInstruction(Insn, 5, 1))
4378  return MCDisassembler::Fail; // UNDEFINED
4379  index = fieldFromInstruction(Insn, 6, 2);
4380  if (fieldFromInstruction(Insn, 4, 1))
4381  align = 2;
4382  break;
4383  case 2:
4384  if (fieldFromInstruction(Insn, 6, 1))
4385  return MCDisassembler::Fail; // UNDEFINED
4386  index = fieldFromInstruction(Insn, 7, 1);
4387 
4388  switch (fieldFromInstruction(Insn, 4, 2)) {
4389  case 0 :
4390  align = 0; break;
4391  case 3:
4392  align = 4; break;
4393  default:
4394  return MCDisassembler::Fail;
4395  }
4396  break;
4397  }
4398 
4399  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4400  return MCDisassembler::Fail;
4401  if (Rm != 0xF) { // Writeback
4402  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4403  return MCDisassembler::Fail;
4404  }
4405  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4406  return MCDisassembler::Fail;
4407  Inst.addOperand(MCOperand::createImm(align));
4408  if (Rm != 0xF) {
4409  if (Rm != 0xD) {
4410  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4411  return MCDisassembler::Fail;
4412  } else
4414  }
4415 
4416  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4417  return MCDisassembler::Fail;
4418  Inst.addOperand(MCOperand::createImm(index));
4419 
4420  return S;
4421 }
4422 
4423 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4424  uint64_t Address, const void *Decoder) {
4426 
4427  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4428  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4429  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4430  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4431  unsigned size = fieldFromInstruction(Insn, 10, 2);
4432 
4433  unsigned align = 0;
4434  unsigned index = 0;
4435  switch (size) {
4436  default:
4437  return MCDisassembler::Fail;
4438  case 0:
4439  if (fieldFromInstruction(Insn, 4, 1))
4440  return MCDisassembler::Fail; // UNDEFINED
4441  index = fieldFromInstruction(Insn, 5, 3);
4442  break;
4443  case 1:
4444  if (fieldFromInstruction(Insn, 5, 1))
4445  return MCDisassembler::Fail; // UNDEFINED
4446  index = fieldFromInstruction(Insn, 6, 2);
4447  if (fieldFromInstruction(Insn, 4, 1))
4448  align = 2;
4449  break;
4450  case 2:
4451  if (fieldFromInstruction(Insn, 6, 1))
4452  return MCDisassembler::Fail; // UNDEFINED
4453  index = fieldFromInstruction(Insn, 7, 1);
4454 
4455  switch (fieldFromInstruction(Insn, 4, 2)) {
4456  case 0:
4457  align = 0; break;
4458  case 3:
4459  align = 4; break;
4460  default:
4461  return MCDisassembler::Fail;
4462  }
4463  break;
4464  }
4465 
4466  if (Rm != 0xF) { // Writeback
4467  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4468  return MCDisassembler::Fail;
4469  }
4470  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4471  return MCDisassembler::Fail;
4472  Inst.addOperand(MCOperand::createImm(align));
4473  if (Rm != 0xF) {
4474  if (Rm != 0xD) {
4475  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4476  return MCDisassembler::Fail;
4477  } else
4479  }
4480 
4481  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4482  return MCDisassembler::Fail;
4483  Inst.addOperand(MCOperand::createImm(index));
4484 
4485  return S;
4486 }
4487 
4488 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4489  uint64_t Address, const void *Decoder) {
4491 
4492  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4493  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4494  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4495  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4496  unsigned size = fieldFromInstruction(Insn, 10, 2);
4497 
4498  unsigned align = 0;
4499  unsigned index = 0;
4500  unsigned inc = 1;
4501  switch (size) {
4502  default:
4503  return MCDisassembler::Fail;
4504  case 0:
4505  index = fieldFromInstruction(Insn, 5, 3);
4506  if (fieldFromInstruction(Insn, 4, 1))
4507  align = 2;
4508  break;
4509  case 1:
4510  index = fieldFromInstruction(Insn, 6, 2);
4511  if (fieldFromInstruction(Insn, 4, 1))
4512  align = 4;
4513  if (fieldFromInstruction(Insn, 5, 1))
4514  inc = 2;
4515  break;
4516  case 2:
4517  if (fieldFromInstruction(Insn, 5, 1))
4518  return MCDisassembler::Fail; // UNDEFINED
4519  index = fieldFromInstruction(Insn, 7, 1);
4520  if (fieldFromInstruction(Insn, 4, 1) != 0)
4521  align = 8;
4522  if (fieldFromInstruction(Insn, 6, 1))
4523  inc = 2;
4524  break;
4525  }
4526 
4527  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4528  return MCDisassembler::Fail;
4529  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4530  return MCDisassembler::Fail;
4531  if (Rm != 0xF) { // Writeback
4532  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4533  return MCDisassembler::Fail;
4534  }
4535  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4536  return MCDisassembler::Fail;
4537  Inst.addOperand(MCOperand::createImm(align));
4538  if (Rm != 0xF) {
4539  if (Rm != 0xD) {
4540  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4541  return MCDisassembler::Fail;
4542  } else
4544  }
4545 
4546  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4547  return MCDisassembler::Fail;
4548  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4549  return MCDisassembler::Fail;
4550  Inst.addOperand(MCOperand::createImm(index));
4551 
4552  return S;
4553 }
4554 
4555 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4556  uint64_t Address, const void *Decoder) {
4558 
4559  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4560  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4561  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4562  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4563  unsigned size = fieldFromInstruction(Insn, 10, 2);
4564 
4565  unsigned align = 0;
4566  unsigned index = 0;
4567  unsigned inc = 1;
4568  switch (size) {
4569  default:
4570  return MCDisassembler::Fail;
4571  case 0:
4572  index = fieldFromInstruction(Insn, 5, 3);
4573  if (fieldFromInstruction(Insn, 4, 1))
4574  align = 2;
4575  break;
4576  case 1:
4577  index = fieldFromInstruction(Insn, 6, 2);
4578  if (fieldFromInstruction(Insn, 4, 1))
4579  align = 4;
4580  if (fieldFromInstruction(Insn, 5, 1))
4581  inc = 2;
4582  break;
4583  case 2:
4584  if (fieldFromInstruction(Insn, 5, 1))
4585  return MCDisassembler::Fail; // UNDEFINED
4586  index = fieldFromInstruction(Insn, 7, 1);
4587  if (fieldFromInstruction(Insn, 4, 1) != 0)
4588  align = 8;
4589  if (fieldFromInstruction(Insn, 6, 1))
4590  inc = 2;
4591  break;
4592  }
4593 
4594  if (Rm != 0xF) { // Writeback
4595  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4596  return MCDisassembler::Fail;
4597  }
4598  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4599  return MCDisassembler::Fail;
4600  Inst.addOperand(MCOperand::createImm(align));
4601  if (Rm != 0xF) {
4602  if (Rm != 0xD) {
4603  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4604  return MCDisassembler::Fail;
4605  } else
4607  }
4608 
4609  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4610  return MCDisassembler::Fail;
4611  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4612  return MCDisassembler::Fail;
4613  Inst.addOperand(MCOperand::createImm(index));
4614 
4615  return S;
4616 }
4617 
4618 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4619  uint64_t Address, const void *Decoder) {
4621 
4622  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4623  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4624  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4625  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4626  unsigned size = fieldFromInstruction(Insn, 10, 2);
4627 
4628  unsigned align = 0;
4629  unsigned index = 0;
4630  unsigned inc = 1;
4631  switch (size) {
4632  default:
4633  return MCDisassembler::Fail;
4634  case 0:
4635  if (fieldFromInstruction(Insn, 4, 1))
4636  return MCDisassembler::Fail; // UNDEFINED
4637  index = fieldFromInstruction(Insn, 5, 3);
4638  break;
4639  case 1:
4640  if (fieldFromInstruction(Insn, 4, 1))
4641  return MCDisassembler::Fail; // UNDEFINED
4642  index = fieldFromInstruction(Insn, 6, 2);
4643  if (fieldFromInstruction(Insn, 5, 1))
4644  inc = 2;
4645  break;
4646  case 2:
4647  if (fieldFromInstruction(Insn, 4, 2))
4648  return MCDisassembler::Fail; // UNDEFINED
4649  index = fieldFromInstruction(Insn, 7, 1);
4650  if (fieldFromInstruction(Insn, 6, 1))
4651  inc = 2;
4652  break;
4653  }
4654 
4655  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4656  return MCDisassembler::Fail;
4657  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4658  return MCDisassembler::Fail;
4659  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4660  return MCDisassembler::Fail;
4661 
4662  if (Rm != 0xF) { // Writeback
4663  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4664  return MCDisassembler::Fail;
4665  }
4666  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4667  return MCDisassembler::Fail;
4668  Inst.addOperand(MCOperand::createImm(align));
4669  if (Rm != 0xF) {
4670  if (Rm != 0xD) {
4671  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4672  return MCDisassembler::Fail;
4673  } else
4675  }
4676 
4677  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4678  return MCDisassembler::Fail;
4679  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4680  return MCDisassembler::Fail;
4681  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4682  return MCDisassembler::Fail;
4683  Inst.addOperand(MCOperand::createImm(index));
4684 
4685  return S;
4686 }
4687 
4688 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4689  uint64_t Address, const void *Decoder) {
4691 
4692  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4693  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4694  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4695  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4696  unsigned size = fieldFromInstruction(Insn, 10, 2);
4697 
4698  unsigned align = 0;
4699  unsigned index = 0;
4700  unsigned inc = 1;
4701  switch (size) {
4702  default:
4703  return MCDisassembler::Fail;
4704  case 0:
4705  if (fieldFromInstruction(Insn, 4, 1))
4706  return MCDisassembler::Fail; // UNDEFINED
4707  index = fieldFromInstruction(Insn, 5, 3);
4708  break;
4709  case 1:
4710  if (fieldFromInstruction(Insn, 4, 1))
4711  return MCDisassembler::Fail; // UNDEFINED
4712  index = fieldFromInstruction(Insn, 6, 2);
4713  if (fieldFromInstruction(Insn, 5, 1))
4714  inc = 2;
4715  break;
4716  case 2:
4717  if (fieldFromInstruction(Insn, 4, 2))
4718  return MCDisassembler::Fail; // UNDEFINED
4719  index = fieldFromInstruction(Insn, 7, 1);
4720  if (fieldFromInstruction(Insn, 6, 1))
4721  inc = 2;
4722  break;
4723  }
4724 
4725  if (Rm != 0xF) { // Writeback
4726  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4727  return MCDisassembler::Fail;
4728  }
4729  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4730  return MCDisassembler::Fail;
4731  Inst.addOperand(MCOperand::createImm(align));
4732  if (Rm != 0xF) {
4733  if (Rm != 0xD) {
4734  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4735  return MCDisassembler::Fail;
4736  } else
4738  }
4739 
4740  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4741  return MCDisassembler::Fail;
4742  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4743  return MCDisassembler::Fail;
4744  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4745  return MCDisassembler::Fail;
4746  Inst.addOperand(MCOperand::createImm(index));
4747 
4748  return S;
4749 }
4750 
4751 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4752  uint64_t Address, const void *Decoder) {
4754 
4755  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4756  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4757  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4758  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4759  unsigned size = fieldFromInstruction(Insn, 10, 2);
4760 
4761  unsigned align = 0;
4762  unsigned index = 0;
4763  unsigned inc = 1;
4764  switch (size) {
4765  default:
4766  return MCDisassembler::Fail;
4767  case 0:
4768  if (fieldFromInstruction(Insn, 4, 1))
4769  align = 4;
4770  index = fieldFromInstruction(Insn, 5, 3);
4771  break;
4772  case 1:
4773  if (fieldFromInstruction(Insn, 4, 1))
4774  align = 8;
4775  index = fieldFromInstruction(Insn, 6, 2);
4776  if (fieldFromInstruction(Insn, 5, 1))
4777  inc = 2;
4778  break;
4779  case 2:
4780  switch (fieldFromInstruction(Insn, 4, 2)) {
4781  case 0:
4782  align = 0; break;
4783  case 3:
4784  return MCDisassembler::Fail;
4785  default:
4786  align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4787  }
4788 
4789  index = fieldFromInstruction(Insn, 7, 1);
4790  if (fieldFromInstruction(Insn, 6, 1))
4791  inc = 2;
4792  break;
4793  }
4794 
4795  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4796  return MCDisassembler::Fail;
4797  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4798  return MCDisassembler::Fail;
4799  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4800  return MCDisassembler::Fail;
4801  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4802  return MCDisassembler::Fail;
4803 
4804  if (Rm != 0xF) { // Writeback
4805  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4806  return MCDisassembler::Fail;
4807  }
4808  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4809  return MCDisassembler::Fail;
4810  Inst.addOperand(MCOperand::createImm(align));
4811  if (Rm != 0xF) {
4812  if (Rm != 0xD) {
4813  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4814  return MCDisassembler::Fail;
4815  } else
4817  }
4818 
4819  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4820  return MCDisassembler::Fail;
4821  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4822  return MCDisassembler::Fail;
4823  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4824  return MCDisassembler::Fail;
4825  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4826  return MCDisassembler::Fail;
4827  Inst.addOperand(MCOperand::createImm(index));
4828 
4829  return S;
4830 }
4831 
4832 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4833  uint64_t Address, const void *Decoder) {
4835 
4836  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4837  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4838  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4839  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4840  unsigned size = fieldFromInstruction(Insn, 10, 2);
4841 
4842  unsigned align = 0;
4843  unsigned index = 0;
4844  unsigned inc = 1;
4845  switch (size) {
4846  default:
4847  return MCDisassembler::Fail;
4848  case 0:
4849  if (fieldFromInstruction(Insn, 4, 1))
4850  align = 4;
4851  index = fieldFromInstruction(Insn, 5, 3);
4852  break;
4853  case 1:
4854  if (fieldFromInstruction(Insn, 4, 1))
4855  align = 8;
4856  index = fieldFromInstruction(Insn, 6, 2);
4857  if (fieldFromInstruction(Insn, 5, 1))
4858  inc = 2;
4859  break;
4860  case 2:
4861  switch (fieldFromInstruction(Insn, 4, 2)) {
4862  case 0:
4863  align = 0; break;
4864  case 3:
4865  return MCDisassembler::Fail;
4866  default:
4867  align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4868  }
4869 
4870  index = fieldFromInstruction(Insn, 7, 1);
4871  if (fieldFromInstruction(Insn, 6, 1))
4872  inc = 2;
4873  break;
4874  }
4875 
4876  if (Rm != 0xF) { // Writeback
4877  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4878  return MCDisassembler::Fail;
4879  }
4880  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4881  return MCDisassembler::Fail;
4882  Inst.addOperand(MCOperand::createImm(align));
4883  if (Rm != 0xF) {
4884  if (Rm != 0xD) {
4885  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4886  return MCDisassembler::Fail;
4887  } else
4889  }
4890 
4891  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4892  return MCDisassembler::Fail;
4893  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4894  return MCDisassembler::Fail;
4895  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4896  return MCDisassembler::Fail;
4897  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4898  return MCDisassembler::Fail;
4899  Inst.addOperand(MCOperand::createImm(index));
4900 
4901  return S;
4902 }
4903 
4904 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4905  uint64_t Address, const void *Decoder) {
4907  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4908  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4909  unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4910  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4911  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4912 
4913  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4915 
4916  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4917  return MCDisassembler::Fail;
4918  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4919  return MCDisassembler::Fail;
4920  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4921  return MCDisassembler::Fail;
4922  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4923  return MCDisassembler::Fail;
4924  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4925  return MCDisassembler::Fail;
4926 
4927  return S;
4928 }
4929 
4930 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4931  uint64_t Address, const void *Decoder) {
4933  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4934  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4935  unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4936  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4937  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4938 
4939  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4941 
4942  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4943  return MCDisassembler::Fail;
4944  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4945  return MCDisassembler::Fail;
4946  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4947  return MCDisassembler::Fail;
4948  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4949  return MCDisassembler::Fail;
4950  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4951  return MCDisassembler::Fail;
4952 
4953  return S;
4954 }
4955 
4956 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4957  uint64_t Address, const void *Decoder) {
4959  unsigned pred = fieldFromInstruction(Insn, 4, 4);
4960  unsigned mask = fieldFromInstruction(Insn, 0, 4);
4961 
4962  if (pred == 0xF) {
4963  pred = 0xE;
4965  }
4966 
4967  if (mask == 0x0)
4968  return MCDisassembler::Fail;
4969 
4970  Inst.addOperand(MCOperand::createImm(pred));
4971  Inst.addOperand(MCOperand::createImm(mask));
4972  return S;
4973 }
4974 
4975 static DecodeStatus
4976 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4977  uint64_t Address, const void *Decoder) {
4979 
4980  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4981  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4982  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4983  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4984  unsigned W = fieldFromInstruction(Insn, 21, 1);
4985  unsigned U = fieldFromInstruction(Insn, 23, 1);
4986  unsigned P = fieldFromInstruction(Insn, 24, 1);
4987  bool writeback = (W == 1) | (P == 0);
4988 
4989  addr |= (U << 8) | (Rn << 9);
4990 
4991  if (writeback && (Rn == Rt || Rn == Rt2))
4993  if (Rt == Rt2)
4995 
4996  // Rt
4997  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4998  return MCDisassembler::Fail;
4999  // Rt2
5000  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5001  return MCDisassembler::Fail;
5002  // Writeback operand
5003  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5004  return MCDisassembler::Fail;
5005  // addr
5006  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5007  return MCDisassembler::Fail;
5008 
5009  return S;
5010 }
5011 
5012 static DecodeStatus
5013 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5014  uint64_t Address, const void *Decoder) {
5016 
5017  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5018  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5019  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5020  unsigned addr = fieldFromInstruction(Insn, 0, 8);
5021  unsigned W = fieldFromInstruction(Insn, 21, 1);
5022  unsigned U = fieldFromInstruction(Insn, 23, 1);
5023  unsigned P = fieldFromInstruction(Insn, 24, 1);
5024  bool writeback = (W == 1) | (P == 0);
5025 
5026  addr |= (U << 8) | (Rn << 9);
5027 
5028  if (writeback && (Rn == Rt || Rn == Rt2))
5030 
5031  // Writeback operand
5032  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5033  return MCDisassembler::Fail;
5034  // Rt
5035  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5036  return MCDisassembler::Fail;
5037  // Rt2
5038  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5039  return MCDisassembler::Fail;
5040  // addr
5041  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5042  return MCDisassembler::Fail;
5043 
5044  return S;
5045 }
5046 
5048  uint64_t Address, const void *Decoder) {
5049  unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5050  unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5051  if (sign1 != sign2) return MCDisassembler::Fail;
5052 
5053  unsigned Val = fieldFromInstruction(Insn, 0, 8);
5054  Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5055  Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5056  Val |= sign1 << 12;
5057  Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5058 
5059  return MCDisassembler::Success;
5060 }
5061 
5063  uint64_t Address,
5064  const void *Decoder) {
5066 
5067  // Shift of "asr #32" is not allowed in Thumb2 mode.
5068  if (Val == 0x20) S = MCDisassembler::Fail;
5069  Inst.addOperand(MCOperand::createImm(Val));
5070  return S;
5071 }
5072 
5073 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5074  uint64_t Address, const void *Decoder) {
5075  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5076  unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5077  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5078  unsigned pred = fieldFromInstruction(Insn, 28, 4);
5079 
5080  if (pred == 0xF)
5081  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5082 
5084 
5085  if (Rt == Rn || Rn == Rt2)
5087 
5088  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5089  return MCDisassembler::Fail;
5090  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5091  return MCDisassembler::Fail;
5092  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5093  return MCDisassembler::Fail;
5094  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5095  return MCDisassembler::Fail;
5096 
5097  return S;
5098 }
5099 
5100 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5101  uint64_t Address, const void *Decoder) {
5102  const FeatureBitset &featureBits =
5103  ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5104  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5105 
5106  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5107  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5108  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5109  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5110  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5111  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5112  unsigned op = fieldFromInstruction(Insn, 5, 1);
5113 
5115 
5116  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5117  if (!(imm & 0x38)) {
5118  if (cmode == 0xF) {
5119  if (op == 1) return MCDisassembler::Fail;
5120  Inst.setOpcode(ARM::VMOVv2f32);
5121  }
5122  if (hasFullFP16) {
5123  if (cmode == 0xE) {
5124  if (op == 1) {
5125  Inst.setOpcode(ARM::VMOVv1i64);
5126  } else {
5127  Inst.setOpcode(ARM::VMOVv8i8);
5128  }
5129  }
5130  if (cmode == 0xD) {
5131  if (op == 1) {
5132  Inst.setOpcode(ARM::VMVNv2i32);
5133  } else {
5134  Inst.setOpcode(ARM::VMOVv2i32);
5135  }
5136  }
5137  if (cmode == 0xC) {
5138  if (op == 1) {
5139  Inst.setOpcode(ARM::VMVNv2i32);
5140  } else {
5141  Inst.setOpcode(ARM::VMOVv2i32);
5142  }
5143  }
5144  }
5145  return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5146  }
5147 
5148  if (!(imm & 0x20)) return MCDisassembler::Fail;
5149 
5150  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5151  return MCDisassembler::Fail;
5152  if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5153  return MCDisassembler::Fail;
5154  Inst.addOperand(MCOperand::createImm(64 - imm));
5155 
5156  return S;
5157 }
5158 
5159 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5160  uint64_t Address, const void *Decoder) {
5161  const FeatureBitset &featureBits =
5162  ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5163  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5164 
5165  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5166  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5167  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5168  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5169  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5170  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5171  unsigned op = fieldFromInstruction(Insn, 5, 1);
5172 
5174 
5175  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5176  if (!(imm & 0x38)) {
5177  if (cmode == 0xF) {
5178  if (op == 1) return MCDisassembler::Fail;
5179  Inst.setOpcode(ARM::VMOVv4f32);
5180  }
5181  if (hasFullFP16) {
5182  if (cmode == 0xE) {
5183  if (op == 1) {
5184  Inst.setOpcode(ARM::VMOVv2i64);
5185  } else {
5186  Inst.setOpcode(ARM::VMOVv16i8);
5187  }
5188  }
5189  if (cmode == 0xD) {
5190  if (op == 1) {
5191  Inst.