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ARMDisassembler.cpp
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1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
13 #include "Utils/ARMBaseInfo.h"
14 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/Compiler.h"
26 #include <algorithm>
27 #include <cassert>
28 #include <cstdint>
29 #include <vector>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "arm-disassembler"
34 
36 
37 namespace {
38 
39  // Handles the condition code status of instructions in IT blocks
40  class ITStatus
41  {
42  public:
43  // Returns the condition code for instruction in IT block
44  unsigned getITCC() {
45  unsigned CC = ARMCC::AL;
46  if (instrInITBlock())
47  CC = ITStates.back();
48  return CC;
49  }
50 
51  // Advances the IT block state to the next T or E
52  void advanceITState() {
53  ITStates.pop_back();
54  }
55 
56  // Returns true if the current instruction is in an IT block
57  bool instrInITBlock() {
58  return !ITStates.empty();
59  }
60 
61  // Returns true if current instruction is the last instruction in an IT block
62  bool instrLastInITBlock() {
63  return ITStates.size() == 1;
64  }
65 
66  // Called when decoding an IT instruction. Sets the IT state for the following
67  // instructions that for the IT block. Firstcond and Mask correspond to the
68  // fields in the IT instruction encoding.
69  void setITState(char Firstcond, char Mask) {
70  // (3 - the number of trailing zeros) is the number of then / else.
71  unsigned CondBit0 = Firstcond & 1;
72  unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
73  unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
74  assert(NumTZ <= 3 && "Invalid IT mask!");
75  // push condition codes onto the stack the correct order for the pops
76  for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77  bool T = ((Mask >> Pos) & 1) == CondBit0;
78  if (T)
79  ITStates.push_back(CCBits);
80  else
81  ITStates.push_back(CCBits ^ 1);
82  }
83  ITStates.push_back(CCBits);
84  }
85 
86  private:
87  std::vector<unsigned char> ITStates;
88  };
89 
90 /// ARM disassembler for all ARM platforms.
91 class ARMDisassembler : public MCDisassembler {
92 public:
93  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94  MCDisassembler(STI, Ctx) {
95  }
96 
97  ~ARMDisassembler() override = default;
98 
99  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
100  ArrayRef<uint8_t> Bytes, uint64_t Address,
101  raw_ostream &VStream,
102  raw_ostream &CStream) const override;
103 };
104 
105 /// Thumb disassembler for all Thumb platforms.
106 class ThumbDisassembler : public MCDisassembler {
107 public:
108  ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
109  MCDisassembler(STI, Ctx) {
110  }
111 
112  ~ThumbDisassembler() override = default;
113 
114  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
115  ArrayRef<uint8_t> Bytes, uint64_t Address,
116  raw_ostream &VStream,
117  raw_ostream &CStream) const override;
118 
119 private:
120  mutable ITStatus ITBlock;
121 
122  DecodeStatus AddThumbPredicate(MCInst&) const;
123  void UpdateThumbVFPPredicate(MCInst&) const;
124 };
125 
126 } // end anonymous namespace
127 
128 static bool Check(DecodeStatus &Out, DecodeStatus In) {
129  switch (In) {
131  // Out stays the same.
132  return true;
134  Out = In;
135  return true;
137  Out = In;
138  return false;
139  }
140  llvm_unreachable("Invalid DecodeStatus!");
141 }
142 
143 // Forward declare these because the autogenerated code will reference them.
144 // Definitions are further down.
145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
146  uint64_t Address, const void *Decoder);
148  unsigned RegNo, uint64_t Address,
149  const void *Decoder);
151  unsigned RegNo, uint64_t Address,
152  const void *Decoder);
153 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154  uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
156  uint64_t Address, const void *Decoder);
157 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
158  uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
160  uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
162  uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
164  uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
166  uint64_t Address, const void *Decoder);
168  unsigned RegNo,
169  uint64_t Address,
170  const void *Decoder);
171 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
172  uint64_t Address, const void *Decoder);
173 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
174  uint64_t Address, const void *Decoder);
176  unsigned RegNo, uint64_t Address,
177  const void *Decoder);
178 
179 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
180  uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
182  uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
184  uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
186  uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
188  uint64_t Address, const void *Decoder);
189 
190 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
191  uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
193  uint64_t Address, const void *Decoder);
195  unsigned Insn,
196  uint64_t Address,
197  const void *Decoder);
198 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
199  uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
201  uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
203  uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
205  uint64_t Address, const void *Decoder);
206 
208  unsigned Insn,
209  uint64_t Adddress,
210  const void *Decoder);
211 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
212  uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
214  uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
216  uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
218  uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
220  uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
222  uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
224  uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
226  uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
228  uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
230  uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
232  uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
234  uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
236  uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
238  uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
240  uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
242  uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
244  uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
246  uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
248  uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
250  uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
252  uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
254  uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
256  uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
258  uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
260  uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
262  uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
264  uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
266  uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
268  uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
270  uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
272  uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
274  uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
276  uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
278  uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
280  uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
282  uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
284  uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
286  uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
288  uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
290  uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
292  uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
294  uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
296  uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
298  uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
300  uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
302  uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
304  uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
306  uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
308  uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
310  uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
312  uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
314  uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
316  uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
318  uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
320  uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
322  uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
324  uint64_t Address, const void *Decoder);
326  unsigned Val,
327  uint64_t Address,
328  const void *Decoder);
329 
330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
331  uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
333  uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
335  uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
337  uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
339  uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
341  uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
343  uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
345  uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
347  uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
349  uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
351  uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
353  uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
355  uint64_t Address, const void* Decoder);
356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
357  uint64_t Address, const void* Decoder);
358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
359  uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
361  uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
363  uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
365  uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
367  uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
369  uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
371  uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
373  uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
375  uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
377  uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
379  uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
381  uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
383  uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
385  uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
387  uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
389  uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
391  uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
393  uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
395  uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
397  uint64_t Address, const void *Decoder);
398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
399  uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
401  uint64_t Address, const void *Decoder);
402 
403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
404  uint64_t Address, const void *Decoder);
405 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
406  uint64_t Address, const void *Decoder);
407 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
408  uint64_t Address, const void *Decoder);
409 
410 #include "ARMGenDisassemblerTables.inc"
411 
413  const MCSubtargetInfo &STI,
414  MCContext &Ctx) {
415  return new ARMDisassembler(STI, Ctx);
416 }
417 
419  const MCSubtargetInfo &STI,
420  MCContext &Ctx) {
421  return new ThumbDisassembler(STI, Ctx);
422 }
423 
424 // Post-decoding checks
426  uint64_t Address, raw_ostream &OS,
427  raw_ostream &CS,
428  uint32_t Insn,
429  DecodeStatus Result) {
430  switch (MI.getOpcode()) {
431  case ARM::HVC: {
432  // HVC is undefined if condition = 0xf otherwise upredictable
433  // if condition != 0xe
434  uint32_t Cond = (Insn >> 28) & 0xF;
435  if (Cond == 0xF)
436  return MCDisassembler::Fail;
437  if (Cond != 0xE)
439  return Result;
440  }
441  default: return Result;
442  }
443 }
444 
445 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
446  ArrayRef<uint8_t> Bytes,
447  uint64_t Address, raw_ostream &OS,
448  raw_ostream &CS) const {
449  CommentStream = &CS;
450 
451  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
452  "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
453  "mode!");
454 
455  // We want to read exactly 4 bytes of data.
456  if (Bytes.size() < 4) {
457  Size = 0;
458  return MCDisassembler::Fail;
459  }
460 
461  // Encoded as a small-endian 32-bit word in the stream.
462  uint32_t Insn =
463  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
464 
465  // Calling the auto-generated decoder function.
466  DecodeStatus Result =
467  decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
468  if (Result != MCDisassembler::Fail) {
469  Size = 4;
470  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
471  }
472 
473  struct DecodeTable {
474  const uint8_t *P;
475  bool DecodePred;
476  };
477 
478  const DecodeTable Tables[] = {
479  {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
480  {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
481  {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
482  {DecoderTablev8Crypto32, false},
483  };
484 
485  for (auto Table : Tables) {
486  Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
487  if (Result != MCDisassembler::Fail) {
488  Size = 4;
489  // Add a fake predicate operand, because we share these instruction
490  // definitions with Thumb2 where these instructions are predicable.
491  if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
492  return MCDisassembler::Fail;
493  return Result;
494  }
495  }
496 
497  Result =
498  decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
499  if (Result != MCDisassembler::Fail) {
500  Size = 4;
501  return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
502  }
503 
504  Size = 4;
505  return MCDisassembler::Fail;
506 }
507 
508 namespace llvm {
509 
510 extern const MCInstrDesc ARMInsts[];
511 
512 } // end namespace llvm
513 
514 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
515 /// immediate Value in the MCInst. The immediate Value has had any PC
516 /// adjustment made by the caller. If the instruction is a branch instruction
517 /// then isBranch is true, else false. If the getOpInfo() function was set as
518 /// part of the setupForSymbolicDisassembly() call then that function is called
519 /// to get any symbolic information at the Address for this instruction. If
520 /// that returns non-zero then the symbolic information it returns is used to
521 /// create an MCExpr and that is added as an operand to the MCInst. If
522 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
523 /// Value is done and if a symbol is found an MCExpr is created with that, else
524 /// an MCExpr with Value is created. This function returns true if it adds an
525 /// operand to the MCInst and false otherwise.
526 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
527  bool isBranch, uint64_t InstSize,
528  MCInst &MI, const void *Decoder) {
529  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
530  // FIXME: Does it make sense for value to be negative?
531  return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
532  /* Offset */ 0, InstSize);
533 }
534 
535 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
536 /// referenced by a load instruction with the base register that is the Pc.
537 /// These can often be values in a literal pool near the Address of the
538 /// instruction. The Address of the instruction and its immediate Value are
539 /// used as a possible literal pool entry. The SymbolLookUp call back will
540 /// return the name of a symbol referenced by the literal pool's entry if
541 /// the referenced address is that of a symbol. Or it will return a pointer to
542 /// a literal 'C' string if the referenced address of the literal pool's entry
543 /// is an address into a section with 'C' string literals.
545  const void *Decoder) {
546  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
547  Dis->tryAddingPcLoadReferenceComment(Value, Address);
548 }
549 
550 // Thumb1 instructions don't have explicit S bits. Rather, they
551 // implicitly set CPSR. Since it's not represented in the encoding, the
552 // auto-generated decoder won't inject the CPSR operand. We need to fix
553 // that as a post-pass.
554 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
555  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
556  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
557  MCInst::iterator I = MI.begin();
558  for (unsigned i = 0; i < NumOps; ++i, ++I) {
559  if (I == MI.end()) break;
560  if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
561  if (i > 0 && OpInfo[i-1].isPredicate()) continue;
562  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
563  return;
564  }
565  }
566 
567  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
568 }
569 
570 // Most Thumb instructions don't have explicit predicates in the
571 // encoding, but rather get their predicates from IT context. We need
572 // to fix up the predicate operands using this context information as a
573 // post-pass.
575 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
577 
578  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
579 
580  // A few instructions actually have predicates encoded in them. Don't
581  // try to overwrite it if we're seeing one of those.
582  switch (MI.getOpcode()) {
583  case ARM::tBcc:
584  case ARM::t2Bcc:
585  case ARM::tCBZ:
586  case ARM::tCBNZ:
587  case ARM::tCPS:
588  case ARM::t2CPS3p:
589  case ARM::t2CPS2p:
590  case ARM::t2CPS1p:
591  case ARM::tMOVSr:
592  case ARM::tSETEND:
593  // Some instructions (mostly conditional branches) are not
594  // allowed in IT blocks.
595  if (ITBlock.instrInITBlock())
596  S = SoftFail;
597  else
598  return Success;
599  break;
600  case ARM::t2HINT:
601  if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
602  S = SoftFail;
603  break;
604  case ARM::tB:
605  case ARM::t2B:
606  case ARM::t2TBB:
607  case ARM::t2TBH:
608  // Some instructions (mostly unconditional branches) can
609  // only appears at the end of, or outside of, an IT.
610  if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
611  S = SoftFail;
612  break;
613  default:
614  break;
615  }
616 
617  // If we're in an IT block, base the predicate on that. Otherwise,
618  // assume a predicate of AL.
619  unsigned CC;
620  CC = ITBlock.getITCC();
621  if (CC == 0xF)
622  CC = ARMCC::AL;
623  if (ITBlock.instrInITBlock())
624  ITBlock.advanceITState();
625 
626  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
627  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
628  MCInst::iterator I = MI.begin();
629  for (unsigned i = 0; i < NumOps; ++i, ++I) {
630  if (I == MI.end()) break;
631  if (OpInfo[i].isPredicate()) {
632  I = MI.insert(I, MCOperand::createImm(CC));
633  ++I;
634  if (CC == ARMCC::AL)
635  MI.insert(I, MCOperand::createReg(0));
636  else
637  MI.insert(I, MCOperand::createReg(ARM::CPSR));
638  return S;
639  }
640  }
641 
642  I = MI.insert(I, MCOperand::createImm(CC));
643  ++I;
644  if (CC == ARMCC::AL)
645  MI.insert(I, MCOperand::createReg(0));
646  else
647  MI.insert(I, MCOperand::createReg(ARM::CPSR));
648 
649  return S;
650 }
651 
652 // Thumb VFP instructions are a special case. Because we share their
653 // encodings between ARM and Thumb modes, and they are predicable in ARM
654 // mode, the auto-generated decoder will give them an (incorrect)
655 // predicate operand. We need to rewrite these operands based on the IT
656 // context as a post-pass.
657 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
658  unsigned CC;
659  CC = ITBlock.getITCC();
660  if (ITBlock.instrInITBlock())
661  ITBlock.advanceITState();
662 
663  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
664  MCInst::iterator I = MI.begin();
665  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
666  for (unsigned i = 0; i < NumOps; ++i, ++I) {
667  if (OpInfo[i].isPredicate() ) {
668  I->setImm(CC);
669  ++I;
670  if (CC == ARMCC::AL)
671  I->setReg(0);
672  else
673  I->setReg(ARM::CPSR);
674  return;
675  }
676  }
677 }
678 
679 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
680  ArrayRef<uint8_t> Bytes,
681  uint64_t Address,
682  raw_ostream &OS,
683  raw_ostream &CS) const {
684  CommentStream = &CS;
685 
686  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
687  "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
688 
689  // We want to read exactly 2 bytes of data.
690  if (Bytes.size() < 2) {
691  Size = 0;
692  return MCDisassembler::Fail;
693  }
694 
695  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
696  DecodeStatus Result =
697  decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
698  if (Result != MCDisassembler::Fail) {
699  Size = 2;
700  Check(Result, AddThumbPredicate(MI));
701  return Result;
702  }
703 
704  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
705  STI);
706  if (Result) {
707  Size = 2;
708  bool InITBlock = ITBlock.instrInITBlock();
709  Check(Result, AddThumbPredicate(MI));
710  AddThumb1SBit(MI, InITBlock);
711  return Result;
712  }
713 
714  Result =
715  decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
716  if (Result != MCDisassembler::Fail) {
717  Size = 2;
718 
719  // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
720  // the Thumb predicate.
721  if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
722  Result = MCDisassembler::SoftFail;
723 
724  Check(Result, AddThumbPredicate(MI));
725 
726  // If we find an IT instruction, we need to parse its condition
727  // code and mask operands so that we can apply them correctly
728  // to the subsequent instructions.
729  if (MI.getOpcode() == ARM::t2IT) {
730 
731  unsigned Firstcond = MI.getOperand(0).getImm();
732  unsigned Mask = MI.getOperand(1).getImm();
733  ITBlock.setITState(Firstcond, Mask);
734  }
735 
736  return Result;
737  }
738 
739  // We want to read exactly 4 bytes of data.
740  if (Bytes.size() < 4) {
741  Size = 0;
742  return MCDisassembler::Fail;
743  }
744 
745  uint32_t Insn32 =
746  (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
747  Result =
748  decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
749  if (Result != MCDisassembler::Fail) {
750  Size = 4;
751  bool InITBlock = ITBlock.instrInITBlock();
752  Check(Result, AddThumbPredicate(MI));
753  AddThumb1SBit(MI, InITBlock);
754  return Result;
755  }
756 
757  Result =
758  decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
759  if (Result != MCDisassembler::Fail) {
760  Size = 4;
761  Check(Result, AddThumbPredicate(MI));
762  return Result;
763  }
764 
765  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
766  Result =
767  decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
768  if (Result != MCDisassembler::Fail) {
769  Size = 4;
770  UpdateThumbVFPPredicate(MI);
771  return Result;
772  }
773  }
774 
775  Result =
776  decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
777  if (Result != MCDisassembler::Fail) {
778  Size = 4;
779  return Result;
780  }
781 
782  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
783  Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
784  STI);
785  if (Result != MCDisassembler::Fail) {
786  Size = 4;
787  Check(Result, AddThumbPredicate(MI));
788  return Result;
789  }
790  }
791 
792  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
793  uint32_t NEONLdStInsn = Insn32;
794  NEONLdStInsn &= 0xF0FFFFFF;
795  NEONLdStInsn |= 0x04000000;
796  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
797  Address, this, STI);
798  if (Result != MCDisassembler::Fail) {
799  Size = 4;
800  Check(Result, AddThumbPredicate(MI));
801  return Result;
802  }
803  }
804 
805  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
806  uint32_t NEONDataInsn = Insn32;
807  NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
808  NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
809  NEONDataInsn |= 0x12000000; // Set bits 28 and 25
810  Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
811  Address, this, STI);
812  if (Result != MCDisassembler::Fail) {
813  Size = 4;
814  Check(Result, AddThumbPredicate(MI));
815  return Result;
816  }
817 
818  uint32_t NEONCryptoInsn = Insn32;
819  NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
820  NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
821  NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
822  Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
823  Address, this, STI);
824  if (Result != MCDisassembler::Fail) {
825  Size = 4;
826  return Result;
827  }
828 
829  uint32_t NEONv8Insn = Insn32;
830  NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
831  Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
832  this, STI);
833  if (Result != MCDisassembler::Fail) {
834  Size = 4;
835  return Result;
836  }
837  }
838 
839  Result =
840  decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
841  if (Result != MCDisassembler::Fail) {
842  Size = 4;
843  Check(Result, AddThumbPredicate(MI));
844  return Result;
845  }
846 
847  Size = 0;
848  return MCDisassembler::Fail;
849 }
850 
851 extern "C" void LLVMInitializeARMDisassembler() {
860 }
861 
862 static const uint16_t GPRDecoderTable[] = {
863  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
864  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
865  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
866  ARM::R12, ARM::SP, ARM::LR, ARM::PC
867 };
868 
869 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
870  uint64_t Address, const void *Decoder) {
871  if (RegNo > 15)
872  return MCDisassembler::Fail;
873 
874  unsigned Register = GPRDecoderTable[RegNo];
875  Inst.addOperand(MCOperand::createReg(Register));
877 }
878 
879 static DecodeStatus
880 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
881  uint64_t Address, const void *Decoder) {
883 
884  if (RegNo == 15)
886 
887  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
888 
889  return S;
890 }
891 
892 static DecodeStatus
894  uint64_t Address, const void *Decoder) {
896 
897  if (RegNo == 15)
898  {
899  Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
901  }
902 
903  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
904  return S;
905 }
906 
907 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
908  uint64_t Address, const void *Decoder) {
909  if (RegNo > 7)
910  return MCDisassembler::Fail;
911  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
912 }
913 
914 static const uint16_t GPRPairDecoderTable[] = {
915  ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
916  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
917 };
918 
919 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
920  uint64_t Address, const void *Decoder) {
922 
923  if (RegNo > 13)
924  return MCDisassembler::Fail;
925 
926  if ((RegNo & 1) || RegNo == 0xe)
928 
929  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
930  Inst.addOperand(MCOperand::createReg(RegisterPair));
931  return S;
932 }
933 
934 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
935  uint64_t Address, const void *Decoder) {
936  unsigned Register = 0;
937  switch (RegNo) {
938  case 0:
939  Register = ARM::R0;
940  break;
941  case 1:
942  Register = ARM::R1;
943  break;
944  case 2:
945  Register = ARM::R2;
946  break;
947  case 3:
948  Register = ARM::R3;
949  break;
950  case 9:
951  Register = ARM::R9;
952  break;
953  case 12:
954  Register = ARM::R12;
955  break;
956  default:
957  return MCDisassembler::Fail;
958  }
959 
960  Inst.addOperand(MCOperand::createReg(Register));
962 }
963 
964 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
965  uint64_t Address, const void *Decoder) {
967 
968  const FeatureBitset &featureBits =
969  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
970 
971  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
973 
974  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
975  return S;
976 }
977 
978 static const uint16_t SPRDecoderTable[] = {
979  ARM::S0, ARM::S1, ARM::S2, ARM::S3,
980  ARM::S4, ARM::S5, ARM::S6, ARM::S7,
981  ARM::S8, ARM::S9, ARM::S10, ARM::S11,
982  ARM::S12, ARM::S13, ARM::S14, ARM::S15,
983  ARM::S16, ARM::S17, ARM::S18, ARM::S19,
984  ARM::S20, ARM::S21, ARM::S22, ARM::S23,
985  ARM::S24, ARM::S25, ARM::S26, ARM::S27,
986  ARM::S28, ARM::S29, ARM::S30, ARM::S31
987 };
988 
989 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
990  uint64_t Address, const void *Decoder) {
991  if (RegNo > 31)
992  return MCDisassembler::Fail;
993 
994  unsigned Register = SPRDecoderTable[RegNo];
995  Inst.addOperand(MCOperand::createReg(Register));
997 }
998 
999 static const uint16_t DPRDecoderTable[] = {
1000  ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1001  ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1002  ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1003  ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1004  ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1005  ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1006  ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1007  ARM::D28, ARM::D29, ARM::D30, ARM::D31
1008 };
1009 
1010 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1011  uint64_t Address, const void *Decoder) {
1012  const FeatureBitset &featureBits =
1013  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1014 
1015  bool hasD16 = featureBits[ARM::FeatureD16];
1016 
1017  if (RegNo > 31 || (hasD16 && RegNo > 15))
1018  return MCDisassembler::Fail;
1019 
1020  unsigned Register = DPRDecoderTable[RegNo];
1021  Inst.addOperand(MCOperand::createReg(Register));
1022  return MCDisassembler::Success;
1023 }
1024 
1025 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1026  uint64_t Address, const void *Decoder) {
1027  if (RegNo > 7)
1028  return MCDisassembler::Fail;
1029  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1030 }
1031 
1032 static DecodeStatus
1033 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1034  uint64_t Address, const void *Decoder) {
1035  if (RegNo > 15)
1036  return MCDisassembler::Fail;
1037  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1038 }
1039 
1040 static const uint16_t QPRDecoderTable[] = {
1041  ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1042  ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1043  ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1044  ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1045 };
1046 
1047 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1048  uint64_t Address, const void *Decoder) {
1049  if (RegNo > 31 || (RegNo & 1) != 0)
1050  return MCDisassembler::Fail;
1051  RegNo >>= 1;
1052 
1053  unsigned Register = QPRDecoderTable[RegNo];
1054  Inst.addOperand(MCOperand::createReg(Register));
1055  return MCDisassembler::Success;
1056 }
1057 
1058 static const uint16_t DPairDecoderTable[] = {
1059  ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1060  ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1061  ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1062  ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1063  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1064  ARM::Q15
1065 };
1066 
1067 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1068  uint64_t Address, const void *Decoder) {
1069  if (RegNo > 30)
1070  return MCDisassembler::Fail;
1071 
1072  unsigned Register = DPairDecoderTable[RegNo];
1073  Inst.addOperand(MCOperand::createReg(Register));
1074  return MCDisassembler::Success;
1075 }
1076 
1077 static const uint16_t DPairSpacedDecoderTable[] = {
1078  ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1079  ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1080  ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1081  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1082  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1083  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1084  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1085  ARM::D28_D30, ARM::D29_D31
1086 };
1087 
1089  unsigned RegNo,
1090  uint64_t Address,
1091  const void *Decoder) {
1092  if (RegNo > 29)
1093  return MCDisassembler::Fail;
1094 
1095  unsigned Register = DPairSpacedDecoderTable[RegNo];
1096  Inst.addOperand(MCOperand::createReg(Register));
1097  return MCDisassembler::Success;
1098 }
1099 
1100 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1101  uint64_t Address, const void *Decoder) {
1102  if (Val == 0xF) return MCDisassembler::Fail;
1103  // AL predicate is not allowed on Thumb1 branches.
1104  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1105  return MCDisassembler::Fail;
1106  Inst.addOperand(MCOperand::createImm(Val));
1107  if (Val == ARMCC::AL) {
1109  } else
1110  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1111  return MCDisassembler::Success;
1112 }
1113 
1114 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1115  uint64_t Address, const void *Decoder) {
1116  if (Val)
1117  Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1118  else
1120  return MCDisassembler::Success;
1121 }
1122 
1123 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1124  uint64_t Address, const void *Decoder) {
1126 
1127  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1128  unsigned type = fieldFromInstruction(Val, 5, 2);
1129  unsigned imm = fieldFromInstruction(Val, 7, 5);
1130 
1131  // Register-immediate
1132  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1133  return MCDisassembler::Fail;
1134 
1135  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1136  switch (type) {
1137  case 0:
1138  Shift = ARM_AM::lsl;
1139  break;
1140  case 1:
1141  Shift = ARM_AM::lsr;
1142  break;
1143  case 2:
1144  Shift = ARM_AM::asr;
1145  break;
1146  case 3:
1147  Shift = ARM_AM::ror;
1148  break;
1149  }
1150 
1151  if (Shift == ARM_AM::ror && imm == 0)
1152  Shift = ARM_AM::rrx;
1153 
1154  unsigned Op = Shift | (imm << 3);
1155  Inst.addOperand(MCOperand::createImm(Op));
1156 
1157  return S;
1158 }
1159 
1160 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1161  uint64_t Address, const void *Decoder) {
1163 
1164  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1165  unsigned type = fieldFromInstruction(Val, 5, 2);
1166  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1167 
1168  // Register-register
1169  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1170  return MCDisassembler::Fail;
1171  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1172  return MCDisassembler::Fail;
1173 
1174  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1175  switch (type) {
1176  case 0:
1177  Shift = ARM_AM::lsl;
1178  break;
1179  case 1:
1180  Shift = ARM_AM::lsr;
1181  break;
1182  case 2:
1183  Shift = ARM_AM::asr;
1184  break;
1185  case 3:
1186  Shift = ARM_AM::ror;
1187  break;
1188  }
1189 
1190  Inst.addOperand(MCOperand::createImm(Shift));
1191 
1192  return S;
1193 }
1194 
1195 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1196  uint64_t Address, const void *Decoder) {
1198 
1199  bool NeedDisjointWriteback = false;
1200  unsigned WritebackReg = 0;
1201  switch (Inst.getOpcode()) {
1202  default:
1203  break;
1204  case ARM::LDMIA_UPD:
1205  case ARM::LDMDB_UPD:
1206  case ARM::LDMIB_UPD:
1207  case ARM::LDMDA_UPD:
1208  case ARM::t2LDMIA_UPD:
1209  case ARM::t2LDMDB_UPD:
1210  case ARM::t2STMIA_UPD:
1211  case ARM::t2STMDB_UPD:
1212  NeedDisjointWriteback = true;
1213  WritebackReg = Inst.getOperand(0).getReg();
1214  break;
1215  }
1216 
1217  // Empty register lists are not allowed.
1218  if (Val == 0) return MCDisassembler::Fail;
1219  for (unsigned i = 0; i < 16; ++i) {
1220  if (Val & (1 << i)) {
1221  if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1222  return MCDisassembler::Fail;
1223  // Writeback not allowed if Rn is in the target list.
1224  if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1226  }
1227  }
1228 
1229  return S;
1230 }
1231 
1232 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1233  uint64_t Address, const void *Decoder) {
1235 
1236  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1237  unsigned regs = fieldFromInstruction(Val, 0, 8);
1238 
1239  // In case of unpredictable encoding, tweak the operands.
1240  if (regs == 0 || (Vd + regs) > 32) {
1241  regs = Vd + regs > 32 ? 32 - Vd : regs;
1242  regs = std::max( 1u, regs);
1244  }
1245 
1246  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1247  return MCDisassembler::Fail;
1248  for (unsigned i = 0; i < (regs - 1); ++i) {
1249  if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1250  return MCDisassembler::Fail;
1251  }
1252 
1253  return S;
1254 }
1255 
1256 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1257  uint64_t Address, const void *Decoder) {
1259 
1260  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1261  unsigned regs = fieldFromInstruction(Val, 1, 7);
1262 
1263  // In case of unpredictable encoding, tweak the operands.
1264  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1265  regs = Vd + regs > 32 ? 32 - Vd : regs;
1266  regs = std::max( 1u, regs);
1267  regs = std::min(16u, regs);
1269  }
1270 
1271  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1272  return MCDisassembler::Fail;
1273  for (unsigned i = 0; i < (regs - 1); ++i) {
1274  if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1275  return MCDisassembler::Fail;
1276  }
1277 
1278  return S;
1279 }
1280 
1281 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1282  uint64_t Address, const void *Decoder) {
1283  // This operand encodes a mask of contiguous zeros between a specified MSB
1284  // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1285  // the mask of all bits LSB-and-lower, and then xor them to create
1286  // the mask of that's all ones on [msb, lsb]. Finally we not it to
1287  // create the final mask.
1288  unsigned msb = fieldFromInstruction(Val, 5, 5);
1289  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1290 
1292  if (lsb > msb) {
1294  // The check above will cause the warning for the "potentially undefined
1295  // instruction encoding" but we can't build a bad MCOperand value here
1296  // with a lsb > msb or else printing the MCInst will cause a crash.
1297  lsb = msb;
1298  }
1299 
1300  uint32_t msb_mask = 0xFFFFFFFF;
1301  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1302  uint32_t lsb_mask = (1U << lsb) - 1;
1303 
1304  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1305  return S;
1306 }
1307 
1308 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1309  uint64_t Address, const void *Decoder) {
1311 
1312  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1313  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1314  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1315  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1316  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1317  unsigned U = fieldFromInstruction(Insn, 23, 1);
1318 
1319  switch (Inst.getOpcode()) {
1320  case ARM::LDC_OFFSET:
1321  case ARM::LDC_PRE:
1322  case ARM::LDC_POST:
1323  case ARM::LDC_OPTION:
1324  case ARM::LDCL_OFFSET:
1325  case ARM::LDCL_PRE:
1326  case ARM::LDCL_POST:
1327  case ARM::LDCL_OPTION:
1328  case ARM::STC_OFFSET:
1329  case ARM::STC_PRE:
1330  case ARM::STC_POST:
1331  case ARM::STC_OPTION:
1332  case ARM::STCL_OFFSET:
1333  case ARM::STCL_PRE:
1334  case ARM::STCL_POST:
1335  case ARM::STCL_OPTION:
1336  case ARM::t2LDC_OFFSET:
1337  case ARM::t2LDC_PRE:
1338  case ARM::t2LDC_POST:
1339  case ARM::t2LDC_OPTION:
1340  case ARM::t2LDCL_OFFSET:
1341  case ARM::t2LDCL_PRE:
1342  case ARM::t2LDCL_POST:
1343  case ARM::t2LDCL_OPTION:
1344  case ARM::t2STC_OFFSET:
1345  case ARM::t2STC_PRE:
1346  case ARM::t2STC_POST:
1347  case ARM::t2STC_OPTION:
1348  case ARM::t2STCL_OFFSET:
1349  case ARM::t2STCL_PRE:
1350  case ARM::t2STCL_POST:
1351  case ARM::t2STCL_OPTION:
1352  if (coproc == 0xA || coproc == 0xB)
1353  return MCDisassembler::Fail;
1354  break;
1355  default:
1356  break;
1357  }
1358 
1359  const FeatureBitset &featureBits =
1360  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1361  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1362  return MCDisassembler::Fail;
1363 
1364  Inst.addOperand(MCOperand::createImm(coproc));
1365  Inst.addOperand(MCOperand::createImm(CRd));
1366  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1367  return MCDisassembler::Fail;
1368 
1369  switch (Inst.getOpcode()) {
1370  case ARM::t2LDC2_OFFSET:
1371  case ARM::t2LDC2L_OFFSET:
1372  case ARM::t2LDC2_PRE:
1373  case ARM::t2LDC2L_PRE:
1374  case ARM::t2STC2_OFFSET:
1375  case ARM::t2STC2L_OFFSET:
1376  case ARM::t2STC2_PRE:
1377  case ARM::t2STC2L_PRE:
1378  case ARM::LDC2_OFFSET:
1379  case ARM::LDC2L_OFFSET:
1380  case ARM::LDC2_PRE:
1381  case ARM::LDC2L_PRE:
1382  case ARM::STC2_OFFSET:
1383  case ARM::STC2L_OFFSET:
1384  case ARM::STC2_PRE:
1385  case ARM::STC2L_PRE:
1386  case ARM::t2LDC_OFFSET:
1387  case ARM::t2LDCL_OFFSET:
1388  case ARM::t2LDC_PRE:
1389  case ARM::t2LDCL_PRE:
1390  case ARM::t2STC_OFFSET:
1391  case ARM::t2STCL_OFFSET:
1392  case ARM::t2STC_PRE:
1393  case ARM::t2STCL_PRE:
1394  case ARM::LDC_OFFSET:
1395  case ARM::LDCL_OFFSET:
1396  case ARM::LDC_PRE:
1397  case ARM::LDCL_PRE:
1398  case ARM::STC_OFFSET:
1399  case ARM::STCL_OFFSET:
1400  case ARM::STC_PRE:
1401  case ARM::STCL_PRE:
1402  imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1403  Inst.addOperand(MCOperand::createImm(imm));
1404  break;
1405  case ARM::t2LDC2_POST:
1406  case ARM::t2LDC2L_POST:
1407  case ARM::t2STC2_POST:
1408  case ARM::t2STC2L_POST:
1409  case ARM::LDC2_POST:
1410  case ARM::LDC2L_POST:
1411  case ARM::STC2_POST:
1412  case ARM::STC2L_POST:
1413  case ARM::t2LDC_POST:
1414  case ARM::t2LDCL_POST:
1415  case ARM::t2STC_POST:
1416  case ARM::t2STCL_POST:
1417  case ARM::LDC_POST:
1418  case ARM::LDCL_POST:
1419  case ARM::STC_POST:
1420  case ARM::STCL_POST:
1421  imm |= U << 8;
1423  default:
1424  // The 'option' variant doesn't encode 'U' in the immediate since
1425  // the immediate is unsigned [0,255].
1426  Inst.addOperand(MCOperand::createImm(imm));
1427  break;
1428  }
1429 
1430  switch (Inst.getOpcode()) {
1431  case ARM::LDC_OFFSET:
1432  case ARM::LDC_PRE:
1433  case ARM::LDC_POST:
1434  case ARM::LDC_OPTION:
1435  case ARM::LDCL_OFFSET:
1436  case ARM::LDCL_PRE:
1437  case ARM::LDCL_POST:
1438  case ARM::LDCL_OPTION:
1439  case ARM::STC_OFFSET:
1440  case ARM::STC_PRE:
1441  case ARM::STC_POST:
1442  case ARM::STC_OPTION:
1443  case ARM::STCL_OFFSET:
1444  case ARM::STCL_PRE:
1445  case ARM::STCL_POST:
1446  case ARM::STCL_OPTION:
1447  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1448  return MCDisassembler::Fail;
1449  break;
1450  default:
1451  break;
1452  }
1453 
1454  return S;
1455 }
1456 
1457 static DecodeStatus
1459  uint64_t Address, const void *Decoder) {
1461 
1462  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1463  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1464  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1465  unsigned imm = fieldFromInstruction(Insn, 0, 12);
1466  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1467  unsigned reg = fieldFromInstruction(Insn, 25, 1);
1468  unsigned P = fieldFromInstruction(Insn, 24, 1);
1469  unsigned W = fieldFromInstruction(Insn, 21, 1);
1470 
1471  // On stores, the writeback operand precedes Rt.
1472  switch (Inst.getOpcode()) {
1473  case ARM::STR_POST_IMM:
1474  case ARM::STR_POST_REG:
1475  case ARM::STRB_POST_IMM:
1476  case ARM::STRB_POST_REG:
1477  case ARM::STRT_POST_REG:
1478  case ARM::STRT_POST_IMM:
1479  case ARM::STRBT_POST_REG:
1480  case ARM::STRBT_POST_IMM:
1481  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1482  return MCDisassembler::Fail;
1483  break;
1484  default:
1485  break;
1486  }
1487 
1488  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1489  return MCDisassembler::Fail;
1490 
1491  // On loads, the writeback operand comes after Rt.
1492  switch (Inst.getOpcode()) {
1493  case ARM::LDR_POST_IMM:
1494  case ARM::LDR_POST_REG:
1495  case ARM::LDRB_POST_IMM:
1496  case ARM::LDRB_POST_REG:
1497  case ARM::LDRBT_POST_REG:
1498  case ARM::LDRBT_POST_IMM:
1499  case ARM::LDRT_POST_REG:
1500  case ARM::LDRT_POST_IMM:
1501  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1502  return MCDisassembler::Fail;
1503  break;
1504  default:
1505  break;
1506  }
1507 
1508  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1509  return MCDisassembler::Fail;
1510 
1512  if (!fieldFromInstruction(Insn, 23, 1))
1513  Op = ARM_AM::sub;
1514 
1515  bool writeback = (P == 0) || (W == 1);
1516  unsigned idx_mode = 0;
1517  if (P && writeback)
1518  idx_mode = ARMII::IndexModePre;
1519  else if (!P && writeback)
1520  idx_mode = ARMII::IndexModePost;
1521 
1522  if (writeback && (Rn == 15 || Rn == Rt))
1523  S = MCDisassembler::SoftFail; // UNPREDICTABLE
1524 
1525  if (reg) {
1526  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1527  return MCDisassembler::Fail;
1529  switch( fieldFromInstruction(Insn, 5, 2)) {
1530  case 0:
1531  Opc = ARM_AM::lsl;
1532  break;
1533  case 1:
1534  Opc = ARM_AM::lsr;
1535  break;
1536  case 2:
1537  Opc = ARM_AM::asr;
1538  break;
1539  case 3:
1540  Opc = ARM_AM::ror;
1541  break;
1542  default:
1543  return MCDisassembler::Fail;
1544  }
1545  unsigned amt = fieldFromInstruction(Insn, 7, 5);
1546  if (Opc == ARM_AM::ror && amt == 0)
1547  Opc = ARM_AM::rrx;
1548  unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1549 
1550  Inst.addOperand(MCOperand::createImm(imm));
1551  } else {
1553  unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1554  Inst.addOperand(MCOperand::createImm(tmp));
1555  }
1556 
1557  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1558  return MCDisassembler::Fail;
1559 
1560  return S;
1561 }
1562 
1563 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1564  uint64_t Address, const void *Decoder) {
1566 
1567  unsigned Rn = fieldFromInstruction(Val, 13, 4);
1568  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1569  unsigned type = fieldFromInstruction(Val, 5, 2);
1570  unsigned imm = fieldFromInstruction(Val, 7, 5);
1571  unsigned U = fieldFromInstruction(Val, 12, 1);
1572 
1574  switch (type) {
1575  case 0:
1576  ShOp = ARM_AM::lsl;
1577  break;
1578  case 1:
1579  ShOp = ARM_AM::lsr;
1580  break;
1581  case 2:
1582  ShOp = ARM_AM::asr;
1583  break;
1584  case 3:
1585  ShOp = ARM_AM::ror;
1586  break;
1587  }
1588 
1589  if (ShOp == ARM_AM::ror && imm == 0)
1590  ShOp = ARM_AM::rrx;
1591 
1592  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1593  return MCDisassembler::Fail;
1594  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1595  return MCDisassembler::Fail;
1596  unsigned shift;
1597  if (U)
1598  shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1599  else
1600  shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1601  Inst.addOperand(MCOperand::createImm(shift));
1602 
1603  return S;
1604 }
1605 
1606 static DecodeStatus
1607 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1608  uint64_t Address, const void *Decoder) {
1610 
1611  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1612  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1613  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1614  unsigned type = fieldFromInstruction(Insn, 22, 1);
1615  unsigned imm = fieldFromInstruction(Insn, 8, 4);
1616  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1617  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1618  unsigned W = fieldFromInstruction(Insn, 21, 1);
1619  unsigned P = fieldFromInstruction(Insn, 24, 1);
1620  unsigned Rt2 = Rt + 1;
1621 
1622  bool writeback = (W == 1) | (P == 0);
1623 
1624  // For {LD,ST}RD, Rt must be even, else undefined.
1625  switch (Inst.getOpcode()) {
1626  case ARM::STRD:
1627  case ARM::STRD_PRE:
1628  case ARM::STRD_POST:
1629  case ARM::LDRD:
1630  case ARM::LDRD_PRE:
1631  case ARM::LDRD_POST:
1632  if (Rt & 0x1) S = MCDisassembler::SoftFail;
1633  break;
1634  default:
1635  break;
1636  }
1637  switch (Inst.getOpcode()) {
1638  case ARM::STRD:
1639  case ARM::STRD_PRE:
1640  case ARM::STRD_POST:
1641  if (P == 0 && W == 1)
1643 
1644  if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1646  if (type && Rm == 15)
1648  if (Rt2 == 15)
1650  if (!type && fieldFromInstruction(Insn, 8, 4))
1652  break;
1653  case ARM::STRH:
1654  case ARM::STRH_PRE:
1655  case ARM::STRH_POST:
1656  if (Rt == 15)
1658  if (writeback && (Rn == 15 || Rn == Rt))
1660  if (!type && Rm == 15)
1662  break;
1663  case ARM::LDRD:
1664  case ARM::LDRD_PRE:
1665  case ARM::LDRD_POST:
1666  if (type && Rn == 15) {
1667  if (Rt2 == 15)
1669  break;
1670  }
1671  if (P == 0 && W == 1)
1673  if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1675  if (!type && writeback && Rn == 15)
1677  if (writeback && (Rn == Rt || Rn == Rt2))
1679  break;
1680  case ARM::LDRH:
1681  case ARM::LDRH_PRE:
1682  case ARM::LDRH_POST:
1683  if (type && Rn == 15) {
1684  if (Rt == 15)
1686  break;
1687  }
1688  if (Rt == 15)
1690  if (!type && Rm == 15)
1692  if (!type && writeback && (Rn == 15 || Rn == Rt))
1694  break;
1695  case ARM::LDRSH:
1696  case ARM::LDRSH_PRE:
1697  case ARM::LDRSH_POST:
1698  case ARM::LDRSB:
1699  case ARM::LDRSB_PRE:
1700  case ARM::LDRSB_POST:
1701  if (type && Rn == 15) {
1702  if (Rt == 15)
1704  break;
1705  }
1706  if (type && (Rt == 15 || (writeback && Rn == Rt)))
1708  if (!type && (Rt == 15 || Rm == 15))
1710  if (!type && writeback && (Rn == 15 || Rn == Rt))
1712  break;
1713  default:
1714  break;
1715  }
1716 
1717  if (writeback) { // Writeback
1718  if (P)
1719  U |= ARMII::IndexModePre << 9;
1720  else
1721  U |= ARMII::IndexModePost << 9;
1722 
1723  // On stores, the writeback operand precedes Rt.
1724  switch (Inst.getOpcode()) {
1725  case ARM::STRD:
1726  case ARM::STRD_PRE:
1727  case ARM::STRD_POST:
1728  case ARM::STRH:
1729  case ARM::STRH_PRE:
1730  case ARM::STRH_POST:
1731  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1732  return MCDisassembler::Fail;
1733  break;
1734  default:
1735  break;
1736  }
1737  }
1738 
1739  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1740  return MCDisassembler::Fail;
1741  switch (Inst.getOpcode()) {
1742  case ARM::STRD:
1743  case ARM::STRD_PRE:
1744  case ARM::STRD_POST:
1745  case ARM::LDRD:
1746  case ARM::LDRD_PRE:
1747  case ARM::LDRD_POST:
1748  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1749  return MCDisassembler::Fail;
1750  break;
1751  default:
1752  break;
1753  }
1754 
1755  if (writeback) {
1756  // On loads, the writeback operand comes after Rt.
1757  switch (Inst.getOpcode()) {
1758  case ARM::LDRD:
1759  case ARM::LDRD_PRE:
1760  case ARM::LDRD_POST:
1761  case ARM::LDRH:
1762  case ARM::LDRH_PRE:
1763  case ARM::LDRH_POST:
1764  case ARM::LDRSH:
1765  case ARM::LDRSH_PRE:
1766  case ARM::LDRSH_POST:
1767  case ARM::LDRSB:
1768  case ARM::LDRSB_PRE:
1769  case ARM::LDRSB_POST:
1770  case ARM::LDRHTr:
1771  case ARM::LDRSBTr:
1772  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1773  return MCDisassembler::Fail;
1774  break;
1775  default:
1776  break;
1777  }
1778  }
1779 
1780  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1781  return MCDisassembler::Fail;
1782 
1783  if (type) {
1785  Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1786  } else {
1787  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1788  return MCDisassembler::Fail;
1790  }
1791 
1792  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1793  return MCDisassembler::Fail;
1794 
1795  return S;
1796 }
1797 
1798 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1799  uint64_t Address, const void *Decoder) {
1801 
1802  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1803  unsigned mode = fieldFromInstruction(Insn, 23, 2);
1804 
1805  switch (mode) {
1806  case 0:
1807  mode = ARM_AM::da;
1808  break;
1809  case 1:
1810  mode = ARM_AM::ia;
1811  break;
1812  case 2:
1813  mode = ARM_AM::db;
1814  break;
1815  case 3:
1816  mode = ARM_AM::ib;
1817  break;
1818  }
1819 
1820  Inst.addOperand(MCOperand::createImm(mode));
1821  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1822  return MCDisassembler::Fail;
1823 
1824  return S;
1825 }
1826 
1827 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1828  uint64_t Address, const void *Decoder) {
1830 
1831  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1832  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1833  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1834  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1835 
1836  if (pred == 0xF)
1837  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1838 
1839  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1840  return MCDisassembler::Fail;
1841  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1842  return MCDisassembler::Fail;
1843  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1844  return MCDisassembler::Fail;
1845  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1846  return MCDisassembler::Fail;
1847  return S;
1848 }
1849 
1851  unsigned Insn,
1852  uint64_t Address, const void *Decoder) {
1854 
1855  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1856  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1857  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1858 
1859  if (pred == 0xF) {
1860  // Ambiguous with RFE and SRS
1861  switch (Inst.getOpcode()) {
1862  case ARM::LDMDA:
1863  Inst.setOpcode(ARM::RFEDA);
1864  break;
1865  case ARM::LDMDA_UPD:
1866  Inst.setOpcode(ARM::RFEDA_UPD);
1867  break;
1868  case ARM::LDMDB:
1869  Inst.setOpcode(ARM::RFEDB);
1870  break;
1871  case ARM::LDMDB_UPD:
1872  Inst.setOpcode(ARM::RFEDB_UPD);
1873  break;
1874  case ARM::LDMIA:
1875  Inst.setOpcode(ARM::RFEIA);
1876  break;
1877  case ARM::LDMIA_UPD:
1878  Inst.setOpcode(ARM::RFEIA_UPD);
1879  break;
1880  case ARM::LDMIB:
1881  Inst.setOpcode(ARM::RFEIB);
1882  break;
1883  case ARM::LDMIB_UPD:
1884  Inst.setOpcode(ARM::RFEIB_UPD);
1885  break;
1886  case ARM::STMDA:
1887  Inst.setOpcode(ARM::SRSDA);
1888  break;
1889  case ARM::STMDA_UPD:
1890  Inst.setOpcode(ARM::SRSDA_UPD);
1891  break;
1892  case ARM::STMDB:
1893  Inst.setOpcode(ARM::SRSDB);
1894  break;
1895  case ARM::STMDB_UPD:
1896  Inst.setOpcode(ARM::SRSDB_UPD);
1897  break;
1898  case ARM::STMIA:
1899  Inst.setOpcode(ARM::SRSIA);
1900  break;
1901  case ARM::STMIA_UPD:
1902  Inst.setOpcode(ARM::SRSIA_UPD);
1903  break;
1904  case ARM::STMIB:
1905  Inst.setOpcode(ARM::SRSIB);
1906  break;
1907  case ARM::STMIB_UPD:
1908  Inst.setOpcode(ARM::SRSIB_UPD);
1909  break;
1910  default:
1911  return MCDisassembler::Fail;
1912  }
1913 
1914  // For stores (which become SRS's, the only operand is the mode.
1915  if (fieldFromInstruction(Insn, 20, 1) == 0) {
1916  // Check SRS encoding constraints
1917  if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1918  fieldFromInstruction(Insn, 20, 1) == 0))
1919  return MCDisassembler::Fail;
1920 
1921  Inst.addOperand(
1922  MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1923  return S;
1924  }
1925 
1926  return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1927  }
1928 
1929  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1930  return MCDisassembler::Fail;
1931  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1932  return MCDisassembler::Fail; // Tied
1933  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1934  return MCDisassembler::Fail;
1935  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1936  return MCDisassembler::Fail;
1937 
1938  return S;
1939 }
1940 
1941 // Check for UNPREDICTABLE predicated ESB instruction
1942 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1943  uint64_t Address, const void *Decoder) {
1944  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1945  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1946  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
1947  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1948 
1950 
1951  Inst.addOperand(MCOperand::createImm(imm8));
1952 
1953  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1954  return MCDisassembler::Fail;
1955 
1956  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1957  // so all predicates should be allowed.
1958  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1960 
1961  return S;
1962 }
1963 
1964 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1965  uint64_t Address, const void *Decoder) {
1966  unsigned imod = fieldFromInstruction(Insn, 18, 2);
1967  unsigned M = fieldFromInstruction(Insn, 17, 1);
1968  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1969  unsigned mode = fieldFromInstruction(Insn, 0, 5);
1970 
1972 
1973  // This decoder is called from multiple location that do not check
1974  // the full encoding is valid before they do.
1975  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1976  fieldFromInstruction(Insn, 16, 1) != 0 ||
1977  fieldFromInstruction(Insn, 20, 8) != 0x10)
1978  return MCDisassembler::Fail;
1979 
1980  // imod == '01' --> UNPREDICTABLE
1981  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1982  // return failure here. The '01' imod value is unprintable, so there's
1983  // nothing useful we could do even if we returned UNPREDICTABLE.
1984 
1985  if (imod == 1) return MCDisassembler::Fail;
1986 
1987  if (imod && M) {
1988  Inst.setOpcode(ARM::CPS3p);
1989  Inst.addOperand(MCOperand::createImm(imod));
1990  Inst.addOperand(MCOperand::createImm(iflags));
1991  Inst.addOperand(MCOperand::createImm(mode));
1992  } else if (imod && !M) {
1993  Inst.setOpcode(ARM::CPS2p);
1994  Inst.addOperand(MCOperand::createImm(imod));
1995  Inst.addOperand(MCOperand::createImm(iflags));
1996  if (mode) S = MCDisassembler::SoftFail;
1997  } else if (!imod && M) {
1998  Inst.setOpcode(ARM::CPS1p);
1999  Inst.addOperand(MCOperand::createImm(mode));
2000  if (iflags) S = MCDisassembler::SoftFail;
2001  } else {
2002  // imod == '00' && M == '0' --> UNPREDICTABLE
2003  Inst.setOpcode(ARM::CPS1p);
2004  Inst.addOperand(MCOperand::createImm(mode));
2006  }
2007 
2008  return S;
2009 }
2010 
2011 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2012  uint64_t Address, const void *Decoder) {
2013  unsigned imod = fieldFromInstruction(Insn, 9, 2);
2014  unsigned M = fieldFromInstruction(Insn, 8, 1);
2015  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2016  unsigned mode = fieldFromInstruction(Insn, 0, 5);
2017 
2019 
2020  // imod == '01' --> UNPREDICTABLE
2021  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2022  // return failure here. The '01' imod value is unprintable, so there's
2023  // nothing useful we could do even if we returned UNPREDICTABLE.
2024 
2025  if (imod == 1) return MCDisassembler::Fail;
2026 
2027  if (imod && M) {
2028  Inst.setOpcode(ARM::t2CPS3p);
2029  Inst.addOperand(MCOperand::createImm(imod));
2030  Inst.addOperand(MCOperand::createImm(iflags));
2031  Inst.addOperand(MCOperand::createImm(mode));
2032  } else if (imod && !M) {
2033  Inst.setOpcode(ARM::t2CPS2p);
2034  Inst.addOperand(MCOperand::createImm(imod));
2035  Inst.addOperand(MCOperand::createImm(iflags));
2036  if (mode) S = MCDisassembler::SoftFail;
2037  } else if (!imod && M) {
2038  Inst.setOpcode(ARM::t2CPS1p);
2039  Inst.addOperand(MCOperand::createImm(mode));
2040  if (iflags) S = MCDisassembler::SoftFail;
2041  } else {
2042  // imod == '00' && M == '0' --> this is a HINT instruction
2043  int imm = fieldFromInstruction(Insn, 0, 8);
2044  // HINT are defined only for immediate in [0..4]
2045  if(imm > 4) return MCDisassembler::Fail;
2046  Inst.setOpcode(ARM::t2HINT);
2047  Inst.addOperand(MCOperand::createImm(imm));
2048  }
2049 
2050  return S;
2051 }
2052 
2053 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2054  uint64_t Address, const void *Decoder) {
2056 
2057  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2058  unsigned imm = 0;
2059 
2060  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2061  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2062  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2063  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2064 
2065  if (Inst.getOpcode() == ARM::t2MOVTi16)
2066  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2067  return MCDisassembler::Fail;
2068  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2069  return MCDisassembler::Fail;
2070 
2071  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2072  Inst.addOperand(MCOperand::createImm(imm));
2073 
2074  return S;
2075 }
2076 
2077 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2078  uint64_t Address, const void *Decoder) {
2080 
2081  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2082  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2083  unsigned imm = 0;
2084 
2085  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2086  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2087 
2088  if (Inst.getOpcode() == ARM::MOVTi16)
2089  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2090  return MCDisassembler::Fail;
2091 
2092  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2093  return MCDisassembler::Fail;
2094 
2095  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2096  Inst.addOperand(MCOperand::createImm(imm));
2097 
2098  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2099  return MCDisassembler::Fail;
2100 
2101  return S;
2102 }
2103 
2104 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2105  uint64_t Address, const void *Decoder) {
2107 
2108  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2109  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2110  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2111  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2112  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2113 
2114  if (pred == 0xF)
2115  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2116 
2117  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2118  return MCDisassembler::Fail;
2119  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2120  return MCDisassembler::Fail;
2121  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2122  return MCDisassembler::Fail;
2123  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2124  return MCDisassembler::Fail;
2125 
2126  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2127  return MCDisassembler::Fail;
2128 
2129  return S;
2130 }
2131 
2132 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2133  uint64_t Address, const void *Decoder) {
2135 
2136  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2137  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2138  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2139 
2140  if (Pred == 0xF)
2141  return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2142 
2143  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2144  return MCDisassembler::Fail;
2145  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2146  return MCDisassembler::Fail;
2147  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2148  return MCDisassembler::Fail;
2149 
2150  return S;
2151 }
2152 
2153 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2154  uint64_t Address, const void *Decoder) {
2156 
2157  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2158 
2159  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2160  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2161 
2162  if (!FeatureBits[ARM::HasV8_1aOps] ||
2163  !FeatureBits[ARM::HasV8Ops])
2164  return MCDisassembler::Fail;
2165 
2166  // Decoder can be called from DecodeTST, which does not check the full
2167  // encoding is valid.
2168  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2169  fieldFromInstruction(Insn, 4,4) != 0)
2170  return MCDisassembler::Fail;
2171  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2172  fieldFromInstruction(Insn, 0,4) != 0)
2174 
2175  Inst.setOpcode(ARM::SETPAN);
2176  Inst.addOperand(MCOperand::createImm(Imm));
2177 
2178  return S;
2179 }
2180 
2182  uint64_t Address, const void *Decoder) {
2184 
2185  unsigned add = fieldFromInstruction(Val, 12, 1);
2186  unsigned imm = fieldFromInstruction(Val, 0, 12);
2187  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2188 
2189  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2190  return MCDisassembler::Fail;
2191 
2192  if (!add) imm *= -1;
2193  if (imm == 0 && !add) imm = INT32_MIN;
2194  Inst.addOperand(MCOperand::createImm(imm));
2195  if (Rn == 15)
2196  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2197 
2198  return S;
2199 }
2200 
2201 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2202  uint64_t Address, const void *Decoder) {
2204 
2205  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2206  // U == 1 to add imm, 0 to subtract it.
2207  unsigned U = fieldFromInstruction(Val, 8, 1);
2208  unsigned imm = fieldFromInstruction(Val, 0, 8);
2209 
2210  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2211  return MCDisassembler::Fail;
2212 
2213  if (U)
2215  else
2217 
2218  return S;
2219 }
2220 
2222  uint64_t Address, const void *Decoder) {
2224 
2225  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2226  // U == 1 to add imm, 0 to subtract it.
2227  unsigned U = fieldFromInstruction(Val, 8, 1);
2228  unsigned imm = fieldFromInstruction(Val, 0, 8);
2229 
2230  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2231  return MCDisassembler::Fail;
2232 
2233  if (U)
2235  else
2237 
2238  return S;
2239 }
2240 
2241 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2242  uint64_t Address, const void *Decoder) {
2243  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2244 }
2245 
2246 static DecodeStatus
2247 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2248  uint64_t Address, const void *Decoder) {
2250 
2251  // Note the J1 and J2 values are from the encoded instruction. So here
2252  // change them to I1 and I2 values via as documented:
2253  // I1 = NOT(J1 EOR S);
2254  // I2 = NOT(J2 EOR S);
2255  // and build the imm32 with one trailing zero as documented:
2256  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2257  unsigned S = fieldFromInstruction(Insn, 26, 1);
2258  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2259  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2260  unsigned I1 = !(J1 ^ S);
2261  unsigned I2 = !(J2 ^ S);
2262  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2263  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2264  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2265  int imm32 = SignExtend32<25>(tmp << 1);
2266  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2267  true, 4, Inst, Decoder))
2268  Inst.addOperand(MCOperand::createImm(imm32));
2269 
2270  return Status;
2271 }
2272 
2273 static DecodeStatus
2274 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2275  uint64_t Address, const void *Decoder) {
2277 
2278  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2279  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2280 
2281  if (pred == 0xF) {
2282  Inst.setOpcode(ARM::BLXi);
2283  imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2284  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2285  true, 4, Inst, Decoder))
2286  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2287  return S;
2288  }
2289 
2290  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2291  true, 4, Inst, Decoder))
2292  Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2293  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2294  return MCDisassembler::Fail;
2295 
2296  return S;
2297 }
2298 
2299 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2300  uint64_t Address, const void *Decoder) {
2302 
2303  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2304  unsigned align = fieldFromInstruction(Val, 4, 2);
2305 
2306  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2307  return MCDisassembler::Fail;
2308  if (!align)
2310  else
2311  Inst.addOperand(MCOperand::createImm(4 << align));
2312 
2313  return S;
2314 }
2315 
2316 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2317  uint64_t Address, const void *Decoder) {
2319 
2320  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2321  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2322  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2323  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2324  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2325  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2326 
2327  // First output register
2328  switch (Inst.getOpcode()) {
2329  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2330  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2331  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2332  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2333  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2334  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2335  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2336  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2337  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2338  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2339  return MCDisassembler::Fail;
2340  break;
2341  case ARM::VLD2b16:
2342  case ARM::VLD2b32:
2343  case ARM::VLD2b8:
2344  case ARM::VLD2b16wb_fixed:
2345  case ARM::VLD2b16wb_register:
2346  case ARM::VLD2b32wb_fixed:
2347  case ARM::VLD2b32wb_register:
2348  case ARM::VLD2b8wb_fixed:
2349  case ARM::VLD2b8wb_register:
2350  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2351  return MCDisassembler::Fail;
2352  break;
2353  default:
2354  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2355  return MCDisassembler::Fail;
2356  }
2357 
2358  // Second output register
2359  switch (Inst.getOpcode()) {
2360  case ARM::VLD3d8:
2361  case ARM::VLD3d16:
2362  case ARM::VLD3d32:
2363  case ARM::VLD3d8_UPD:
2364  case ARM::VLD3d16_UPD:
2365  case ARM::VLD3d32_UPD:
2366  case ARM::VLD4d8:
2367  case ARM::VLD4d16:
2368  case ARM::VLD4d32:
2369  case ARM::VLD4d8_UPD:
2370  case ARM::VLD4d16_UPD:
2371  case ARM::VLD4d32_UPD:
2372  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2373  return MCDisassembler::Fail;
2374  break;
2375  case ARM::VLD3q8:
2376  case ARM::VLD3q16:
2377  case ARM::VLD3q32:
2378  case ARM::VLD3q8_UPD:
2379  case ARM::VLD3q16_UPD:
2380  case ARM::VLD3q32_UPD:
2381  case ARM::VLD4q8:
2382  case ARM::VLD4q16:
2383  case ARM::VLD4q32:
2384  case ARM::VLD4q8_UPD:
2385  case ARM::VLD4q16_UPD:
2386  case ARM::VLD4q32_UPD:
2387  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2388  return MCDisassembler::Fail;
2389  default:
2390  break;
2391  }
2392 
2393  // Third output register
2394  switch(Inst.getOpcode()) {
2395  case ARM::VLD3d8:
2396  case ARM::VLD3d16:
2397  case ARM::VLD3d32:
2398  case ARM::VLD3d8_UPD:
2399  case ARM::VLD3d16_UPD:
2400  case ARM::VLD3d32_UPD:
2401  case ARM::VLD4d8:
2402  case ARM::VLD4d16:
2403  case ARM::VLD4d32:
2404  case ARM::VLD4d8_UPD:
2405  case ARM::VLD4d16_UPD:
2406  case ARM::VLD4d32_UPD:
2407  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2408  return MCDisassembler::Fail;
2409  break;
2410  case ARM::VLD3q8:
2411  case ARM::VLD3q16:
2412  case ARM::VLD3q32:
2413  case ARM::VLD3q8_UPD:
2414  case ARM::VLD3q16_UPD:
2415  case ARM::VLD3q32_UPD:
2416  case ARM::VLD4q8:
2417  case ARM::VLD4q16:
2418  case ARM::VLD4q32:
2419  case ARM::VLD4q8_UPD:
2420  case ARM::VLD4q16_UPD:
2421  case ARM::VLD4q32_UPD:
2422  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2423  return MCDisassembler::Fail;
2424  break;
2425  default:
2426  break;
2427  }
2428 
2429  // Fourth output register
2430  switch (Inst.getOpcode()) {
2431  case ARM::VLD4d8:
2432  case ARM::VLD4d16:
2433  case ARM::VLD4d32:
2434  case ARM::VLD4d8_UPD:
2435  case ARM::VLD4d16_UPD:
2436  case ARM::VLD4d32_UPD:
2437  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2438  return MCDisassembler::Fail;
2439  break;
2440  case ARM::VLD4q8:
2441  case ARM::VLD4q16:
2442  case ARM::VLD4q32:
2443  case ARM::VLD4q8_UPD:
2444  case ARM::VLD4q16_UPD:
2445  case ARM::VLD4q32_UPD:
2446  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2447  return MCDisassembler::Fail;
2448  break;
2449  default:
2450  break;
2451  }
2452 
2453  // Writeback operand
2454  switch (Inst.getOpcode()) {
2455  case ARM::VLD1d8wb_fixed:
2456  case ARM::VLD1d16wb_fixed:
2457  case ARM::VLD1d32wb_fixed:
2458  case ARM::VLD1d64wb_fixed:
2459  case ARM::VLD1d8wb_register:
2460  case ARM::VLD1d16wb_register:
2461  case ARM::VLD1d32wb_register:
2462  case ARM::VLD1d64wb_register:
2463  case ARM::VLD1q8wb_fixed:
2464  case ARM::VLD1q16wb_fixed:
2465  case ARM::VLD1q32wb_fixed:
2466  case ARM::VLD1q64wb_fixed:
2467  case ARM::VLD1q8wb_register:
2468  case ARM::VLD1q16wb_register:
2469  case ARM::VLD1q32wb_register:
2470  case ARM::VLD1q64wb_register:
2471  case ARM::VLD1d8Twb_fixed:
2472  case ARM::VLD1d8Twb_register:
2473  case ARM::VLD1d16Twb_fixed:
2474  case ARM::VLD1d16Twb_register:
2475  case ARM::VLD1d32Twb_fixed:
2476  case ARM::VLD1d32Twb_register:
2477  case ARM::VLD1d64Twb_fixed:
2478  case ARM::VLD1d64Twb_register:
2479  case ARM::VLD1d8Qwb_fixed:
2480  case ARM::VLD1d8Qwb_register:
2481  case ARM::VLD1d16Qwb_fixed:
2482  case ARM::VLD1d16Qwb_register:
2483  case ARM::VLD1d32Qwb_fixed:
2484  case ARM::VLD1d32Qwb_register:
2485  case ARM::VLD1d64Qwb_fixed:
2486  case ARM::VLD1d64Qwb_register:
2487  case ARM::VLD2d8wb_fixed:
2488  case ARM::VLD2d16wb_fixed:
2489  case ARM::VLD2d32wb_fixed:
2490  case ARM::VLD2q8wb_fixed:
2491  case ARM::VLD2q16wb_fixed:
2492  case ARM::VLD2q32wb_fixed:
2493  case ARM::VLD2d8wb_register:
2494  case ARM::VLD2d16wb_register:
2495  case ARM::VLD2d32wb_register:
2496  case ARM::VLD2q8wb_register:
2497  case ARM::VLD2q16wb_register:
2498  case ARM::VLD2q32wb_register:
2499  case ARM::VLD2b8wb_fixed:
2500  case ARM::VLD2b16wb_fixed:
2501  case ARM::VLD2b32wb_fixed:
2502  case ARM::VLD2b8wb_register:
2503  case ARM::VLD2b16wb_register:
2504  case ARM::VLD2b32wb_register:
2506  break;
2507  case ARM::VLD3d8_UPD:
2508  case ARM::VLD3d16_UPD:
2509  case ARM::VLD3d32_UPD:
2510  case ARM::VLD3q8_UPD:
2511  case ARM::VLD3q16_UPD:
2512  case ARM::VLD3q32_UPD:
2513  case ARM::VLD4d8_UPD:
2514  case ARM::VLD4d16_UPD:
2515  case ARM::VLD4d32_UPD:
2516  case ARM::VLD4q8_UPD:
2517  case ARM::VLD4q16_UPD:
2518  case ARM::VLD4q32_UPD:
2519  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2520  return MCDisassembler::Fail;
2521  break;
2522  default:
2523  break;
2524  }
2525 
2526  // AddrMode6 Base (register+alignment)
2527  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2528  return MCDisassembler::Fail;
2529 
2530  // AddrMode6 Offset (register)
2531  switch (Inst.getOpcode()) {
2532  default:
2533  // The below have been updated to have explicit am6offset split
2534  // between fixed and register offset. For those instructions not
2535  // yet updated, we need to add an additional reg0 operand for the
2536  // fixed variant.
2537  //
2538  // The fixed offset encodes as Rm == 0xd, so we check for that.
2539  if (Rm == 0xd) {
2541  break;
2542  }
2543  // Fall through to handle the register offset variant.
2545  case ARM::VLD1d8wb_fixed:
2546  case ARM::VLD1d16wb_fixed:
2547  case ARM::VLD1d32wb_fixed:
2548  case ARM::VLD1d64wb_fixed:
2549  case ARM::VLD1d8Twb_fixed:
2550  case ARM::VLD1d16Twb_fixed:
2551  case ARM::VLD1d32Twb_fixed:
2552  case ARM::VLD1d64Twb_fixed:
2553  case ARM::VLD1d8Qwb_fixed:
2554  case ARM::VLD1d16Qwb_fixed:
2555  case ARM::VLD1d32Qwb_fixed:
2556  case ARM::VLD1d64Qwb_fixed:
2557  case ARM::VLD1d8wb_register:
2558  case ARM::VLD1d16wb_register:
2559  case ARM::VLD1d32wb_register:
2560  case ARM::VLD1d64wb_register:
2561  case ARM::VLD1q8wb_fixed:
2562  case ARM::VLD1q16wb_fixed:
2563  case ARM::VLD1q32wb_fixed:
2564  case ARM::VLD1q64wb_fixed:
2565  case ARM::VLD1q8wb_register:
2566  case ARM::VLD1q16wb_register:
2567  case ARM::VLD1q32wb_register:
2568  case ARM::VLD1q64wb_register:
2569  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2570  // variant encodes Rm == 0xf. Anything else is a register offset post-
2571  // increment and we need to add the register operand to the instruction.
2572  if (Rm != 0xD && Rm != 0xF &&
2573  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2574  return MCDisassembler::Fail;
2575  break;
2576  case ARM::VLD2d8wb_fixed:
2577  case ARM::VLD2d16wb_fixed:
2578  case ARM::VLD2d32wb_fixed:
2579  case ARM::VLD2b8wb_fixed:
2580  case ARM::VLD2b16wb_fixed:
2581  case ARM::VLD2b32wb_fixed:
2582  case ARM::VLD2q8wb_fixed:
2583  case ARM::VLD2q16wb_fixed:
2584  case ARM::VLD2q32wb_fixed:
2585  break;
2586  }
2587 
2588  return S;
2589 }
2590 
2591 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2592  uint64_t Address, const void *Decoder) {
2593  unsigned type = fieldFromInstruction(Insn, 8, 4);
2594  unsigned align = fieldFromInstruction(Insn, 4, 2);
2595  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2596  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2597  if (type == 10 && align == 3) return MCDisassembler::Fail;
2598 
2599  unsigned load = fieldFromInstruction(Insn, 21, 1);
2600  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2601  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2602 }
2603 
2604 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2605  uint64_t Address, const void *Decoder) {
2606  unsigned size = fieldFromInstruction(Insn, 6, 2);
2607  if (size == 3) return MCDisassembler::Fail;
2608 
2609  unsigned type = fieldFromInstruction(Insn, 8, 4);
2610  unsigned align = fieldFromInstruction(Insn, 4, 2);
2611  if (type == 8 && align == 3) return MCDisassembler::Fail;
2612  if (type == 9 && align == 3) return MCDisassembler::Fail;
2613 
2614  unsigned load = fieldFromInstruction(Insn, 21, 1);
2615  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2616  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2617 }
2618 
2619 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2620  uint64_t Address, const void *Decoder) {
2621  unsigned size = fieldFromInstruction(Insn, 6, 2);
2622  if (size == 3) return MCDisassembler::Fail;
2623 
2624  unsigned align = fieldFromInstruction(Insn, 4, 2);
2625  if (align & 2) return MCDisassembler::Fail;
2626 
2627  unsigned load = fieldFromInstruction(Insn, 21, 1);
2628  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2629  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2630 }
2631 
2632 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2633  uint64_t Address, const void *Decoder) {
2634  unsigned size = fieldFromInstruction(Insn, 6, 2);
2635  if (size == 3) return MCDisassembler::Fail;
2636 
2637  unsigned load = fieldFromInstruction(Insn, 21, 1);
2638  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2639  : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2640 }
2641 
2642 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2643  uint64_t Address, const void *Decoder) {
2645 
2646  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2647  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2648  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2649  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2650  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2651  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2652 
2653  // Writeback Operand
2654  switch (Inst.getOpcode()) {
2655  case ARM::VST1d8wb_fixed:
2656  case ARM::VST1d16wb_fixed:
2657  case ARM::VST1d32wb_fixed:
2658  case ARM::VST1d64wb_fixed:
2659  case ARM::VST1d8wb_register:
2660  case ARM::VST1d16wb_register:
2661  case ARM::VST1d32wb_register:
2662  case ARM::VST1d64wb_register:
2663  case ARM::VST1q8wb_fixed:
2664  case ARM::VST1q16wb_fixed:
2665  case ARM::VST1q32wb_fixed:
2666  case ARM::VST1q64wb_fixed:
2667  case ARM::VST1q8wb_register:
2668  case ARM::VST1q16wb_register:
2669  case ARM::VST1q32wb_register:
2670  case ARM::VST1q64wb_register:
2671  case ARM::VST1d8Twb_fixed:
2672  case ARM::VST1d16Twb_fixed:
2673  case ARM::VST1d32Twb_fixed:
2674  case ARM::VST1d64Twb_fixed:
2675  case ARM::VST1d8Twb_register:
2676  case ARM::VST1d16Twb_register:
2677  case ARM::VST1d32Twb_register:
2678  case ARM::VST1d64Twb_register:
2679  case ARM::VST1d8Qwb_fixed:
2680  case ARM::VST1d16Qwb_fixed:
2681  case ARM::VST1d32Qwb_fixed:
2682  case ARM::VST1d64Qwb_fixed:
2683  case ARM::VST1d8Qwb_register:
2684  case ARM::VST1d16Qwb_register:
2685  case ARM::VST1d32Qwb_register:
2686  case ARM::VST1d64Qwb_register:
2687  case ARM::VST2d8wb_fixed:
2688  case ARM::VST2d16wb_fixed:
2689  case ARM::VST2d32wb_fixed:
2690  case ARM::VST2d8wb_register:
2691  case ARM::VST2d16wb_register:
2692  case ARM::VST2d32wb_register:
2693  case ARM::VST2q8wb_fixed:
2694  case ARM::VST2q16wb_fixed:
2695  case ARM::VST2q32wb_fixed:
2696  case ARM::VST2q8wb_register:
2697  case ARM::VST2q16wb_register:
2698  case ARM::VST2q32wb_register:
2699  case ARM::VST2b8wb_fixed:
2700  case ARM::VST2b16wb_fixed:
2701  case ARM::VST2b32wb_fixed:
2702  case ARM::VST2b8wb_register:
2703  case ARM::VST2b16wb_register:
2704  case ARM::VST2b32wb_register:
2705  if (Rm == 0xF)
2706  return MCDisassembler::Fail;
2708  break;
2709  case ARM::VST3d8_UPD:
2710  case ARM::VST3d16_UPD:
2711  case ARM::VST3d32_UPD:
2712  case ARM::VST3q8_UPD:
2713  case ARM::VST3q16_UPD:
2714  case ARM::VST3q32_UPD:
2715  case ARM::VST4d8_UPD:
2716  case ARM::VST4d16_UPD:
2717  case ARM::VST4d32_UPD:
2718  case ARM::VST4q8_UPD:
2719  case ARM::VST4q16_UPD:
2720  case ARM::VST4q32_UPD:
2721  if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2722  return MCDisassembler::Fail;
2723  break;
2724  default:
2725  break;
2726  }
2727 
2728  // AddrMode6 Base (register+alignment)
2729  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2730  return MCDisassembler::Fail;
2731 
2732  // AddrMode6 Offset (register)
2733  switch (Inst.getOpcode()) {
2734  default:
2735  if (Rm == 0xD)
2737  else if (Rm != 0xF) {
2738  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2739  return MCDisassembler::Fail;
2740  }
2741  break;
2742  case ARM::VST1d8wb_fixed:
2743  case ARM::VST1d16wb_fixed:
2744  case ARM::VST1d32wb_fixed:
2745  case ARM::VST1d64wb_fixed:
2746  case ARM::VST1q8wb_fixed:
2747  case ARM::VST1q16wb_fixed:
2748  case ARM::VST1q32wb_fixed:
2749  case ARM::VST1q64wb_fixed:
2750  case ARM::VST1d8Twb_fixed:
2751  case ARM::VST1d16Twb_fixed:
2752  case ARM::VST1d32Twb_fixed:
2753  case ARM::VST1d64Twb_fixed:
2754  case ARM::VST1d8Qwb_fixed:
2755  case ARM::VST1d16Qwb_fixed:
2756  case ARM::VST1d32Qwb_fixed:
2757  case ARM::VST1d64Qwb_fixed:
2758  case ARM::VST2d8wb_fixed:
2759  case ARM::VST2d16wb_fixed:
2760  case ARM::VST2d32wb_fixed:
2761  case ARM::VST2q8wb_fixed:
2762  case ARM::VST2q16wb_fixed:
2763  case ARM::VST2q32wb_fixed:
2764  case ARM::VST2b8wb_fixed:
2765  case ARM::VST2b16wb_fixed:
2766  case ARM::VST2b32wb_fixed:
2767  break;
2768  }
2769 
2770  // First input register
2771  switch (Inst.getOpcode()) {
2772  case ARM::VST1q16:
2773  case ARM::VST1q32:
2774  case ARM::VST1q64:
2775  case ARM::VST1q8:
2776  case ARM::VST1q16wb_fixed:
2777  case ARM::VST1q16wb_register:
2778  case ARM::VST1q32wb_fixed:
2779  case ARM::VST1q32wb_register:
2780  case ARM::VST1q64wb_fixed:
2781  case ARM::VST1q64wb_register:
2782  case ARM::VST1q8wb_fixed:
2783  case ARM::VST1q8wb_register:
2784  case ARM::VST2d16:
2785  case ARM::VST2d32:
2786  case ARM::VST2d8:
2787  case ARM::VST2d16wb_fixed:
2788  case ARM::VST2d16wb_register:
2789  case ARM::VST2d32wb_fixed:
2790  case ARM::VST2d32wb_register:
2791  case ARM::VST2d8wb_fixed:
2792  case ARM::VST2d8wb_register:
2793  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2794  return MCDisassembler::Fail;
2795  break;
2796  case ARM::VST2b16:
2797  case ARM::VST2b32:
2798  case ARM::VST2b8:
2799  case ARM::VST2b16wb_fixed:
2800  case ARM::VST2b16wb_register:
2801  case ARM::VST2b32wb_fixed:
2802  case ARM::VST2b32wb_register:
2803  case ARM::VST2b8wb_fixed:
2804  case ARM::VST2b8wb_register:
2805  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2806  return MCDisassembler::Fail;
2807  break;
2808  default:
2809  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2810  return MCDisassembler::Fail;
2811  }
2812 
2813  // Second input register
2814  switch (Inst.getOpcode()) {
2815  case ARM::VST3d8:
2816  case ARM::VST3d16:
2817  case ARM::VST3d32:
2818  case ARM::VST3d8_UPD:
2819  case ARM::VST3d16_UPD:
2820  case ARM::VST3d32_UPD:
2821  case ARM::VST4d8:
2822  case ARM::VST4d16:
2823  case ARM::VST4d32:
2824  case ARM::VST4d8_UPD:
2825  case ARM::VST4d16_UPD:
2826  case ARM::VST4d32_UPD:
2827  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2828  return MCDisassembler::Fail;
2829  break;
2830  case ARM::VST3q8:
2831  case ARM::VST3q16:
2832  case ARM::VST3q32:
2833  case ARM::VST3q8_UPD:
2834  case ARM::VST3q16_UPD:
2835  case ARM::VST3q32_UPD:
2836  case ARM::VST4q8:
2837  case ARM::VST4q16:
2838  case ARM::VST4q32:
2839  case ARM::VST4q8_UPD:
2840  case ARM::VST4q16_UPD:
2841  case ARM::VST4q32_UPD:
2842  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2843  return MCDisassembler::Fail;
2844  break;
2845  default:
2846  break;
2847  }
2848 
2849  // Third input register
2850  switch (Inst.getOpcode()) {
2851  case ARM::VST3d8:
2852  case ARM::VST3d16:
2853  case ARM::VST3d32:
2854  case ARM::VST3d8_UPD:
2855  case ARM::VST3d16_UPD:
2856  case ARM::VST3d32_UPD:
2857  case ARM::VST4d8:
2858  case ARM::VST4d16:
2859  case ARM::VST4d32:
2860  case ARM::VST4d8_UPD:
2861  case ARM::VST4d16_UPD:
2862  case ARM::VST4d32_UPD:
2863  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2864  return MCDisassembler::Fail;
2865  break;
2866  case ARM::VST3q8:
2867  case ARM::VST3q16:
2868  case ARM::VST3q32:
2869  case ARM::VST3q8_UPD:
2870  case ARM::VST3q16_UPD:
2871  case ARM::VST3q32_UPD:
2872  case ARM::VST4q8:
2873  case ARM::VST4q16:
2874  case ARM::VST4q32:
2875  case ARM::VST4q8_UPD:
2876  case ARM::VST4q16_UPD:
2877  case ARM::VST4q32_UPD:
2878  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2879  return MCDisassembler::Fail;
2880  break;
2881  default:
2882  break;
2883  }
2884 
2885  // Fourth input register
2886  switch (Inst.getOpcode()) {
2887  case ARM::VST4d8:
2888  case ARM::VST4d16:
2889  case ARM::VST4d32:
2890  case ARM::VST4d8_UPD:
2891  case ARM::VST4d16_UPD:
2892  case ARM::VST4d32_UPD:
2893  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2894  return MCDisassembler::Fail;
2895  break;
2896  case ARM::VST4q8:
2897  case ARM::VST4q16:
2898  case ARM::VST4q32:
2899  case ARM::VST4q8_UPD:
2900  case ARM::VST4q16_UPD:
2901  case ARM::VST4q32_UPD:
2902  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2903  return MCDisassembler::Fail;
2904  break;
2905  default:
2906  break;
2907  }
2908 
2909  return S;
2910 }
2911 
2912 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2913  uint64_t Address, const void *Decoder) {
2915 
2916  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2917  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2918  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2919  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2920  unsigned align = fieldFromInstruction(Insn, 4, 1);
2921  unsigned size = fieldFromInstruction(Insn, 6, 2);
2922 
2923  if (size == 0 && align == 1)
2924  return MCDisassembler::Fail;
2925  align *= (1 << size);
2926 
2927  switch (Inst.getOpcode()) {
2928  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2929  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2930  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2931  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2932  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2933  return MCDisassembler::Fail;
2934  break;
2935  default:
2936  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2937  return MCDisassembler::Fail;
2938  break;
2939  }
2940  if (Rm != 0xF) {
2941  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2942  return MCDisassembler::Fail;
2943  }
2944 
2945  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2946  return MCDisassembler::Fail;
2947  Inst.addOperand(MCOperand::createImm(align));
2948 
2949  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2950  // variant encodes Rm == 0xf. Anything else is a register offset post-
2951  // increment and we need to add the register operand to the instruction.
2952  if (Rm != 0xD && Rm != 0xF &&
2953  !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2954  return MCDisassembler::Fail;
2955 
2956  return S;
2957 }
2958 
2959 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2960  uint64_t Address, const void *Decoder) {
2962 
2963  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2964  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2965  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2966  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2967  unsigned align = fieldFromInstruction(Insn, 4, 1);
2968  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2969  align *= 2*size;
2970 
2971  switch (Inst.getOpcode()) {
2972  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2973  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2974  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2975  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2976  if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2977  return MCDisassembler::Fail;
2978  break;
2979  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2980  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2981  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2982  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2983  if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2984  return MCDisassembler::Fail;
2985  break;
2986  default:
2987  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2988  return MCDisassembler::Fail;
2989  break;
2990  }
2991 
2992  if (Rm != 0xF)
2994 
2995  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2996  return MCDisassembler::Fail;
2997  Inst.addOperand(MCOperand::createImm(align));
2998 
2999  if (Rm != 0xD && Rm != 0xF) {
3000  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3001  return MCDisassembler::Fail;
3002  }
3003 
3004  return S;
3005 }
3006 
3007 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3008  uint64_t Address, const void *Decoder) {
3010 
3011  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3012  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3013  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3014  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3015  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3016 
3017  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3018  return MCDisassembler::Fail;
3019  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3020  return MCDisassembler::Fail;
3021  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3022  return MCDisassembler::Fail;
3023  if (Rm != 0xF) {
3024  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3025  return MCDisassembler::Fail;
3026  }
3027 
3028  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3029  return MCDisassembler::Fail;
3031 
3032  if (Rm == 0xD)
3034  else if (Rm != 0xF) {
3035  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3036  return MCDisassembler::Fail;
3037  }
3038 
3039  return S;
3040 }
3041 
3042 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3043  uint64_t Address, const void *Decoder) {
3045 
3046  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3047  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3048  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3049  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3050  unsigned size = fieldFromInstruction(Insn, 6, 2);
3051  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3052  unsigned align = fieldFromInstruction(Insn, 4, 1);
3053 
3054  if (size == 0x3) {
3055  if (align == 0)
3056  return MCDisassembler::Fail;
3057  align = 16;
3058  } else {
3059  if (size == 2) {
3060  align *= 8;
3061  } else {
3062  size = 1 << size;
3063  align *= 4*size;
3064  }
3065  }
3066 
3067  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3068  return MCDisassembler::Fail;
3069  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3070  return MCDisassembler::Fail;
3071  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3072  return MCDisassembler::Fail;
3073  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3074  return MCDisassembler::Fail;
3075  if (Rm != 0xF) {
3076  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3077  return MCDisassembler::Fail;
3078  }
3079 
3080  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3081  return MCDisassembler::Fail;
3082  Inst.addOperand(MCOperand::createImm(align));
3083 
3084  if (Rm == 0xD)
3086  else if (Rm != 0xF) {
3087  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3088  return MCDisassembler::Fail;
3089  }
3090 
3091  return S;
3092 }
3093 
3094 static DecodeStatus
3096  uint64_t Address, const void *Decoder) {
3098 
3099  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3100  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3101  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3102  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3103  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3104  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3105  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3106  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3107 
3108  if (Q) {
3109  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3110  return MCDisassembler::Fail;
3111  } else {
3112  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3113  return MCDisassembler::Fail;
3114  }
3115 
3116  Inst.addOperand(MCOperand::createImm(imm));
3117 
3118  switch (Inst.getOpcode()) {
3119  case ARM::VORRiv4i16:
3120  case ARM::VORRiv2i32:
3121  case ARM::VBICiv4i16:
3122  case ARM::VBICiv2i32:
3123  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3124  return MCDisassembler::Fail;
3125  break;
3126  case ARM::VORRiv8i16:
3127  case ARM::VORRiv4i32:
3128  case ARM::VBICiv8i16:
3129  case ARM::VBICiv4i32:
3130  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3131  return MCDisassembler::Fail;
3132  break;
3133  default:
3134  break;
3135  }
3136 
3137  return S;
3138 }
3139 
3140 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3141  uint64_t Address, const void *Decoder) {
3143 
3144  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3145  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3146  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3147  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3148  unsigned size = fieldFromInstruction(Insn, 18, 2);
3149 
3150  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3151  return MCDisassembler::Fail;
3152  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3153  return MCDisassembler::Fail;
3154  Inst.addOperand(MCOperand::createImm(8 << size));
3155 
3156  return S;
3157 }
3158 
3159 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3160  uint64_t Address, const void *Decoder) {
3161  Inst.addOperand(MCOperand::createImm(8 - Val));
3162  return MCDisassembler::Success;
3163 }
3164 
3165 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3166  uint64_t Address, const void *Decoder) {
3167  Inst.addOperand(MCOperand::createImm(16 - Val));
3168  return MCDisassembler::Success;
3169 }
3170 
3171 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3172  uint64_t Address, const void *Decoder) {
3173  Inst.addOperand(MCOperand::createImm(32 - Val));
3174  return MCDisassembler::Success;
3175 }
3176 
3177 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3178  uint64_t Address, const void *Decoder) {
3179  Inst.addOperand(MCOperand::createImm(64 - Val));
3180  return MCDisassembler::Success;
3181 }
3182 
3183 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3184  uint64_t Address, const void *Decoder) {
3186 
3187  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3188  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3189  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3190  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3191  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3192  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3193  unsigned op = fieldFromInstruction(Insn, 6, 1);
3194 
3195  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3196  return MCDisassembler::Fail;
3197  if (op) {
3198  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3199  return MCDisassembler::Fail; // Writeback
3200  }
3201 
3202  switch (Inst.getOpcode()) {
3203  case ARM::VTBL2:
3204  case ARM::VTBX2:
3205  if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3206  return MCDisassembler::Fail;
3207  break;
3208  default:
3209  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3210  return MCDisassembler::Fail;
3211  }
3212 
3213  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3214  return MCDisassembler::Fail;
3215 
3216  return S;
3217 }
3218 
3219 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3220  uint64_t Address, const void *Decoder) {
3222 
3223  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3224  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3225 
3226  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3227  return MCDisassembler::Fail;
3228 
3229  switch(Inst.getOpcode()) {
3230  default:
3231  return MCDisassembler::Fail;
3232  case ARM::tADR:
3233  break; // tADR does not explicitly represent the PC as an operand.
3234  case ARM::tADDrSPi:
3235  Inst.addOperand(MCOperand::createReg(ARM::SP));
3236  break;
3237  }
3238 
3239  Inst.addOperand(MCOperand::createImm(imm));
3240  return S;
3241 }
3242 
3243 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3244  uint64_t Address, const void *Decoder) {
3245  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3246  true, 2, Inst, Decoder))
3247  Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3248  return MCDisassembler::Success;
3249 }
3250 
3251 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3252  uint64_t Address, const void *Decoder) {
3253  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3254  true, 4, Inst, Decoder))
3255  Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3256  return MCDisassembler::Success;
3257 }
3258 
3259 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3260  uint64_t Address, const void *Decoder) {
3261  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3262  true, 2, Inst, Decoder))
3263  Inst.addOperand(MCOperand::createImm(Val << 1));
3264  return MCDisassembler::Success;
3265 }
3266 
3267 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3268  uint64_t Address, const void *Decoder) {
3270 
3271  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3272  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3273 
3274  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3275  return MCDisassembler::Fail;
3276  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3277  return MCDisassembler::Fail;
3278 
3279  return S;
3280 }
3281 
3282 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3283  uint64_t Address, const void *Decoder) {
3285 
3286  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3287  unsigned imm = fieldFromInstruction(Val, 3, 5);
3288 
3289  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3290  return MCDisassembler::Fail;
3291  Inst.addOperand(MCOperand::createImm(imm));
3292 
3293  return S;
3294 }
3295 
3296 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3297  uint64_t Address, const void *Decoder) {
3298  unsigned imm = Val << 2;
3299 
3300  Inst.addOperand(MCOperand::createImm(imm));
3301  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3302 
3303  return MCDisassembler::Success;
3304 }
3305 
3306 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3307  uint64_t Address, const void *Decoder) {
3308  Inst.addOperand(MCOperand::createReg(ARM::SP));
3309  Inst.addOperand(MCOperand::createImm(Val));
3310 
3311  return MCDisassembler::Success;
3312 }
3313 
3314 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3315  uint64_t Address, const void *Decoder) {
3317 
3318  unsigned Rn = fieldFromInstruction(Val, 6, 4);
3319  unsigned Rm = fieldFromInstruction(Val, 2, 4);
3320  unsigned imm = fieldFromInstruction(Val, 0, 2);
3321 
3322  // Thumb stores cannot use PC as dest register.
3323  switch (Inst.getOpcode()) {
3324  case ARM::t2STRHs:
3325  case ARM::t2STRBs:
3326  case ARM::t2STRs:
3327  if (Rn == 15)
3328  return MCDisassembler::Fail;
3329  default:
3330  break;
3331  }
3332 
3333  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3334  return MCDisassembler::Fail;
3335  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3336  return MCDisassembler::Fail;
3337  Inst.addOperand(MCOperand::createImm(imm));
3338 
3339  return S;
3340 }
3341 
3342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3343  uint64_t Address, const void *Decoder) {
3345 
3346  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3347  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3348 
3349  const FeatureBitset &featureBits =
3350  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3351 
3352  bool hasMP = featureBits[ARM::FeatureMP];
3353  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3354 
3355  if (Rn == 15) {
3356  switch (Inst.getOpcode()) {
3357  case ARM::t2LDRBs:
3358  Inst.setOpcode(ARM::t2LDRBpci);
3359  break;
3360  case ARM::t2LDRHs:
3361  Inst.setOpcode(ARM::t2LDRHpci);
3362  break;
3363  case ARM::t2LDRSHs:
3364  Inst.setOpcode(ARM::t2LDRSHpci);
3365  break;
3366  case ARM::t2LDRSBs:
3367  Inst.setOpcode(ARM::t2LDRSBpci);
3368  break;
3369  case ARM::t2LDRs:
3370  Inst.setOpcode(ARM::t2LDRpci);
3371  break;
3372  case ARM::t2PLDs:
3373  Inst.setOpcode(ARM::t2PLDpci);
3374  break;
3375  case ARM::t2PLIs:
3376  Inst.setOpcode(ARM::t2PLIpci);
3377  break;
3378  default:
3379  return MCDisassembler::Fail;
3380  }
3381 
3382  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3383  }
3384 
3385  if (Rt == 15) {
3386  switch (Inst.getOpcode()) {
3387  case ARM::t2LDRSHs:
3388  return MCDisassembler::Fail;
3389  case ARM::t2LDRHs:
3390  Inst.setOpcode(ARM::t2PLDWs);
3391  break;
3392  case ARM::t2LDRSBs:
3393  Inst.setOpcode(ARM::t2PLIs);
3394  default:
3395  break;
3396  }
3397  }
3398 
3399  switch (Inst.getOpcode()) {
3400  case ARM::t2PLDs:
3401  break;
3402  case ARM::t2PLIs:
3403  if (!hasV7Ops)
3404  return MCDisassembler::Fail;
3405  break;
3406  case ARM::t2PLDWs:
3407  if (!hasV7Ops || !hasMP)
3408  return MCDisassembler::Fail;
3409  break;
3410  default:
3411  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3412  return MCDisassembler::Fail;
3413  }
3414 
3415  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3416  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3417  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3418  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3419  return MCDisassembler::Fail;
3420 
3421  return S;
3422 }
3423 
3424 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3425  uint64_t Address, const void* Decoder) {
3427 
3428  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3429  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3430  unsigned U = fieldFromInstruction(Insn, 9, 1);
3431  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3432  imm |= (U << 8);
3433  imm |= (Rn << 9);
3434  unsigned add = fieldFromInstruction(Insn, 9, 1);
3435 
3436  const FeatureBitset &featureBits =
3437  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3438 
3439  bool hasMP = featureBits[ARM::FeatureMP];
3440  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3441 
3442  if (Rn == 15) {
3443  switch (Inst.getOpcode()) {
3444  case ARM::t2LDRi8:
3445  Inst.setOpcode(ARM::t2LDRpci);
3446  break;
3447  case ARM::t2LDRBi8:
3448  Inst.setOpcode(ARM::t2LDRBpci);
3449  break;
3450  case ARM::t2LDRSBi8:
3451  Inst.setOpcode(ARM::t2LDRSBpci);
3452  break;
3453  case ARM::t2LDRHi8:
3454  Inst.setOpcode(ARM::t2LDRHpci);
3455  break;
3456  case ARM::t2LDRSHi8:
3457  Inst.setOpcode(ARM::t2LDRSHpci);
3458  break;
3459  case ARM::t2PLDi8:
3460  Inst.setOpcode(ARM::t2PLDpci);
3461  break;
3462  case ARM::t2PLIi8:
3463  Inst.setOpcode(ARM::t2PLIpci);
3464  break;
3465  default:
3466  return MCDisassembler::Fail;
3467  }
3468  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3469  }
3470 
3471  if (Rt == 15) {
3472  switch (Inst.getOpcode()) {
3473  case ARM::t2LDRSHi8:
3474  return MCDisassembler::Fail;
3475  case ARM::t2LDRHi8:
3476  if (!add)
3477  Inst.setOpcode(ARM::t2PLDWi8);
3478  break;
3479  case ARM::t2LDRSBi8:
3480  Inst.setOpcode(ARM::t2PLIi8);
3481  break;
3482  default:
3483  break;
3484  }
3485  }
3486 
3487  switch (Inst.getOpcode()) {
3488  case ARM::t2PLDi8:
3489  break;
3490  case ARM::t2PLIi8:
3491  if (!hasV7Ops)
3492  return MCDisassembler::Fail;
3493  break;
3494  case ARM::t2PLDWi8:
3495  if (!hasV7Ops || !hasMP)
3496  return MCDisassembler::Fail;
3497  break;
3498  default:
3499  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3500  return MCDisassembler::Fail;
3501  }
3502 
3503  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3504  return MCDisassembler::Fail;
3505  return S;
3506 }
3507 
3508 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3509  uint64_t Address, const void* Decoder) {
3511 
3512  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3513  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3514  unsigned imm = fieldFromInstruction(Insn, 0, 12);
3515  imm |= (Rn << 13);
3516 
3517  const FeatureBitset &featureBits =
3518  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3519 
3520  bool hasMP = featureBits[ARM::FeatureMP];
3521  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3522 
3523  if (Rn == 15) {
3524  switch (Inst.getOpcode()) {
3525  case ARM::t2LDRi12:
3526  Inst.setOpcode(ARM::t2LDRpci);
3527  break;
3528  case ARM::t2LDRHi12:
3529  Inst.setOpcode(ARM::t2LDRHpci);
3530  break;
3531  case ARM::t2LDRSHi12:
3532  Inst.setOpcode(ARM::t2LDRSHpci);
3533  break;
3534  case ARM::t2LDRBi12:
3535  Inst.setOpcode(ARM::t2LDRBpci);
3536  break;
3537  case ARM::t2LDRSBi12:
3538  Inst.setOpcode(ARM::t2LDRSBpci);
3539  break;
3540  case ARM::t2PLDi12:
3541  Inst.setOpcode(ARM::t2PLDpci);
3542  break;
3543  case ARM::t2PLIi12:
3544  Inst.setOpcode(ARM::t2PLIpci);
3545  break;
3546  default:
3547  return MCDisassembler::Fail;
3548  }
3549  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3550  }
3551 
3552  if (Rt == 15) {
3553  switch (Inst.getOpcode()) {
3554  case ARM::t2LDRSHi12:
3555  return MCDisassembler::Fail;
3556  case ARM::t2LDRHi12:
3557  Inst.setOpcode(ARM::t2PLDWi12);
3558  break;
3559  case ARM::t2LDRSBi12:
3560  Inst.setOpcode(ARM::t2PLIi12);
3561  break;
3562  default:
3563  break;
3564  }
3565  }
3566 
3567  switch (Inst.getOpcode()) {
3568  case ARM::t2PLDi12:
3569  break;
3570  case ARM::t2PLIi12:
3571  if (!hasV7Ops)
3572  return MCDisassembler::Fail;
3573  break;
3574  case ARM::t2PLDWi12:
3575  if (!hasV7Ops || !hasMP)
3576  return MCDisassembler::Fail;
3577  break;
3578  default:
3579  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3580  return MCDisassembler::Fail;
3581  }
3582 
3583  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3584  return MCDisassembler::Fail;
3585  return S;
3586 }
3587 
3588 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3589  uint64_t Address, const void* Decoder) {
3591 
3592  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3593  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3594  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3595  imm |= (Rn << 9);
3596 
3597  if (Rn == 15) {
3598  switch (Inst.getOpcode()) {
3599  case ARM::t2LDRT:
3600  Inst.setOpcode(ARM::t2LDRpci);
3601  break;
3602  case ARM::t2LDRBT:
3603  Inst.setOpcode(ARM::t2LDRBpci);
3604  break;
3605  case ARM::t2LDRHT:
3606  Inst.setOpcode(ARM::t2LDRHpci);
3607  break;
3608  case ARM::t2LDRSBT:
3609  Inst.setOpcode(ARM::t2LDRSBpci);
3610  break;
3611  case ARM::t2LDRSHT:
3612  Inst.setOpcode(ARM::t2LDRSHpci);
3613  break;
3614  default:
3615  return MCDisassembler::Fail;
3616  }
3617  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3618  }
3619 
3620  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3621  return MCDisassembler::Fail;
3622  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3623  return MCDisassembler::Fail;
3624  return S;
3625 }
3626 
3627 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3628  uint64_t Address, const void* Decoder) {
3630 
3631  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3632  unsigned U = fieldFromInstruction(Insn, 23, 1);
3633  int imm = fieldFromInstruction(Insn, 0, 12);
3634 
3635  const FeatureBitset &featureBits =
3636  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3637 
3638  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3639 
3640  if (Rt == 15) {
3641  switch (Inst.getOpcode()) {
3642  case ARM::t2LDRBpci:
3643  case ARM::t2LDRHpci:
3644  Inst.setOpcode(ARM::t2PLDpci);
3645  break;
3646  case ARM::t2LDRSBpci:
3647  Inst.setOpcode(ARM::t2PLIpci);
3648  break;
3649  case ARM::t2LDRSHpci:
3650  return MCDisassembler::Fail;
3651  default:
3652  break;
3653  }
3654  }
3655 
3656  switch(Inst.getOpcode()) {
3657  case ARM::t2PLDpci:
3658  break;
3659  case ARM::t2PLIpci:
3660  if (!hasV7Ops)
3661  return MCDisassembler::Fail;
3662  break;
3663  default:
3664  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3665  return MCDisassembler::Fail;
3666  }
3667 
3668  if (!U) {
3669  // Special case for #-0.
3670  if (imm == 0)
3671  imm = INT32_MIN;
3672  else
3673  imm = -imm;
3674  }
3675  Inst.addOperand(MCOperand::createImm(imm));
3676 
3677  return S;
3678 }
3679 
3680 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3681  uint64_t Address, const void *Decoder) {
3682  if (Val == 0)
3683  Inst.addOperand(MCOperand::createImm(INT32_MIN));
3684  else {
3685  int imm = Val & 0xFF;
3686 
3687  if (!(Val & 0x100)) imm *= -1;
3688  Inst.addOperand(MCOperand::createImm(imm * 4));
3689  }
3690 
3691  return MCDisassembler::Success;
3692 }
3693 
3694 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3695  uint64_t Address, const void *Decoder) {
3697 
3698  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3699  unsigned imm = fieldFromInstruction(Val, 0, 9);
3700 
3701  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3702  return MCDisassembler::Fail;
3703  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3704  return MCDisassembler::Fail;
3705 
3706  return S;
3707 }
3708 
3710  uint64_t Address, const void *Decoder) {
3712 
3713  unsigned Rn = fieldFromInstruction(Val, 8, 4);
3714  unsigned imm = fieldFromInstruction(Val, 0, 8);
3715 
3716  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3717  return MCDisassembler::Fail;
3718 
3719  Inst.addOperand(MCOperand::createImm(imm));
3720 
3721  return S;
3722 }
3723 
3724 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3725  uint64_t Address, const void *Decoder) {
3726  int imm = Val & 0xFF;
3727  if (Val == 0)
3728  imm = INT32_MIN;
3729  else if (!(Val & 0x100))
3730  imm *= -1;
3731  Inst.addOperand(MCOperand::createImm(imm));
3732 
3733  return MCDisassembler::Success;
3734 }
3735 
3736 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3737  uint64_t Address, const void *Decoder) {
3739 
3740  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3741  unsigned imm = fieldFromInstruction(Val, 0, 9);
3742 
3743  // Thumb stores cannot use PC as dest register.
3744  switch (Inst.getOpcode()) {
3745  case ARM::t2STRT:
3746  case ARM::t2STRBT:
3747  case ARM::t2STRHT:
3748  case ARM::t2STRi8:
3749  case ARM::t2STRHi8:
3750  case ARM::t2STRBi8:
3751  if (Rn == 15)
3752  return MCDisassembler::Fail;
3753  break;
3754  default:
3755  break;
3756  }
3757 
3758  // Some instructions always use an additive offset.
3759  switch (Inst.getOpcode()) {
3760  case ARM::t2LDRT:
3761  case ARM::t2LDRBT:
3762  case ARM::t2LDRHT:
3763  case ARM::t2LDRSBT:
3764  case ARM::t2LDRSHT:
3765  case ARM::t2STRT:
3766  case ARM::t2STRBT:
3767  case ARM::t2STRHT:
3768  imm |= 0x100;
3769  break;
3770  default:
3771  break;
3772  }
3773 
3774  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3775  return MCDisassembler::Fail;
3776  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3777  return MCDisassembler::Fail;
3778 
3779  return S;
3780 }
3781 
3782 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3783  uint64_t Address, const void *Decoder) {
3785 
3786  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3787  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3788  unsigned addr = fieldFromInstruction(Insn, 0, 8);
3789  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3790  addr |= Rn << 9;
3791  unsigned load = fieldFromInstruction(Insn, 20, 1);
3792 
3793  if (Rn == 15) {
3794  switch (Inst.getOpcode()) {
3795  case ARM::t2LDR_PRE:
3796  case ARM::t2LDR_POST:
3797  Inst.setOpcode(ARM::t2LDRpci);
3798  break;
3799  case ARM::t2LDRB_PRE:
3800  case ARM::t2LDRB_POST:
3801  Inst.setOpcode(ARM::t2LDRBpci);
3802  break;
3803  case ARM::t2LDRH_PRE:
3804  case ARM::t2LDRH_POST:
3805  Inst.setOpcode(ARM::t2LDRHpci);
3806  break;
3807  case ARM::t2LDRSB_PRE:
3808  case ARM::t2LDRSB_POST:
3809  if (Rt == 15)
3810  Inst.setOpcode(ARM::t2PLIpci);
3811  else
3812  Inst.setOpcode(ARM::t2LDRSBpci);
3813  break;
3814  case ARM::t2LDRSH_PRE:
3815  case ARM::t2LDRSH_POST:
3816  Inst.setOpcode(ARM::t2LDRSHpci);
3817  break;
3818  default:
3819  return MCDisassembler::Fail;
3820  }
3821  return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3822  }
3823 
3824  if (!load) {
3825  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3826  return MCDisassembler::Fail;
3827  }
3828 
3829  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3830  return MCDisassembler::Fail;
3831 
3832  if (load) {
3833  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3834  return MCDisassembler::Fail;
3835  }
3836 
3837  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3838  return MCDisassembler::Fail;
3839 
3840  return S;
3841 }
3842 
3843 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3844  uint64_t Address, const void *Decoder) {
3846 
3847  unsigned Rn = fieldFromInstruction(Val, 13, 4);
3848  unsigned imm = fieldFromInstruction(Val, 0, 12);
3849 
3850  // Thumb stores cannot use PC as dest register.
3851  switch (Inst.getOpcode()) {
3852  case ARM::t2STRi12:
3853  case ARM::t2STRBi12:
3854  case ARM::t2STRHi12:
3855  if (Rn == 15)
3856  return MCDisassembler::Fail;
3857  default:
3858  break;
3859  }
3860 
3861  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3862  return MCDisassembler::Fail;
3863  Inst.addOperand(MCOperand::createImm(imm));
3864 
3865  return S;
3866 }
3867 
3868 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3869  uint64_t Address, const void *Decoder) {
3870  unsigned imm = fieldFromInstruction(Insn, 0, 7);
3871 
3872  Inst.addOperand(MCOperand::createReg(ARM::SP));
3873  Inst.addOperand(MCOperand::createReg(ARM::SP));
3874  Inst.addOperand(MCOperand::createImm(imm));
3875 
3876  return MCDisassembler::Success;
3877 }
3878 
3879 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3880  uint64_t Address, const void *Decoder) {
3882 
3883  if (Inst.getOpcode() == ARM::tADDrSP) {
3884  unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3885  Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3886 
3887  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3888  return MCDisassembler::Fail;
3889  Inst.addOperand(MCOperand::createReg(ARM::SP));
3890  if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3891  return MCDisassembler::Fail;
3892  } else if (Inst.getOpcode() == ARM::tADDspr) {
3893  unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3894 
3895  Inst.addOperand(MCOperand::createReg(ARM::SP));
3896  Inst.addOperand(MCOperand::createReg(ARM::SP));
3897  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3898  return MCDisassembler::Fail;
3899  }
3900 
3901  return S;
3902 }
3903 
3904 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3905  uint64_t Address, const void *Decoder) {
3906  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3907  unsigned flags = fieldFromInstruction(Insn, 0, 3);
3908 
3909  Inst.addOperand(MCOperand::createImm(imod));
3910  Inst.addOperand(MCOperand::createImm(flags));
3911 
3912  return MCDisassembler::Success;
3913 }
3914 
3915 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3916  uint64_t Address, const void *Decoder) {
3918  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3919  unsigned add = fieldFromInstruction(Insn, 4, 1);
3920 
3921  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3922  return MCDisassembler::Fail;
3923  Inst.addOperand(MCOperand::createImm(add));
3924 
3925  return S;
3926 }
3927 
3928 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3929  uint64_t Address, const void *Decoder) {
3930  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3931  // Note only one trailing zero not two. Also the J1 and J2 values are from
3932  // the encoded instruction. So here change to I1 and I2 values via:
3933  // I1 = NOT(J1 EOR S);
3934  // I2 = NOT(J2 EOR S);
3935  // and build the imm32 with two trailing zeros as documented:
3936  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3937  unsigned S = (Val >> 23) & 1;
3938  unsigned J1 = (Val >> 22) & 1;
3939  unsigned J2 = (Val >> 21) & 1;
3940  unsigned I1 = !(J1 ^ S);
3941  unsigned I2 = !(J2 ^ S);
3942  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3943  int imm32 = SignExtend32<25>(tmp << 1);
3944 
3945  if (!tryAddingSymbolicOperand(Address,
3946  (Address & ~2u) + imm32 + 4,
3947  true, 4, Inst, Decoder))
3948  Inst.addOperand(MCOperand::createImm(imm32));
3949  return MCDisassembler::Success;
3950 }
3951 
3952 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3953  uint64_t Address, const void *Decoder) {
3954  if (Val == 0xA || Val == 0xB)
3955  return MCDisassembler::Fail;
3956 
3957  const FeatureBitset &featureBits =
3958  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3959 
3960  if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3961  return MCDisassembler::Fail;
3962 
3963  Inst.addOperand(MCOperand::createImm(Val));
3964  return MCDisassembler::Success;
3965 }
3966 
3967 static DecodeStatus
3968 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3969  uint64_t Address, const void *Decoder) {
3971 
3972  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3973  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3974 
3975  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3976  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3977  return MCDisassembler::Fail;
3978  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3979  return MCDisassembler::Fail;
3980  return S;
3981 }
3982 
3983 static DecodeStatus
3984 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3985  uint64_t Address, const void *Decoder) {
3987 
3988  unsigned pred = fieldFromInstruction(Insn, 22, 4);
3989  if (pred == 0xE || pred == 0xF) {
3990  unsigned opc = fieldFromInstruction(Insn, 4, 28);
3991  switch (opc) {
3992  default:
3993  return MCDisassembler::Fail;
3994  case 0xf3bf8f4:
3995  Inst.setOpcode(ARM::t2DSB);
3996  break;
3997  case 0xf3bf8f5:
3998  Inst.setOpcode(ARM::t2DMB);
3999  break;
4000  case 0xf3bf8f6:
4001  Inst.setOpcode(ARM::t2ISB);
4002  break;
4003  }
4004 
4005  unsigned imm = fieldFromInstruction(Insn, 0, 4);
4006  return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4007  }
4008 
4009  unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4010  brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4011  brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4012  brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4013  brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4014 
4015  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4016  return MCDisassembler::Fail;
4017  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4018  return MCDisassembler::Fail;
4019 
4020  return S;
4021 }
4022 
4023 // Decode a shifted immediate operand. These basically consist
4024 // of an 8-bit value, and a 4-bit directive that specifies either
4025 // a splat operation or a rotation.
4026 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4027  uint64_t Address, const void *Decoder) {
4028  unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4029  if (ctrl == 0) {
4030  unsigned byte = fieldFromInstruction(Val, 8, 2);
4031  unsigned imm = fieldFromInstruction(Val, 0, 8);
4032  switch (byte) {
4033  case 0:
4034  Inst.addOperand(MCOperand::createImm(imm));
4035  break;
4036  case 1:
4037  Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4038  break;
4039  case 2:
4040  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4041  break;
4042  case 3:
4043  Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4044  (imm << 8) | imm));
4045  break;
4046  }
4047  } else {
4048  unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4049  unsigned rot = fieldFromInstruction(Val, 7, 5);
4050  unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4051  Inst.addOperand(MCOperand::createImm(imm));
4052  }
4053 
4054  return MCDisassembler::Success;
4055 }
4056 
4057 static DecodeStatus
4059  uint64_t Address, const void *Decoder) {
4060  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4061  true, 2, Inst, Decoder))
4062  Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4063  return MCDisassembler::Success;
4064 }
4065 
4067  uint64_t Address,
4068  const void *Decoder) {
4069  // Val is passed in as S:J1:J2:imm10:imm11
4070  // Note no trailing zero after imm11. Also the J1 and J2 values are from
4071  // the encoded instruction. So here change to I1 and I2 values via:
4072  // I1 = NOT(J1 EOR S);
4073  // I2 = NOT(J2 EOR S);
4074  // and build the imm32 with one trailing zero as documented:
4075  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4076  unsigned S = (Val >> 23) & 1;
4077  unsigned J1 = (Val >> 22) & 1;
4078  unsigned J2 = (Val >> 21) & 1;
4079  unsigned I1 = !(J1 ^ S);
4080  unsigned I2 = !(J2 ^ S);
4081  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4082  int imm32 = SignExtend32<25>(tmp << 1);
4083 
4084  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4085  true, 4, Inst, Decoder))
4086  Inst.addOperand(MCOperand::createImm(imm32));
4087  return MCDisassembler::Success;
4088 }
4089 
4090 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4091  uint64_t Address, const void *Decoder) {
4092  if (Val & ~0xf)
4093  return MCDisassembler::Fail;
4094 
4095  Inst.addOperand(MCOperand::createImm(Val));
4096  return MCDisassembler::Success;
4097 }
4098 
4100  uint64_t Address, const void *Decoder) {
4101  if (Val & ~0xf)
4102  return MCDisassembler::Fail;
4103 
4104  Inst.addOperand(MCOperand::createImm(Val));
4105  return MCDisassembler::Success;
4106 }
4107 
4108 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4109  uint64_t Address, const void *Decoder) {
4111  const FeatureBitset &FeatureBits =
4112  ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4113 
4114  if (FeatureBits[ARM::FeatureMClass]) {
4115  unsigned ValLow = Val & 0xff;
4116 
4117  // Validate the SYSm value first.
4118  switch (ValLow) {
4119  case 0: // apsr
4120  case 1: // iapsr
4121  case 2: // eapsr
4122  case 3: // xpsr
4123  case 5: // ipsr
4124  case 6: // epsr
4125  case 7: // iepsr
4126  case 8: // msp
4127  case 9: // psp
4128  case 16: // primask
4129  case 20: // control
4130  break;
4131  case 17: // basepri
4132  case 18: // basepri_max
4133  case 19: // faultmask
4134  if (!(FeatureBits[ARM::HasV7Ops]))
4135  // Values basepri, basepri_max and faultmask are only valid for v7m.
4136  return MCDisassembler::Fail;
4137  break;
4138  case 0x8a: // msplim_ns
4139  case 0x8b: // psplim_ns
4140  case 0x91: // basepri_ns
4141  case 0x92: // basepri_max_ns
4142  case 0x93: // faultmask_ns
4143  if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4144  return MCDisassembler::Fail;
4146  case 10: // msplim
4147  case 11: // psplim
4148  case 0x88: // msp_ns
4149  case 0x89: // psp_ns
4150  case 0x90: // primask_ns
4151  case 0x94: // control_ns
4152  case 0x98: // sp_ns
4153  if (!(FeatureBits[ARM::Feature8MSecExt]))
4154  return MCDisassembler::Fail;
4155  break;
4156  default:
4157  return MCDisassembler::Fail;
4158  }
4159 
4160  if (Inst.getOpcode() == ARM::t2MSR_M) {
4161  unsigned Mask = fieldFromInstruction(Val, 10, 2);
4162  if (!(FeatureBits[ARM::HasV7Ops])) {
4163  // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4164  // unpredictable.
4165  if (Mask != 2)
4167  }
4168  else {
4169  // The ARMv7-M architecture stores an additional 2-bit mask value in
4170  // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4171  // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4172  // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4173  // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4174  // only if the processor includes the DSP extension.
4175  if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4176  (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4178  }
4179  }
4180  } else {
4181  // A/R class
4182  if (Val == 0)
4183  return MCDisassembler::Fail;
4184  }
4185  Inst.addOperand(MCOperand::createImm(Val));
4186  return S;
4187 }
4188 
4189 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4190  uint64_t Address, const void *Decoder) {
4191  unsigned R = fieldFromInstruction(Val, 5, 1);
4192  unsigned SysM = fieldFromInstruction(Val, 0, 5);
4193 
4194  // The table of encodings for these banked registers comes from B9.2.3 of the
4195  // ARM ARM. There are patterns, but nothing regular enough to make this logic
4196  // neater. So by fiat, these values are UNPREDICTABLE:
4197  if (!R) {
4198  if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4199  SysM == 0x1a || SysM == 0x1b)
4200  return MCDisassembler::SoftFail;
4201  } else {
4202  if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4203  SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4204  return MCDisassembler::SoftFail;
4205  }
4206 
4207  Inst.addOperand(MCOperand::createImm(Val));
4208  return MCDisassembler::Success;
4209 }
4210 
4211 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4212  uint64_t Address, const void *Decoder) {
4214 
4215  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4216  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4217  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4218 
4219  if (Rn == 0xF)
4221 
4222  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4223  return MCDisassembler::Fail;
4224  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4225  return MCDisassembler::Fail;
4226  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4227  return MCDisassembler::Fail;
4228 
4229  return S;
4230 }
4231 
4232 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4233  uint64_t Address,
4234  const void *Decoder) {
4236 
4237  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4238  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4239  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4240  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4241 
4242  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4243  return MCDisassembler::Fail;
4244 
4245  if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4247 
4248  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4249  return MCDisassembler::Fail;
4250  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4251  return MCDisassembler::Fail;
4252  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4253  return MCDisassembler::Fail;
4254 
4255  return S;
4256 }
4257 
4258 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4259  uint64_t Address, const void *Decoder) {
4261 
4262  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4263  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4264  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4265  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4266  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4267  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4268 
4269  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4270 
4271  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4272  return MCDisassembler::Fail;
4273  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4274  return MCDisassembler::Fail;
4275  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4276  return MCDisassembler::Fail;
4277  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4278  return MCDisassembler::Fail;
4279 
4280  return S;
4281 }
4282 
4283 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4284  uint64_t Address, const void *Decoder) {
4286 
4287  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4288  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4289  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4290  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4291  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4292  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4293  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4294 
4295  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4296  if (Rm == 0xF) S = MCDisassembler::SoftFail;
4297 
4298  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4299  return MCDisassembler::Fail;
4300  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4301  return MCDisassembler::Fail;
4302  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4303  return MCDisassembler::Fail;
4304  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4305  return MCDisassembler::Fail;
4306 
4307  return S;
4308 }
4309 
4310 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4311  uint64_t Address, const void *Decoder) {
4313 
4314  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4315  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4316  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4317  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4318  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4319  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4320 
4321  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4322 
4323  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4324  return MCDisassembler::Fail;
4325  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4326  return MCDisassembler::Fail;
4327  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4328  return MCDisassembler::Fail;
4329  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4330  return MCDisassembler::Fail;
4331 
4332  return S;
4333 }
4334 
4335 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4336  uint64_t Address, const void *Decoder) {
4338 
4339  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4340  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4341  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4342  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4343  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4344  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4345 
4346  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4347 
4348  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4349  return MCDisassembler::Fail;
4350  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4351  return MCDisassembler::Fail;
4352  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4353  return MCDisassembler::Fail;
4354  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4355  return MCDisassembler::Fail;
4356 
4357  return S;
4358 }
4359 
4360 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4361  uint64_t Address, const void *Decoder) {
4363 
4364  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4365  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4366  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4367  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4368  unsigned size = fieldFromInstruction(Insn, 10, 2);
4369 
4370  unsigned align = 0;
4371  unsigned index = 0;
4372  switch (size) {
4373  default:
4374  return MCDisassembler::Fail;
4375  case 0:
4376  if (fieldFromInstruction(Insn, 4, 1))
4377  return MCDisassembler::Fail; // UNDEFINED
4378  index = fieldFromInstruction(Insn, 5, 3);
4379  break;
4380  case 1:
4381  if (fieldFromInstruction(Insn, 5, 1))
4382  return MCDisassembler::Fail; // UNDEFINED
4383  index = fieldFromInstruction(Insn, 6, 2);
4384  if (fieldFromInstruction(Insn, 4, 1))
4385  align = 2;
4386  break;
4387  case 2:
4388  if (fieldFromInstruction(Insn, 6, 1))
4389  return MCDisassembler::Fail; // UNDEFINED
4390  index = fieldFromInstruction(Insn, 7, 1);
4391 
4392  switch (fieldFromInstruction(Insn, 4, 2)) {
4393  case 0 :
4394  align = 0; break;
4395  case 3:
4396  align = 4; break;
4397  default:
4398  return MCDisassembler::Fail;
4399  }
4400  break;
4401  }
4402 
4403  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4404  return MCDisassembler::Fail;
4405  if (Rm != 0xF) { // Writeback
4406  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4407  return MCDisassembler::Fail;
4408  }
4409  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4410  return MCDisassembler::Fail;
4411  Inst.addOperand(MCOperand::createImm(align));
4412  if (Rm != 0xF) {
4413  if (Rm != 0xD) {
4414  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4415  return MCDisassembler::Fail;
4416  } else
4418  }
4419 
4420  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4421  return MCDisassembler::Fail;
4422  Inst.addOperand(MCOperand::createImm(index));
4423 
4424  return S;
4425 }
4426 
4427 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4428  uint64_t Address, const void *Decoder) {
4430 
4431  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4432  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4433  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4434  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4435  unsigned size = fieldFromInstruction(Insn, 10, 2);
4436 
4437  unsigned align = 0;
4438  unsigned index = 0;
4439  switch (size) {
4440  default:
4441  return MCDisassembler::Fail;
4442  case 0:
4443  if (fieldFromInstruction(Insn, 4, 1))
4444  return MCDisassembler::Fail; // UNDEFINED
4445  index = fieldFromInstruction(Insn, 5, 3);
4446  break;
4447  case 1:
4448  if (fieldFromInstruction(Insn, 5, 1))
4449  return MCDisassembler::Fail; // UNDEFINED
4450  index = fieldFromInstruction(Insn, 6, 2);
4451  if (fieldFromInstruction(Insn, 4, 1))
4452  align = 2;
4453  break;
4454  case 2:
4455  if (fieldFromInstruction(Insn, 6, 1))
4456  return MCDisassembler::Fail; // UNDEFINED
4457  index = fieldFromInstruction(Insn, 7, 1);
4458 
4459  switch (fieldFromInstruction(Insn, 4, 2)) {
4460  case 0:
4461  align = 0; break;
4462  case 3:
4463  align = 4; break;
4464  default:
4465  return MCDisassembler::Fail;
4466  }
4467  break;
4468  }
4469 
4470  if (Rm != 0xF) { // Writeback
4471  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4472  return MCDisassembler::Fail;
4473  }
4474  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4475  return MCDisassembler::Fail;
4476  Inst.addOperand(MCOperand::createImm(align));
4477  if (Rm != 0xF) {
4478  if (Rm != 0xD) {
4479  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4480  return MCDisassembler::Fail;
4481  } else
4483  }
4484 
4485  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4486  return MCDisassembler::Fail;
4487  Inst.addOperand(MCOperand::createImm(index));
4488 
4489  return S;
4490 }
4491 
4492 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4493  uint64_t Address, const void *Decoder) {
4495 
4496  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4497  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4498  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4499  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4500  unsigned size = fieldFromInstruction(Insn, 10, 2);
4501 
4502  unsigned align = 0;
4503  unsigned index = 0;
4504  unsigned inc = 1;
4505  switch (size) {
4506  default:
4507  return MCDisassembler::Fail;
4508  case 0:
4509  index = fieldFromInstruction(Insn, 5, 3);
4510  if (fieldFromInstruction(Insn, 4, 1))
4511  align = 2;
4512  break;
4513  case 1:
4514  index = fieldFromInstruction(Insn, 6, 2);
4515  if (fieldFromInstruction(Insn, 4, 1))
4516  align = 4;
4517  if (fieldFromInstruction(Insn, 5, 1))
4518  inc = 2;
4519  break;
4520  case 2:
4521  if (fieldFromInstruction(Insn, 5, 1))
4522  return MCDisassembler::Fail; // UNDEFINED
4523  index = fieldFromInstruction(Insn, 7, 1);
4524  if (fieldFromInstruction(Insn, 4, 1) != 0)
4525  align = 8;
4526  if (fieldFromInstruction(Insn, 6, 1))
4527  inc = 2;
4528  break;
4529  }
4530 
4531  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4532  return MCDisassembler::Fail;
4533  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4534  return MCDisassembler::Fail;
4535  if (Rm != 0xF) { // Writeback
4536  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4537  return MCDisassembler::Fail;
4538  }
4539  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4540  return MCDisassembler::Fail;
4541  Inst.addOperand(MCOperand::createImm(align));
4542  if (Rm != 0xF) {
4543  if (Rm != 0xD) {
4544  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4545  return MCDisassembler::Fail;
4546  } else
4548  }
4549 
4550  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4551  return MCDisassembler::Fail;
4552  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4553  return MCDisassembler::Fail;
4554  Inst.addOperand(MCOperand::createImm(index));
4555 
4556  return S;
4557 }
4558 
4559 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4560  uint64_t Address, const void *Decoder) {
4562 
4563  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4564  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4565  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4566  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4567  unsigned size = fieldFromInstruction(Insn, 10, 2);
4568 
4569  unsigned align = 0;
4570  unsigned index = 0;
4571  unsigned inc = 1;
4572  switch (size) {
4573  default:
4574  return MCDisassembler::Fail;
4575  case 0:
4576  index = fieldFromInstruction(Insn, 5, 3);
4577  if (fieldFromInstruction(Insn, 4, 1))
4578  align = 2;
4579  break;
4580  case 1:
4581  index = fieldFromInstruction(Insn, 6, 2);
4582  if (fieldFromInstruction(Insn, 4, 1))
4583  align = 4;
4584  if (fieldFromInstruction(Insn, 5, 1))
4585  inc = 2;
4586  break;
4587  case 2:
4588  if (fieldFromInstruction(Insn, 5, 1))
4589  return MCDisassembler::Fail; // UNDEFINED
4590  index = fieldFromInstruction(Insn, 7, 1);
4591  if (fieldFromInstruction(Insn, 4, 1) != 0)
4592  align = 8;
4593  if (fieldFromInstruction(Insn, 6, 1))
4594  inc = 2;
4595  break;
4596  }
4597 
4598  if (Rm != 0xF) { // Writeback
4599  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4600  return MCDisassembler::Fail;
4601  }
4602  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4603  return MCDisassembler::Fail;
4604  Inst.addOperand(MCOperand::createImm(align));
4605  if (Rm != 0xF) {
4606  if (Rm != 0xD) {
4607  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4608  return MCDisassembler::Fail;
4609  } else
4611  }
4612 
4613  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4614  return MCDisassembler::Fail;
4615  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4616  return MCDisassembler::Fail;
4617  Inst.addOperand(MCOperand::createImm(index));
4618 
4619  return S;
4620 }
4621 
4622 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4623  uint64_t Address, const void *Decoder) {
4625 
4626  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4627  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4628  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4629  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4630  unsigned size = fieldFromInstruction(Insn, 10, 2);
4631 
4632  unsigned align = 0;
4633  unsigned index = 0;
4634  unsigned inc = 1;
4635  switch (size) {
4636  default:
4637  return MCDisassembler::Fail;
4638  case 0:
4639  if (fieldFromInstruction(Insn, 4, 1))
4640  return MCDisassembler::Fail; // UNDEFINED
4641  index = fieldFromInstruction(Insn, 5, 3);
4642  break;
4643  case 1:
4644  if (fieldFromInstruction(Insn, 4, 1))
4645  return MCDisassembler::Fail; // UNDEFINED
4646  index = fieldFromInstruction(Insn, 6, 2);
4647  if (fieldFromInstruction(Insn, 5, 1))
4648  inc = 2;
4649  break;
4650  case 2:
4651  if (fieldFromInstruction(Insn, 4, 2))
4652  return MCDisassembler::Fail; // UNDEFINED
4653  index = fieldFromInstruction(Insn, 7, 1);
4654  if (fieldFromInstruction(Insn, 6, 1))
4655  inc = 2;
4656  break;
4657  }
4658 
4659  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4660  return MCDisassembler::Fail;
4661  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4662  return MCDisassembler::Fail;
4663  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4664  return MCDisassembler::Fail;
4665 
4666  if (Rm != 0xF) { // Writeback
4667  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4668  return MCDisassembler::Fail;
4669  }
4670  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4671  return MCDisassembler::Fail;
4672  Inst.addOperand(MCOperand::createImm(align));
4673  if (Rm != 0xF) {
4674  if (Rm != 0xD) {
4675  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4676  return MCDisassembler::Fail;
4677  } else
4679  }
4680 
4681  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4682  return MCDisassembler::Fail;
4683  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4684  return MCDisassembler::Fail;
4685  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4686  return MCDisassembler::Fail;
4687  Inst.addOperand(MCOperand::createImm(index));
4688 
4689  return S;
4690 }
4691 
4692 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4693  uint64_t Address, const void *Decoder) {
4695 
4696  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4697  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4698  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4699  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4700  unsigned size = fieldFromInstruction(Insn, 10, 2);
4701 
4702  unsigned align = 0;
4703  unsigned index = 0;
4704  unsigned inc = 1;
4705  switch (size) {
4706  default:
4707  return MCDisassembler::Fail;
4708  case 0:
4709  if (fieldFromInstruction(Insn, 4, 1))
4710  return MCDisassembler::Fail; // UNDEFINED
4711  index = fieldFromInstruction(Insn, 5, 3);
4712  break;
4713  case 1:
4714  if (fieldFromInstruction(Insn, 4, 1))
4715  return MCDisassembler::Fail; // UNDEFINED
4716  index = fieldFromInstruction(Insn, 6, 2);
4717  if (fieldFromInstruction(Insn, 5, 1))
4718  inc = 2;
4719  break;
4720  case 2:
4721  if (fieldFromInstruction(Insn, 4, 2))
4722  return MCDisassembler::Fail; // UNDEFINED
4723  index = fieldFromInstruction(Insn, 7, 1);
4724  if (fieldFromInstruction(Insn, 6, 1))
4725  inc = 2;
4726  break;
4727  }
4728 
4729  if (Rm != 0xF) { // Writeback
4730  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4731  return MCDisassembler::Fail;
4732  }
4733  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4734  return MCDisassembler::Fail;
4735  Inst.addOperand(MCOperand::createImm(align));
4736  if (Rm != 0xF) {
4737  if (Rm != 0xD) {
4738  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4739  return MCDisassembler::Fail;
4740  } else
4742  }
4743 
4744  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4745  return MCDisassembler::Fail;
4746  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4747  return MCDisassembler::Fail;
4748  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4749  return MCDisassembler::Fail;
4750  Inst.addOperand(MCOperand::createImm(index));
4751 
4752  return S;
4753 }
4754 
4755 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4756  uint64_t Address, const void *Decoder) {
4758 
4759  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4760  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4761  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4762  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4763  unsigned size = fieldFromInstruction(Insn, 10, 2);
4764 
4765  unsigned align = 0;
4766  unsigned index = 0;
4767  unsigned inc = 1;
4768  switch (size) {
4769  default:
4770  return MCDisassembler::Fail;
4771  case 0:
4772  if (fieldFromInstruction(Insn, 4, 1))
4773  align = 4;
4774  index = fieldFromInstruction(Insn, 5, 3);
4775  break;
4776  case 1:
4777  if (fieldFromInstruction(Insn, 4, 1))
4778  align = 8;
4779  index = fieldFromInstruction(Insn, 6, 2);
4780  if (fieldFromInstruction(Insn, 5, 1))
4781  inc = 2;
4782  break;
4783  case 2:
4784  switch (fieldFromInstruction(Insn, 4, 2)) {
4785  case 0:
4786  align = 0; break;
4787  case 3:
4788  return MCDisassembler::Fail;
4789  default:
4790  align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4791  }
4792 
4793  index = fieldFromInstruction(Insn, 7, 1);
4794  if (fieldFromInstruction(Insn, 6, 1))
4795  inc = 2;
4796  break;
4797  }
4798 
4799  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4800  return MCDisassembler::Fail;
4801  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4802  return MCDisassembler::Fail;
4803  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4804  return MCDisassembler::Fail;
4805  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4806  return MCDisassembler::Fail;
4807 
4808  if (Rm != 0xF) { // Writeback
4809  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4810  return MCDisassembler::Fail;
4811  }
4812  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4813  return MCDisassembler::Fail;
4814  Inst.addOperand(MCOperand::createImm(align));
4815  if (Rm != 0xF) {
4816  if (Rm != 0xD) {
4817  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4818  return MCDisassembler::Fail;
4819  } else
4821  }
4822 
4823  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4824  return MCDisassembler::Fail;
4825  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4826  return MCDisassembler::Fail;
4827  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4828  return MCDisassembler::Fail;
4829  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4830  return MCDisassembler::Fail;
4831  Inst.addOperand(MCOperand::createImm(index));
4832 
4833  return S;
4834 }
4835 
4836 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4837  uint64_t Address, const void *Decoder) {
4839 
4840  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4841  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4842  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4843  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4844  unsigned size = fieldFromInstruction(Insn, 10, 2);
4845 
4846  unsigned align = 0;
4847  unsigned index = 0;
4848  unsigned inc = 1;
4849  switch (size) {
4850  default:
4851  return MCDisassembler::Fail;
4852  case 0:
4853  if (fieldFromInstruction(Insn, 4, 1))
4854  align = 4;
4855  index = fieldFromInstruction(Insn, 5, 3);
4856  break;
4857  case 1:
4858  if (fieldFromInstruction(Insn, 4, 1))
4859  align = 8;
4860  index = fieldFromInstruction(Insn, 6, 2);
4861  if (fieldFromInstruction(Insn, 5, 1))
4862  inc = 2;
4863  break;
4864  case 2:
4865  switch (fieldFromInstruction(Insn, 4, 2)) {
4866  case 0:
4867  align = 0; break;
4868  case 3:
4869  return MCDisassembler::Fail;
4870  default:
4871  align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4872  }
4873 
4874  index = fieldFromInstruction(Insn, 7, 1);
4875  if (fieldFromInstruction(Insn, 6, 1))
4876  inc = 2;
4877  break;
4878  }
4879 
4880  if (Rm != 0xF) { // Writeback
4881  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4882  return MCDisassembler::Fail;
4883  }
4884  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4885  return MCDisassembler::Fail;
4886  Inst.addOperand(MCOperand::createImm(align));
4887  if (Rm != 0xF) {
4888  if (Rm != 0xD) {
4889  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4890  return MCDisassembler::Fail;
4891  } else
4893  }
4894 
4895  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4896  return MCDisassembler::Fail;
4897  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4898  return MCDisassembler::Fail;
4899  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4900  return MCDisassembler::Fail;
4901  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4902  return MCDisassembler::Fail;
4903  Inst.addOperand(MCOperand::createImm(index));
4904 
4905  return S;
4906 }
4907 
4908 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4909  uint64_t Address, const void *Decoder) {
4911  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4912  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4913  unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4914  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4915  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4916 
4917  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4919 
4920  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4921  return MCDisassembler::Fail;
4922  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4923  return MCDisassembler::Fail;
4924  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4925  return MCDisassembler::Fail;
4926  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4927  return MCDisassembler::Fail;
4928  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4929  return MCDisassembler::Fail;
4930 
4931  return S;
4932 }
4933 
4934 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4935  uint64_t Address, const void *Decoder) {
4937  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4938  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4939  unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4940  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4941  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4942 
4943  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4945 
4946  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4947  return MCDisassembler::Fail;
4948  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4949  return MCDisassembler::Fail;
4950  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4951  return MCDisassembler::Fail;
4952  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4953  return MCDisassembler::Fail;
4954  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4955  return MCDisassembler::Fail;
4956 
4957  return S;
4958 }
4959 
4960 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4961  uint64_t Address, const void *Decoder) {
4963  unsigned pred = fieldFromInstruction(Insn, 4, 4);
4964  unsigned mask = fieldFromInstruction(Insn, 0, 4);
4965 
4966  if (pred == 0xF) {
4967  pred = 0xE;
4969  }
4970 
4971  if (mask == 0x0)
4972  return MCDisassembler::Fail;
4973 
4974  Inst.addOperand(MCOperand::createImm(pred));
4975  Inst.addOperand(MCOperand::createImm(mask));
4976  return S;
4977 }
4978 
4979 static DecodeStatus
4980 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4981  uint64_t Address, const void *Decoder) {
4983 
4984  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4985  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4986  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4987  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4988  unsigned W = fieldFromInstruction(Insn, 21, 1);
4989  unsigned U = fieldFromInstruction(Insn, 23, 1);
4990  unsigned P = fieldFromInstruction(Insn, 24, 1);
4991  bool writeback = (W == 1) | (P == 0);
4992 
4993  addr |= (U << 8) | (Rn << 9);
4994 
4995  if (writeback && (Rn == Rt || Rn == Rt2))
4997  if (Rt == Rt2)
4999 
5000  // Rt
5001  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5002  return MCDisassembler::Fail;
5003  // Rt2
5004  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5005  return MCDisassembler::Fail;
5006  // Writeback operand
5007  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5008  return MCDisassembler::Fail;
5009  // addr
5010  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5011  return MCDisassembler::Fail;
5012 
5013  return S;
5014 }
5015 
5016 static DecodeStatus
5017 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5018  uint64_t Address, const void *Decoder) {
5020 
5021  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5022  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5023  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5024  unsigned addr = fieldFromInstruction(Insn, 0, 8);
5025  unsigned W = fieldFromInstruction(Insn, 21, 1);
5026  unsigned U = fieldFromInstruction(Insn, 23, 1);
5027  unsigned P = fieldFromInstruction(Insn, 24, 1);
5028  bool writeback = (W == 1) | (P == 0);
5029 
5030  addr |= (U << 8) | (Rn << 9);
5031 
5032  if (writeback && (Rn == Rt || Rn == Rt2))
5034 
5035  // Writeback operand
5036  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5037  return MCDisassembler::Fail;
5038  // Rt
5039  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5040  return MCDisassembler::Fail;
5041  // Rt2
5042  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5043  return MCDisassembler::Fail;
5044  // addr
5045  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5046  return MCDisassembler::Fail;
5047 
5048  return S;
5049 }
5050 
5052  uint64_t Address, const void *Decoder) {
5053  unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5054  unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5055  if (sign1 != sign2) return MCDisassembler::Fail;
5056 
5057  unsigned Val = fieldFromInstruction(Insn, 0, 8);
5058  Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5059  Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5060  Val |= sign1 << 12;
5061  Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5062 
5063  return MCDisassembler::Success;
5064 }
5065 
5067  uint64_t Address,
5068  const void *Decoder) {
5070 
5071  // Shift of "asr #32" is not allowed in Thumb2 mode.
5072  if (Val == 0x20) S = MCDisassembler::Fail;
5073  Inst.addOperand(MCOperand::createImm(Val));
5074  return S;
5075 }
5076 
5077 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5078  uint64_t Address, const void *Decoder) {
5079  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5080  unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5081  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5082  unsigned pred = fieldFromInstruction(Insn, 28, 4);
5083 
5084  if (pred == 0xF)
5085  return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5086 
5088 
5089  if (Rt == Rn || Rn == Rt2)
5091 
5092  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5093  return MCDisassembler::Fail;
5094  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5095  return MCDisassembler::Fail;
5096  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5097  return MCDisassembler::Fail;
5098  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5099  return MCDisassembler::Fail;
5100 
5101  return S;
5102 }
5103 
5104 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5105  uint64_t Address, const void *Decoder) {
5106  const FeatureBitset &featureBits =
5107  ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5108  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5109 
5110  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5111  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5112  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5113  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5114  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5115  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5116  unsigned op = fieldFromInstruction(Insn, 5, 1);
5117 
5119 
5120  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5121  if (!(imm & 0x38)) {
5122  if (cmode == 0xF) {
5123  if (op == 1) return MCDisassembler::Fail;
5124  Inst.setOpcode(ARM::VMOVv2f32);
5125  }
5126  if (hasFullFP16) {
5127  if (cmode == 0xE) {
5128  if (op == 1) {
5129  Inst.setOpcode(ARM::VMOVv1i64);
5130  } else {
5131  Inst.setOpcode(ARM::VMOVv8i8);
5132  }
5133  }
5134  if (cmode == 0xD) {
5135  if (op == 1) {
5136  Inst.setOpcode(ARM::VMVNv2i32);
5137  } else {
5138  Inst.setOpcode(ARM::VMOVv2i32);
5139  }
5140  }
5141  if (cmode == 0xC) {
5142  if (op == 1) {
5143  Inst.setOpcode(ARM::VMVNv2i32);
5144  } else {
5145  Inst.setOpcode(ARM::VMOVv2i32);
5146  }
5147  }
5148  }
5149  return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5150  }
5151 
5152  if (!(imm & 0x20)) return MCDisassembler::Fail;
5153 
5154  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5155  return MCDisassembler::Fail;
5156  if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5157  return MCDisassembler::Fail;
5158  Inst.addOperand(MCOperand::createImm(64 - imm));
5159 
5160  return S;
5161 }
5162 
5163 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5164  uint64_t Address, const void *Decoder) {
5165  const FeatureBitset &featureBits =
5166  ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5167  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5168 
5169  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5170  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5171  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5172  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5173  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5174  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5175  unsigned op = fieldFromInstruction(Insn, 5, 1);
5176 
5178 
5179  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5180  if (!(imm & 0x38)) {
5181  if (cmode == 0xF) {
5182  if (op == 1) return MCDisassembler::Fail;
5183  Inst.setOpcode(ARM::VMOVv4f32);
5184  }
5185  if (hasFullFP16) {
5186  if (cmode == 0xE) {
5187  if (op == 1) {
5188  Inst.setOpcode(ARM::VMOVv2i6