LLVM  10.0.0svn
ARMHazardRecognizer.cpp
Go to the documentation of this file.
1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMHazardRecognizer.h"
10 #include "ARMBaseInstrInfo.h"
11 #include "ARMBaseRegisterInfo.h"
12 #include "ARMSubtarget.h"
16 using namespace llvm;
17 
19  const TargetRegisterInfo &TRI) {
20  // FIXME: Detect integer instructions properly.
21  const MCInstrDesc &MCID = MI->getDesc();
22  unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
23  if (MI->mayStore())
24  return false;
25  unsigned Opcode = MCID.getOpcode();
26  if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
27  return false;
28  if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
29  return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
30  return false;
31 }
32 
35  assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
36 
37  MachineInstr *MI = SU->getInstr();
38 
39  if (!MI->isDebugInstr()) {
40  // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
41  // a VMLA / VMLS will cause 4 cycle stall.
42  const MCInstrDesc &MCID = MI->getDesc();
43  if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
44  MachineInstr *DefMI = LastMI;
45  const MCInstrDesc &LastMCID = LastMI->getDesc();
46  const MachineFunction *MF = MI->getParent()->getParent();
47  const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
48  MF->getSubtarget().getInstrInfo());
49 
50  // Skip over one non-VFP / NEON instruction.
51  if (!LastMI->isBarrier() &&
52  !(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) &&
55  if (I != LastMI->getParent()->begin()) {
56  I = std::prev(I);
57  DefMI = &*I;
58  }
59  }
60 
61  if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
62  (TII.canCauseFpMLxStall(MI->getOpcode()) ||
63  hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
64  // Try to schedule another instruction for the next 4 cycles.
65  if (FpMLxStalls == 0)
66  FpMLxStalls = 4;
67  return Hazard;
68  }
69  }
70  }
71 
73 }
74 
76  LastMI = nullptr;
77  FpMLxStalls = 0;
79 }
80 
82  MachineInstr *MI = SU->getInstr();
83  if (!MI->isDebugInstr()) {
84  LastMI = MI;
85  FpMLxStalls = 0;
86  }
87 
89 }
90 
92  if (FpMLxStalls && --FpMLxStalls == 0)
93  // Stalled for 4 cycles but still can't schedule any other instructions.
94  LastMI = nullptr;
96 }
97 
99  llvm_unreachable("reverse ARM hazard checking unsupported");
100 }
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:832
unsigned const TargetRegisterInfo * TRI
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:658
const ARMSubtarget & getSubtarget() const
virtual const TargetInstrInfo * getInstrInfo() const
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:822
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI)
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
MachineInstrBuilder MachineInstrBuilder & DefMI
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:218
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:642
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...