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ARMHazardRecognizer.cpp
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1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMHazardRecognizer.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMBaseRegisterInfo.h"
13 #include "ARMSubtarget.h"
17 using namespace llvm;
18 
20  const TargetRegisterInfo &TRI) {
21  // FIXME: Detect integer instructions properly.
22  const MCInstrDesc &MCID = MI->getDesc();
23  unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
24  if (MI->mayStore())
25  return false;
26  unsigned Opcode = MCID.getOpcode();
27  if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
28  return false;
29  if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
30  return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
31  return false;
32 }
33 
36  assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
37 
38  MachineInstr *MI = SU->getInstr();
39 
40  if (!MI->isDebugValue()) {
41  // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
42  // a VMLA / VMLS will cause 4 cycle stall.
43  const MCInstrDesc &MCID = MI->getDesc();
44  if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
45  MachineInstr *DefMI = LastMI;
46  const MCInstrDesc &LastMCID = LastMI->getDesc();
47  const MachineFunction *MF = MI->getParent()->getParent();
48  const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
49  MF->getSubtarget().getInstrInfo());
50 
51  // Skip over one non-VFP / NEON instruction.
52  if (!LastMI->isBarrier() &&
53  !(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) &&
56  if (I != LastMI->getParent()->begin()) {
57  I = std::prev(I);
58  DefMI = &*I;
59  }
60  }
61 
62  if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
63  (TII.canCauseFpMLxStall(MI->getOpcode()) ||
64  hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
65  // Try to schedule another instruction for the next 4 cycles.
66  if (FpMLxStalls == 0)
67  FpMLxStalls = 4;
68  return Hazard;
69  }
70  }
71  }
72 
74 }
75 
77  LastMI = nullptr;
78  FpMLxStalls = 0;
80 }
81 
83  MachineInstr *MI = SU->getInstr();
84  if (!MI->isDebugValue()) {
85  LastMI = MI;
86  FpMLxStalls = 0;
87  }
88 
90 }
91 
93  if (FpMLxStalls && --FpMLxStalls == 0)
94  // Stalled for 4 cycles but still can't schedule any other instructions.
95  LastMI = nullptr;
97 }
98 
100  llvm_unreachable("reverse ARM hazard checking unsupported");
101 }
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:649
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:573
const ARMSubtarget & getSubtarget() const
virtual const TargetInstrInfo * getInstrInfo() const
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:639
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:378
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI)
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineInstrBuilder MachineInstrBuilder & DefMI
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:927
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:465
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...