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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
17 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/IRBuilder.h"
32 #include "llvm/IR/InlineAsm.h"
33 #include "llvm/Support/CodeGen.h"
34 #include <utility>
35 
36 namespace llvm {
37 
38 class ARMSubtarget;
39 class DataLayout;
40 class FastISel;
41 class FunctionLoweringInfo;
42 class GlobalValue;
43 class InstrItineraryData;
44 class Instruction;
45 class MachineBasicBlock;
46 class MachineInstr;
47 class SelectionDAG;
48 class TargetLibraryInfo;
49 class TargetMachine;
50 class TargetRegisterInfo;
51 class VectorType;
52 
53  namespace ARMISD {
54 
55  // ARM Specific DAG Nodes
56  enum NodeType : unsigned {
57  // Start the numbering where the builtin ops and target ops leave off.
59 
60  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61  // TargetExternalSymbol, and TargetGlobalAddress.
62  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63  // PIC mode.
64  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
65 
66  // Add pseudo op to model memcpy for struct byval.
68 
69  CALL, // Function call.
70  CALL_PRED, // Function call that's predicable.
71  CALL_NOLINK, // Function call with branch not branch-and-link.
72  BRCOND, // Conditional branch.
73  BR_JT, // Jumptable branch.
74  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75  RET_FLAG, // Return with a flag operand.
76  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
77 
78  PIC_ADD, // Add with a PC operand and a PIC label.
79 
80  CMP, // ARM compare instructions.
81  CMN, // ARM CMN instructions.
82  CMPZ, // ARM compare that sets only Z flag.
83  CMPFP, // ARM VFP compare instruction, sets FPSCR.
84  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
85  FMSTAT, // ARM fmstat instruction.
86 
87  CMOV, // ARM conditional move instructions.
88 
89  SSAT, // Signed saturation
90  USAT, // Unsigned saturation
91 
93 
94  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
95  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
96  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
97 
98  ADDC, // Add with carry
99  ADDE, // Add using carry
100  SUBC, // Sub with carry
101  SUBE, // Sub using carry
102 
103  VMOVRRD, // double to two gprs.
104  VMOVDRR, // Two gprs to double.
105 
106  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
107  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
108  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
109 
110  TC_RETURN, // Tail call return pseudo.
111 
113 
114  DYN_ALLOC, // Dynamic allocation on the stack.
115 
116  MEMBARRIER_MCR, // Memory barrier (MCR)
117 
118  PRELOAD, // Preload
119 
120  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
121  WIN__DBZCHK, // Windows' divide by zero check
122 
123  VCEQ, // Vector compare equal.
124  VCEQZ, // Vector compare equal to zero.
125  VCGE, // Vector compare greater than or equal.
126  VCGEZ, // Vector compare greater than or equal to zero.
127  VCLEZ, // Vector compare less than or equal to zero.
128  VCGEU, // Vector compare unsigned greater than or equal.
129  VCGT, // Vector compare greater than.
130  VCGTZ, // Vector compare greater than zero.
131  VCLTZ, // Vector compare less than zero.
132  VCGTU, // Vector compare unsigned greater than.
133  VTST, // Vector test bits.
134 
135  // Vector shift by immediate:
136  VSHL, // ...left
137  VSHRs, // ...right (signed)
138  VSHRu, // ...right (unsigned)
139 
140  // Vector rounding shift by immediate:
141  VRSHRs, // ...right (signed)
142  VRSHRu, // ...right (unsigned)
143  VRSHRN, // ...right narrow
144 
145  // Vector saturating shift by immediate:
146  VQSHLs, // ...left (signed)
147  VQSHLu, // ...left (unsigned)
148  VQSHLsu, // ...left (signed to unsigned)
149  VQSHRNs, // ...right narrow (signed)
150  VQSHRNu, // ...right narrow (unsigned)
151  VQSHRNsu, // ...right narrow (signed to unsigned)
152 
153  // Vector saturating rounding shift by immediate:
154  VQRSHRNs, // ...right narrow (signed)
155  VQRSHRNu, // ...right narrow (unsigned)
156  VQRSHRNsu, // ...right narrow (signed to unsigned)
157 
158  // Vector shift and insert:
159  VSLI, // ...left
160  VSRI, // ...right
161 
162  // Vector get lane (VMOV scalar to ARM core register)
163  // (These are used for 8- and 16-bit element types only.)
164  VGETLANEu, // zero-extend vector extract element
165  VGETLANEs, // sign-extend vector extract element
166 
167  // Vector move immediate and move negated immediate:
170 
171  // Vector move f32 immediate:
173 
174  // Vector duplicate:
177 
178  // Vector shuffles:
179  VEXT, // extract
180  VREV64, // reverse elements within 64-bit doublewords
181  VREV32, // reverse elements within 32-bit words
182  VREV16, // reverse elements within 16-bit halfwords
183  VZIP, // zip (interleave)
184  VUZP, // unzip (deinterleave)
185  VTRN, // transpose
186  VTBL1, // 1-register shuffle with mask
187  VTBL2, // 2-register shuffle with mask
188 
189  // Vector multiply long:
190  VMULLs, // ...signed
191  VMULLu, // ...unsigned
192 
193  SMULWB, // Signed multiply word by half word, bottom
194  SMULWT, // Signed multiply word by half word, top
195  UMLAL, // 64bit Unsigned Accumulate Multiply
196  SMLAL, // 64bit Signed Accumulate Multiply
197  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
198  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
199  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
200  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
201  SMLALTT, // 64-bit signed accumulate multiply top, top 16
202  SMLALD, // Signed multiply accumulate long dual
203  SMLALDX, // Signed multiply accumulate long dual exchange
204  SMLSLD, // Signed multiply subtract long dual
205  SMLSLDX, // Signed multiply subtract long dual exchange
206  SMMLAR, // Signed multiply long, round and add
207  SMMLSR, // Signed multiply long, subtract and round
208 
209  // Operands of the standard BUILD_VECTOR node are not legalized, which
210  // is fine if BUILD_VECTORs are always lowered to shuffles or other
211  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
212  // operands need to be legalized. Define an ARM-specific version of
213  // BUILD_VECTOR for this purpose.
215 
216  // Bit-field insert
218 
219  // Vector OR with immediate
221  // Vector AND with NOT of immediate
223 
224  // Vector bitwise select
226 
227  // Pseudo-instruction representing a memory copy using ldm/stm
228  // instructions.
230 
231  // Vector load N-element structure to all lanes:
236 
237  // NEON loads with post-increment base updates:
249 
250  // NEON stores with post-increment base updates:
258  };
259 
260  } // end namespace ARMISD
261 
262  /// Define some predicates that are used for node matching.
263  namespace ARM {
264 
265  bool isBitFieldInvertedMask(unsigned v);
266 
267  } // end namespace ARM
268 
269  //===--------------------------------------------------------------------===//
270  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
271 
273  public:
274  explicit ARMTargetLowering(const TargetMachine &TM,
275  const ARMSubtarget &STI);
276 
277  unsigned getJumpTableEncoding() const override;
278  bool useSoftFloat() const override;
279 
280  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
281 
282  /// ReplaceNodeResults - Replace the results of node with an illegal result
283  /// type with new values built out of custom code.
284  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
285  SelectionDAG &DAG) const override;
286 
287  const char *getTargetNodeName(unsigned Opcode) const override;
288 
289  bool isSelectSupported(SelectSupportKind Kind) const override {
290  // ARM does not support scalar condition selects on vectors.
291  return (Kind != ScalarCondVectorVal);
292  }
293 
294  bool isReadOnly(const GlobalValue *GV) const;
295 
296  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
297  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
298  EVT VT) const override;
299 
301  EmitInstrWithCustomInserter(MachineInstr &MI,
302  MachineBasicBlock *MBB) const override;
303 
304  void AdjustInstrPostInstrSelection(MachineInstr &MI,
305  SDNode *Node) const override;
306 
307  SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
308  SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
309  SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
310  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
311 
312  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
313 
314  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
315  /// unaligned memory accesses of the specified type. Returns whether it
316  /// is "fast" by reference in the second argument.
317  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
318  unsigned Align,
319  bool *Fast) const override;
320 
321  EVT getOptimalMemOpType(uint64_t Size,
322  unsigned DstAlign, unsigned SrcAlign,
323  bool IsMemset, bool ZeroMemset,
324  bool MemcpyStrSrc,
325  MachineFunction &MF) const override;
326 
327  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
328  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
329  bool isZExtFree(SDValue Val, EVT VT2) const override;
330 
331  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
332 
333  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
334 
335 
336  /// isLegalAddressingMode - Return true if the addressing mode represented
337  /// by AM is legal for this target, for a load/store of the specified type.
338  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
339  Type *Ty, unsigned AS,
340  Instruction *I = nullptr) const override;
341 
342  /// getScalingFactorCost - Return the cost of the scaling used in
343  /// addressing mode represented by AM.
344  /// If the AM is supported, the return value must be >= 0.
345  /// If the AM is not supported, the return value must be negative.
346  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
347  unsigned AS) const override;
348 
349  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
350 
351  /// \brief Returns true if the addresing mode representing by AM is legal
352  /// for the Thumb1 target, for a load/store of the specified type.
353  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
354 
355  /// isLegalICmpImmediate - Return true if the specified immediate is legal
356  /// icmp immediate, that is the target has icmp instructions which can
357  /// compare a register against the immediate without having to materialize
358  /// the immediate into a register.
359  bool isLegalICmpImmediate(int64_t Imm) const override;
360 
361  /// isLegalAddImmediate - Return true if the specified immediate is legal
362  /// add immediate, that is the target has add instructions which can
363  /// add a register and the immediate without having to materialize
364  /// the immediate into a register.
365  bool isLegalAddImmediate(int64_t Imm) const override;
366 
367  /// getPreIndexedAddressParts - returns true by value, base pointer and
368  /// offset pointer and addressing mode by reference if the node's address
369  /// can be legally represented as pre-indexed load / store address.
370  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
372  SelectionDAG &DAG) const override;
373 
374  /// getPostIndexedAddressParts - returns true by value, base pointer and
375  /// offset pointer and addressing mode by reference if this node can be
376  /// combined with a load / store to form a post-indexed load / store.
377  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
378  SDValue &Offset, ISD::MemIndexedMode &AM,
379  SelectionDAG &DAG) const override;
380 
381  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
382  const APInt &DemandedElts,
383  const SelectionDAG &DAG,
384  unsigned Depth) const override;
385 
386 
387  bool ExpandInlineAsm(CallInst *CI) const override;
388 
389  ConstraintType getConstraintType(StringRef Constraint) const override;
390 
391  /// Examine constraint string and operand type and determine a weight value.
392  /// The operand object must already have been set up with the operand type.
393  ConstraintWeight getSingleConstraintMatchWeight(
394  AsmOperandInfo &info, const char *constraint) const override;
395 
396  std::pair<unsigned, const TargetRegisterClass *>
397  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
398  StringRef Constraint, MVT VT) const override;
399 
400  const char *LowerXConstraint(EVT ConstraintVT) const override;
401 
402  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
403  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
404  /// true it means one of the asm constraint of the inline asm instruction
405  /// being processed is 'm'.
406  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
407  std::vector<SDValue> &Ops,
408  SelectionDAG &DAG) const override;
409 
410  unsigned
411  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
412  if (ConstraintCode == "Q")
414  else if (ConstraintCode == "o")
416  else if (ConstraintCode.size() == 2) {
417  if (ConstraintCode[0] == 'U') {
418  switch(ConstraintCode[1]) {
419  default:
420  break;
421  case 'm':
423  case 'n':
425  case 'q':
427  case 's':
429  case 't':
431  case 'v':
433  case 'y':
435  }
436  }
437  }
438  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
439  }
440 
441  const ARMSubtarget* getSubtarget() const {
442  return Subtarget;
443  }
444 
445  /// getRegClassFor - Return the register class that should be used for the
446  /// specified value type.
447  const TargetRegisterClass *getRegClassFor(MVT VT) const override;
448 
449  /// Returns true if a cast between SrcAS and DestAS is a noop.
450  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
451  // Addrspacecasts are always noops.
452  return true;
453  }
454 
455  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
456  unsigned &PrefAlign) const override;
457 
458  /// createFastISel - This method returns a target specific FastISel object,
459  /// or null if the target does not support "fast" ISel.
461  const TargetLibraryInfo *libInfo) const override;
462 
463  Sched::Preference getSchedulingPreference(SDNode *N) const override;
464 
465  bool
466  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
467  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
468 
469  /// isFPImmLegal - Returns true if the target can instruction select the
470  /// specified FP immediate natively. If false, the legalizer will
471  /// materialize the FP immediate as a load from a constant pool.
472  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
473 
474  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
475  const CallInst &I,
476  MachineFunction &MF,
477  unsigned Intrinsic) const override;
478 
479  /// \brief Returns true if it is beneficial to convert a load of a constant
480  /// to just the constant itself.
481  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
482  Type *Ty) const override;
483 
484  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
485  /// with this index.
486  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
487  unsigned Index) const override;
488 
489  /// \brief Returns true if an argument of type Ty needs to be passed in a
490  /// contiguous block of registers in calling convention CallConv.
491  bool functionArgumentNeedsConsecutiveRegisters(
492  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
493 
494  /// If a physical register, this returns the register that receives the
495  /// exception address on entry to an EH pad.
496  unsigned
497  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
498 
499  /// If a physical register, this returns the register that receives the
500  /// exception typeid on entry to a landing pad.
501  unsigned
502  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
503 
504  Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
505  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
506  AtomicOrdering Ord) const override;
507  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
508  Value *Addr, AtomicOrdering Ord) const override;
509 
510  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
511 
512  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
513  AtomicOrdering Ord) const override;
514  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
515  AtomicOrdering Ord) const override;
516 
517  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
518 
519  bool lowerInterleavedLoad(LoadInst *LI,
521  ArrayRef<unsigned> Indices,
522  unsigned Factor) const override;
523  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
524  unsigned Factor) const override;
525 
526  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
528  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
529  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
531  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
532  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
533 
534  bool useLoadStackGuardNode() const override;
535 
536  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
537  unsigned &Cost) const override;
538 
539  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
540  const SelectionDAG &DAG) const override {
541  // Do not merge to larger than i32.
542  return (MemVT.getSizeInBits() <= 32);
543  }
544 
545  bool isCheapToSpeculateCttz() const override;
546  bool isCheapToSpeculateCtlz() const override;
547 
548  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
549  return VT.isScalarInteger();
550  }
551 
552  bool supportSwiftError() const override {
553  return true;
554  }
555 
556  bool hasStandaloneRem(EVT VT) const override {
557  return HasStandaloneRem;
558  }
559 
560  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
561  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
562 
563  /// Returns true if \p VecTy is a legal interleaved access type. This
564  /// function checks the vector element type and the overall width of the
565  /// vector.
566  bool isLegalInterleavedAccessType(VectorType *VecTy,
567  const DataLayout &DL) const;
568 
569  /// Returns the number of interleaved accesses that will be generated when
570  /// lowering accesses of the given type.
571  unsigned getNumInterleavedAccesses(VectorType *VecTy,
572  const DataLayout &DL) const;
573 
574  void finalizeLowering(MachineFunction &MF) const override;
575 
576  protected:
577  std::pair<const TargetRegisterClass *, uint8_t>
578  findRepresentativeClass(const TargetRegisterInfo *TRI,
579  MVT VT) const override;
580 
581  private:
582  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
583  /// make the right decision when generating code for different targets.
584  const ARMSubtarget *Subtarget;
585 
586  const TargetRegisterInfo *RegInfo;
587 
588  const InstrItineraryData *Itins;
589 
590  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
591  unsigned ARMPCLabelIndex;
592 
593  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
594  // check.
595  bool InsertFencesForAtomic;
596 
597  bool HasStandaloneRem = true;
598 
599  void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
600  void addDRTypeForNEON(MVT VT);
601  void addQRTypeForNEON(MVT VT);
602  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
603 
605 
606  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
607  SDValue &Arg, RegsToPassVector &RegsToPass,
608  CCValAssign &VA, CCValAssign &NextVA,
609  SDValue &StackPtr,
610  SmallVectorImpl<SDValue> &MemOpChains,
611  ISD::ArgFlagsTy Flags) const;
612  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
613  SDValue &Root, SelectionDAG &DAG,
614  const SDLoc &dl) const;
615 
616  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
617  bool isVarArg) const;
618  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
619  bool isVarArg) const;
620  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
621  const SDLoc &dl, SelectionDAG &DAG,
622  const CCValAssign &VA,
623  ISD::ArgFlagsTy Flags) const;
624  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
625  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
626  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
627  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
628  const ARMSubtarget *Subtarget) const;
629  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
630  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
631  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
632  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
633  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
634  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
635  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
636  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
637  SelectionDAG &DAG) const;
638  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
639  SelectionDAG &DAG,
640  TLSModel::Model model) const;
641  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
642  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
643  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
644  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
645  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
646  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
647  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
648  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
649  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
650  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
651  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
653  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
654  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
655  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
656  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
657  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
658  const ARMSubtarget *ST) const;
659  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
660  const ARMSubtarget *ST) const;
661  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
662  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
663  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
664  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
665  SmallVectorImpl<SDValue> &Results) const;
666  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
667  SDValue &Chain) const;
668  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
670  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
671  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
672  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
673  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
674 
675  unsigned getRegisterByName(const char* RegName, EVT VT,
676  SelectionDAG &DAG) const override;
677 
678  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
679  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
680  /// expanded to FMAs when this method returns true, otherwise fmuladd is
681  /// expanded to fmul + fadd.
682  ///
683  /// ARM supports both fused and unfused multiply-add operations; we already
684  /// lower a pair of fmul and fadd to the latter so it's not clear that there
685  /// would be a gain or that the gain would be worthwhile enough to risk
686  /// correctness bugs.
687  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
688 
689  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
690 
691  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
692  CallingConv::ID CallConv, bool isVarArg,
694  const SDLoc &dl, SelectionDAG &DAG,
695  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
696  SDValue ThisVal) const;
697 
698  bool supportSplitCSR(MachineFunction *MF) const override {
700  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
701  }
702 
703  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
704  void insertCopiesSplitCSR(
705  MachineBasicBlock *Entry,
706  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
707 
708  SDValue
709  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
711  const SDLoc &dl, SelectionDAG &DAG,
712  SmallVectorImpl<SDValue> &InVals) const override;
713 
714  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
715  SDValue &Chain, const Value *OrigArg,
716  unsigned InRegsParamRecordIdx, int ArgOffset,
717  unsigned ArgSize) const;
718 
719  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
720  const SDLoc &dl, SDValue &Chain,
721  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
722  bool ForceMutable = false) const;
723 
725  SmallVectorImpl<SDValue> &InVals) const override;
726 
727  /// HandleByVal - Target-specific cleanup for ByVal support.
728  void HandleByVal(CCState *, unsigned &, unsigned) const override;
729 
730  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
731  /// for tail call optimization. Targets which want to do tail call
732  /// optimization should implement this function.
733  bool IsEligibleForTailCallOptimization(SDValue Callee,
734  CallingConv::ID CalleeCC,
735  bool isVarArg,
736  bool isCalleeStructRet,
737  bool isCallerStructRet,
739  const SmallVectorImpl<SDValue> &OutVals,
741  SelectionDAG& DAG) const;
742 
743  bool CanLowerReturn(CallingConv::ID CallConv,
744  MachineFunction &MF, bool isVarArg,
746  LLVMContext &Context) const override;
747 
748  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
750  const SmallVectorImpl<SDValue> &OutVals,
751  const SDLoc &dl, SelectionDAG &DAG) const override;
752 
753  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
754 
755  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
756 
757  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
758  SDValue ARMcc, SDValue CCR, SDValue Cmp,
759  SelectionDAG &DAG) const;
760  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
761  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
762  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
763  const SDLoc &dl, bool InvalidOnQNaN) const;
764  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
765 
766  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
767 
768  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
769  MachineBasicBlock *DispatchBB, int FI) const;
770 
771  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
772 
773  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
774 
775  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
776  MachineBasicBlock *MBB) const;
777 
778  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
779  MachineBasicBlock *MBB) const;
780  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
781  MachineBasicBlock *MBB) const;
782  };
783 
788  };
789 
790  namespace ARM {
791 
793  const TargetLibraryInfo *libInfo);
794 
795  } // end namespace ARM
796 
797 } // end namespace llvm
798 
799 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:835
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:146
This class represents a function call, abstracting a target machine&#39;s calling convention.
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:668
This file contains the simple types necessary to represent the attributes associated with functions a...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
An instruction for storing to memory.
Definition: Instructions.h:306
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:917
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
const ARMSubtarget * getSubtarget() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:22
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:842
Represents one node in the SelectionDAG.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class to represent vector types.
Definition: DerivedTypes.h:393
Class for arbitrary precision integers.
Definition: APInt.h:69
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
amdgpu Simplify well known AMD library false Value Value * Arg
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:60
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
SelectSupportKind
Enum that describes what type of support for selects the target has.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const unsigned Kind
bool isSelectSupported(SelectSupportKind Kind) const override
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
Definition: Value.h:73
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isBitFieldInvertedMask(unsigned v)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:872