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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that ARM uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/IRBuilder.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/Support/CodeGen.h"
33 #include <utility>
34 
35 namespace llvm {
36 
37 class ARMSubtarget;
38 class DataLayout;
39 class FastISel;
40 class FunctionLoweringInfo;
41 class GlobalValue;
42 class InstrItineraryData;
43 class Instruction;
44 class MachineBasicBlock;
45 class MachineInstr;
46 class SelectionDAG;
47 class TargetLibraryInfo;
48 class TargetMachine;
49 class TargetRegisterInfo;
50 class VectorType;
51 
52  namespace ARMISD {
53 
54  // ARM Specific DAG Nodes
55  enum NodeType : unsigned {
56  // Start the numbering where the builtin ops and target ops leave off.
58 
59  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
60  // TargetExternalSymbol, and TargetGlobalAddress.
61  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
62  // PIC mode.
63  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
64 
65  // Add pseudo op to model memcpy for struct byval.
67 
68  CALL, // Function call.
69  CALL_PRED, // Function call that's predicable.
70  CALL_NOLINK, // Function call with branch not branch-and-link.
71  BRCOND, // Conditional branch.
72  BR_JT, // Jumptable branch.
73  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
74  RET_FLAG, // Return with a flag operand.
75  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
76 
77  PIC_ADD, // Add with a PC operand and a PIC label.
78 
79  CMP, // ARM compare instructions.
80  CMN, // ARM CMN instructions.
81  CMPZ, // ARM compare that sets only Z flag.
82  CMPFP, // ARM VFP compare instruction, sets FPSCR.
83  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
84  FMSTAT, // ARM fmstat instruction.
85 
86  CMOV, // ARM conditional move instructions.
87  SUBS, // Flag-setting subtraction.
88 
89  SSAT, // Signed saturation
90  USAT, // Unsigned saturation
91 
93 
94  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
95  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
96  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
97 
98  ADDC, // Add with carry
99  ADDE, // Add using carry
100  SUBC, // Sub with carry
101  SUBE, // Sub using carry
102 
103  VMOVRRD, // double to two gprs.
104  VMOVDRR, // Two gprs to double.
105  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
106 
107  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
108  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
109  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
110 
111  TC_RETURN, // Tail call return pseudo.
112 
114 
115  DYN_ALLOC, // Dynamic allocation on the stack.
116 
117  MEMBARRIER_MCR, // Memory barrier (MCR)
118 
119  PRELOAD, // Preload
120 
121  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
122  WIN__DBZCHK, // Windows' divide by zero check
123 
124  VCEQ, // Vector compare equal.
125  VCEQZ, // Vector compare equal to zero.
126  VCGE, // Vector compare greater than or equal.
127  VCGEZ, // Vector compare greater than or equal to zero.
128  VCLEZ, // Vector compare less than or equal to zero.
129  VCGEU, // Vector compare unsigned greater than or equal.
130  VCGT, // Vector compare greater than.
131  VCGTZ, // Vector compare greater than zero.
132  VCLTZ, // Vector compare less than zero.
133  VCGTU, // Vector compare unsigned greater than.
134  VTST, // Vector test bits.
135 
136  // Vector shift by immediate:
137  VSHL, // ...left
138  VSHRs, // ...right (signed)
139  VSHRu, // ...right (unsigned)
140 
141  // Vector rounding shift by immediate:
142  VRSHRs, // ...right (signed)
143  VRSHRu, // ...right (unsigned)
144  VRSHRN, // ...right narrow
145 
146  // Vector saturating shift by immediate:
147  VQSHLs, // ...left (signed)
148  VQSHLu, // ...left (unsigned)
149  VQSHLsu, // ...left (signed to unsigned)
150  VQSHRNs, // ...right narrow (signed)
151  VQSHRNu, // ...right narrow (unsigned)
152  VQSHRNsu, // ...right narrow (signed to unsigned)
153 
154  // Vector saturating rounding shift by immediate:
155  VQRSHRNs, // ...right narrow (signed)
156  VQRSHRNu, // ...right narrow (unsigned)
157  VQRSHRNsu, // ...right narrow (signed to unsigned)
158 
159  // Vector shift and insert:
160  VSLI, // ...left
161  VSRI, // ...right
162 
163  // Vector get lane (VMOV scalar to ARM core register)
164  // (These are used for 8- and 16-bit element types only.)
165  VGETLANEu, // zero-extend vector extract element
166  VGETLANEs, // sign-extend vector extract element
167 
168  // Vector move immediate and move negated immediate:
171 
172  // Vector move f32 immediate:
174 
175  // Move H <-> R, clearing top 16 bits
178 
179  // Vector duplicate:
182 
183  // Vector shuffles:
184  VEXT, // extract
185  VREV64, // reverse elements within 64-bit doublewords
186  VREV32, // reverse elements within 32-bit words
187  VREV16, // reverse elements within 16-bit halfwords
188  VZIP, // zip (interleave)
189  VUZP, // unzip (deinterleave)
190  VTRN, // transpose
191  VTBL1, // 1-register shuffle with mask
192  VTBL2, // 2-register shuffle with mask
193 
194  // Vector multiply long:
195  VMULLs, // ...signed
196  VMULLu, // ...unsigned
197 
198  SMULWB, // Signed multiply word by half word, bottom
199  SMULWT, // Signed multiply word by half word, top
200  UMLAL, // 64bit Unsigned Accumulate Multiply
201  SMLAL, // 64bit Signed Accumulate Multiply
202  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
203  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
204  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
205  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
206  SMLALTT, // 64-bit signed accumulate multiply top, top 16
207  SMLALD, // Signed multiply accumulate long dual
208  SMLALDX, // Signed multiply accumulate long dual exchange
209  SMLSLD, // Signed multiply subtract long dual
210  SMLSLDX, // Signed multiply subtract long dual exchange
211  SMMLAR, // Signed multiply long, round and add
212  SMMLSR, // Signed multiply long, subtract and round
213 
214  // Operands of the standard BUILD_VECTOR node are not legalized, which
215  // is fine if BUILD_VECTORs are always lowered to shuffles or other
216  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
217  // operands need to be legalized. Define an ARM-specific version of
218  // BUILD_VECTOR for this purpose.
220 
221  // Bit-field insert
223 
224  // Vector OR with immediate
226  // Vector AND with NOT of immediate
228 
229  // Vector bitwise select
231 
232  // Pseudo-instruction representing a memory copy using ldm/stm
233  // instructions.
235 
236  // Vector load N-element structure to all lanes:
241 
242  // NEON loads with post-increment base updates:
254 
255  // NEON stores with post-increment base updates:
263  };
264 
265  } // end namespace ARMISD
266 
267  /// Define some predicates that are used for node matching.
268  namespace ARM {
269 
270  bool isBitFieldInvertedMask(unsigned v);
271 
272  } // end namespace ARM
273 
274  //===--------------------------------------------------------------------===//
275  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
276 
278  public:
279  explicit ARMTargetLowering(const TargetMachine &TM,
280  const ARMSubtarget &STI);
281 
282  unsigned getJumpTableEncoding() const override;
283  bool useSoftFloat() const override;
284 
285  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
286 
287  /// ReplaceNodeResults - Replace the results of node with an illegal result
288  /// type with new values built out of custom code.
289  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
290  SelectionDAG &DAG) const override;
291 
292  const char *getTargetNodeName(unsigned Opcode) const override;
293 
294  bool isSelectSupported(SelectSupportKind Kind) const override {
295  // ARM does not support scalar condition selects on vectors.
296  return (Kind != ScalarCondVectorVal);
297  }
298 
299  bool isReadOnly(const GlobalValue *GV) const;
300 
301  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
302  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
303  EVT VT) const override;
304 
306  EmitInstrWithCustomInserter(MachineInstr &MI,
307  MachineBasicBlock *MBB) const override;
308 
309  void AdjustInstrPostInstrSelection(MachineInstr &MI,
310  SDNode *Node) const override;
311 
312  SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
313  SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
314  SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
315  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
316 
317  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
318 
319  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
320  /// unaligned memory accesses of the specified type. Returns whether it
321  /// is "fast" by reference in the second argument.
322  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
323  unsigned Align,
324  bool *Fast) const override;
325 
326  EVT getOptimalMemOpType(uint64_t Size,
327  unsigned DstAlign, unsigned SrcAlign,
328  bool IsMemset, bool ZeroMemset,
329  bool MemcpyStrSrc,
330  MachineFunction &MF) const override;
331 
332  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
333  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
334  bool isZExtFree(SDValue Val, EVT VT2) const override;
335  bool shouldSinkOperands(Instruction *I,
336  SmallVectorImpl<Use *> &Ops) const override;
337 
338  bool isFNegFree(EVT VT) const override;
339 
340  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
341 
342  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
343 
344 
345  /// isLegalAddressingMode - Return true if the addressing mode represented
346  /// by AM is legal for this target, for a load/store of the specified type.
347  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
348  Type *Ty, unsigned AS,
349  Instruction *I = nullptr) const override;
350 
351  /// getScalingFactorCost - Return the cost of the scaling used in
352  /// addressing mode represented by AM.
353  /// If the AM is supported, the return value must be >= 0.
354  /// If the AM is not supported, the return value must be negative.
355  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
356  unsigned AS) const override;
357 
358  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
359 
360  /// Returns true if the addresing mode representing by AM is legal
361  /// for the Thumb1 target, for a load/store of the specified type.
362  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
363 
364  /// isLegalICmpImmediate - Return true if the specified immediate is legal
365  /// icmp immediate, that is the target has icmp instructions which can
366  /// compare a register against the immediate without having to materialize
367  /// the immediate into a register.
368  bool isLegalICmpImmediate(int64_t Imm) const override;
369 
370  /// isLegalAddImmediate - Return true if the specified immediate is legal
371  /// add immediate, that is the target has add instructions which can
372  /// add a register and the immediate without having to materialize
373  /// the immediate into a register.
374  bool isLegalAddImmediate(int64_t Imm) const override;
375 
376  /// getPreIndexedAddressParts - returns true by value, base pointer and
377  /// offset pointer and addressing mode by reference if the node's address
378  /// can be legally represented as pre-indexed load / store address.
379  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
381  SelectionDAG &DAG) const override;
382 
383  /// getPostIndexedAddressParts - returns true by value, base pointer and
384  /// offset pointer and addressing mode by reference if this node can be
385  /// combined with a load / store to form a post-indexed load / store.
386  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
387  SDValue &Offset, ISD::MemIndexedMode &AM,
388  SelectionDAG &DAG) const override;
389 
390  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
391  const APInt &DemandedElts,
392  const SelectionDAG &DAG,
393  unsigned Depth) const override;
394 
395  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
396  TargetLoweringOpt &TLO) const override;
397 
398 
399  bool ExpandInlineAsm(CallInst *CI) const override;
400 
401  ConstraintType getConstraintType(StringRef Constraint) const override;
402 
403  /// Examine constraint string and operand type and determine a weight value.
404  /// The operand object must already have been set up with the operand type.
405  ConstraintWeight getSingleConstraintMatchWeight(
406  AsmOperandInfo &info, const char *constraint) const override;
407 
408  std::pair<unsigned, const TargetRegisterClass *>
409  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
410  StringRef Constraint, MVT VT) const override;
411 
412  const char *LowerXConstraint(EVT ConstraintVT) const override;
413 
414  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
415  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
416  /// true it means one of the asm constraint of the inline asm instruction
417  /// being processed is 'm'.
418  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
419  std::vector<SDValue> &Ops,
420  SelectionDAG &DAG) const override;
421 
422  unsigned
423  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
424  if (ConstraintCode == "Q")
426  else if (ConstraintCode == "o")
428  else if (ConstraintCode.size() == 2) {
429  if (ConstraintCode[0] == 'U') {
430  switch(ConstraintCode[1]) {
431  default:
432  break;
433  case 'm':
435  case 'n':
437  case 'q':
439  case 's':
441  case 't':
443  case 'v':
445  case 'y':
447  }
448  }
449  }
450  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
451  }
452 
453  const ARMSubtarget* getSubtarget() const {
454  return Subtarget;
455  }
456 
457  /// getRegClassFor - Return the register class that should be used for the
458  /// specified value type.
459  const TargetRegisterClass *getRegClassFor(MVT VT) const override;
460 
461  /// Returns true if a cast between SrcAS and DestAS is a noop.
462  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
463  // Addrspacecasts are always noops.
464  return true;
465  }
466 
467  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
468  unsigned &PrefAlign) const override;
469 
470  /// createFastISel - This method returns a target specific FastISel object,
471  /// or null if the target does not support "fast" ISel.
473  const TargetLibraryInfo *libInfo) const override;
474 
475  Sched::Preference getSchedulingPreference(SDNode *N) const override;
476 
477  bool
478  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
479  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
480 
481  /// isFPImmLegal - Returns true if the target can instruction select the
482  /// specified FP immediate natively. If false, the legalizer will
483  /// materialize the FP immediate as a load from a constant pool.
484  bool isFPImmLegal(const APFloat &Imm, EVT VT,
485  bool ForCodeSize = false) const override;
486 
487  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
488  const CallInst &I,
489  MachineFunction &MF,
490  unsigned Intrinsic) const override;
491 
492  /// Returns true if it is beneficial to convert a load of a constant
493  /// to just the constant itself.
494  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
495  Type *Ty) const override;
496 
497  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
498  /// with this index.
499  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
500  unsigned Index) const override;
501 
502  /// Returns true if an argument of type Ty needs to be passed in a
503  /// contiguous block of registers in calling convention CallConv.
504  bool functionArgumentNeedsConsecutiveRegisters(
505  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
506 
507  /// If a physical register, this returns the register that receives the
508  /// exception address on entry to an EH pad.
509  unsigned
510  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
511 
512  /// If a physical register, this returns the register that receives the
513  /// exception typeid on entry to a landing pad.
514  unsigned
515  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
516 
517  Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
518  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
519  AtomicOrdering Ord) const override;
520  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
521  Value *Addr, AtomicOrdering Ord) const override;
522 
523  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
524 
525  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
526  AtomicOrdering Ord) const override;
527  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
528  AtomicOrdering Ord) const override;
529 
530  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
531 
532  bool lowerInterleavedLoad(LoadInst *LI,
534  ArrayRef<unsigned> Indices,
535  unsigned Factor) const override;
536  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
537  unsigned Factor) const override;
538 
539  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
541  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
542  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
544  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
546  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
547 
548  bool useLoadStackGuardNode() const override;
549 
550  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
551  unsigned &Cost) const override;
552 
553  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
554  const SelectionDAG &DAG) const override {
555  // Do not merge to larger than i32.
556  return (MemVT.getSizeInBits() <= 32);
557  }
558 
559  bool isCheapToSpeculateCttz() const override;
560  bool isCheapToSpeculateCtlz() const override;
561 
562  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
563  return VT.isScalarInteger();
564  }
565 
566  bool supportSwiftError() const override {
567  return true;
568  }
569 
570  bool hasStandaloneRem(EVT VT) const override {
571  return HasStandaloneRem;
572  }
573 
574  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
575 
576  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
577  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
578 
579  /// Returns true if \p VecTy is a legal interleaved access type. This
580  /// function checks the vector element type and the overall width of the
581  /// vector.
582  bool isLegalInterleavedAccessType(VectorType *VecTy,
583  const DataLayout &DL) const;
584 
585  bool alignLoopsWithOptSize() const override;
586 
587  /// Returns the number of interleaved accesses that will be generated when
588  /// lowering accesses of the given type.
589  unsigned getNumInterleavedAccesses(VectorType *VecTy,
590  const DataLayout &DL) const;
591 
592  void finalizeLowering(MachineFunction &MF) const override;
593 
594  /// Return the correct alignment for the current calling convention.
595  unsigned getABIAlignmentForCallingConv(Type *ArgTy,
596  DataLayout DL) const override;
597 
598  bool isDesirableToCommuteWithShift(const SDNode *N,
599  CombineLevel Level) const override;
600 
601  bool shouldFoldConstantShiftPairToMask(const SDNode *N,
602  CombineLevel Level) const override;
603  protected:
604  std::pair<const TargetRegisterClass *, uint8_t>
605  findRepresentativeClass(const TargetRegisterInfo *TRI,
606  MVT VT) const override;
607 
608  private:
609  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
610  /// make the right decision when generating code for different targets.
611  const ARMSubtarget *Subtarget;
612 
613  const TargetRegisterInfo *RegInfo;
614 
615  const InstrItineraryData *Itins;
616 
617  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
618  unsigned ARMPCLabelIndex;
619 
620  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
621  // check.
622  bool InsertFencesForAtomic;
623 
624  bool HasStandaloneRem = true;
625 
626  void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
627  void addDRTypeForNEON(MVT VT);
628  void addQRTypeForNEON(MVT VT);
629  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
630 
632 
633  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
634  SDValue &Arg, RegsToPassVector &RegsToPass,
635  CCValAssign &VA, CCValAssign &NextVA,
636  SDValue &StackPtr,
637  SmallVectorImpl<SDValue> &MemOpChains,
638  ISD::ArgFlagsTy Flags) const;
639  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
640  SDValue &Root, SelectionDAG &DAG,
641  const SDLoc &dl) const;
642 
643  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
644  bool isVarArg) const;
645  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
646  bool isVarArg) const;
647  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
648  const SDLoc &dl, SelectionDAG &DAG,
649  const CCValAssign &VA,
650  ISD::ArgFlagsTy Flags) const;
651  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
652  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
653  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
654  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
655  const ARMSubtarget *Subtarget) const;
656  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
657  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
658  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
659  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
660  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
661  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
662  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
663  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
664  SelectionDAG &DAG) const;
665  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
666  SelectionDAG &DAG,
667  TLSModel::Model model) const;
668  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
669  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
670  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
671  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
672  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
673  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
674  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
675  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
676  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
677  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
678  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
680  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
681  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
682  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
683  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
684  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
685  const ARMSubtarget *ST) const;
686  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
687  const ARMSubtarget *ST) const;
688  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
689  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
690  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
691  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
692  SmallVectorImpl<SDValue> &Results) const;
693  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
694  SDValue &Chain) const;
695  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
697  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
698  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
699  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
700  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
701  void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
702  SelectionDAG &DAG) const;
703 
704  unsigned getRegisterByName(const char* RegName, EVT VT,
705  SelectionDAG &DAG) const override;
706 
707  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
708  SmallVectorImpl<SDNode *> &Created) const override;
709 
710  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
711  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
712  /// expanded to FMAs when this method returns true, otherwise fmuladd is
713  /// expanded to fmul + fadd.
714  ///
715  /// ARM supports both fused and unfused multiply-add operations; we already
716  /// lower a pair of fmul and fadd to the latter so it's not clear that there
717  /// would be a gain or that the gain would be worthwhile enough to risk
718  /// correctness bugs.
719  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
720 
721  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
722 
723  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
724  CallingConv::ID CallConv, bool isVarArg,
726  const SDLoc &dl, SelectionDAG &DAG,
727  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
728  SDValue ThisVal) const;
729 
730  bool supportSplitCSR(MachineFunction *MF) const override {
732  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
733  }
734 
735  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
736  void insertCopiesSplitCSR(
737  MachineBasicBlock *Entry,
738  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
739 
740  SDValue
741  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
743  const SDLoc &dl, SelectionDAG &DAG,
744  SmallVectorImpl<SDValue> &InVals) const override;
745 
746  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
747  SDValue &Chain, const Value *OrigArg,
748  unsigned InRegsParamRecordIdx, int ArgOffset,
749  unsigned ArgSize) const;
750 
751  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
752  const SDLoc &dl, SDValue &Chain,
753  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
754  bool ForceMutable = false) const;
755 
757  SmallVectorImpl<SDValue> &InVals) const override;
758 
759  /// HandleByVal - Target-specific cleanup for ByVal support.
760  void HandleByVal(CCState *, unsigned &, unsigned) const override;
761 
762  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
763  /// for tail call optimization. Targets which want to do tail call
764  /// optimization should implement this function.
765  bool IsEligibleForTailCallOptimization(SDValue Callee,
766  CallingConv::ID CalleeCC,
767  bool isVarArg,
768  bool isCalleeStructRet,
769  bool isCallerStructRet,
771  const SmallVectorImpl<SDValue> &OutVals,
773  SelectionDAG& DAG) const;
774 
775  bool CanLowerReturn(CallingConv::ID CallConv,
776  MachineFunction &MF, bool isVarArg,
778  LLVMContext &Context) const override;
779 
780  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
782  const SmallVectorImpl<SDValue> &OutVals,
783  const SDLoc &dl, SelectionDAG &DAG) const override;
784 
785  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
786 
787  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
788 
789  bool shouldConsiderGEPOffsetSplit() const override { return true; }
790 
791  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
792  SDValue ARMcc, SDValue CCR, SDValue Cmp,
793  SelectionDAG &DAG) const;
794  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
795  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
796  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
797  const SDLoc &dl, bool InvalidOnQNaN) const;
798  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
799 
800  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
801 
802  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
803  MachineBasicBlock *DispatchBB, int FI) const;
804 
805  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
806 
807  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
808 
809  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
810  MachineBasicBlock *MBB) const;
811 
812  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
813  MachineBasicBlock *MBB) const;
814  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
815  MachineBasicBlock *MBB) const;
816  };
817 
822  };
823 
824  namespace ARM {
825 
827  const TargetLibraryInfo *libInfo);
828 
829  } // end namespace ARM
830 
831 } // end namespace llvm
832 
833 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:886
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
This class represents a function call, abstracting a target machine&#39;s calling convention.
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
unsigned const TargetRegisterInfo * TRI
An instruction for reading from memory.
Definition: Instructions.h:167
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
This file contains the simple types necessary to represent the attributes associated with functions a...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
Itinerary data supplied by a subtarget to be used by a target.
An instruction for storing to memory.
Definition: Instructions.h:320
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:968
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
This is an important base class in LLVM.
Definition: Constant.h:41
CombineLevel
Definition: DAGCombine.h:15
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const ARMSubtarget * getSubtarget() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:21
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:893
Represents one node in the SelectionDAG.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class to represent vector types.
Definition: DerivedTypes.h:424
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:63
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
SelectSupportKind
Enum that describes what type of support for selects the target has.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
uint32_t Size
Definition: Profile.cpp:46
bool isSelectSupported(SelectSupportKind Kind) const override
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
Definition: Value.h:72
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isBitFieldInvertedMask(unsigned v)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:923