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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
17 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/IRBuilder.h"
32 #include "llvm/IR/InlineAsm.h"
33 #include "llvm/Support/CodeGen.h"
34 #include <utility>
35 
36 namespace llvm {
37 
38 class ARMSubtarget;
39 class DataLayout;
40 class FastISel;
41 class FunctionLoweringInfo;
42 class GlobalValue;
43 class InstrItineraryData;
44 class Instruction;
45 class MachineBasicBlock;
46 class MachineInstr;
47 class SelectionDAG;
48 class TargetLibraryInfo;
49 class TargetMachine;
50 class TargetRegisterInfo;
51 class VectorType;
52 
53  namespace ARMISD {
54 
55  // ARM Specific DAG Nodes
56  enum NodeType : unsigned {
57  // Start the numbering where the builtin ops and target ops leave off.
59 
60  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61  // TargetExternalSymbol, and TargetGlobalAddress.
62  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63  // PIC mode.
64  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
65 
66  // Add pseudo op to model memcpy for struct byval.
68 
69  CALL, // Function call.
70  CALL_PRED, // Function call that's predicable.
71  CALL_NOLINK, // Function call with branch not branch-and-link.
72  BRCOND, // Conditional branch.
73  BR_JT, // Jumptable branch.
74  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75  RET_FLAG, // Return with a flag operand.
76  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
77 
78  PIC_ADD, // Add with a PC operand and a PIC label.
79 
80  CMP, // ARM compare instructions.
81  CMN, // ARM CMN instructions.
82  CMPZ, // ARM compare that sets only Z flag.
83  CMPFP, // ARM VFP compare instruction, sets FPSCR.
84  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
85  FMSTAT, // ARM fmstat instruction.
86 
87  CMOV, // ARM conditional move instructions.
88 
89  SSAT, // Signed saturation
90 
92 
93  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
94  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
95  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
96 
97  ADDC, // Add with carry
98  ADDE, // Add using carry
99  SUBC, // Sub with carry
100  SUBE, // Sub using carry
101 
102  VMOVRRD, // double to two gprs.
103  VMOVDRR, // Two gprs to double.
104 
105  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
106  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
107  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
108 
109  TC_RETURN, // Tail call return pseudo.
110 
112 
113  DYN_ALLOC, // Dynamic allocation on the stack.
114 
115  MEMBARRIER_MCR, // Memory barrier (MCR)
116 
117  PRELOAD, // Preload
118 
119  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
120  WIN__DBZCHK, // Windows' divide by zero check
121 
122  VCEQ, // Vector compare equal.
123  VCEQZ, // Vector compare equal to zero.
124  VCGE, // Vector compare greater than or equal.
125  VCGEZ, // Vector compare greater than or equal to zero.
126  VCLEZ, // Vector compare less than or equal to zero.
127  VCGEU, // Vector compare unsigned greater than or equal.
128  VCGT, // Vector compare greater than.
129  VCGTZ, // Vector compare greater than zero.
130  VCLTZ, // Vector compare less than zero.
131  VCGTU, // Vector compare unsigned greater than.
132  VTST, // Vector test bits.
133 
134  // Vector shift by immediate:
135  VSHL, // ...left
136  VSHRs, // ...right (signed)
137  VSHRu, // ...right (unsigned)
138 
139  // Vector rounding shift by immediate:
140  VRSHRs, // ...right (signed)
141  VRSHRu, // ...right (unsigned)
142  VRSHRN, // ...right narrow
143 
144  // Vector saturating shift by immediate:
145  VQSHLs, // ...left (signed)
146  VQSHLu, // ...left (unsigned)
147  VQSHLsu, // ...left (signed to unsigned)
148  VQSHRNs, // ...right narrow (signed)
149  VQSHRNu, // ...right narrow (unsigned)
150  VQSHRNsu, // ...right narrow (signed to unsigned)
151 
152  // Vector saturating rounding shift by immediate:
153  VQRSHRNs, // ...right narrow (signed)
154  VQRSHRNu, // ...right narrow (unsigned)
155  VQRSHRNsu, // ...right narrow (signed to unsigned)
156 
157  // Vector shift and insert:
158  VSLI, // ...left
159  VSRI, // ...right
160 
161  // Vector get lane (VMOV scalar to ARM core register)
162  // (These are used for 8- and 16-bit element types only.)
163  VGETLANEu, // zero-extend vector extract element
164  VGETLANEs, // sign-extend vector extract element
165 
166  // Vector move immediate and move negated immediate:
169 
170  // Vector move f32 immediate:
172 
173  // Vector duplicate:
176 
177  // Vector shuffles:
178  VEXT, // extract
179  VREV64, // reverse elements within 64-bit doublewords
180  VREV32, // reverse elements within 32-bit words
181  VREV16, // reverse elements within 16-bit halfwords
182  VZIP, // zip (interleave)
183  VUZP, // unzip (deinterleave)
184  VTRN, // transpose
185  VTBL1, // 1-register shuffle with mask
186  VTBL2, // 2-register shuffle with mask
187 
188  // Vector multiply long:
189  VMULLs, // ...signed
190  VMULLu, // ...unsigned
191 
192  SMULWB, // Signed multiply word by half word, bottom
193  SMULWT, // Signed multiply word by half word, top
194  UMLAL, // 64bit Unsigned Accumulate Multiply
195  SMLAL, // 64bit Signed Accumulate Multiply
196  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
197  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
198  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
199  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
200  SMLALTT, // 64-bit signed accumulate multiply top, top 16
201  SMLALD, // Signed multiply accumulate long dual
202  SMLALDX, // Signed multiply accumulate long dual exchange
203  SMLSLD, // Signed multiply subtract long dual
204  SMLSLDX, // Signed multiply subtract long dual exchange
205 
206  // Operands of the standard BUILD_VECTOR node are not legalized, which
207  // is fine if BUILD_VECTORs are always lowered to shuffles or other
208  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
209  // operands need to be legalized. Define an ARM-specific version of
210  // BUILD_VECTOR for this purpose.
212 
213  // Bit-field insert
215 
216  // Vector OR with immediate
218  // Vector AND with NOT of immediate
220 
221  // Vector bitwise select
223 
224  // Pseudo-instruction representing a memory copy using ldm/stm
225  // instructions.
227 
228  // Vector load N-element structure to all lanes:
233 
234  // NEON loads with post-increment base updates:
246 
247  // NEON stores with post-increment base updates:
255  };
256 
257  } // end namespace ARMISD
258 
259  /// Define some predicates that are used for node matching.
260  namespace ARM {
261 
262  bool isBitFieldInvertedMask(unsigned v);
263 
264  } // end namespace ARM
265 
266  //===--------------------------------------------------------------------===//
267  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
268 
270  public:
271  explicit ARMTargetLowering(const TargetMachine &TM,
272  const ARMSubtarget &STI);
273 
274  unsigned getJumpTableEncoding() const override;
275  bool useSoftFloat() const override;
276 
277  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
278 
279  /// ReplaceNodeResults - Replace the results of node with an illegal result
280  /// type with new values built out of custom code.
281  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
282  SelectionDAG &DAG) const override;
283 
284  const char *getTargetNodeName(unsigned Opcode) const override;
285 
286  bool isSelectSupported(SelectSupportKind Kind) const override {
287  // ARM does not support scalar condition selects on vectors.
288  return (Kind != ScalarCondVectorVal);
289  }
290 
291  bool isReadOnly(const GlobalValue *GV) const;
292 
293  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
294  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
295  EVT VT) const override;
296 
298  EmitInstrWithCustomInserter(MachineInstr &MI,
299  MachineBasicBlock *MBB) const override;
300 
301  void AdjustInstrPostInstrSelection(MachineInstr &MI,
302  SDNode *Node) const override;
303 
304  SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
305  SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
306  SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
307  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
308 
309  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
310 
311  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
312  /// unaligned memory accesses of the specified type. Returns whether it
313  /// is "fast" by reference in the second argument.
314  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
315  unsigned Align,
316  bool *Fast) const override;
317 
318  EVT getOptimalMemOpType(uint64_t Size,
319  unsigned DstAlign, unsigned SrcAlign,
320  bool IsMemset, bool ZeroMemset,
321  bool MemcpyStrSrc,
322  MachineFunction &MF) const override;
323 
324  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
325  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
326  bool isZExtFree(SDValue Val, EVT VT2) const override;
327 
328  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
329 
330  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
331 
332 
333  /// isLegalAddressingMode - Return true if the addressing mode represented
334  /// by AM is legal for this target, for a load/store of the specified type.
335  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
336  Type *Ty, unsigned AS,
337  Instruction *I = nullptr) const override;
338 
339  /// getScalingFactorCost - Return the cost of the scaling used in
340  /// addressing mode represented by AM.
341  /// If the AM is supported, the return value must be >= 0.
342  /// If the AM is not supported, the return value must be negative.
343  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
344  unsigned AS) const override;
345 
346  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
347 
348  /// \brief Returns true if the addresing mode representing by AM is legal
349  /// for the Thumb1 target, for a load/store of the specified type.
350  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
351 
352  /// isLegalICmpImmediate - Return true if the specified immediate is legal
353  /// icmp immediate, that is the target has icmp instructions which can
354  /// compare a register against the immediate without having to materialize
355  /// the immediate into a register.
356  bool isLegalICmpImmediate(int64_t Imm) const override;
357 
358  /// isLegalAddImmediate - Return true if the specified immediate is legal
359  /// add immediate, that is the target has add instructions which can
360  /// add a register and the immediate without having to materialize
361  /// the immediate into a register.
362  bool isLegalAddImmediate(int64_t Imm) const override;
363 
364  /// getPreIndexedAddressParts - returns true by value, base pointer and
365  /// offset pointer and addressing mode by reference if the node's address
366  /// can be legally represented as pre-indexed load / store address.
367  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
369  SelectionDAG &DAG) const override;
370 
371  /// getPostIndexedAddressParts - returns true by value, base pointer and
372  /// offset pointer and addressing mode by reference if this node can be
373  /// combined with a load / store to form a post-indexed load / store.
374  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
375  SDValue &Offset, ISD::MemIndexedMode &AM,
376  SelectionDAG &DAG) const override;
377 
378  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
379  const APInt &DemandedElts,
380  const SelectionDAG &DAG,
381  unsigned Depth) const override;
382 
383 
384  bool ExpandInlineAsm(CallInst *CI) const override;
385 
386  ConstraintType getConstraintType(StringRef Constraint) const override;
387 
388  /// Examine constraint string and operand type and determine a weight value.
389  /// The operand object must already have been set up with the operand type.
390  ConstraintWeight getSingleConstraintMatchWeight(
391  AsmOperandInfo &info, const char *constraint) const override;
392 
393  std::pair<unsigned, const TargetRegisterClass *>
394  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
395  StringRef Constraint, MVT VT) const override;
396 
397  const char *LowerXConstraint(EVT ConstraintVT) const override;
398 
399  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
400  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
401  /// true it means one of the asm constraint of the inline asm instruction
402  /// being processed is 'm'.
403  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
404  std::vector<SDValue> &Ops,
405  SelectionDAG &DAG) const override;
406 
407  unsigned
408  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
409  if (ConstraintCode == "Q")
411  else if (ConstraintCode == "o")
413  else if (ConstraintCode.size() == 2) {
414  if (ConstraintCode[0] == 'U') {
415  switch(ConstraintCode[1]) {
416  default:
417  break;
418  case 'm':
420  case 'n':
422  case 'q':
424  case 's':
426  case 't':
428  case 'v':
430  case 'y':
432  }
433  }
434  }
435  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
436  }
437 
438  const ARMSubtarget* getSubtarget() const {
439  return Subtarget;
440  }
441 
442  /// getRegClassFor - Return the register class that should be used for the
443  /// specified value type.
444  const TargetRegisterClass *getRegClassFor(MVT VT) const override;
445 
446  /// Returns true if a cast between SrcAS and DestAS is a noop.
447  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
448  // Addrspacecasts are always noops.
449  return true;
450  }
451 
452  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
453  unsigned &PrefAlign) const override;
454 
455  /// createFastISel - This method returns a target specific FastISel object,
456  /// or null if the target does not support "fast" ISel.
458  const TargetLibraryInfo *libInfo) const override;
459 
460  Sched::Preference getSchedulingPreference(SDNode *N) const override;
461 
462  bool
463  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
464  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
465 
466  /// isFPImmLegal - Returns true if the target can instruction select the
467  /// specified FP immediate natively. If false, the legalizer will
468  /// materialize the FP immediate as a load from a constant pool.
469  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
470 
471  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
472  const CallInst &I,
473  unsigned Intrinsic) const override;
474 
475  /// \brief Returns true if it is beneficial to convert a load of a constant
476  /// to just the constant itself.
477  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
478  Type *Ty) const override;
479 
480  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
481  /// with this index.
482  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
483  unsigned Index) const override;
484 
485  /// \brief Returns true if an argument of type Ty needs to be passed in a
486  /// contiguous block of registers in calling convention CallConv.
487  bool functionArgumentNeedsConsecutiveRegisters(
488  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
489 
490  /// If a physical register, this returns the register that receives the
491  /// exception address on entry to an EH pad.
492  unsigned
493  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
494 
495  /// If a physical register, this returns the register that receives the
496  /// exception typeid on entry to a landing pad.
497  unsigned
498  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
499 
500  Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
501  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
502  AtomicOrdering Ord) const override;
503  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
504  Value *Addr, AtomicOrdering Ord) const override;
505 
506  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
507 
508  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
509  AtomicOrdering Ord) const override;
510  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
511  AtomicOrdering Ord) const override;
512 
513  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
514 
515  bool lowerInterleavedLoad(LoadInst *LI,
517  ArrayRef<unsigned> Indices,
518  unsigned Factor) const override;
519  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
520  unsigned Factor) const override;
521 
522  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
524  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
525  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
527  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
528  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
529 
530  bool useLoadStackGuardNode() const override;
531 
532  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
533  unsigned &Cost) const override;
534 
535  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
536  const SelectionDAG &DAG) const override {
537  // Do not merge to larger than i32.
538  return (MemVT.getSizeInBits() <= 32);
539  }
540 
541  bool isCheapToSpeculateCttz() const override;
542  bool isCheapToSpeculateCtlz() const override;
543 
544  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
545  return VT.isScalarInteger();
546  }
547 
548  bool supportSwiftError() const override {
549  return true;
550  }
551 
552  bool hasStandaloneRem(EVT VT) const override {
553  return HasStandaloneRem;
554  }
555 
556  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
557  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
558 
559  /// Returns true if \p VecTy is a legal interleaved access type. This
560  /// function checks the vector element type and the overall width of the
561  /// vector.
562  bool isLegalInterleavedAccessType(VectorType *VecTy,
563  const DataLayout &DL) const;
564 
565  /// Returns the number of interleaved accesses that will be generated when
566  /// lowering accesses of the given type.
567  unsigned getNumInterleavedAccesses(VectorType *VecTy,
568  const DataLayout &DL) const;
569 
570  void finalizeLowering(MachineFunction &MF) const override;
571 
572  protected:
573  std::pair<const TargetRegisterClass *, uint8_t>
574  findRepresentativeClass(const TargetRegisterInfo *TRI,
575  MVT VT) const override;
576 
577  private:
578  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
579  /// make the right decision when generating code for different targets.
580  const ARMSubtarget *Subtarget;
581 
582  const TargetRegisterInfo *RegInfo;
583 
584  const InstrItineraryData *Itins;
585 
586  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
587  unsigned ARMPCLabelIndex;
588 
589  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
590  // check.
591  bool InsertFencesForAtomic;
592 
593  bool HasStandaloneRem = true;
594 
595  void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
596  void addDRTypeForNEON(MVT VT);
597  void addQRTypeForNEON(MVT VT);
598  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
599 
601 
602  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
603  SDValue &Arg, RegsToPassVector &RegsToPass,
604  CCValAssign &VA, CCValAssign &NextVA,
605  SDValue &StackPtr,
606  SmallVectorImpl<SDValue> &MemOpChains,
607  ISD::ArgFlagsTy Flags) const;
608  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
609  SDValue &Root, SelectionDAG &DAG,
610  const SDLoc &dl) const;
611 
612  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
613  bool isVarArg) const;
614  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
615  bool isVarArg) const;
616  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
617  const SDLoc &dl, SelectionDAG &DAG,
618  const CCValAssign &VA,
619  ISD::ArgFlagsTy Flags) const;
620  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
621  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
622  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
623  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
624  const ARMSubtarget *Subtarget) const;
625  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
626  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
627  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
628  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
629  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
630  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
631  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
632  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
633  SelectionDAG &DAG) const;
634  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
635  SelectionDAG &DAG,
636  TLSModel::Model model) const;
637  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
638  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
639  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
640  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
641  SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
642  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
643  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
644  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
645  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
647  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
648  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
649  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
650  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
651  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
652  const ARMSubtarget *ST) const;
653  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
654  const ARMSubtarget *ST) const;
655  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
656  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
657  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
658  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
659  SmallVectorImpl<SDValue> &Results) const;
660  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
661  SDValue &Chain) const;
662  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
664  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
665  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
666  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
667  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
668 
669  unsigned getRegisterByName(const char* RegName, EVT VT,
670  SelectionDAG &DAG) const override;
671 
672  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
673  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
674  /// expanded to FMAs when this method returns true, otherwise fmuladd is
675  /// expanded to fmul + fadd.
676  ///
677  /// ARM supports both fused and unfused multiply-add operations; we already
678  /// lower a pair of fmul and fadd to the latter so it's not clear that there
679  /// would be a gain or that the gain would be worthwhile enough to risk
680  /// correctness bugs.
681  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
682 
683  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
684 
685  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
686  CallingConv::ID CallConv, bool isVarArg,
688  const SDLoc &dl, SelectionDAG &DAG,
689  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
690  SDValue ThisVal) const;
691 
692  bool supportSplitCSR(MachineFunction *MF) const override {
694  MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
695  }
696 
697  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
698  void insertCopiesSplitCSR(
699  MachineBasicBlock *Entry,
700  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
701 
702  SDValue
703  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
705  const SDLoc &dl, SelectionDAG &DAG,
706  SmallVectorImpl<SDValue> &InVals) const override;
707 
708  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
709  SDValue &Chain, const Value *OrigArg,
710  unsigned InRegsParamRecordIdx, int ArgOffset,
711  unsigned ArgSize) const;
712 
713  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
714  const SDLoc &dl, SDValue &Chain,
715  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
716  bool ForceMutable = false) const;
717 
719  SmallVectorImpl<SDValue> &InVals) const override;
720 
721  /// HandleByVal - Target-specific cleanup for ByVal support.
722  void HandleByVal(CCState *, unsigned &, unsigned) const override;
723 
724  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
725  /// for tail call optimization. Targets which want to do tail call
726  /// optimization should implement this function.
727  bool IsEligibleForTailCallOptimization(SDValue Callee,
728  CallingConv::ID CalleeCC,
729  bool isVarArg,
730  bool isCalleeStructRet,
731  bool isCallerStructRet,
733  const SmallVectorImpl<SDValue> &OutVals,
735  SelectionDAG& DAG) const;
736 
737  bool CanLowerReturn(CallingConv::ID CallConv,
738  MachineFunction &MF, bool isVarArg,
740  LLVMContext &Context) const override;
741 
742  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
744  const SmallVectorImpl<SDValue> &OutVals,
745  const SDLoc &dl, SelectionDAG &DAG) const override;
746 
747  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
748 
749  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
750 
751  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
752  SDValue ARMcc, SDValue CCR, SDValue Cmp,
753  SelectionDAG &DAG) const;
754  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
755  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
756  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
757  const SDLoc &dl, bool InvalidOnQNaN) const;
758  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
759 
760  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
761 
762  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
763  MachineBasicBlock *DispatchBB, int FI) const;
764 
765  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
766 
767  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
768 
769  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
770  MachineBasicBlock *MBB) const;
771 
772  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
773  MachineBasicBlock *MBB) const;
774  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
775  MachineBasicBlock *MBB) const;
776  };
777 
782  };
783 
784  namespace ARM {
785 
787  const TargetLibraryInfo *libInfo);
788 
789  } // end namespace ARM
790 
791 } // end namespace llvm
792 
793 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:146
This class represents a function call, abstracting a target machine&#39;s calling convention.
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:668
This file contains the simple types necessary to represent the attributes associated with functions a...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
An instruction for storing to memory.
Definition: Instructions.h:306
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
const ARMSubtarget * getSubtarget() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:22
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:841
Represents one node in the SelectionDAG.
Class to represent vector types.
Definition: DerivedTypes.h:393
Class for arbitrary precision integers.
Definition: APInt.h:69
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
amdgpu Simplify well known AMD library false Value Value * Arg
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:59
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG)
SelectSupportKind
Enum that describes what type of support for selects the target has.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned Kind
bool isSelectSupported(SelectSupportKind Kind) const override
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
Definition: Value.h:73
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isBitFieldInvertedMask(unsigned v)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:871