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ARMISelLowering.h
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1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
17 
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/IRBuilder.h"
31 #include "llvm/IR/InlineAsm.h"
32 #include "llvm/Support/CodeGen.h"
34 #include <utility>
35 
36 namespace llvm {
37 
38 class ARMSubtarget;
39 class DataLayout;
40 class FastISel;
41 class FunctionLoweringInfo;
42 class GlobalValue;
43 class InstrItineraryData;
44 class Instruction;
45 class MachineBasicBlock;
46 class MachineInstr;
47 class SelectionDAG;
48 class TargetLibraryInfo;
49 class TargetMachine;
50 class TargetRegisterInfo;
51 class VectorType;
52 
53  namespace ARMISD {
54 
55  // ARM Specific DAG Nodes
56  enum NodeType : unsigned {
57  // Start the numbering where the builtin ops and target ops leave off.
59 
60  Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61  // TargetExternalSymbol, and TargetGlobalAddress.
62  WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63  // PIC mode.
64  WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
65 
66  // Add pseudo op to model memcpy for struct byval.
68 
69  CALL, // Function call.
70  CALL_PRED, // Function call that's predicable.
71  CALL_NOLINK, // Function call with branch not branch-and-link.
72  BRCOND, // Conditional branch.
73  BR_JT, // Jumptable branch.
74  BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75  RET_FLAG, // Return with a flag operand.
76  INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
77 
78  PIC_ADD, // Add with a PC operand and a PIC label.
79 
80  CMP, // ARM compare instructions.
81  CMN, // ARM CMN instructions.
82  CMPZ, // ARM compare that sets only Z flag.
83  CMPFP, // ARM VFP compare instruction, sets FPSCR.
84  CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
85  FMSTAT, // ARM fmstat instruction.
86 
87  CMOV, // ARM conditional move instructions.
88 
89  SSAT, // Signed saturation
90  USAT, // Unsigned saturation
91 
93 
94  SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
95  SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
96  RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
97 
98  ADDC, // Add with carry
99  ADDE, // Add using carry
100  SUBC, // Sub with carry
101  SUBE, // Sub using carry
102 
103  VMOVRRD, // double to two gprs.
104  VMOVDRR, // Two gprs to double.
105  VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
106 
107  EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
108  EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
109  EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
110 
111  TC_RETURN, // Tail call return pseudo.
112 
114 
115  DYN_ALLOC, // Dynamic allocation on the stack.
116 
117  MEMBARRIER_MCR, // Memory barrier (MCR)
118 
119  PRELOAD, // Preload
120 
121  WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
122  WIN__DBZCHK, // Windows' divide by zero check
123 
124  VCEQ, // Vector compare equal.
125  VCEQZ, // Vector compare equal to zero.
126  VCGE, // Vector compare greater than or equal.
127  VCGEZ, // Vector compare greater than or equal to zero.
128  VCLEZ, // Vector compare less than or equal to zero.
129  VCGEU, // Vector compare unsigned greater than or equal.
130  VCGT, // Vector compare greater than.
131  VCGTZ, // Vector compare greater than zero.
132  VCLTZ, // Vector compare less than zero.
133  VCGTU, // Vector compare unsigned greater than.
134  VTST, // Vector test bits.
135 
136  // Vector shift by immediate:
137  VSHL, // ...left
138  VSHRs, // ...right (signed)
139  VSHRu, // ...right (unsigned)
140 
141  // Vector rounding shift by immediate:
142  VRSHRs, // ...right (signed)
143  VRSHRu, // ...right (unsigned)
144  VRSHRN, // ...right narrow
145 
146  // Vector saturating shift by immediate:
147  VQSHLs, // ...left (signed)
148  VQSHLu, // ...left (unsigned)
149  VQSHLsu, // ...left (signed to unsigned)
150  VQSHRNs, // ...right narrow (signed)
151  VQSHRNu, // ...right narrow (unsigned)
152  VQSHRNsu, // ...right narrow (signed to unsigned)
153 
154  // Vector saturating rounding shift by immediate:
155  VQRSHRNs, // ...right narrow (signed)
156  VQRSHRNu, // ...right narrow (unsigned)
157  VQRSHRNsu, // ...right narrow (signed to unsigned)
158 
159  // Vector shift and insert:
160  VSLI, // ...left
161  VSRI, // ...right
162 
163  // Vector get lane (VMOV scalar to ARM core register)
164  // (These are used for 8- and 16-bit element types only.)
165  VGETLANEu, // zero-extend vector extract element
166  VGETLANEs, // sign-extend vector extract element
167 
168  // Vector move immediate and move negated immediate:
171 
172  // Vector move f32 immediate:
174 
175  // Move H <-> R, clearing top 16 bits
178 
179  // Vector duplicate:
182 
183  // Vector shuffles:
184  VEXT, // extract
185  VREV64, // reverse elements within 64-bit doublewords
186  VREV32, // reverse elements within 32-bit words
187  VREV16, // reverse elements within 16-bit halfwords
188  VZIP, // zip (interleave)
189  VUZP, // unzip (deinterleave)
190  VTRN, // transpose
191  VTBL1, // 1-register shuffle with mask
192  VTBL2, // 2-register shuffle with mask
193 
194  // Vector multiply long:
195  VMULLs, // ...signed
196  VMULLu, // ...unsigned
197 
198  SMULWB, // Signed multiply word by half word, bottom
199  SMULWT, // Signed multiply word by half word, top
200  UMLAL, // 64bit Unsigned Accumulate Multiply
201  SMLAL, // 64bit Signed Accumulate Multiply
202  UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
203  SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
204  SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
205  SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
206  SMLALTT, // 64-bit signed accumulate multiply top, top 16
207  SMLALD, // Signed multiply accumulate long dual
208  SMLALDX, // Signed multiply accumulate long dual exchange
209  SMLSLD, // Signed multiply subtract long dual
210  SMLSLDX, // Signed multiply subtract long dual exchange
211  SMMLAR, // Signed multiply long, round and add
212  SMMLSR, // Signed multiply long, subtract and round
213 
214  // Operands of the standard BUILD_VECTOR node are not legalized, which
215  // is fine if BUILD_VECTORs are always lowered to shuffles or other
216  // operations, but for ARM some BUILD_VECTORs are legal as-is and their
217  // operands need to be legalized. Define an ARM-specific version of
218  // BUILD_VECTOR for this purpose.
220 
221  // Bit-field insert
223 
224  // Vector OR with immediate
226  // Vector AND with NOT of immediate
228 
229  // Vector bitwise select
231 
232  // Pseudo-instruction representing a memory copy using ldm/stm
233  // instructions.
235 
236  // Vector load N-element structure to all lanes:
241 
242  // NEON loads with post-increment base updates:
254 
255  // NEON stores with post-increment base updates:
263  };
264 
265  } // end namespace ARMISD
266 
267  /// Define some predicates that are used for node matching.
268  namespace ARM {
269 
270  bool isBitFieldInvertedMask(unsigned v);
271 
272  } // end namespace ARM
273 
274  //===--------------------------------------------------------------------===//
275  // ARMTargetLowering - ARM Implementation of the TargetLowering interface
276 
278  public:
279  explicit ARMTargetLowering(const TargetMachine &TM,
280  const ARMSubtarget &STI);
281 
282  unsigned getJumpTableEncoding() const override;
283  bool useSoftFloat() const override;
284 
285  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
286 
287  /// ReplaceNodeResults - Replace the results of node with an illegal result
288  /// type with new values built out of custom code.
289  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
290  SelectionDAG &DAG) const override;
291 
292  const char *getTargetNodeName(unsigned Opcode) const override;
293 
294  bool isSelectSupported(SelectSupportKind Kind) const override {
295  // ARM does not support scalar condition selects on vectors.
296  return (Kind != ScalarCondVectorVal);
297  }
298 
299  bool isReadOnly(const GlobalValue *GV) const;
300 
301  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
302  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
303  EVT VT) const override;
304 
306  EmitInstrWithCustomInserter(MachineInstr &MI,
307  MachineBasicBlock *MBB) const override;
308 
309  void AdjustInstrPostInstrSelection(MachineInstr &MI,
310  SDNode *Node) const override;
311 
312  SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
313  SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
314  SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
315  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
316 
317  bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
318 
319  /// allowsMisalignedMemoryAccesses - Returns true if the target allows
320  /// unaligned memory accesses of the specified type. Returns whether it
321  /// is "fast" by reference in the second argument.
322  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
323  unsigned Align,
324  bool *Fast) const override;
325 
326  EVT getOptimalMemOpType(uint64_t Size,
327  unsigned DstAlign, unsigned SrcAlign,
328  bool IsMemset, bool ZeroMemset,
329  bool MemcpyStrSrc,
330  MachineFunction &MF) const override;
331 
332  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
333  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
334  bool isZExtFree(SDValue Val, EVT VT2) const override;
335  bool isFNegFree(EVT VT) const override;
336 
337  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
338 
339  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
340 
341 
342  /// isLegalAddressingMode - Return true if the addressing mode represented
343  /// by AM is legal for this target, for a load/store of the specified type.
344  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
345  Type *Ty, unsigned AS,
346  Instruction *I = nullptr) const override;
347 
348  /// getScalingFactorCost - Return the cost of the scaling used in
349  /// addressing mode represented by AM.
350  /// If the AM is supported, the return value must be >= 0.
351  /// If the AM is not supported, the return value must be negative.
352  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
353  unsigned AS) const override;
354 
355  bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
356 
357  /// \brief Returns true if the addresing mode representing by AM is legal
358  /// for the Thumb1 target, for a load/store of the specified type.
359  bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
360 
361  /// isLegalICmpImmediate - Return true if the specified immediate is legal
362  /// icmp immediate, that is the target has icmp instructions which can
363  /// compare a register against the immediate without having to materialize
364  /// the immediate into a register.
365  bool isLegalICmpImmediate(int64_t Imm) const override;
366 
367  /// isLegalAddImmediate - Return true if the specified immediate is legal
368  /// add immediate, that is the target has add instructions which can
369  /// add a register and the immediate without having to materialize
370  /// the immediate into a register.
371  bool isLegalAddImmediate(int64_t Imm) const override;
372 
373  /// getPreIndexedAddressParts - returns true by value, base pointer and
374  /// offset pointer and addressing mode by reference if the node's address
375  /// can be legally represented as pre-indexed load / store address.
376  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
378  SelectionDAG &DAG) const override;
379 
380  /// getPostIndexedAddressParts - returns true by value, base pointer and
381  /// offset pointer and addressing mode by reference if this node can be
382  /// combined with a load / store to form a post-indexed load / store.
383  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
384  SDValue &Offset, ISD::MemIndexedMode &AM,
385  SelectionDAG &DAG) const override;
386 
387  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
388  const APInt &DemandedElts,
389  const SelectionDAG &DAG,
390  unsigned Depth) const override;
391 
392 
393  bool ExpandInlineAsm(CallInst *CI) const override;
394 
395  ConstraintType getConstraintType(StringRef Constraint) const override;
396 
397  /// Examine constraint string and operand type and determine a weight value.
398  /// The operand object must already have been set up with the operand type.
399  ConstraintWeight getSingleConstraintMatchWeight(
400  AsmOperandInfo &info, const char *constraint) const override;
401 
402  std::pair<unsigned, const TargetRegisterClass *>
403  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
404  StringRef Constraint, MVT VT) const override;
405 
406  const char *LowerXConstraint(EVT ConstraintVT) const override;
407 
408  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
409  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
410  /// true it means one of the asm constraint of the inline asm instruction
411  /// being processed is 'm'.
412  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
413  std::vector<SDValue> &Ops,
414  SelectionDAG &DAG) const override;
415 
416  unsigned
417  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
418  if (ConstraintCode == "Q")
420  else if (ConstraintCode == "o")
422  else if (ConstraintCode.size() == 2) {
423  if (ConstraintCode[0] == 'U') {
424  switch(ConstraintCode[1]) {
425  default:
426  break;
427  case 'm':
429  case 'n':
431  case 'q':
433  case 's':
435  case 't':
437  case 'v':
439  case 'y':
441  }
442  }
443  }
444  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
445  }
446 
447  const ARMSubtarget* getSubtarget() const {
448  return Subtarget;
449  }
450 
451  /// getRegClassFor - Return the register class that should be used for the
452  /// specified value type.
453  const TargetRegisterClass *getRegClassFor(MVT VT) const override;
454 
455  /// Returns true if a cast between SrcAS and DestAS is a noop.
456  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
457  // Addrspacecasts are always noops.
458  return true;
459  }
460 
461  bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
462  unsigned &PrefAlign) const override;
463 
464  /// createFastISel - This method returns a target specific FastISel object,
465  /// or null if the target does not support "fast" ISel.
467  const TargetLibraryInfo *libInfo) const override;
468 
469  Sched::Preference getSchedulingPreference(SDNode *N) const override;
470 
471  bool
472  isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
473  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
474 
475  /// isFPImmLegal - Returns true if the target can instruction select the
476  /// specified FP immediate natively. If false, the legalizer will
477  /// materialize the FP immediate as a load from a constant pool.
478  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
479 
480  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
481  const CallInst &I,
482  MachineFunction &MF,
483  unsigned Intrinsic) const override;
484 
485  /// \brief Returns true if it is beneficial to convert a load of a constant
486  /// to just the constant itself.
487  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
488  Type *Ty) const override;
489 
490  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
491  /// with this index.
492  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
493  unsigned Index) const override;
494 
495  /// \brief Returns true if an argument of type Ty needs to be passed in a
496  /// contiguous block of registers in calling convention CallConv.
497  bool functionArgumentNeedsConsecutiveRegisters(
498  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
499 
500  /// If a physical register, this returns the register that receives the
501  /// exception address on entry to an EH pad.
502  unsigned
503  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
504 
505  /// If a physical register, this returns the register that receives the
506  /// exception typeid on entry to a landing pad.
507  unsigned
508  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
509 
510  Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
511  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
512  AtomicOrdering Ord) const override;
513  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
514  Value *Addr, AtomicOrdering Ord) const override;
515 
516  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
517 
518  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
519  AtomicOrdering Ord) const override;
520  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
521  AtomicOrdering Ord) const override;
522 
523  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
524 
525  bool lowerInterleavedLoad(LoadInst *LI,
527  ArrayRef<unsigned> Indices,
528  unsigned Factor) const override;
529  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
530  unsigned Factor) const override;
531 
532  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
534  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
535  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
537  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
538  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
539 
540  bool useLoadStackGuardNode() const override;
541 
542  bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
543  unsigned &Cost) const override;
544 
545  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
546  const SelectionDAG &DAG) const override {
547  // Do not merge to larger than i32.
548  return (MemVT.getSizeInBits() <= 32);
549  }
550 
551  bool isCheapToSpeculateCttz() const override;
552  bool isCheapToSpeculateCtlz() const override;
553 
554  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
555  return VT.isScalarInteger();
556  }
557 
558  bool supportSwiftError() const override {
559  return true;
560  }
561 
562  bool hasStandaloneRem(EVT VT) const override {
563  return HasStandaloneRem;
564  }
565 
566  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
567  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
568 
569  /// Returns true if \p VecTy is a legal interleaved access type. This
570  /// function checks the vector element type and the overall width of the
571  /// vector.
572  bool isLegalInterleavedAccessType(VectorType *VecTy,
573  const DataLayout &DL) const;
574 
575  /// Returns the number of interleaved accesses that will be generated when
576  /// lowering accesses of the given type.
577  unsigned getNumInterleavedAccesses(VectorType *VecTy,
578  const DataLayout &DL) const;
579 
580  void finalizeLowering(MachineFunction &MF) const override;
581 
582  protected:
583  std::pair<const TargetRegisterClass *, uint8_t>
584  findRepresentativeClass(const TargetRegisterInfo *TRI,
585  MVT VT) const override;
586 
587  private:
588  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
589  /// make the right decision when generating code for different targets.
590  const ARMSubtarget *Subtarget;
591 
592  const TargetRegisterInfo *RegInfo;
593 
594  const InstrItineraryData *Itins;
595 
596  /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
597  unsigned ARMPCLabelIndex;
598 
599  // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
600  // check.
601  bool InsertFencesForAtomic;
602 
603  bool HasStandaloneRem = true;
604 
605  void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
606  void addDRTypeForNEON(MVT VT);
607  void addQRTypeForNEON(MVT VT);
608  std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
609 
611 
612  void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
613  SDValue &Arg, RegsToPassVector &RegsToPass,
614  CCValAssign &VA, CCValAssign &NextVA,
615  SDValue &StackPtr,
616  SmallVectorImpl<SDValue> &MemOpChains,
617  ISD::ArgFlagsTy Flags) const;
618  SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
619  SDValue &Root, SelectionDAG &DAG,
620  const SDLoc &dl) const;
621 
622  CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
623  bool isVarArg) const;
624  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
625  bool isVarArg) const;
626  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
627  const SDLoc &dl, SelectionDAG &DAG,
628  const CCValAssign &VA,
629  ISD::ArgFlagsTy Flags) const;
630  SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
631  SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
632  SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
633  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
634  const ARMSubtarget *Subtarget) const;
635  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
636  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
637  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
638  SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
639  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
640  SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
641  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
642  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
643  SelectionDAG &DAG) const;
644  SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
645  SelectionDAG &DAG,
646  TLSModel::Model model) const;
647  SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
648  SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
649  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
650  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
651  SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
652  SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
653  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
654  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
655  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
656  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
657  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
659  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
660  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
661  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
662  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
663  SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
664  const ARMSubtarget *ST) const;
665  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
666  const ARMSubtarget *ST) const;
667  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
668  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
669  SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
670  void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
671  SmallVectorImpl<SDValue> &Results) const;
672  SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
673  SDValue &Chain) const;
674  SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
676  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
677  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
678  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
679  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
680 
681  unsigned getRegisterByName(const char* RegName, EVT VT,
682  SelectionDAG &DAG) const override;
683 
684  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
685  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
686  /// expanded to FMAs when this method returns true, otherwise fmuladd is
687  /// expanded to fmul + fadd.
688  ///
689  /// ARM supports both fused and unfused multiply-add operations; we already
690  /// lower a pair of fmul and fadd to the latter so it's not clear that there
691  /// would be a gain or that the gain would be worthwhile enough to risk
692  /// correctness bugs.
693  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
694 
695  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
696 
697  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
698  CallingConv::ID CallConv, bool isVarArg,
700  const SDLoc &dl, SelectionDAG &DAG,
701  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
702  SDValue ThisVal) const;
703 
704  bool supportSplitCSR(MachineFunction *MF) const override {
706  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
707  }
708 
709  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
710  void insertCopiesSplitCSR(
711  MachineBasicBlock *Entry,
712  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
713 
714  SDValue
715  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
717  const SDLoc &dl, SelectionDAG &DAG,
718  SmallVectorImpl<SDValue> &InVals) const override;
719 
720  int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
721  SDValue &Chain, const Value *OrigArg,
722  unsigned InRegsParamRecordIdx, int ArgOffset,
723  unsigned ArgSize) const;
724 
725  void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
726  const SDLoc &dl, SDValue &Chain,
727  unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
728  bool ForceMutable = false) const;
729 
731  SmallVectorImpl<SDValue> &InVals) const override;
732 
733  /// HandleByVal - Target-specific cleanup for ByVal support.
734  void HandleByVal(CCState *, unsigned &, unsigned) const override;
735 
736  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
737  /// for tail call optimization. Targets which want to do tail call
738  /// optimization should implement this function.
739  bool IsEligibleForTailCallOptimization(SDValue Callee,
740  CallingConv::ID CalleeCC,
741  bool isVarArg,
742  bool isCalleeStructRet,
743  bool isCallerStructRet,
745  const SmallVectorImpl<SDValue> &OutVals,
747  SelectionDAG& DAG) const;
748 
749  bool CanLowerReturn(CallingConv::ID CallConv,
750  MachineFunction &MF, bool isVarArg,
752  LLVMContext &Context) const override;
753 
754  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
756  const SmallVectorImpl<SDValue> &OutVals,
757  const SDLoc &dl, SelectionDAG &DAG) const override;
758 
759  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
760 
761  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
762 
763  SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
764  SDValue ARMcc, SDValue CCR, SDValue Cmp,
765  SelectionDAG &DAG) const;
766  SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
767  SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
768  SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
769  const SDLoc &dl, bool InvalidOnQNaN) const;
770  SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
771 
772  SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
773 
774  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
775  MachineBasicBlock *DispatchBB, int FI) const;
776 
777  void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
778 
779  bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
780 
781  MachineBasicBlock *EmitStructByval(MachineInstr &MI,
782  MachineBasicBlock *MBB) const;
783 
784  MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
785  MachineBasicBlock *MBB) const;
786  MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
787  MachineBasicBlock *MBB) const;
788  };
789 
794  };
795 
796  namespace ARM {
797 
799  const TargetLibraryInfo *libInfo);
800 
801  } // end namespace ARM
802 
803 } // end namespace llvm
804 
805 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:146
This class represents a function call, abstracting a target machine&#39;s calling convention.
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:677
This file contains the simple types necessary to represent the attributes associated with functions a...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
An instruction for storing to memory.
Definition: Instructions.h:306
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:918
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
const ARMSubtarget * getSubtarget() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:212
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:862
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:22
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:843
Represents one node in the SelectionDAG.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class to represent vector types.
Definition: DerivedTypes.h:393
Class for arbitrary precision integers.
Definition: APInt.h:69
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
amdgpu Simplify well known AMD library false Value Value * Arg
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:60
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
SelectSupportKind
Enum that describes what type of support for selects the target has.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const unsigned Kind
bool isSelectSupported(SelectSupportKind Kind) const override
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
Definition: Value.h:73
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isBitFieldInvertedMask(unsigned v)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:873