LLVM  9.0.0svn
ARMInstPrinter.cpp
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1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an ARM MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMInstPrinter.h"
14 #include "Utils/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Casting.h"
28 #include <algorithm>
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "asm-printer"
35 
36 #define PRINT_ALIAS_INSTR
37 #include "ARMGenAsmWriter.inc"
38 
39 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
40 ///
41 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
42 static unsigned translateShiftImm(unsigned imm) {
43  // lsr #32 and asr #32 exist, but should be encoded as a 0.
44  assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
45 
46  if (imm == 0)
47  return 32;
48  return imm;
49 }
50 
51 /// Prints the shift value with an immediate value.
53  unsigned ShImm, bool UseMarkup) {
54  if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
55  return;
56  O << ", ";
57 
58  assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
59  O << getShiftOpcStr(ShOpc);
60 
61  if (ShOpc != ARM_AM::rrx) {
62  O << " ";
63  if (UseMarkup)
64  O << "<imm:";
65  O << "#" << translateShiftImm(ShImm);
66  if (UseMarkup)
67  O << ">";
68  }
69 }
70 
72  const MCRegisterInfo &MRI)
73  : MCInstPrinter(MAI, MII, MRI) {}
74 
75 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
76  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
77 }
78 
80  StringRef Annot, const MCSubtargetInfo &STI) {
81  unsigned Opcode = MI->getOpcode();
82 
83  switch (Opcode) {
84  // Check for MOVs and print canonical forms, instead.
85  case ARM::MOVsr: {
86  // FIXME: Thumb variants?
87  const MCOperand &Dst = MI->getOperand(0);
88  const MCOperand &MO1 = MI->getOperand(1);
89  const MCOperand &MO2 = MI->getOperand(2);
90  const MCOperand &MO3 = MI->getOperand(3);
91 
93  printSBitModifierOperand(MI, 6, STI, O);
94  printPredicateOperand(MI, 4, STI, O);
95 
96  O << '\t';
97  printRegName(O, Dst.getReg());
98  O << ", ";
99  printRegName(O, MO1.getReg());
100 
101  O << ", ";
102  printRegName(O, MO2.getReg());
103  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
104  printAnnotation(O, Annot);
105  return;
106  }
107 
108  case ARM::MOVsi: {
109  // FIXME: Thumb variants?
110  const MCOperand &Dst = MI->getOperand(0);
111  const MCOperand &MO1 = MI->getOperand(1);
112  const MCOperand &MO2 = MI->getOperand(2);
113 
115  printSBitModifierOperand(MI, 5, STI, O);
116  printPredicateOperand(MI, 3, STI, O);
117 
118  O << '\t';
119  printRegName(O, Dst.getReg());
120  O << ", ";
121  printRegName(O, MO1.getReg());
122 
123  if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
124  printAnnotation(O, Annot);
125  return;
126  }
127 
128  O << ", " << markup("<imm:") << "#"
130  printAnnotation(O, Annot);
131  return;
132  }
133 
134  // A8.6.123 PUSH
135  case ARM::STMDB_UPD:
136  case ARM::t2STMDB_UPD:
137  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
138  // Should only print PUSH if there are at least two registers in the list.
139  O << '\t' << "push";
140  printPredicateOperand(MI, 2, STI, O);
141  if (Opcode == ARM::t2STMDB_UPD)
142  O << ".w";
143  O << '\t';
144  printRegisterList(MI, 4, STI, O);
145  printAnnotation(O, Annot);
146  return;
147  } else
148  break;
149 
150  case ARM::STR_PRE_IMM:
151  if (MI->getOperand(2).getReg() == ARM::SP &&
152  MI->getOperand(3).getImm() == -4) {
153  O << '\t' << "push";
154  printPredicateOperand(MI, 4, STI, O);
155  O << "\t{";
156  printRegName(O, MI->getOperand(1).getReg());
157  O << "}";
158  printAnnotation(O, Annot);
159  return;
160  } else
161  break;
162 
163  // A8.6.122 POP
164  case ARM::LDMIA_UPD:
165  case ARM::t2LDMIA_UPD:
166  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
167  // Should only print POP if there are at least two registers in the list.
168  O << '\t' << "pop";
169  printPredicateOperand(MI, 2, STI, O);
170  if (Opcode == ARM::t2LDMIA_UPD)
171  O << ".w";
172  O << '\t';
173  printRegisterList(MI, 4, STI, O);
174  printAnnotation(O, Annot);
175  return;
176  } else
177  break;
178 
179  case ARM::LDR_POST_IMM:
180  if (MI->getOperand(2).getReg() == ARM::SP &&
181  MI->getOperand(4).getImm() == 4) {
182  O << '\t' << "pop";
183  printPredicateOperand(MI, 5, STI, O);
184  O << "\t{";
185  printRegName(O, MI->getOperand(0).getReg());
186  O << "}";
187  printAnnotation(O, Annot);
188  return;
189  } else
190  break;
191 
192  // A8.6.355 VPUSH
193  case ARM::VSTMSDB_UPD:
194  case ARM::VSTMDDB_UPD:
195  if (MI->getOperand(0).getReg() == ARM::SP) {
196  O << '\t' << "vpush";
197  printPredicateOperand(MI, 2, STI, O);
198  O << '\t';
199  printRegisterList(MI, 4, STI, O);
200  printAnnotation(O, Annot);
201  return;
202  } else
203  break;
204 
205  // A8.6.354 VPOP
206  case ARM::VLDMSIA_UPD:
207  case ARM::VLDMDIA_UPD:
208  if (MI->getOperand(0).getReg() == ARM::SP) {
209  O << '\t' << "vpop";
210  printPredicateOperand(MI, 2, STI, O);
211  O << '\t';
212  printRegisterList(MI, 4, STI, O);
213  printAnnotation(O, Annot);
214  return;
215  } else
216  break;
217 
218  case ARM::tLDMIA: {
219  bool Writeback = true;
220  unsigned BaseReg = MI->getOperand(0).getReg();
221  for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
222  if (MI->getOperand(i).getReg() == BaseReg)
223  Writeback = false;
224  }
225 
226  O << "\tldm";
227 
228  printPredicateOperand(MI, 1, STI, O);
229  O << '\t';
230  printRegName(O, BaseReg);
231  if (Writeback)
232  O << "!";
233  O << ", ";
234  printRegisterList(MI, 3, STI, O);
235  printAnnotation(O, Annot);
236  return;
237  }
238 
239  // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
240  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
241  // a single GPRPair reg operand is used in the .td file to replace the two
242  // GPRs. However, when decoding them, the two GRPs cannot be automatically
243  // expressed as a GPRPair, so we have to manually merge them.
244  // FIXME: We would really like to be able to tablegen'erate this.
245  case ARM::LDREXD:
246  case ARM::STREXD:
247  case ARM::LDAEXD:
248  case ARM::STLEXD: {
249  const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
250  bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
251  unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
252  if (MRC.contains(Reg)) {
253  MCInst NewMI;
254  MCOperand NewReg;
255  NewMI.setOpcode(Opcode);
256 
257  if (isStore)
258  NewMI.addOperand(MI->getOperand(0));
260  Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
261  NewMI.addOperand(NewReg);
262 
263  // Copy the rest operands into NewMI.
264  for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
265  NewMI.addOperand(MI->getOperand(i));
266  printInstruction(&NewMI, STI, O);
267  return;
268  }
269  break;
270  }
271  case ARM::TSB:
272  case ARM::t2TSB:
273  O << "\ttsb\tcsync";
274  return;
275  case ARM::t2DSB:
276  switch (MI->getOperand(0).getImm()) {
277  default:
278  if (!printAliasInstr(MI, STI, O))
279  printInstruction(MI, STI, O);
280  break;
281  case 0:
282  O << "\tssbb";
283  break;
284  case 4:
285  O << "\tpssbb";
286  break;
287  }
288  printAnnotation(O, Annot);
289  return;
290  }
291 
292  if (!printAliasInstr(MI, STI, O))
293  printInstruction(MI, STI, O);
294 
295  printAnnotation(O, Annot);
296 }
297 
298 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
299  const MCSubtargetInfo &STI, raw_ostream &O) {
300  const MCOperand &Op = MI->getOperand(OpNo);
301  if (Op.isReg()) {
302  unsigned Reg = Op.getReg();
303  printRegName(O, Reg);
304  } else if (Op.isImm()) {
305  O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
306  } else {
307  assert(Op.isExpr() && "unknown operand kind in printOperand");
308  const MCExpr *Expr = Op.getExpr();
309  switch (Expr->getKind()) {
310  case MCExpr::Binary:
311  O << '#';
312  Expr->print(O, &MAI);
313  break;
314  case MCExpr::Constant: {
315  // If a symbolic branch target was added as a constant expression then
316  // print that address in hex. And only print 32 unsigned bits for the
317  // address.
318  const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
319  int64_t TargetAddress;
320  if (!Constant->evaluateAsAbsolute(TargetAddress)) {
321  O << '#';
322  Expr->print(O, &MAI);
323  } else {
324  O << "0x";
325  O.write_hex(static_cast<uint32_t>(TargetAddress));
326  }
327  break;
328  }
329  default:
330  // FIXME: Should we always treat this as if it is a constant literal and
331  // prefix it with '#'?
332  Expr->print(O, &MAI);
333  break;
334  }
335  }
336 }
337 
339  const MCSubtargetInfo &STI,
340  raw_ostream &O) {
341  const MCOperand &MO1 = MI->getOperand(OpNum);
342  if (MO1.isExpr()) {
343  MO1.getExpr()->print(O, &MAI);
344  return;
345  }
346 
347  O << markup("<mem:") << "[pc, ";
348 
349  int32_t OffImm = (int32_t)MO1.getImm();
350  bool isSub = OffImm < 0;
351 
352  // Special value for #-0. All others are normal.
353  if (OffImm == INT32_MIN)
354  OffImm = 0;
355  if (isSub) {
356  O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
357  } else {
358  O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
359  }
360  O << "]" << markup(">");
361 }
362 
363 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
364 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
365 // REG 0 0 - e.g. R5
366 // REG REG 0,SH_OPC - e.g. R5, ROR R3
367 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
368 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
369  const MCSubtargetInfo &STI,
370  raw_ostream &O) {
371  const MCOperand &MO1 = MI->getOperand(OpNum);
372  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
373  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
374 
375  printRegName(O, MO1.getReg());
376 
377  // Print the shift opc.
379  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
380  if (ShOpc == ARM_AM::rrx)
381  return;
382 
383  O << ' ';
384  printRegName(O, MO2.getReg());
385  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
386 }
387 
388 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
389  const MCSubtargetInfo &STI,
390  raw_ostream &O) {
391  const MCOperand &MO1 = MI->getOperand(OpNum);
392  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
393 
394  printRegName(O, MO1.getReg());
395 
396  // Print the shift opc.
399 }
400 
401 //===--------------------------------------------------------------------===//
402 // Addressing Mode #2
403 //===--------------------------------------------------------------------===//
404 
406  const MCSubtargetInfo &STI,
407  raw_ostream &O) {
408  const MCOperand &MO1 = MI->getOperand(Op);
409  const MCOperand &MO2 = MI->getOperand(Op + 1);
410  const MCOperand &MO3 = MI->getOperand(Op + 2);
411 
412  O << markup("<mem:") << "[";
413  printRegName(O, MO1.getReg());
414 
415  if (!MO2.getReg()) {
416  if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
417  O << ", " << markup("<imm:") << "#"
419  << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
420  }
421  O << "]" << markup(">");
422  return;
423  }
424 
425  O << ", ";
427  printRegName(O, MO2.getReg());
428 
431  O << "]" << markup(">");
432 }
433 
435  const MCSubtargetInfo &STI,
436  raw_ostream &O) {
437  const MCOperand &MO1 = MI->getOperand(Op);
438  const MCOperand &MO2 = MI->getOperand(Op + 1);
439  O << markup("<mem:") << "[";
440  printRegName(O, MO1.getReg());
441  O << ", ";
442  printRegName(O, MO2.getReg());
443  O << "]" << markup(">");
444 }
445 
447  const MCSubtargetInfo &STI,
448  raw_ostream &O) {
449  const MCOperand &MO1 = MI->getOperand(Op);
450  const MCOperand &MO2 = MI->getOperand(Op + 1);
451  O << markup("<mem:") << "[";
452  printRegName(O, MO1.getReg());
453  O << ", ";
454  printRegName(O, MO2.getReg());
455  O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
456 }
457 
459  const MCSubtargetInfo &STI,
460  raw_ostream &O) {
461  const MCOperand &MO1 = MI->getOperand(Op);
462 
463  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
464  printOperand(MI, Op, STI, O);
465  return;
466  }
467 
468 #ifndef NDEBUG
469  const MCOperand &MO3 = MI->getOperand(Op + 2);
470  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
471  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
472 #endif
473 
474  printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
475 }
476 
478  unsigned OpNum,
479  const MCSubtargetInfo &STI,
480  raw_ostream &O) {
481  const MCOperand &MO1 = MI->getOperand(OpNum);
482  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
483 
484  if (!MO1.getReg()) {
485  unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
486  O << markup("<imm:") << '#'
487  << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
488  << markup(">");
489  return;
490  }
491 
493  printRegName(O, MO1.getReg());
494 
497 }
498 
499 //===--------------------------------------------------------------------===//
500 // Addressing Mode #3
501 //===--------------------------------------------------------------------===//
502 
504  raw_ostream &O,
505  bool AlwaysPrintImm0) {
506  const MCOperand &MO1 = MI->getOperand(Op);
507  const MCOperand &MO2 = MI->getOperand(Op + 1);
508  const MCOperand &MO3 = MI->getOperand(Op + 2);
509 
510  O << markup("<mem:") << '[';
511  printRegName(O, MO1.getReg());
512 
513  if (MO2.getReg()) {
514  O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
515  printRegName(O, MO2.getReg());
516  O << ']' << markup(">");
517  return;
518  }
519 
520  // If the op is sub we have to print the immediate even if it is 0
521  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
523 
524  if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
525  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
526  << markup(">");
527  }
528  O << ']' << markup(">");
529 }
530 
531 template <bool AlwaysPrintImm0>
533  const MCSubtargetInfo &STI,
534  raw_ostream &O) {
535  const MCOperand &MO1 = MI->getOperand(Op);
536  if (!MO1.isReg()) { // For label symbolic references.
537  printOperand(MI, Op, STI, O);
538  return;
539  }
540 
543  "unexpected idxmode");
544  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
545 }
546 
548  unsigned OpNum,
549  const MCSubtargetInfo &STI,
550  raw_ostream &O) {
551  const MCOperand &MO1 = MI->getOperand(OpNum);
552  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
553 
554  if (MO1.getReg()) {
556  printRegName(O, MO1.getReg());
557  return;
558  }
559 
560  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
561  O << markup("<imm:") << '#'
562  << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
563  << markup(">");
564 }
565 
567  const MCSubtargetInfo &STI,
568  raw_ostream &O) {
569  const MCOperand &MO = MI->getOperand(OpNum);
570  unsigned Imm = MO.getImm();
571  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
572  << markup(">");
573 }
574 
576  const MCSubtargetInfo &STI,
577  raw_ostream &O) {
578  const MCOperand &MO1 = MI->getOperand(OpNum);
579  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
580 
581  O << (MO2.getImm() ? "" : "-");
582  printRegName(O, MO1.getReg());
583 }
584 
586  const MCSubtargetInfo &STI,
587  raw_ostream &O) {
588  const MCOperand &MO = MI->getOperand(OpNum);
589  unsigned Imm = MO.getImm();
590  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
591  << markup(">");
592 }
593 
594 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
595  const MCSubtargetInfo &STI,
596  raw_ostream &O) {
599  O << ARM_AM::getAMSubModeStr(Mode);
600 }
601 
602 template <bool AlwaysPrintImm0>
603 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
604  const MCSubtargetInfo &STI,
605  raw_ostream &O) {
606  const MCOperand &MO1 = MI->getOperand(OpNum);
607  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
608 
609  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
610  printOperand(MI, OpNum, STI, O);
611  return;
612  }
613 
614  O << markup("<mem:") << "[";
615  printRegName(O, MO1.getReg());
616 
617  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
619  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
620  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
621  << ImmOffs * 4 << markup(">");
622  }
623  O << "]" << markup(">");
624 }
625 
626 template <bool AlwaysPrintImm0>
628  const MCSubtargetInfo &STI,
629  raw_ostream &O) {
630  const MCOperand &MO1 = MI->getOperand(OpNum);
631  const MCOperand &MO2 = MI->getOperand(OpNum+1);
632 
633  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
634  printOperand(MI, OpNum, STI, O);
635  return;
636  }
637 
638  O << markup("<mem:") << "[";
639  printRegName(O, MO1.getReg());
640 
641  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
642  unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
643  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
644  O << ", "
645  << markup("<imm:")
646  << "#"
648  << ImmOffs * 2
649  << markup(">");
650  }
651  O << "]" << markup(">");
652 }
653 
654 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
655  const MCSubtargetInfo &STI,
656  raw_ostream &O) {
657  const MCOperand &MO1 = MI->getOperand(OpNum);
658  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
659 
660  O << markup("<mem:") << "[";
661  printRegName(O, MO1.getReg());
662  if (MO2.getImm()) {
663  O << ":" << (MO2.getImm() << 3);
664  }
665  O << "]" << markup(">");
666 }
667 
668 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
669  const MCSubtargetInfo &STI,
670  raw_ostream &O) {
671  const MCOperand &MO1 = MI->getOperand(OpNum);
672  O << markup("<mem:") << "[";
673  printRegName(O, MO1.getReg());
674  O << "]" << markup(">");
675 }
676 
678  unsigned OpNum,
679  const MCSubtargetInfo &STI,
680  raw_ostream &O) {
681  const MCOperand &MO = MI->getOperand(OpNum);
682  if (MO.getReg() == 0)
683  O << "!";
684  else {
685  O << ", ";
686  printRegName(O, MO.getReg());
687  }
688 }
689 
691  unsigned OpNum,
692  const MCSubtargetInfo &STI,
693  raw_ostream &O) {
694  const MCOperand &MO = MI->getOperand(OpNum);
695  uint32_t v = ~MO.getImm();
696  int32_t lsb = countTrailingZeros(v);
697  int32_t width = (32 - countLeadingZeros(v)) - lsb;
698  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
699  O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
700  << '#' << width << markup(">");
701 }
702 
703 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
704  const MCSubtargetInfo &STI,
705  raw_ostream &O) {
706  unsigned val = MI->getOperand(OpNum).getImm();
707  O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
708 }
709 
710 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
711  const MCSubtargetInfo &STI,
712  raw_ostream &O) {
713  unsigned val = MI->getOperand(OpNum).getImm();
715 }
716 
717 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
718  const MCSubtargetInfo &STI,
719  raw_ostream &O) {
720  unsigned val = MI->getOperand(OpNum).getImm();
722 }
723 
724 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
725  const MCSubtargetInfo &STI,
726  raw_ostream &O) {
727  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
728  bool isASR = (ShiftOp & (1 << 5)) != 0;
729  unsigned Amt = ShiftOp & 0x1f;
730  if (isASR) {
731  O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
732  << markup(">");
733  } else if (Amt) {
734  O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
735  }
736 }
737 
738 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
739  const MCSubtargetInfo &STI,
740  raw_ostream &O) {
741  unsigned Imm = MI->getOperand(OpNum).getImm();
742  if (Imm == 0)
743  return;
744  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
745  O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
746 }
747 
748 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
749  const MCSubtargetInfo &STI,
750  raw_ostream &O) {
751  unsigned Imm = MI->getOperand(OpNum).getImm();
752  // A shift amount of 32 is encoded as 0.
753  if (Imm == 0)
754  Imm = 32;
755  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
756  O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
757 }
758 
759 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
760  const MCSubtargetInfo &STI,
761  raw_ostream &O) {
762  assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
763  [&](const MCOperand &LHS, const MCOperand &RHS) {
764  return MRI.getEncodingValue(LHS.getReg()) <
765  MRI.getEncodingValue(RHS.getReg());
766  }));
767 
768  O << "{";
769  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
770  if (i != OpNum)
771  O << ", ";
772  printRegName(O, MI->getOperand(i).getReg());
773  }
774  O << "}";
775 }
776 
777 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
778  const MCSubtargetInfo &STI,
779  raw_ostream &O) {
780  unsigned Reg = MI->getOperand(OpNum).getReg();
781  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
782  O << ", ";
783  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
784 }
785 
786 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
787  const MCSubtargetInfo &STI,
788  raw_ostream &O) {
789  const MCOperand &Op = MI->getOperand(OpNum);
790  if (Op.getImm())
791  O << "be";
792  else
793  O << "le";
794 }
795 
796 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
797  const MCSubtargetInfo &STI, raw_ostream &O) {
798  const MCOperand &Op = MI->getOperand(OpNum);
799  O << ARM_PROC::IModToString(Op.getImm());
800 }
801 
802 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
803  const MCSubtargetInfo &STI, raw_ostream &O) {
804  const MCOperand &Op = MI->getOperand(OpNum);
805  unsigned IFlags = Op.getImm();
806  for (int i = 2; i >= 0; --i)
807  if (IFlags & (1 << i))
808  O << ARM_PROC::IFlagsToString(1 << i);
809 
810  if (IFlags == 0)
811  O << "none";
812 }
813 
814 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
815  const MCSubtargetInfo &STI,
816  raw_ostream &O) {
817  const MCOperand &Op = MI->getOperand(OpNum);
818  const FeatureBitset &FeatureBits = STI.getFeatureBits();
819  if (FeatureBits[ARM::FeatureMClass]) {
820 
821  unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
822  unsigned Opcode = MI->getOpcode();
823 
824  // For writes, handle extended mask bits if the DSP extension is present.
825  if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
827  if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
828  O << TheReg->Name;
829  return;
830  }
831  }
832 
833  // Handle the basic 8-bit mask.
834  SYSm &= 0xff;
835  if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
836  // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
837  // alias for MSR APSR_nzcvq.
839  if (TheReg) {
840  O << TheReg->Name;
841  return;
842  }
843  }
844 
846  if (TheReg) {
847  O << TheReg->Name;
848  return;
849  }
850 
851  O << SYSm;
852 
853  return;
854  }
855 
856  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
857  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
858  unsigned SpecRegRBit = Op.getImm() >> 4;
859  unsigned Mask = Op.getImm() & 0xf;
860 
861  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
862  O << "APSR_";
863  switch (Mask) {
864  default:
865  llvm_unreachable("Unexpected mask value!");
866  case 4:
867  O << "g";
868  return;
869  case 8:
870  O << "nzcvq";
871  return;
872  case 12:
873  O << "nzcvqg";
874  return;
875  }
876  }
877 
878  if (SpecRegRBit)
879  O << "SPSR";
880  else
881  O << "CPSR";
882 
883  if (Mask) {
884  O << '_';
885  if (Mask & 8)
886  O << 'f';
887  if (Mask & 4)
888  O << 's';
889  if (Mask & 2)
890  O << 'x';
891  if (Mask & 1)
892  O << 'c';
893  }
894 }
895 
896 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
897  const MCSubtargetInfo &STI,
898  raw_ostream &O) {
899  uint32_t Banked = MI->getOperand(OpNum).getImm();
900  auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
901  assert(TheReg && "invalid banked register operand");
902  std::string Name = TheReg->Name;
903 
904  uint32_t isSPSR = (Banked & 0x20) >> 5;
905  if (isSPSR)
906  Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
907  O << Name;
908 }
909 
910 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
911  const MCSubtargetInfo &STI,
912  raw_ostream &O) {
914  // Handle the undefined 15 CC value here for printing so we don't abort().
915  if ((unsigned)CC == 15)
916  O << "<und>";
917  else if (CC != ARMCC::AL)
918  O << ARMCondCodeToString(CC);
919 }
920 
922  unsigned OpNum,
923  const MCSubtargetInfo &STI,
924  raw_ostream &O) {
926  O << ARMCondCodeToString(CC);
927 }
928 
930  const MCSubtargetInfo &STI,
931  raw_ostream &O) {
932  if (MI->getOperand(OpNum).getReg()) {
933  assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
934  "Expect ARM CPSR register!");
935  O << 's';
936  }
937 }
938 
939 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
940  const MCSubtargetInfo &STI,
941  raw_ostream &O) {
942  O << MI->getOperand(OpNum).getImm();
943 }
944 
945 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
946  const MCSubtargetInfo &STI,
947  raw_ostream &O) {
948  O << "p" << MI->getOperand(OpNum).getImm();
949 }
950 
951 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
952  const MCSubtargetInfo &STI,
953  raw_ostream &O) {
954  O << "c" << MI->getOperand(OpNum).getImm();
955 }
956 
957 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
958  const MCSubtargetInfo &STI,
959  raw_ostream &O) {
960  O << "{" << MI->getOperand(OpNum).getImm() << "}";
961 }
962 
963 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
964  const MCSubtargetInfo &STI, raw_ostream &O) {
965  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
966 }
967 
968 template <unsigned scale>
969 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
970  const MCSubtargetInfo &STI,
971  raw_ostream &O) {
972  const MCOperand &MO = MI->getOperand(OpNum);
973 
974  if (MO.isExpr()) {
975  MO.getExpr()->print(O, &MAI);
976  return;
977  }
978 
979  int32_t OffImm = (int32_t)MO.getImm() << scale;
980 
981  O << markup("<imm:");
982  if (OffImm == INT32_MIN)
983  O << "#-0";
984  else if (OffImm < 0)
985  O << "#-" << -OffImm;
986  else
987  O << "#" << OffImm;
988  O << markup(">");
989 }
990 
992  const MCSubtargetInfo &STI,
993  raw_ostream &O) {
994  O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
995  << markup(">");
996 }
997 
998 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
999  const MCSubtargetInfo &STI,
1000  raw_ostream &O) {
1001  unsigned Imm = MI->getOperand(OpNum).getImm();
1002  O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1003  << markup(">");
1004 }
1005 
1006 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1007  const MCSubtargetInfo &STI,
1008  raw_ostream &O) {
1009  // (3 - the number of trailing zeros) is the number of then / else.
1010  unsigned Mask = MI->getOperand(OpNum).getImm();
1011  unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1012  unsigned CondBit0 = Firstcond & 1;
1013  unsigned NumTZ = countTrailingZeros(Mask);
1014  assert(NumTZ <= 3 && "Invalid IT mask!");
1015  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1016  bool T = ((Mask >> Pos) & 1) == CondBit0;
1017  if (T)
1018  O << 't';
1019  else
1020  O << 'e';
1021  }
1022 }
1023 
1025  const MCSubtargetInfo &STI,
1026  raw_ostream &O) {
1027  const MCOperand &MO1 = MI->getOperand(Op);
1028  const MCOperand &MO2 = MI->getOperand(Op + 1);
1029 
1030  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1031  printOperand(MI, Op, STI, O);
1032  return;
1033  }
1034 
1035  O << markup("<mem:") << "[";
1036  printRegName(O, MO1.getReg());
1037  if (unsigned RegNum = MO2.getReg()) {
1038  O << ", ";
1039  printRegName(O, RegNum);
1040  }
1041  O << "]" << markup(">");
1042 }
1043 
1045  unsigned Op,
1046  const MCSubtargetInfo &STI,
1047  raw_ostream &O,
1048  unsigned Scale) {
1049  const MCOperand &MO1 = MI->getOperand(Op);
1050  const MCOperand &MO2 = MI->getOperand(Op + 1);
1051 
1052  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1053  printOperand(MI, Op, STI, O);
1054  return;
1055  }
1056 
1057  O << markup("<mem:") << "[";
1058  printRegName(O, MO1.getReg());
1059  if (unsigned ImmOffs = MO2.getImm()) {
1060  O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1061  << markup(">");
1062  }
1063  O << "]" << markup(">");
1064 }
1065 
1067  unsigned Op,
1068  const MCSubtargetInfo &STI,
1069  raw_ostream &O) {
1070  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1071 }
1072 
1074  unsigned Op,
1075  const MCSubtargetInfo &STI,
1076  raw_ostream &O) {
1077  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1078 }
1079 
1081  unsigned Op,
1082  const MCSubtargetInfo &STI,
1083  raw_ostream &O) {
1084  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1085 }
1086 
1088  const MCSubtargetInfo &STI,
1089  raw_ostream &O) {
1090  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1091 }
1092 
1093 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1094 // register with shift forms.
1095 // REG 0 0 - e.g. R5
1096 // REG IMM, SH_OPC - e.g. R5, LSL #3
1097 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1098  const MCSubtargetInfo &STI,
1099  raw_ostream &O) {
1100  const MCOperand &MO1 = MI->getOperand(OpNum);
1101  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1102 
1103  unsigned Reg = MO1.getReg();
1104  printRegName(O, Reg);
1105 
1106  // Print the shift opc.
1107  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1110 }
1111 
1112 template <bool AlwaysPrintImm0>
1114  const MCSubtargetInfo &STI,
1115  raw_ostream &O) {
1116  const MCOperand &MO1 = MI->getOperand(OpNum);
1117  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1118 
1119  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1120  printOperand(MI, OpNum, STI, O);
1121  return;
1122  }
1123 
1124  O << markup("<mem:") << "[";
1125  printRegName(O, MO1.getReg());
1126 
1127  int32_t OffImm = (int32_t)MO2.getImm();
1128  bool isSub = OffImm < 0;
1129  // Special value for #-0. All others are normal.
1130  if (OffImm == INT32_MIN)
1131  OffImm = 0;
1132  if (isSub) {
1133  O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1134  } else if (AlwaysPrintImm0 || OffImm > 0) {
1135  O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1136  }
1137  O << "]" << markup(">");
1138 }
1139 
1140 template <bool AlwaysPrintImm0>
1142  unsigned OpNum,
1143  const MCSubtargetInfo &STI,
1144  raw_ostream &O) {
1145  const MCOperand &MO1 = MI->getOperand(OpNum);
1146  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1147 
1148  O << markup("<mem:") << "[";
1149  printRegName(O, MO1.getReg());
1150 
1151  int32_t OffImm = (int32_t)MO2.getImm();
1152  bool isSub = OffImm < 0;
1153  // Don't print +0.
1154  if (OffImm == INT32_MIN)
1155  OffImm = 0;
1156  if (isSub) {
1157  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1158  } else if (AlwaysPrintImm0 || OffImm > 0) {
1159  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1160  }
1161  O << "]" << markup(">");
1162 }
1163 
1164 template <bool AlwaysPrintImm0>
1166  unsigned OpNum,
1167  const MCSubtargetInfo &STI,
1168  raw_ostream &O) {
1169  const MCOperand &MO1 = MI->getOperand(OpNum);
1170  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1171 
1172  if (!MO1.isReg()) { // For label symbolic references.
1173  printOperand(MI, OpNum, STI, O);
1174  return;
1175  }
1176 
1177  O << markup("<mem:") << "[";
1178  printRegName(O, MO1.getReg());
1179 
1180  int32_t OffImm = (int32_t)MO2.getImm();
1181  bool isSub = OffImm < 0;
1182 
1183  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1184 
1185  // Don't print +0.
1186  if (OffImm == INT32_MIN)
1187  OffImm = 0;
1188  if (isSub) {
1189  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1190  } else if (AlwaysPrintImm0 || OffImm > 0) {
1191  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1192  }
1193  O << "]" << markup(">");
1194 }
1195 
1197  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1198  raw_ostream &O) {
1199  const MCOperand &MO1 = MI->getOperand(OpNum);
1200  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1201 
1202  O << markup("<mem:") << "[";
1203  printRegName(O, MO1.getReg());
1204  if (MO2.getImm()) {
1205  O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1206  << markup(">");
1207  }
1208  O << "]" << markup(">");
1209 }
1210 
1212  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1213  raw_ostream &O) {
1214  const MCOperand &MO1 = MI->getOperand(OpNum);
1215  int32_t OffImm = (int32_t)MO1.getImm();
1216  O << ", " << markup("<imm:");
1217  if (OffImm == INT32_MIN)
1218  O << "#-0";
1219  else if (OffImm < 0)
1220  O << "#-" << -OffImm;
1221  else
1222  O << "#" << OffImm;
1223  O << markup(">");
1224 }
1225 
1227  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1228  raw_ostream &O) {
1229  const MCOperand &MO1 = MI->getOperand(OpNum);
1230  int32_t OffImm = (int32_t)MO1.getImm();
1231 
1232  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1233 
1234  O << ", " << markup("<imm:");
1235  if (OffImm == INT32_MIN)
1236  O << "#-0";
1237  else if (OffImm < 0)
1238  O << "#-" << -OffImm;
1239  else
1240  O << "#" << OffImm;
1241  O << markup(">");
1242 }
1243 
1245  unsigned OpNum,
1246  const MCSubtargetInfo &STI,
1247  raw_ostream &O) {
1248  const MCOperand &MO1 = MI->getOperand(OpNum);
1249  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1250  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1251 
1252  O << markup("<mem:") << "[";
1253  printRegName(O, MO1.getReg());
1254 
1255  assert(MO2.getReg() && "Invalid so_reg load / store address!");
1256  O << ", ";
1257  printRegName(O, MO2.getReg());
1258 
1259  unsigned ShAmt = MO3.getImm();
1260  if (ShAmt) {
1261  assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1262  O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1263  }
1264  O << "]" << markup(">");
1265 }
1266 
1267 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1268  const MCSubtargetInfo &STI,
1269  raw_ostream &O) {
1270  const MCOperand &MO = MI->getOperand(OpNum);
1271  O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1272  << markup(">");
1273 }
1274 
1276  const MCSubtargetInfo &STI,
1277  raw_ostream &O) {
1278  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1279  unsigned EltBits;
1280  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1281  O << markup("<imm:") << "#0x";
1282  O.write_hex(Val);
1283  O << markup(">");
1284 }
1285 
1287  const MCSubtargetInfo &STI,
1288  raw_ostream &O) {
1289  unsigned Imm = MI->getOperand(OpNum).getImm();
1290  O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1291 }
1292 
1293 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1294  const MCSubtargetInfo &STI,
1295  raw_ostream &O) {
1296  unsigned Imm = MI->getOperand(OpNum).getImm();
1297  if (Imm == 0)
1298  return;
1299  assert(Imm <= 3 && "illegal ror immediate!");
1300  O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1301 }
1302 
1303 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1304  const MCSubtargetInfo &STI,
1305  raw_ostream &O) {
1306  MCOperand Op = MI->getOperand(OpNum);
1307 
1308  // Support for fixups (MCFixup)
1309  if (Op.isExpr())
1310  return printOperand(MI, OpNum, STI, O);
1311 
1312  unsigned Bits = Op.getImm() & 0xFF;
1313  unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1314 
1315  bool PrintUnsigned = false;
1316  switch (MI->getOpcode()) {
1317  case ARM::MOVi:
1318  // Movs to PC should be treated unsigned
1319  PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1320  break;
1321  case ARM::MSRi:
1322  // Movs to special registers should be treated unsigned
1323  PrintUnsigned = true;
1324  break;
1325  }
1326 
1327  int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1328  if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1329  // #rot has the least possible value
1330  O << "#" << markup("<imm:");
1331  if (PrintUnsigned)
1332  O << static_cast<uint32_t>(Rotated);
1333  else
1334  O << Rotated;
1335  O << markup(">");
1336  return;
1337  }
1338 
1339  // Explicit #bits, #rot implied
1340  O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1341  << Rot << markup(">");
1342 }
1343 
1344 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1345  const MCSubtargetInfo &STI, raw_ostream &O) {
1346  O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1347  << markup(">");
1348 }
1349 
1350 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1351  const MCSubtargetInfo &STI, raw_ostream &O) {
1352  O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1353  << markup(">");
1354 }
1355 
1356 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1357  const MCSubtargetInfo &STI,
1358  raw_ostream &O) {
1359  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1360 }
1361 
1362 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1363  const MCSubtargetInfo &STI,
1364  raw_ostream &O) {
1365  O << "{";
1366  printRegName(O, MI->getOperand(OpNum).getReg());
1367  O << "}";
1368 }
1369 
1370 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1371  const MCSubtargetInfo &STI,
1372  raw_ostream &O) {
1373  unsigned Reg = MI->getOperand(OpNum).getReg();
1374  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1375  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1376  O << "{";
1377  printRegName(O, Reg0);
1378  O << ", ";
1379  printRegName(O, Reg1);
1380  O << "}";
1381 }
1382 
1384  const MCSubtargetInfo &STI,
1385  raw_ostream &O) {
1386  unsigned Reg = MI->getOperand(OpNum).getReg();
1387  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1388  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1389  O << "{";
1390  printRegName(O, Reg0);
1391  O << ", ";
1392  printRegName(O, Reg1);
1393  O << "}";
1394 }
1395 
1396 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1397  const MCSubtargetInfo &STI,
1398  raw_ostream &O) {
1399  // Normally, it's not safe to use register enum values directly with
1400  // addition to get the next register, but for VFP registers, the
1401  // sort order is guaranteed because they're all of the form D<n>.
1402  O << "{";
1403  printRegName(O, MI->getOperand(OpNum).getReg());
1404  O << ", ";
1405  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1406  O << ", ";
1407  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1408  O << "}";
1409 }
1410 
1411 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1412  const MCSubtargetInfo &STI,
1413  raw_ostream &O) {
1414  // Normally, it's not safe to use register enum values directly with
1415  // addition to get the next register, but for VFP registers, the
1416  // sort order is guaranteed because they're all of the form D<n>.
1417  O << "{";
1418  printRegName(O, MI->getOperand(OpNum).getReg());
1419  O << ", ";
1420  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1421  O << ", ";
1422  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1423  O << ", ";
1424  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1425  O << "}";
1426 }
1427 
1429  unsigned OpNum,
1430  const MCSubtargetInfo &STI,
1431  raw_ostream &O) {
1432  O << "{";
1433  printRegName(O, MI->getOperand(OpNum).getReg());
1434  O << "[]}";
1435 }
1436 
1438  unsigned OpNum,
1439  const MCSubtargetInfo &STI,
1440  raw_ostream &O) {
1441  unsigned Reg = MI->getOperand(OpNum).getReg();
1442  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1443  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1444  O << "{";
1445  printRegName(O, Reg0);
1446  O << "[], ";
1447  printRegName(O, Reg1);
1448  O << "[]}";
1449 }
1450 
1452  unsigned OpNum,
1453  const MCSubtargetInfo &STI,
1454  raw_ostream &O) {
1455  // Normally, it's not safe to use register enum values directly with
1456  // addition to get the next register, but for VFP registers, the
1457  // sort order is guaranteed because they're all of the form D<n>.
1458  O << "{";
1459  printRegName(O, MI->getOperand(OpNum).getReg());
1460  O << "[], ";
1461  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1462  O << "[], ";
1463  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1464  O << "[]}";
1465 }
1466 
1468  unsigned OpNum,
1469  const MCSubtargetInfo &STI,
1470  raw_ostream &O) {
1471  // Normally, it's not safe to use register enum values directly with
1472  // addition to get the next register, but for VFP registers, the
1473  // sort order is guaranteed because they're all of the form D<n>.
1474  O << "{";
1475  printRegName(O, MI->getOperand(OpNum).getReg());
1476  O << "[], ";
1477  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1478  O << "[], ";
1479  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1480  O << "[], ";
1481  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1482  O << "[]}";
1483 }
1484 
1486  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1487  raw_ostream &O) {
1488  unsigned Reg = MI->getOperand(OpNum).getReg();
1489  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1490  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1491  O << "{";
1492  printRegName(O, Reg0);
1493  O << "[], ";
1494  printRegName(O, Reg1);
1495  O << "[]}";
1496 }
1497 
1499  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1500  raw_ostream &O) {
1501  // Normally, it's not safe to use register enum values directly with
1502  // addition to get the next register, but for VFP registers, the
1503  // sort order is guaranteed because they're all of the form D<n>.
1504  O << "{";
1505  printRegName(O, MI->getOperand(OpNum).getReg());
1506  O << "[], ";
1507  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1508  O << "[], ";
1509  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1510  O << "[]}";
1511 }
1512 
1514  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1515  raw_ostream &O) {
1516  // Normally, it's not safe to use register enum values directly with
1517  // addition to get the next register, but for VFP registers, the
1518  // sort order is guaranteed because they're all of the form D<n>.
1519  O << "{";
1520  printRegName(O, MI->getOperand(OpNum).getReg());
1521  O << "[], ";
1522  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1523  O << "[], ";
1524  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1525  O << "[], ";
1526  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1527  O << "[]}";
1528 }
1529 
1531  unsigned OpNum,
1532  const MCSubtargetInfo &STI,
1533  raw_ostream &O) {
1534  // Normally, it's not safe to use register enum values directly with
1535  // addition to get the next register, but for VFP registers, the
1536  // sort order is guaranteed because they're all of the form D<n>.
1537  O << "{";
1538  printRegName(O, MI->getOperand(OpNum).getReg());
1539  O << ", ";
1540  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1541  O << ", ";
1542  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1543  O << "}";
1544 }
1545 
1547  const MCSubtargetInfo &STI,
1548  raw_ostream &O) {
1549  // Normally, it's not safe to use register enum values directly with
1550  // addition to get the next register, but for VFP registers, the
1551  // sort order is guaranteed because they're all of the form D<n>.
1552  O << "{";
1553  printRegName(O, MI->getOperand(OpNum).getReg());
1554  O << ", ";
1555  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1556  O << ", ";
1557  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1558  O << ", ";
1559  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1560  O << "}";
1561 }
1562 
1563 template<int64_t Angle, int64_t Remainder>
1565  const MCSubtargetInfo &STI,
1566  raw_ostream &O) {
1567  unsigned Val = MI->getOperand(OpNo).getImm();
1568  O << "#" << (Val * Angle) + Remainder;
1569 }
1570 
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
iterator end()
Definition: MCInst.h:193
iterator begin()
Definition: MCInst.h:191
bool isImm() const
Definition: MCInst.h:58
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
SI Whole Quad Mode
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
unsigned Reg
unsigned getAM2IdxMode(unsigned AM2Opc)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:57
const char * getAMSubModeStr(AMSubMode Mode)
#define op(i)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits)
decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size...
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:33
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const char * getShiftOpcStr(ShiftOpc Op)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AMSubMode getAM4SubMode(unsigned Mode)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:95
static bool isStore(int Opcode)
float getFPImmFloat(unsigned Imm)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:95
static const char * getRegisterName(unsigned RegNo)
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
int64_t getImm() const
Definition: MCInst.h:75
unsigned char getAM5Offset(unsigned AM5Opc)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM3Op(unsigned AM3Opc)
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:134
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getSORegOffset(unsigned Op)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
Definition: Constant.h:41
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
Definition: ARMBaseInfo.cpp:28
static const char * TraceSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:105
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
bool isExpr() const
Definition: MCInst.h:60
unsigned getNumOperands() const
Definition: MCInst.h:181
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:22
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:69
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:46
const char * getAddrOpcStr(AddrOpc Op)
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void setOpcode(unsigned Op)
Definition: MCInst.h:170
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
unsigned getAM2Offset(unsigned AM2Opc)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:77
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:449
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:37
ShiftOpc getSORegShOp(unsigned Op)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:45
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
bool UseMarkup
True if we are printing marked up assembly.
Definition: MCInstPrinter.h:50
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Constant expressions.
Definition: MCExpr.h:39
Binary expressions.
Definition: MCExpr.h:38
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5Op(unsigned AM5Opc)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getOpcode() const
Definition: MCInst.h:171
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:47
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)