LLVM  7.0.0svn
ARMInstPrinter.cpp
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1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an ARM MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstPrinter.h"
15 #include "Utils/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/Casting.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "asm-printer"
36 
37 #define PRINT_ALIAS_INSTR
38 #include "ARMGenAsmWriter.inc"
39 
40 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
41 ///
42 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
43 static unsigned translateShiftImm(unsigned imm) {
44  // lsr #32 and asr #32 exist, but should be encoded as a 0.
45  assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
46 
47  if (imm == 0)
48  return 32;
49  return imm;
50 }
51 
52 /// Prints the shift value with an immediate value.
54  unsigned ShImm, bool UseMarkup) {
55  if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
56  return;
57  O << ", ";
58 
59  assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
60  O << getShiftOpcStr(ShOpc);
61 
62  if (ShOpc != ARM_AM::rrx) {
63  O << " ";
64  if (UseMarkup)
65  O << "<imm:";
66  O << "#" << translateShiftImm(ShImm);
67  if (UseMarkup)
68  O << ">";
69  }
70 }
71 
73  const MCRegisterInfo &MRI)
74  : MCInstPrinter(MAI, MII, MRI) {}
75 
76 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
77  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
78 }
79 
81  StringRef Annot, const MCSubtargetInfo &STI) {
82  unsigned Opcode = MI->getOpcode();
83 
84  switch (Opcode) {
85  // Check for MOVs and print canonical forms, instead.
86  case ARM::MOVsr: {
87  // FIXME: Thumb variants?
88  const MCOperand &Dst = MI->getOperand(0);
89  const MCOperand &MO1 = MI->getOperand(1);
90  const MCOperand &MO2 = MI->getOperand(2);
91  const MCOperand &MO3 = MI->getOperand(3);
92 
94  printSBitModifierOperand(MI, 6, STI, O);
95  printPredicateOperand(MI, 4, STI, O);
96 
97  O << '\t';
98  printRegName(O, Dst.getReg());
99  O << ", ";
100  printRegName(O, MO1.getReg());
101 
102  O << ", ";
103  printRegName(O, MO2.getReg());
104  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
105  printAnnotation(O, Annot);
106  return;
107  }
108 
109  case ARM::MOVsi: {
110  // FIXME: Thumb variants?
111  const MCOperand &Dst = MI->getOperand(0);
112  const MCOperand &MO1 = MI->getOperand(1);
113  const MCOperand &MO2 = MI->getOperand(2);
114 
116  printSBitModifierOperand(MI, 5, STI, O);
117  printPredicateOperand(MI, 3, STI, O);
118 
119  O << '\t';
120  printRegName(O, Dst.getReg());
121  O << ", ";
122  printRegName(O, MO1.getReg());
123 
124  if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
125  printAnnotation(O, Annot);
126  return;
127  }
128 
129  O << ", " << markup("<imm:") << "#"
131  printAnnotation(O, Annot);
132  return;
133  }
134 
135  // A8.6.123 PUSH
136  case ARM::STMDB_UPD:
137  case ARM::t2STMDB_UPD:
138  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
139  // Should only print PUSH if there are at least two registers in the list.
140  O << '\t' << "push";
141  printPredicateOperand(MI, 2, STI, O);
142  if (Opcode == ARM::t2STMDB_UPD)
143  O << ".w";
144  O << '\t';
145  printRegisterList(MI, 4, STI, O);
146  printAnnotation(O, Annot);
147  return;
148  } else
149  break;
150 
151  case ARM::STR_PRE_IMM:
152  if (MI->getOperand(2).getReg() == ARM::SP &&
153  MI->getOperand(3).getImm() == -4) {
154  O << '\t' << "push";
155  printPredicateOperand(MI, 4, STI, O);
156  O << "\t{";
157  printRegName(O, MI->getOperand(1).getReg());
158  O << "}";
159  printAnnotation(O, Annot);
160  return;
161  } else
162  break;
163 
164  // A8.6.122 POP
165  case ARM::LDMIA_UPD:
166  case ARM::t2LDMIA_UPD:
167  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
168  // Should only print POP if there are at least two registers in the list.
169  O << '\t' << "pop";
170  printPredicateOperand(MI, 2, STI, O);
171  if (Opcode == ARM::t2LDMIA_UPD)
172  O << ".w";
173  O << '\t';
174  printRegisterList(MI, 4, STI, O);
175  printAnnotation(O, Annot);
176  return;
177  } else
178  break;
179 
180  case ARM::LDR_POST_IMM:
181  if (MI->getOperand(2).getReg() == ARM::SP &&
182  MI->getOperand(4).getImm() == 4) {
183  O << '\t' << "pop";
184  printPredicateOperand(MI, 5, STI, O);
185  O << "\t{";
186  printRegName(O, MI->getOperand(0).getReg());
187  O << "}";
188  printAnnotation(O, Annot);
189  return;
190  } else
191  break;
192 
193  // A8.6.355 VPUSH
194  case ARM::VSTMSDB_UPD:
195  case ARM::VSTMDDB_UPD:
196  if (MI->getOperand(0).getReg() == ARM::SP) {
197  O << '\t' << "vpush";
198  printPredicateOperand(MI, 2, STI, O);
199  O << '\t';
200  printRegisterList(MI, 4, STI, O);
201  printAnnotation(O, Annot);
202  return;
203  } else
204  break;
205 
206  // A8.6.354 VPOP
207  case ARM::VLDMSIA_UPD:
208  case ARM::VLDMDIA_UPD:
209  if (MI->getOperand(0).getReg() == ARM::SP) {
210  O << '\t' << "vpop";
211  printPredicateOperand(MI, 2, STI, O);
212  O << '\t';
213  printRegisterList(MI, 4, STI, O);
214  printAnnotation(O, Annot);
215  return;
216  } else
217  break;
218 
219  case ARM::tLDMIA: {
220  bool Writeback = true;
221  unsigned BaseReg = MI->getOperand(0).getReg();
222  for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
223  if (MI->getOperand(i).getReg() == BaseReg)
224  Writeback = false;
225  }
226 
227  O << "\tldm";
228 
229  printPredicateOperand(MI, 1, STI, O);
230  O << '\t';
231  printRegName(O, BaseReg);
232  if (Writeback)
233  O << "!";
234  O << ", ";
235  printRegisterList(MI, 3, STI, O);
236  printAnnotation(O, Annot);
237  return;
238  }
239 
240  // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
241  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
242  // a single GPRPair reg operand is used in the .td file to replace the two
243  // GPRs. However, when decoding them, the two GRPs cannot be automatically
244  // expressed as a GPRPair, so we have to manually merge them.
245  // FIXME: We would really like to be able to tablegen'erate this.
246  case ARM::LDREXD:
247  case ARM::STREXD:
248  case ARM::LDAEXD:
249  case ARM::STLEXD: {
250  const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
251  bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
252  unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
253  if (MRC.contains(Reg)) {
254  MCInst NewMI;
255  MCOperand NewReg;
256  NewMI.setOpcode(Opcode);
257 
258  if (isStore)
259  NewMI.addOperand(MI->getOperand(0));
261  Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
262  NewMI.addOperand(NewReg);
263 
264  // Copy the rest operands into NewMI.
265  for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
266  NewMI.addOperand(MI->getOperand(i));
267  printInstruction(&NewMI, STI, O);
268  return;
269  }
270  break;
271  }
272  }
273 
274  if (!printAliasInstr(MI, STI, O))
275  printInstruction(MI, STI, O);
276 
277  printAnnotation(O, Annot);
278 }
279 
280 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
281  const MCSubtargetInfo &STI, raw_ostream &O) {
282  const MCOperand &Op = MI->getOperand(OpNo);
283  if (Op.isReg()) {
284  unsigned Reg = Op.getReg();
285  printRegName(O, Reg);
286  } else if (Op.isImm()) {
287  O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
288  } else {
289  assert(Op.isExpr() && "unknown operand kind in printOperand");
290  const MCExpr *Expr = Op.getExpr();
291  switch (Expr->getKind()) {
292  case MCExpr::Binary:
293  O << '#';
294  Expr->print(O, &MAI);
295  break;
296  case MCExpr::Constant: {
297  // If a symbolic branch target was added as a constant expression then
298  // print that address in hex. And only print 32 unsigned bits for the
299  // address.
300  const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
301  int64_t TargetAddress;
302  if (!Constant->evaluateAsAbsolute(TargetAddress)) {
303  O << '#';
304  Expr->print(O, &MAI);
305  } else {
306  O << "0x";
307  O.write_hex(static_cast<uint32_t>(TargetAddress));
308  }
309  break;
310  }
311  default:
312  // FIXME: Should we always treat this as if it is a constant literal and
313  // prefix it with '#'?
314  Expr->print(O, &MAI);
315  break;
316  }
317  }
318 }
319 
321  const MCSubtargetInfo &STI,
322  raw_ostream &O) {
323  const MCOperand &MO1 = MI->getOperand(OpNum);
324  if (MO1.isExpr()) {
325  MO1.getExpr()->print(O, &MAI);
326  return;
327  }
328 
329  O << markup("<mem:") << "[pc, ";
330 
331  int32_t OffImm = (int32_t)MO1.getImm();
332  bool isSub = OffImm < 0;
333 
334  // Special value for #-0. All others are normal.
335  if (OffImm == INT32_MIN)
336  OffImm = 0;
337  if (isSub) {
338  O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
339  } else {
340  O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
341  }
342  O << "]" << markup(">");
343 }
344 
345 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
346 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
347 // REG 0 0 - e.g. R5
348 // REG REG 0,SH_OPC - e.g. R5, ROR R3
349 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
350 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
351  const MCSubtargetInfo &STI,
352  raw_ostream &O) {
353  const MCOperand &MO1 = MI->getOperand(OpNum);
354  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
355  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
356 
357  printRegName(O, MO1.getReg());
358 
359  // Print the shift opc.
361  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
362  if (ShOpc == ARM_AM::rrx)
363  return;
364 
365  O << ' ';
366  printRegName(O, MO2.getReg());
367  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
368 }
369 
370 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
371  const MCSubtargetInfo &STI,
372  raw_ostream &O) {
373  const MCOperand &MO1 = MI->getOperand(OpNum);
374  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
375 
376  printRegName(O, MO1.getReg());
377 
378  // Print the shift opc.
381 }
382 
383 //===--------------------------------------------------------------------===//
384 // Addressing Mode #2
385 //===--------------------------------------------------------------------===//
386 
388  const MCSubtargetInfo &STI,
389  raw_ostream &O) {
390  const MCOperand &MO1 = MI->getOperand(Op);
391  const MCOperand &MO2 = MI->getOperand(Op + 1);
392  const MCOperand &MO3 = MI->getOperand(Op + 2);
393 
394  O << markup("<mem:") << "[";
395  printRegName(O, MO1.getReg());
396 
397  if (!MO2.getReg()) {
398  if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
399  O << ", " << markup("<imm:") << "#"
401  << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
402  }
403  O << "]" << markup(">");
404  return;
405  }
406 
407  O << ", ";
409  printRegName(O, MO2.getReg());
410 
413  O << "]" << markup(">");
414 }
415 
417  const MCSubtargetInfo &STI,
418  raw_ostream &O) {
419  const MCOperand &MO1 = MI->getOperand(Op);
420  const MCOperand &MO2 = MI->getOperand(Op + 1);
421  O << markup("<mem:") << "[";
422  printRegName(O, MO1.getReg());
423  O << ", ";
424  printRegName(O, MO2.getReg());
425  O << "]" << markup(">");
426 }
427 
429  const MCSubtargetInfo &STI,
430  raw_ostream &O) {
431  const MCOperand &MO1 = MI->getOperand(Op);
432  const MCOperand &MO2 = MI->getOperand(Op + 1);
433  O << markup("<mem:") << "[";
434  printRegName(O, MO1.getReg());
435  O << ", ";
436  printRegName(O, MO2.getReg());
437  O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
438 }
439 
441  const MCSubtargetInfo &STI,
442  raw_ostream &O) {
443  const MCOperand &MO1 = MI->getOperand(Op);
444 
445  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
446  printOperand(MI, Op, STI, O);
447  return;
448  }
449 
450 #ifndef NDEBUG
451  const MCOperand &MO3 = MI->getOperand(Op + 2);
452  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
453  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
454 #endif
455 
456  printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
457 }
458 
460  unsigned OpNum,
461  const MCSubtargetInfo &STI,
462  raw_ostream &O) {
463  const MCOperand &MO1 = MI->getOperand(OpNum);
464  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
465 
466  if (!MO1.getReg()) {
467  unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
468  O << markup("<imm:") << '#'
469  << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
470  << markup(">");
471  return;
472  }
473 
475  printRegName(O, MO1.getReg());
476 
479 }
480 
481 //===--------------------------------------------------------------------===//
482 // Addressing Mode #3
483 //===--------------------------------------------------------------------===//
484 
486  raw_ostream &O,
487  bool AlwaysPrintImm0) {
488  const MCOperand &MO1 = MI->getOperand(Op);
489  const MCOperand &MO2 = MI->getOperand(Op + 1);
490  const MCOperand &MO3 = MI->getOperand(Op + 2);
491 
492  O << markup("<mem:") << '[';
493  printRegName(O, MO1.getReg());
494 
495  if (MO2.getReg()) {
496  O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
497  printRegName(O, MO2.getReg());
498  O << ']' << markup(">");
499  return;
500  }
501 
502  // If the op is sub we have to print the immediate even if it is 0
503  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
505 
506  if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
507  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
508  << markup(">");
509  }
510  O << ']' << markup(">");
511 }
512 
513 template <bool AlwaysPrintImm0>
515  const MCSubtargetInfo &STI,
516  raw_ostream &O) {
517  const MCOperand &MO1 = MI->getOperand(Op);
518  if (!MO1.isReg()) { // For label symbolic references.
519  printOperand(MI, Op, STI, O);
520  return;
521  }
522 
525  "unexpected idxmode");
526  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
527 }
528 
530  unsigned OpNum,
531  const MCSubtargetInfo &STI,
532  raw_ostream &O) {
533  const MCOperand &MO1 = MI->getOperand(OpNum);
534  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
535 
536  if (MO1.getReg()) {
538  printRegName(O, MO1.getReg());
539  return;
540  }
541 
542  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
543  O << markup("<imm:") << '#'
544  << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
545  << markup(">");
546 }
547 
549  const MCSubtargetInfo &STI,
550  raw_ostream &O) {
551  const MCOperand &MO = MI->getOperand(OpNum);
552  unsigned Imm = MO.getImm();
553  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
554  << markup(">");
555 }
556 
558  const MCSubtargetInfo &STI,
559  raw_ostream &O) {
560  const MCOperand &MO1 = MI->getOperand(OpNum);
561  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
562 
563  O << (MO2.getImm() ? "" : "-");
564  printRegName(O, MO1.getReg());
565 }
566 
568  const MCSubtargetInfo &STI,
569  raw_ostream &O) {
570  const MCOperand &MO = MI->getOperand(OpNum);
571  unsigned Imm = MO.getImm();
572  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
573  << markup(">");
574 }
575 
576 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
577  const MCSubtargetInfo &STI,
578  raw_ostream &O) {
581  O << ARM_AM::getAMSubModeStr(Mode);
582 }
583 
584 template <bool AlwaysPrintImm0>
585 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
586  const MCSubtargetInfo &STI,
587  raw_ostream &O) {
588  const MCOperand &MO1 = MI->getOperand(OpNum);
589  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
590 
591  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
592  printOperand(MI, OpNum, STI, O);
593  return;
594  }
595 
596  O << markup("<mem:") << "[";
597  printRegName(O, MO1.getReg());
598 
599  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
601  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
602  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
603  << ImmOffs * 4 << markup(">");
604  }
605  O << "]" << markup(">");
606 }
607 
608 template <bool AlwaysPrintImm0>
610  const MCSubtargetInfo &STI,
611  raw_ostream &O) {
612  const MCOperand &MO1 = MI->getOperand(OpNum);
613  const MCOperand &MO2 = MI->getOperand(OpNum+1);
614 
615  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
616  printOperand(MI, OpNum, STI, O);
617  return;
618  }
619 
620  O << markup("<mem:") << "[";
621  printRegName(O, MO1.getReg());
622 
623  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
624  unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
625  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
626  O << ", "
627  << markup("<imm:")
628  << "#"
630  << ImmOffs * 2
631  << markup(">");
632  }
633  O << "]" << markup(">");
634 }
635 
636 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
637  const MCSubtargetInfo &STI,
638  raw_ostream &O) {
639  const MCOperand &MO1 = MI->getOperand(OpNum);
640  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
641 
642  O << markup("<mem:") << "[";
643  printRegName(O, MO1.getReg());
644  if (MO2.getImm()) {
645  O << ":" << (MO2.getImm() << 3);
646  }
647  O << "]" << markup(">");
648 }
649 
650 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
651  const MCSubtargetInfo &STI,
652  raw_ostream &O) {
653  const MCOperand &MO1 = MI->getOperand(OpNum);
654  O << markup("<mem:") << "[";
655  printRegName(O, MO1.getReg());
656  O << "]" << markup(">");
657 }
658 
660  unsigned OpNum,
661  const MCSubtargetInfo &STI,
662  raw_ostream &O) {
663  const MCOperand &MO = MI->getOperand(OpNum);
664  if (MO.getReg() == 0)
665  O << "!";
666  else {
667  O << ", ";
668  printRegName(O, MO.getReg());
669  }
670 }
671 
673  unsigned OpNum,
674  const MCSubtargetInfo &STI,
675  raw_ostream &O) {
676  const MCOperand &MO = MI->getOperand(OpNum);
677  uint32_t v = ~MO.getImm();
678  int32_t lsb = countTrailingZeros(v);
679  int32_t width = (32 - countLeadingZeros(v)) - lsb;
680  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
681  O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
682  << '#' << width << markup(">");
683 }
684 
685 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
686  const MCSubtargetInfo &STI,
687  raw_ostream &O) {
688  unsigned val = MI->getOperand(OpNum).getImm();
689  O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
690 }
691 
692 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
693  const MCSubtargetInfo &STI,
694  raw_ostream &O) {
695  unsigned val = MI->getOperand(OpNum).getImm();
697 }
698 
699 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
700  const MCSubtargetInfo &STI,
701  raw_ostream &O) {
702  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
703  bool isASR = (ShiftOp & (1 << 5)) != 0;
704  unsigned Amt = ShiftOp & 0x1f;
705  if (isASR) {
706  O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
707  << markup(">");
708  } else if (Amt) {
709  O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
710  }
711 }
712 
713 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
714  const MCSubtargetInfo &STI,
715  raw_ostream &O) {
716  unsigned Imm = MI->getOperand(OpNum).getImm();
717  if (Imm == 0)
718  return;
719  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
720  O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
721 }
722 
723 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
724  const MCSubtargetInfo &STI,
725  raw_ostream &O) {
726  unsigned Imm = MI->getOperand(OpNum).getImm();
727  // A shift amount of 32 is encoded as 0.
728  if (Imm == 0)
729  Imm = 32;
730  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
731  O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
732 }
733 
734 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
735  const MCSubtargetInfo &STI,
736  raw_ostream &O) {
737  assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
738  [&](const MCOperand &LHS, const MCOperand &RHS) {
739  return MRI.getEncodingValue(LHS.getReg()) <
740  MRI.getEncodingValue(RHS.getReg());
741  }));
742 
743  O << "{";
744  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
745  if (i != OpNum)
746  O << ", ";
747  printRegName(O, MI->getOperand(i).getReg());
748  }
749  O << "}";
750 }
751 
752 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
753  const MCSubtargetInfo &STI,
754  raw_ostream &O) {
755  unsigned Reg = MI->getOperand(OpNum).getReg();
756  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
757  O << ", ";
758  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
759 }
760 
761 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
762  const MCSubtargetInfo &STI,
763  raw_ostream &O) {
764  const MCOperand &Op = MI->getOperand(OpNum);
765  if (Op.getImm())
766  O << "be";
767  else
768  O << "le";
769 }
770 
771 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
772  const MCSubtargetInfo &STI, raw_ostream &O) {
773  const MCOperand &Op = MI->getOperand(OpNum);
774  O << ARM_PROC::IModToString(Op.getImm());
775 }
776 
777 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
778  const MCSubtargetInfo &STI, raw_ostream &O) {
779  const MCOperand &Op = MI->getOperand(OpNum);
780  unsigned IFlags = Op.getImm();
781  for (int i = 2; i >= 0; --i)
782  if (IFlags & (1 << i))
783  O << ARM_PROC::IFlagsToString(1 << i);
784 
785  if (IFlags == 0)
786  O << "none";
787 }
788 
789 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
790  const MCSubtargetInfo &STI,
791  raw_ostream &O) {
792  const MCOperand &Op = MI->getOperand(OpNum);
793  const FeatureBitset &FeatureBits = STI.getFeatureBits();
794  if (FeatureBits[ARM::FeatureMClass]) {
795 
796  unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
797  unsigned Opcode = MI->getOpcode();
798 
799  // For writes, handle extended mask bits if the DSP extension is present.
800  if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
802  if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
803  O << TheReg->Name;
804  return;
805  }
806  }
807 
808  // Handle the basic 8-bit mask.
809  SYSm &= 0xff;
810  if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
811  // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
812  // alias for MSR APSR_nzcvq.
814  if (TheReg) {
815  O << TheReg->Name;
816  return;
817  }
818  }
819 
821  if (TheReg) {
822  O << TheReg->Name;
823  return;
824  }
825 
826  O << SYSm;
827 
828  return;
829  }
830 
831  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
832  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
833  unsigned SpecRegRBit = Op.getImm() >> 4;
834  unsigned Mask = Op.getImm() & 0xf;
835 
836  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
837  O << "APSR_";
838  switch (Mask) {
839  default:
840  llvm_unreachable("Unexpected mask value!");
841  case 4:
842  O << "g";
843  return;
844  case 8:
845  O << "nzcvq";
846  return;
847  case 12:
848  O << "nzcvqg";
849  return;
850  }
851  }
852 
853  if (SpecRegRBit)
854  O << "SPSR";
855  else
856  O << "CPSR";
857 
858  if (Mask) {
859  O << '_';
860  if (Mask & 8)
861  O << 'f';
862  if (Mask & 4)
863  O << 's';
864  if (Mask & 2)
865  O << 'x';
866  if (Mask & 1)
867  O << 'c';
868  }
869 }
870 
871 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
872  const MCSubtargetInfo &STI,
873  raw_ostream &O) {
874  uint32_t Banked = MI->getOperand(OpNum).getImm();
875  auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
876  assert(TheReg && "invalid banked register operand");
877  std::string Name = TheReg->Name;
878 
879  uint32_t isSPSR = (Banked & 0x20) >> 5;
880  if (isSPSR)
881  Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
882  O << Name;
883 }
884 
885 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
886  const MCSubtargetInfo &STI,
887  raw_ostream &O) {
889  // Handle the undefined 15 CC value here for printing so we don't abort().
890  if ((unsigned)CC == 15)
891  O << "<und>";
892  else if (CC != ARMCC::AL)
893  O << ARMCondCodeToString(CC);
894 }
895 
897  unsigned OpNum,
898  const MCSubtargetInfo &STI,
899  raw_ostream &O) {
901  O << ARMCondCodeToString(CC);
902 }
903 
905  const MCSubtargetInfo &STI,
906  raw_ostream &O) {
907  if (MI->getOperand(OpNum).getReg()) {
908  assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
909  "Expect ARM CPSR register!");
910  O << 's';
911  }
912 }
913 
914 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
915  const MCSubtargetInfo &STI,
916  raw_ostream &O) {
917  O << MI->getOperand(OpNum).getImm();
918 }
919 
920 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
921  const MCSubtargetInfo &STI,
922  raw_ostream &O) {
923  O << "p" << MI->getOperand(OpNum).getImm();
924 }
925 
926 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
927  const MCSubtargetInfo &STI,
928  raw_ostream &O) {
929  O << "c" << MI->getOperand(OpNum).getImm();
930 }
931 
932 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
933  const MCSubtargetInfo &STI,
934  raw_ostream &O) {
935  O << "{" << MI->getOperand(OpNum).getImm() << "}";
936 }
937 
938 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
939  const MCSubtargetInfo &STI, raw_ostream &O) {
940  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
941 }
942 
943 template <unsigned scale>
944 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
945  const MCSubtargetInfo &STI,
946  raw_ostream &O) {
947  const MCOperand &MO = MI->getOperand(OpNum);
948 
949  if (MO.isExpr()) {
950  MO.getExpr()->print(O, &MAI);
951  return;
952  }
953 
954  int32_t OffImm = (int32_t)MO.getImm() << scale;
955 
956  O << markup("<imm:");
957  if (OffImm == INT32_MIN)
958  O << "#-0";
959  else if (OffImm < 0)
960  O << "#-" << -OffImm;
961  else
962  O << "#" << OffImm;
963  O << markup(">");
964 }
965 
967  const MCSubtargetInfo &STI,
968  raw_ostream &O) {
969  O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
970  << markup(">");
971 }
972 
973 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
974  const MCSubtargetInfo &STI,
975  raw_ostream &O) {
976  unsigned Imm = MI->getOperand(OpNum).getImm();
977  O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
978  << markup(">");
979 }
980 
981 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
982  const MCSubtargetInfo &STI,
983  raw_ostream &O) {
984  // (3 - the number of trailing zeros) is the number of then / else.
985  unsigned Mask = MI->getOperand(OpNum).getImm();
986  unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
987  unsigned CondBit0 = Firstcond & 1;
988  unsigned NumTZ = countTrailingZeros(Mask);
989  assert(NumTZ <= 3 && "Invalid IT mask!");
990  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
991  bool T = ((Mask >> Pos) & 1) == CondBit0;
992  if (T)
993  O << 't';
994  else
995  O << 'e';
996  }
997 }
998 
1000  const MCSubtargetInfo &STI,
1001  raw_ostream &O) {
1002  const MCOperand &MO1 = MI->getOperand(Op);
1003  const MCOperand &MO2 = MI->getOperand(Op + 1);
1004 
1005  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1006  printOperand(MI, Op, STI, O);
1007  return;
1008  }
1009 
1010  O << markup("<mem:") << "[";
1011  printRegName(O, MO1.getReg());
1012  if (unsigned RegNum = MO2.getReg()) {
1013  O << ", ";
1014  printRegName(O, RegNum);
1015  }
1016  O << "]" << markup(">");
1017 }
1018 
1020  unsigned Op,
1021  const MCSubtargetInfo &STI,
1022  raw_ostream &O,
1023  unsigned Scale) {
1024  const MCOperand &MO1 = MI->getOperand(Op);
1025  const MCOperand &MO2 = MI->getOperand(Op + 1);
1026 
1027  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1028  printOperand(MI, Op, STI, O);
1029  return;
1030  }
1031 
1032  O << markup("<mem:") << "[";
1033  printRegName(O, MO1.getReg());
1034  if (unsigned ImmOffs = MO2.getImm()) {
1035  O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1036  << markup(">");
1037  }
1038  O << "]" << markup(">");
1039 }
1040 
1042  unsigned Op,
1043  const MCSubtargetInfo &STI,
1044  raw_ostream &O) {
1045  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1046 }
1047 
1049  unsigned Op,
1050  const MCSubtargetInfo &STI,
1051  raw_ostream &O) {
1052  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1053 }
1054 
1056  unsigned Op,
1057  const MCSubtargetInfo &STI,
1058  raw_ostream &O) {
1059  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1060 }
1061 
1063  const MCSubtargetInfo &STI,
1064  raw_ostream &O) {
1065  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1066 }
1067 
1068 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1069 // register with shift forms.
1070 // REG 0 0 - e.g. R5
1071 // REG IMM, SH_OPC - e.g. R5, LSL #3
1072 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1073  const MCSubtargetInfo &STI,
1074  raw_ostream &O) {
1075  const MCOperand &MO1 = MI->getOperand(OpNum);
1076  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1077 
1078  unsigned Reg = MO1.getReg();
1079  printRegName(O, Reg);
1080 
1081  // Print the shift opc.
1082  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1085 }
1086 
1087 template <bool AlwaysPrintImm0>
1089  const MCSubtargetInfo &STI,
1090  raw_ostream &O) {
1091  const MCOperand &MO1 = MI->getOperand(OpNum);
1092  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1093 
1094  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1095  printOperand(MI, OpNum, STI, O);
1096  return;
1097  }
1098 
1099  O << markup("<mem:") << "[";
1100  printRegName(O, MO1.getReg());
1101 
1102  int32_t OffImm = (int32_t)MO2.getImm();
1103  bool isSub = OffImm < 0;
1104  // Special value for #-0. All others are normal.
1105  if (OffImm == INT32_MIN)
1106  OffImm = 0;
1107  if (isSub) {
1108  O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1109  } else if (AlwaysPrintImm0 || OffImm > 0) {
1110  O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1111  }
1112  O << "]" << markup(">");
1113 }
1114 
1115 template <bool AlwaysPrintImm0>
1117  unsigned OpNum,
1118  const MCSubtargetInfo &STI,
1119  raw_ostream &O) {
1120  const MCOperand &MO1 = MI->getOperand(OpNum);
1121  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1122 
1123  O << markup("<mem:") << "[";
1124  printRegName(O, MO1.getReg());
1125 
1126  int32_t OffImm = (int32_t)MO2.getImm();
1127  bool isSub = OffImm < 0;
1128  // Don't print +0.
1129  if (OffImm == INT32_MIN)
1130  OffImm = 0;
1131  if (isSub) {
1132  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1133  } else if (AlwaysPrintImm0 || OffImm > 0) {
1134  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1135  }
1136  O << "]" << markup(">");
1137 }
1138 
1139 template <bool AlwaysPrintImm0>
1141  unsigned OpNum,
1142  const MCSubtargetInfo &STI,
1143  raw_ostream &O) {
1144  const MCOperand &MO1 = MI->getOperand(OpNum);
1145  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1146 
1147  if (!MO1.isReg()) { // For label symbolic references.
1148  printOperand(MI, OpNum, STI, O);
1149  return;
1150  }
1151 
1152  O << markup("<mem:") << "[";
1153  printRegName(O, MO1.getReg());
1154 
1155  int32_t OffImm = (int32_t)MO2.getImm();
1156  bool isSub = OffImm < 0;
1157 
1158  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1159 
1160  // Don't print +0.
1161  if (OffImm == INT32_MIN)
1162  OffImm = 0;
1163  if (isSub) {
1164  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1165  } else if (AlwaysPrintImm0 || OffImm > 0) {
1166  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1167  }
1168  O << "]" << markup(">");
1169 }
1170 
1172  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1173  raw_ostream &O) {
1174  const MCOperand &MO1 = MI->getOperand(OpNum);
1175  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1176 
1177  O << markup("<mem:") << "[";
1178  printRegName(O, MO1.getReg());
1179  if (MO2.getImm()) {
1180  O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1181  << markup(">");
1182  }
1183  O << "]" << markup(">");
1184 }
1185 
1187  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1188  raw_ostream &O) {
1189  const MCOperand &MO1 = MI->getOperand(OpNum);
1190  int32_t OffImm = (int32_t)MO1.getImm();
1191  O << ", " << markup("<imm:");
1192  if (OffImm == INT32_MIN)
1193  O << "#-0";
1194  else if (OffImm < 0)
1195  O << "#-" << -OffImm;
1196  else
1197  O << "#" << OffImm;
1198  O << markup(">");
1199 }
1200 
1202  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1203  raw_ostream &O) {
1204  const MCOperand &MO1 = MI->getOperand(OpNum);
1205  int32_t OffImm = (int32_t)MO1.getImm();
1206 
1207  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1208 
1209  O << ", " << markup("<imm:");
1210  if (OffImm == INT32_MIN)
1211  O << "#-0";
1212  else if (OffImm < 0)
1213  O << "#-" << -OffImm;
1214  else
1215  O << "#" << OffImm;
1216  O << markup(">");
1217 }
1218 
1220  unsigned OpNum,
1221  const MCSubtargetInfo &STI,
1222  raw_ostream &O) {
1223  const MCOperand &MO1 = MI->getOperand(OpNum);
1224  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1225  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1226 
1227  O << markup("<mem:") << "[";
1228  printRegName(O, MO1.getReg());
1229 
1230  assert(MO2.getReg() && "Invalid so_reg load / store address!");
1231  O << ", ";
1232  printRegName(O, MO2.getReg());
1233 
1234  unsigned ShAmt = MO3.getImm();
1235  if (ShAmt) {
1236  assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1237  O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1238  }
1239  O << "]" << markup(">");
1240 }
1241 
1242 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1243  const MCSubtargetInfo &STI,
1244  raw_ostream &O) {
1245  const MCOperand &MO = MI->getOperand(OpNum);
1246  O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1247  << markup(">");
1248 }
1249 
1251  const MCSubtargetInfo &STI,
1252  raw_ostream &O) {
1253  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1254  unsigned EltBits;
1255  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1256  O << markup("<imm:") << "#0x";
1257  O.write_hex(Val);
1258  O << markup(">");
1259 }
1260 
1262  const MCSubtargetInfo &STI,
1263  raw_ostream &O) {
1264  unsigned Imm = MI->getOperand(OpNum).getImm();
1265  O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1266 }
1267 
1268 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1269  const MCSubtargetInfo &STI,
1270  raw_ostream &O) {
1271  unsigned Imm = MI->getOperand(OpNum).getImm();
1272  if (Imm == 0)
1273  return;
1274  assert(Imm <= 3 && "illegal ror immediate!");
1275  O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1276 }
1277 
1278 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1279  const MCSubtargetInfo &STI,
1280  raw_ostream &O) {
1281  MCOperand Op = MI->getOperand(OpNum);
1282 
1283  // Support for fixups (MCFixup)
1284  if (Op.isExpr())
1285  return printOperand(MI, OpNum, STI, O);
1286 
1287  unsigned Bits = Op.getImm() & 0xFF;
1288  unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1289 
1290  bool PrintUnsigned = false;
1291  switch (MI->getOpcode()) {
1292  case ARM::MOVi:
1293  // Movs to PC should be treated unsigned
1294  PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1295  break;
1296  case ARM::MSRi:
1297  // Movs to special registers should be treated unsigned
1298  PrintUnsigned = true;
1299  break;
1300  }
1301 
1302  int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1303  if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1304  // #rot has the least possible value
1305  O << "#" << markup("<imm:");
1306  if (PrintUnsigned)
1307  O << static_cast<uint32_t>(Rotated);
1308  else
1309  O << Rotated;
1310  O << markup(">");
1311  return;
1312  }
1313 
1314  // Explicit #bits, #rot implied
1315  O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1316  << Rot << markup(">");
1317 }
1318 
1319 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1320  const MCSubtargetInfo &STI, raw_ostream &O) {
1321  O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1322  << markup(">");
1323 }
1324 
1325 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1326  const MCSubtargetInfo &STI, raw_ostream &O) {
1327  O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1328  << markup(">");
1329 }
1330 
1331 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1332  const MCSubtargetInfo &STI,
1333  raw_ostream &O) {
1334  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1335 }
1336 
1337 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1338  const MCSubtargetInfo &STI,
1339  raw_ostream &O) {
1340  O << "{";
1341  printRegName(O, MI->getOperand(OpNum).getReg());
1342  O << "}";
1343 }
1344 
1345 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1346  const MCSubtargetInfo &STI,
1347  raw_ostream &O) {
1348  unsigned Reg = MI->getOperand(OpNum).getReg();
1349  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1350  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1351  O << "{";
1352  printRegName(O, Reg0);
1353  O << ", ";
1354  printRegName(O, Reg1);
1355  O << "}";
1356 }
1357 
1359  const MCSubtargetInfo &STI,
1360  raw_ostream &O) {
1361  unsigned Reg = MI->getOperand(OpNum).getReg();
1362  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1363  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1364  O << "{";
1365  printRegName(O, Reg0);
1366  O << ", ";
1367  printRegName(O, Reg1);
1368  O << "}";
1369 }
1370 
1371 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1372  const MCSubtargetInfo &STI,
1373  raw_ostream &O) {
1374  // Normally, it's not safe to use register enum values directly with
1375  // addition to get the next register, but for VFP registers, the
1376  // sort order is guaranteed because they're all of the form D<n>.
1377  O << "{";
1378  printRegName(O, MI->getOperand(OpNum).getReg());
1379  O << ", ";
1380  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1381  O << ", ";
1382  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1383  O << "}";
1384 }
1385 
1386 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1387  const MCSubtargetInfo &STI,
1388  raw_ostream &O) {
1389  // Normally, it's not safe to use register enum values directly with
1390  // addition to get the next register, but for VFP registers, the
1391  // sort order is guaranteed because they're all of the form D<n>.
1392  O << "{";
1393  printRegName(O, MI->getOperand(OpNum).getReg());
1394  O << ", ";
1395  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1396  O << ", ";
1397  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1398  O << ", ";
1399  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1400  O << "}";
1401 }
1402 
1404  unsigned OpNum,
1405  const MCSubtargetInfo &STI,
1406  raw_ostream &O) {
1407  O << "{";
1408  printRegName(O, MI->getOperand(OpNum).getReg());
1409  O << "[]}";
1410 }
1411 
1413  unsigned OpNum,
1414  const MCSubtargetInfo &STI,
1415  raw_ostream &O) {
1416  unsigned Reg = MI->getOperand(OpNum).getReg();
1417  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1418  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1419  O << "{";
1420  printRegName(O, Reg0);
1421  O << "[], ";
1422  printRegName(O, Reg1);
1423  O << "[]}";
1424 }
1425 
1427  unsigned OpNum,
1428  const MCSubtargetInfo &STI,
1429  raw_ostream &O) {
1430  // Normally, it's not safe to use register enum values directly with
1431  // addition to get the next register, but for VFP registers, the
1432  // sort order is guaranteed because they're all of the form D<n>.
1433  O << "{";
1434  printRegName(O, MI->getOperand(OpNum).getReg());
1435  O << "[], ";
1436  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1437  O << "[], ";
1438  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1439  O << "[]}";
1440 }
1441 
1443  unsigned OpNum,
1444  const MCSubtargetInfo &STI,
1445  raw_ostream &O) {
1446  // Normally, it's not safe to use register enum values directly with
1447  // addition to get the next register, but for VFP registers, the
1448  // sort order is guaranteed because they're all of the form D<n>.
1449  O << "{";
1450  printRegName(O, MI->getOperand(OpNum).getReg());
1451  O << "[], ";
1452  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1453  O << "[], ";
1454  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1455  O << "[], ";
1456  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1457  O << "[]}";
1458 }
1459 
1461  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1462  raw_ostream &O) {
1463  unsigned Reg = MI->getOperand(OpNum).getReg();
1464  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1465  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1466  O << "{";
1467  printRegName(O, Reg0);
1468  O << "[], ";
1469  printRegName(O, Reg1);
1470  O << "[]}";
1471 }
1472 
1474  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1475  raw_ostream &O) {
1476  // Normally, it's not safe to use register enum values directly with
1477  // addition to get the next register, but for VFP registers, the
1478  // sort order is guaranteed because they're all of the form D<n>.
1479  O << "{";
1480  printRegName(O, MI->getOperand(OpNum).getReg());
1481  O << "[], ";
1482  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1483  O << "[], ";
1484  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1485  O << "[]}";
1486 }
1487 
1489  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1490  raw_ostream &O) {
1491  // Normally, it's not safe to use register enum values directly with
1492  // addition to get the next register, but for VFP registers, the
1493  // sort order is guaranteed because they're all of the form D<n>.
1494  O << "{";
1495  printRegName(O, MI->getOperand(OpNum).getReg());
1496  O << "[], ";
1497  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1498  O << "[], ";
1499  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1500  O << "[], ";
1501  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1502  O << "[]}";
1503 }
1504 
1506  unsigned OpNum,
1507  const MCSubtargetInfo &STI,
1508  raw_ostream &O) {
1509  // Normally, it's not safe to use register enum values directly with
1510  // addition to get the next register, but for VFP registers, the
1511  // sort order is guaranteed because they're all of the form D<n>.
1512  O << "{";
1513  printRegName(O, MI->getOperand(OpNum).getReg());
1514  O << ", ";
1515  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1516  O << ", ";
1517  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1518  O << "}";
1519 }
1520 
1522  const MCSubtargetInfo &STI,
1523  raw_ostream &O) {
1524  // Normally, it's not safe to use register enum values directly with
1525  // addition to get the next register, but for VFP registers, the
1526  // sort order is guaranteed because they're all of the form D<n>.
1527  O << "{";
1528  printRegName(O, MI->getOperand(OpNum).getReg());
1529  O << ", ";
1530  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1531  O << ", ";
1532  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1533  O << ", ";
1534  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1535  O << "}";
1536 }
1537 
1538 template<int64_t Angle, int64_t Remainder>
1540  const MCSubtargetInfo &STI,
1541  raw_ostream &O) {
1542  unsigned Val = MI->getOperand(OpNo).getImm();
1543  O << "#" << (Val * Angle) + Remainder;
1544 }
1545 
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
iterator end()
Definition: MCInst.h:196
iterator begin()
Definition: MCInst.h:194
bool isImm() const
Definition: MCInst.h:59
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
SI Whole Quad Mode
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getAM2IdxMode(unsigned AM2Opc)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:58
const char * getAMSubModeStr(AMSubMode Mode)
#define op(i)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:181
uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits)
decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size...
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:34
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const char * getShiftOpcStr(ShiftOpc Op)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AMSubMode getAM4SubMode(unsigned Mode)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Reg
All possible values of the reg field in the ModR/M byte.
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:97
static bool isStore(int Opcode)
float getFPImmFloat(unsigned Imm)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:96
static const char * getRegisterName(unsigned RegNo)
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:76
unsigned char getAM5Offset(unsigned AM5Opc)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM3Op(unsigned AM3Opc)
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:121
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getSORegOffset(unsigned Op)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
Definition: Constant.h:42
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
Definition: ARMBaseInfo.cpp:29
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
bool isExpr() const
Definition: MCInst.h:61
unsigned getNumOperands() const
Definition: MCInst.h:184
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:23
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:70
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:47
const char * getAddrOpcStr(AddrOpc Op)
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void setOpcode(unsigned Op)
Definition: MCInst.h:173
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
unsigned getAM2Offset(unsigned AM2Opc)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:78
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:433
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:38
ShiftOpc getSORegShOp(unsigned Op)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
bool UseMarkup
True if we are printing marked up assembly.
Definition: MCInstPrinter.h:52
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Constant expressions.
Definition: MCExpr.h:40
Binary expressions.
Definition: MCExpr.h:39
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5Op(unsigned AM5Opc)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getOpcode() const
Definition: MCInst.h:174
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:49
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)