LLVM  9.0.0svn
ARMInstPrinter.cpp
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1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an ARM MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMInstPrinter.h"
14 #include "Utils/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Casting.h"
28 #include <algorithm>
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "asm-printer"
35 
36 #define PRINT_ALIAS_INSTR
37 #include "ARMGenAsmWriter.inc"
38 
39 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
40 ///
41 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
42 static unsigned translateShiftImm(unsigned imm) {
43  // lsr #32 and asr #32 exist, but should be encoded as a 0.
44  assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
45 
46  if (imm == 0)
47  return 32;
48  return imm;
49 }
50 
51 /// Prints the shift value with an immediate value.
53  unsigned ShImm, bool UseMarkup) {
54  if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
55  return;
56  O << ", ";
57 
58  assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
59  O << getShiftOpcStr(ShOpc);
60 
61  if (ShOpc != ARM_AM::rrx) {
62  O << " ";
63  if (UseMarkup)
64  O << "<imm:";
65  O << "#" << translateShiftImm(ShImm);
66  if (UseMarkup)
67  O << ">";
68  }
69 }
70 
72  const MCRegisterInfo &MRI)
73  : MCInstPrinter(MAI, MII, MRI) {}
74 
76  if (Opt == "reg-names-std") {
77  DefaultAltIdx = ARM::NoRegAltName;
78  return true;
79  }
80  if (Opt == "reg-names-raw") {
81  DefaultAltIdx = ARM::RegNamesRaw;
82  return true;
83  }
84  return false;
85 }
86 
87 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
88  OS << markup("<reg:") << getRegisterName(RegNo, DefaultAltIdx) << markup(">");
89 }
90 
92  StringRef Annot, const MCSubtargetInfo &STI) {
93  unsigned Opcode = MI->getOpcode();
94 
95  switch (Opcode) {
96  // Check for MOVs and print canonical forms, instead.
97  case ARM::MOVsr: {
98  // FIXME: Thumb variants?
99  const MCOperand &Dst = MI->getOperand(0);
100  const MCOperand &MO1 = MI->getOperand(1);
101  const MCOperand &MO2 = MI->getOperand(2);
102  const MCOperand &MO3 = MI->getOperand(3);
103 
105  printSBitModifierOperand(MI, 6, STI, O);
106  printPredicateOperand(MI, 4, STI, O);
107 
108  O << '\t';
109  printRegName(O, Dst.getReg());
110  O << ", ";
111  printRegName(O, MO1.getReg());
112 
113  O << ", ";
114  printRegName(O, MO2.getReg());
115  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
116  printAnnotation(O, Annot);
117  return;
118  }
119 
120  case ARM::MOVsi: {
121  // FIXME: Thumb variants?
122  const MCOperand &Dst = MI->getOperand(0);
123  const MCOperand &MO1 = MI->getOperand(1);
124  const MCOperand &MO2 = MI->getOperand(2);
125 
127  printSBitModifierOperand(MI, 5, STI, O);
128  printPredicateOperand(MI, 3, STI, O);
129 
130  O << '\t';
131  printRegName(O, Dst.getReg());
132  O << ", ";
133  printRegName(O, MO1.getReg());
134 
135  if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
136  printAnnotation(O, Annot);
137  return;
138  }
139 
140  O << ", " << markup("<imm:") << "#"
142  printAnnotation(O, Annot);
143  return;
144  }
145 
146  // A8.6.123 PUSH
147  case ARM::STMDB_UPD:
148  case ARM::t2STMDB_UPD:
149  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
150  // Should only print PUSH if there are at least two registers in the list.
151  O << '\t' << "push";
152  printPredicateOperand(MI, 2, STI, O);
153  if (Opcode == ARM::t2STMDB_UPD)
154  O << ".w";
155  O << '\t';
156  printRegisterList(MI, 4, STI, O);
157  printAnnotation(O, Annot);
158  return;
159  } else
160  break;
161 
162  case ARM::STR_PRE_IMM:
163  if (MI->getOperand(2).getReg() == ARM::SP &&
164  MI->getOperand(3).getImm() == -4) {
165  O << '\t' << "push";
166  printPredicateOperand(MI, 4, STI, O);
167  O << "\t{";
168  printRegName(O, MI->getOperand(1).getReg());
169  O << "}";
170  printAnnotation(O, Annot);
171  return;
172  } else
173  break;
174 
175  // A8.6.122 POP
176  case ARM::LDMIA_UPD:
177  case ARM::t2LDMIA_UPD:
178  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
179  // Should only print POP if there are at least two registers in the list.
180  O << '\t' << "pop";
181  printPredicateOperand(MI, 2, STI, O);
182  if (Opcode == ARM::t2LDMIA_UPD)
183  O << ".w";
184  O << '\t';
185  printRegisterList(MI, 4, STI, O);
186  printAnnotation(O, Annot);
187  return;
188  } else
189  break;
190 
191  case ARM::LDR_POST_IMM:
192  if (MI->getOperand(2).getReg() == ARM::SP &&
193  MI->getOperand(4).getImm() == 4) {
194  O << '\t' << "pop";
195  printPredicateOperand(MI, 5, STI, O);
196  O << "\t{";
197  printRegName(O, MI->getOperand(0).getReg());
198  O << "}";
199  printAnnotation(O, Annot);
200  return;
201  } else
202  break;
203 
204  // A8.6.355 VPUSH
205  case ARM::VSTMSDB_UPD:
206  case ARM::VSTMDDB_UPD:
207  if (MI->getOperand(0).getReg() == ARM::SP) {
208  O << '\t' << "vpush";
209  printPredicateOperand(MI, 2, STI, O);
210  O << '\t';
211  printRegisterList(MI, 4, STI, O);
212  printAnnotation(O, Annot);
213  return;
214  } else
215  break;
216 
217  // A8.6.354 VPOP
218  case ARM::VLDMSIA_UPD:
219  case ARM::VLDMDIA_UPD:
220  if (MI->getOperand(0).getReg() == ARM::SP) {
221  O << '\t' << "vpop";
222  printPredicateOperand(MI, 2, STI, O);
223  O << '\t';
224  printRegisterList(MI, 4, STI, O);
225  printAnnotation(O, Annot);
226  return;
227  } else
228  break;
229 
230  case ARM::tLDMIA: {
231  bool Writeback = true;
232  unsigned BaseReg = MI->getOperand(0).getReg();
233  for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
234  if (MI->getOperand(i).getReg() == BaseReg)
235  Writeback = false;
236  }
237 
238  O << "\tldm";
239 
240  printPredicateOperand(MI, 1, STI, O);
241  O << '\t';
242  printRegName(O, BaseReg);
243  if (Writeback)
244  O << "!";
245  O << ", ";
246  printRegisterList(MI, 3, STI, O);
247  printAnnotation(O, Annot);
248  return;
249  }
250 
251  // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
252  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
253  // a single GPRPair reg operand is used in the .td file to replace the two
254  // GPRs. However, when decoding them, the two GRPs cannot be automatically
255  // expressed as a GPRPair, so we have to manually merge them.
256  // FIXME: We would really like to be able to tablegen'erate this.
257  case ARM::LDREXD:
258  case ARM::STREXD:
259  case ARM::LDAEXD:
260  case ARM::STLEXD: {
261  const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
262  bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
263  unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
264  if (MRC.contains(Reg)) {
265  MCInst NewMI;
266  MCOperand NewReg;
267  NewMI.setOpcode(Opcode);
268 
269  if (isStore)
270  NewMI.addOperand(MI->getOperand(0));
272  Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
273  NewMI.addOperand(NewReg);
274 
275  // Copy the rest operands into NewMI.
276  for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
277  NewMI.addOperand(MI->getOperand(i));
278  printInstruction(&NewMI, STI, O);
279  return;
280  }
281  break;
282  }
283  case ARM::TSB:
284  case ARM::t2TSB:
285  O << "\ttsb\tcsync";
286  return;
287  case ARM::t2DSB:
288  switch (MI->getOperand(0).getImm()) {
289  default:
290  if (!printAliasInstr(MI, STI, O))
291  printInstruction(MI, STI, O);
292  break;
293  case 0:
294  O << "\tssbb";
295  break;
296  case 4:
297  O << "\tpssbb";
298  break;
299  }
300  printAnnotation(O, Annot);
301  return;
302  }
303 
304  if (!printAliasInstr(MI, STI, O))
305  printInstruction(MI, STI, O);
306 
307  printAnnotation(O, Annot);
308 }
309 
310 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
311  const MCSubtargetInfo &STI, raw_ostream &O) {
312  const MCOperand &Op = MI->getOperand(OpNo);
313  if (Op.isReg()) {
314  unsigned Reg = Op.getReg();
315  printRegName(O, Reg);
316  } else if (Op.isImm()) {
317  O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
318  } else {
319  assert(Op.isExpr() && "unknown operand kind in printOperand");
320  const MCExpr *Expr = Op.getExpr();
321  switch (Expr->getKind()) {
322  case MCExpr::Binary:
323  O << '#';
324  Expr->print(O, &MAI);
325  break;
326  case MCExpr::Constant: {
327  // If a symbolic branch target was added as a constant expression then
328  // print that address in hex. And only print 32 unsigned bits for the
329  // address.
330  const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
331  int64_t TargetAddress;
332  if (!Constant->evaluateAsAbsolute(TargetAddress)) {
333  O << '#';
334  Expr->print(O, &MAI);
335  } else {
336  O << "0x";
337  O.write_hex(static_cast<uint32_t>(TargetAddress));
338  }
339  break;
340  }
341  default:
342  // FIXME: Should we always treat this as if it is a constant literal and
343  // prefix it with '#'?
344  Expr->print(O, &MAI);
345  break;
346  }
347  }
348 }
349 
351  const MCSubtargetInfo &STI,
352  raw_ostream &O) {
353  const MCOperand &MO1 = MI->getOperand(OpNum);
354  if (MO1.isExpr()) {
355  MO1.getExpr()->print(O, &MAI);
356  return;
357  }
358 
359  O << markup("<mem:") << "[pc, ";
360 
361  int32_t OffImm = (int32_t)MO1.getImm();
362  bool isSub = OffImm < 0;
363 
364  // Special value for #-0. All others are normal.
365  if (OffImm == INT32_MIN)
366  OffImm = 0;
367  if (isSub) {
368  O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
369  } else {
370  O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
371  }
372  O << "]" << markup(">");
373 }
374 
375 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
376 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
377 // REG 0 0 - e.g. R5
378 // REG REG 0,SH_OPC - e.g. R5, ROR R3
379 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
380 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
381  const MCSubtargetInfo &STI,
382  raw_ostream &O) {
383  const MCOperand &MO1 = MI->getOperand(OpNum);
384  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
385  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
386 
387  printRegName(O, MO1.getReg());
388 
389  // Print the shift opc.
391  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
392  if (ShOpc == ARM_AM::rrx)
393  return;
394 
395  O << ' ';
396  printRegName(O, MO2.getReg());
397  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
398 }
399 
400 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
401  const MCSubtargetInfo &STI,
402  raw_ostream &O) {
403  const MCOperand &MO1 = MI->getOperand(OpNum);
404  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
405 
406  printRegName(O, MO1.getReg());
407 
408  // Print the shift opc.
411 }
412 
413 //===--------------------------------------------------------------------===//
414 // Addressing Mode #2
415 //===--------------------------------------------------------------------===//
416 
418  const MCSubtargetInfo &STI,
419  raw_ostream &O) {
420  const MCOperand &MO1 = MI->getOperand(Op);
421  const MCOperand &MO2 = MI->getOperand(Op + 1);
422  const MCOperand &MO3 = MI->getOperand(Op + 2);
423 
424  O << markup("<mem:") << "[";
425  printRegName(O, MO1.getReg());
426 
427  if (!MO2.getReg()) {
428  if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
429  O << ", " << markup("<imm:") << "#"
431  << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
432  }
433  O << "]" << markup(">");
434  return;
435  }
436 
437  O << ", ";
439  printRegName(O, MO2.getReg());
440 
443  O << "]" << markup(">");
444 }
445 
447  const MCSubtargetInfo &STI,
448  raw_ostream &O) {
449  const MCOperand &MO1 = MI->getOperand(Op);
450  const MCOperand &MO2 = MI->getOperand(Op + 1);
451  O << markup("<mem:") << "[";
452  printRegName(O, MO1.getReg());
453  O << ", ";
454  printRegName(O, MO2.getReg());
455  O << "]" << markup(">");
456 }
457 
459  const MCSubtargetInfo &STI,
460  raw_ostream &O) {
461  const MCOperand &MO1 = MI->getOperand(Op);
462  const MCOperand &MO2 = MI->getOperand(Op + 1);
463  O << markup("<mem:") << "[";
464  printRegName(O, MO1.getReg());
465  O << ", ";
466  printRegName(O, MO2.getReg());
467  O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
468 }
469 
471  const MCSubtargetInfo &STI,
472  raw_ostream &O) {
473  const MCOperand &MO1 = MI->getOperand(Op);
474 
475  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
476  printOperand(MI, Op, STI, O);
477  return;
478  }
479 
480 #ifndef NDEBUG
481  const MCOperand &MO3 = MI->getOperand(Op + 2);
482  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
483  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
484 #endif
485 
486  printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
487 }
488 
490  unsigned OpNum,
491  const MCSubtargetInfo &STI,
492  raw_ostream &O) {
493  const MCOperand &MO1 = MI->getOperand(OpNum);
494  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
495 
496  if (!MO1.getReg()) {
497  unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
498  O << markup("<imm:") << '#'
499  << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
500  << markup(">");
501  return;
502  }
503 
505  printRegName(O, MO1.getReg());
506 
509 }
510 
511 //===--------------------------------------------------------------------===//
512 // Addressing Mode #3
513 //===--------------------------------------------------------------------===//
514 
516  raw_ostream &O,
517  bool AlwaysPrintImm0) {
518  const MCOperand &MO1 = MI->getOperand(Op);
519  const MCOperand &MO2 = MI->getOperand(Op + 1);
520  const MCOperand &MO3 = MI->getOperand(Op + 2);
521 
522  O << markup("<mem:") << '[';
523  printRegName(O, MO1.getReg());
524 
525  if (MO2.getReg()) {
526  O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
527  printRegName(O, MO2.getReg());
528  O << ']' << markup(">");
529  return;
530  }
531 
532  // If the op is sub we have to print the immediate even if it is 0
533  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
535 
536  if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
537  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
538  << markup(">");
539  }
540  O << ']' << markup(">");
541 }
542 
543 template <bool AlwaysPrintImm0>
545  const MCSubtargetInfo &STI,
546  raw_ostream &O) {
547  const MCOperand &MO1 = MI->getOperand(Op);
548  if (!MO1.isReg()) { // For label symbolic references.
549  printOperand(MI, Op, STI, O);
550  return;
551  }
552 
555  "unexpected idxmode");
556  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
557 }
558 
560  unsigned OpNum,
561  const MCSubtargetInfo &STI,
562  raw_ostream &O) {
563  const MCOperand &MO1 = MI->getOperand(OpNum);
564  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
565 
566  if (MO1.getReg()) {
568  printRegName(O, MO1.getReg());
569  return;
570  }
571 
572  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
573  O << markup("<imm:") << '#'
574  << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
575  << markup(">");
576 }
577 
579  const MCSubtargetInfo &STI,
580  raw_ostream &O) {
581  const MCOperand &MO = MI->getOperand(OpNum);
582  unsigned Imm = MO.getImm();
583  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
584  << markup(">");
585 }
586 
588  const MCSubtargetInfo &STI,
589  raw_ostream &O) {
590  const MCOperand &MO1 = MI->getOperand(OpNum);
591  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
592 
593  O << (MO2.getImm() ? "" : "-");
594  printRegName(O, MO1.getReg());
595 }
596 
598  const MCSubtargetInfo &STI,
599  raw_ostream &O) {
600  const MCOperand &MO = MI->getOperand(OpNum);
601  unsigned Imm = MO.getImm();
602  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
603  << markup(">");
604 }
605 
606 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
607  const MCSubtargetInfo &STI,
608  raw_ostream &O) {
611  O << ARM_AM::getAMSubModeStr(Mode);
612 }
613 
614 template <bool AlwaysPrintImm0>
615 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
616  const MCSubtargetInfo &STI,
617  raw_ostream &O) {
618  const MCOperand &MO1 = MI->getOperand(OpNum);
619  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
620 
621  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
622  printOperand(MI, OpNum, STI, O);
623  return;
624  }
625 
626  O << markup("<mem:") << "[";
627  printRegName(O, MO1.getReg());
628 
629  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
631  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
632  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
633  << ImmOffs * 4 << markup(">");
634  }
635  O << "]" << markup(">");
636 }
637 
638 template <bool AlwaysPrintImm0>
640  const MCSubtargetInfo &STI,
641  raw_ostream &O) {
642  const MCOperand &MO1 = MI->getOperand(OpNum);
643  const MCOperand &MO2 = MI->getOperand(OpNum+1);
644 
645  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
646  printOperand(MI, OpNum, STI, O);
647  return;
648  }
649 
650  O << markup("<mem:") << "[";
651  printRegName(O, MO1.getReg());
652 
653  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
654  unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
655  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
656  O << ", "
657  << markup("<imm:")
658  << "#"
660  << ImmOffs * 2
661  << markup(">");
662  }
663  O << "]" << markup(">");
664 }
665 
666 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
667  const MCSubtargetInfo &STI,
668  raw_ostream &O) {
669  const MCOperand &MO1 = MI->getOperand(OpNum);
670  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
671 
672  O << markup("<mem:") << "[";
673  printRegName(O, MO1.getReg());
674  if (MO2.getImm()) {
675  O << ":" << (MO2.getImm() << 3);
676  }
677  O << "]" << markup(">");
678 }
679 
680 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
681  const MCSubtargetInfo &STI,
682  raw_ostream &O) {
683  const MCOperand &MO1 = MI->getOperand(OpNum);
684  O << markup("<mem:") << "[";
685  printRegName(O, MO1.getReg());
686  O << "]" << markup(">");
687 }
688 
690  unsigned OpNum,
691  const MCSubtargetInfo &STI,
692  raw_ostream &O) {
693  const MCOperand &MO = MI->getOperand(OpNum);
694  if (MO.getReg() == 0)
695  O << "!";
696  else {
697  O << ", ";
698  printRegName(O, MO.getReg());
699  }
700 }
701 
703  unsigned OpNum,
704  const MCSubtargetInfo &STI,
705  raw_ostream &O) {
706  const MCOperand &MO = MI->getOperand(OpNum);
707  uint32_t v = ~MO.getImm();
708  int32_t lsb = countTrailingZeros(v);
709  int32_t width = (32 - countLeadingZeros(v)) - lsb;
710  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
711  O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
712  << '#' << width << markup(">");
713 }
714 
715 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
716  const MCSubtargetInfo &STI,
717  raw_ostream &O) {
718  unsigned val = MI->getOperand(OpNum).getImm();
719  O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
720 }
721 
722 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
723  const MCSubtargetInfo &STI,
724  raw_ostream &O) {
725  unsigned val = MI->getOperand(OpNum).getImm();
727 }
728 
729 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
730  const MCSubtargetInfo &STI,
731  raw_ostream &O) {
732  unsigned val = MI->getOperand(OpNum).getImm();
734 }
735 
736 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
737  const MCSubtargetInfo &STI,
738  raw_ostream &O) {
739  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
740  bool isASR = (ShiftOp & (1 << 5)) != 0;
741  unsigned Amt = ShiftOp & 0x1f;
742  if (isASR) {
743  O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
744  << markup(">");
745  } else if (Amt) {
746  O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
747  }
748 }
749 
750 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
751  const MCSubtargetInfo &STI,
752  raw_ostream &O) {
753  unsigned Imm = MI->getOperand(OpNum).getImm();
754  if (Imm == 0)
755  return;
756  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
757  O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
758 }
759 
760 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
761  const MCSubtargetInfo &STI,
762  raw_ostream &O) {
763  unsigned Imm = MI->getOperand(OpNum).getImm();
764  // A shift amount of 32 is encoded as 0.
765  if (Imm == 0)
766  Imm = 32;
767  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
768  O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
769 }
770 
771 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
772  const MCSubtargetInfo &STI,
773  raw_ostream &O) {
774  assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
775  [&](const MCOperand &LHS, const MCOperand &RHS) {
776  return MRI.getEncodingValue(LHS.getReg()) <
777  MRI.getEncodingValue(RHS.getReg());
778  }));
779 
780  O << "{";
781  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
782  if (i != OpNum)
783  O << ", ";
784  printRegName(O, MI->getOperand(i).getReg());
785  }
786  O << "}";
787 }
788 
789 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
790  const MCSubtargetInfo &STI,
791  raw_ostream &O) {
792  unsigned Reg = MI->getOperand(OpNum).getReg();
793  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
794  O << ", ";
795  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
796 }
797 
798 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
799  const MCSubtargetInfo &STI,
800  raw_ostream &O) {
801  const MCOperand &Op = MI->getOperand(OpNum);
802  if (Op.getImm())
803  O << "be";
804  else
805  O << "le";
806 }
807 
808 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
809  const MCSubtargetInfo &STI, raw_ostream &O) {
810  const MCOperand &Op = MI->getOperand(OpNum);
811  O << ARM_PROC::IModToString(Op.getImm());
812 }
813 
814 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
815  const MCSubtargetInfo &STI, raw_ostream &O) {
816  const MCOperand &Op = MI->getOperand(OpNum);
817  unsigned IFlags = Op.getImm();
818  for (int i = 2; i >= 0; --i)
819  if (IFlags & (1 << i))
820  O << ARM_PROC::IFlagsToString(1 << i);
821 
822  if (IFlags == 0)
823  O << "none";
824 }
825 
826 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
827  const MCSubtargetInfo &STI,
828  raw_ostream &O) {
829  const MCOperand &Op = MI->getOperand(OpNum);
830  const FeatureBitset &FeatureBits = STI.getFeatureBits();
831  if (FeatureBits[ARM::FeatureMClass]) {
832 
833  unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
834  unsigned Opcode = MI->getOpcode();
835 
836  // For writes, handle extended mask bits if the DSP extension is present.
837  if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
839  if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
840  O << TheReg->Name;
841  return;
842  }
843  }
844 
845  // Handle the basic 8-bit mask.
846  SYSm &= 0xff;
847  if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
848  // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
849  // alias for MSR APSR_nzcvq.
851  if (TheReg) {
852  O << TheReg->Name;
853  return;
854  }
855  }
856 
858  if (TheReg) {
859  O << TheReg->Name;
860  return;
861  }
862 
863  O << SYSm;
864 
865  return;
866  }
867 
868  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
869  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
870  unsigned SpecRegRBit = Op.getImm() >> 4;
871  unsigned Mask = Op.getImm() & 0xf;
872 
873  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
874  O << "APSR_";
875  switch (Mask) {
876  default:
877  llvm_unreachable("Unexpected mask value!");
878  case 4:
879  O << "g";
880  return;
881  case 8:
882  O << "nzcvq";
883  return;
884  case 12:
885  O << "nzcvqg";
886  return;
887  }
888  }
889 
890  if (SpecRegRBit)
891  O << "SPSR";
892  else
893  O << "CPSR";
894 
895  if (Mask) {
896  O << '_';
897  if (Mask & 8)
898  O << 'f';
899  if (Mask & 4)
900  O << 's';
901  if (Mask & 2)
902  O << 'x';
903  if (Mask & 1)
904  O << 'c';
905  }
906 }
907 
908 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
909  const MCSubtargetInfo &STI,
910  raw_ostream &O) {
911  uint32_t Banked = MI->getOperand(OpNum).getImm();
912  auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
913  assert(TheReg && "invalid banked register operand");
914  std::string Name = TheReg->Name;
915 
916  uint32_t isSPSR = (Banked & 0x20) >> 5;
917  if (isSPSR)
918  Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
919  O << Name;
920 }
921 
922 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
923  const MCSubtargetInfo &STI,
924  raw_ostream &O) {
926  // Handle the undefined 15 CC value here for printing so we don't abort().
927  if ((unsigned)CC == 15)
928  O << "<und>";
929  else if (CC != ARMCC::AL)
930  O << ARMCondCodeToString(CC);
931 }
932 
934  unsigned OpNum,
935  const MCSubtargetInfo &STI,
936  raw_ostream &O) {
938  O << ARMCondCodeToString(CC);
939 }
940 
942  const MCSubtargetInfo &STI,
943  raw_ostream &O) {
944  if (MI->getOperand(OpNum).getReg()) {
945  assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
946  "Expect ARM CPSR register!");
947  O << 's';
948  }
949 }
950 
951 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
952  const MCSubtargetInfo &STI,
953  raw_ostream &O) {
954  O << MI->getOperand(OpNum).getImm();
955 }
956 
957 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
958  const MCSubtargetInfo &STI,
959  raw_ostream &O) {
960  O << "p" << MI->getOperand(OpNum).getImm();
961 }
962 
963 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
964  const MCSubtargetInfo &STI,
965  raw_ostream &O) {
966  O << "c" << MI->getOperand(OpNum).getImm();
967 }
968 
969 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
970  const MCSubtargetInfo &STI,
971  raw_ostream &O) {
972  O << "{" << MI->getOperand(OpNum).getImm() << "}";
973 }
974 
975 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
976  const MCSubtargetInfo &STI, raw_ostream &O) {
977  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
978 }
979 
980 template <unsigned scale>
981 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
982  const MCSubtargetInfo &STI,
983  raw_ostream &O) {
984  const MCOperand &MO = MI->getOperand(OpNum);
985 
986  if (MO.isExpr()) {
987  MO.getExpr()->print(O, &MAI);
988  return;
989  }
990 
991  int32_t OffImm = (int32_t)MO.getImm() << scale;
992 
993  O << markup("<imm:");
994  if (OffImm == INT32_MIN)
995  O << "#-0";
996  else if (OffImm < 0)
997  O << "#-" << -OffImm;
998  else
999  O << "#" << OffImm;
1000  O << markup(">");
1001 }
1002 
1004  const MCSubtargetInfo &STI,
1005  raw_ostream &O) {
1006  O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1007  << markup(">");
1008 }
1009 
1010 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1011  const MCSubtargetInfo &STI,
1012  raw_ostream &O) {
1013  unsigned Imm = MI->getOperand(OpNum).getImm();
1014  O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1015  << markup(">");
1016 }
1017 
1018 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1019  const MCSubtargetInfo &STI,
1020  raw_ostream &O) {
1021  // (3 - the number of trailing zeros) is the number of then / else.
1022  unsigned Mask = MI->getOperand(OpNum).getImm();
1023  unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1024  unsigned CondBit0 = Firstcond & 1;
1025  unsigned NumTZ = countTrailingZeros(Mask);
1026  assert(NumTZ <= 3 && "Invalid IT mask!");
1027  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1028  bool T = ((Mask >> Pos) & 1) == CondBit0;
1029  if (T)
1030  O << 't';
1031  else
1032  O << 'e';
1033  }
1034 }
1035 
1037  const MCSubtargetInfo &STI,
1038  raw_ostream &O) {
1039  const MCOperand &MO1 = MI->getOperand(Op);
1040  const MCOperand &MO2 = MI->getOperand(Op + 1);
1041 
1042  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1043  printOperand(MI, Op, STI, O);
1044  return;
1045  }
1046 
1047  O << markup("<mem:") << "[";
1048  printRegName(O, MO1.getReg());
1049  if (unsigned RegNum = MO2.getReg()) {
1050  O << ", ";
1051  printRegName(O, RegNum);
1052  }
1053  O << "]" << markup(">");
1054 }
1055 
1057  unsigned Op,
1058  const MCSubtargetInfo &STI,
1059  raw_ostream &O,
1060  unsigned Scale) {
1061  const MCOperand &MO1 = MI->getOperand(Op);
1062  const MCOperand &MO2 = MI->getOperand(Op + 1);
1063 
1064  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1065  printOperand(MI, Op, STI, O);
1066  return;
1067  }
1068 
1069  O << markup("<mem:") << "[";
1070  printRegName(O, MO1.getReg());
1071  if (unsigned ImmOffs = MO2.getImm()) {
1072  O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1073  << markup(">");
1074  }
1075  O << "]" << markup(">");
1076 }
1077 
1079  unsigned Op,
1080  const MCSubtargetInfo &STI,
1081  raw_ostream &O) {
1082  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1083 }
1084 
1086  unsigned Op,
1087  const MCSubtargetInfo &STI,
1088  raw_ostream &O) {
1089  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1090 }
1091 
1093  unsigned Op,
1094  const MCSubtargetInfo &STI,
1095  raw_ostream &O) {
1096  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1097 }
1098 
1100  const MCSubtargetInfo &STI,
1101  raw_ostream &O) {
1102  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1103 }
1104 
1105 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1106 // register with shift forms.
1107 // REG 0 0 - e.g. R5
1108 // REG IMM, SH_OPC - e.g. R5, LSL #3
1109 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1110  const MCSubtargetInfo &STI,
1111  raw_ostream &O) {
1112  const MCOperand &MO1 = MI->getOperand(OpNum);
1113  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1114 
1115  unsigned Reg = MO1.getReg();
1116  printRegName(O, Reg);
1117 
1118  // Print the shift opc.
1119  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1122 }
1123 
1124 template <bool AlwaysPrintImm0>
1126  const MCSubtargetInfo &STI,
1127  raw_ostream &O) {
1128  const MCOperand &MO1 = MI->getOperand(OpNum);
1129  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1130 
1131  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1132  printOperand(MI, OpNum, STI, O);
1133  return;
1134  }
1135 
1136  O << markup("<mem:") << "[";
1137  printRegName(O, MO1.getReg());
1138 
1139  int32_t OffImm = (int32_t)MO2.getImm();
1140  bool isSub = OffImm < 0;
1141  // Special value for #-0. All others are normal.
1142  if (OffImm == INT32_MIN)
1143  OffImm = 0;
1144  if (isSub) {
1145  O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1146  } else if (AlwaysPrintImm0 || OffImm > 0) {
1147  O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1148  }
1149  O << "]" << markup(">");
1150 }
1151 
1152 template <bool AlwaysPrintImm0>
1154  unsigned OpNum,
1155  const MCSubtargetInfo &STI,
1156  raw_ostream &O) {
1157  const MCOperand &MO1 = MI->getOperand(OpNum);
1158  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1159 
1160  O << markup("<mem:") << "[";
1161  printRegName(O, MO1.getReg());
1162 
1163  int32_t OffImm = (int32_t)MO2.getImm();
1164  bool isSub = OffImm < 0;
1165  // Don't print +0.
1166  if (OffImm == INT32_MIN)
1167  OffImm = 0;
1168  if (isSub) {
1169  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1170  } else if (AlwaysPrintImm0 || OffImm > 0) {
1171  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1172  }
1173  O << "]" << markup(">");
1174 }
1175 
1176 template <bool AlwaysPrintImm0>
1178  unsigned OpNum,
1179  const MCSubtargetInfo &STI,
1180  raw_ostream &O) {
1181  const MCOperand &MO1 = MI->getOperand(OpNum);
1182  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1183 
1184  if (!MO1.isReg()) { // For label symbolic references.
1185  printOperand(MI, OpNum, STI, O);
1186  return;
1187  }
1188 
1189  O << markup("<mem:") << "[";
1190  printRegName(O, MO1.getReg());
1191 
1192  int32_t OffImm = (int32_t)MO2.getImm();
1193  bool isSub = OffImm < 0;
1194 
1195  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1196 
1197  // Don't print +0.
1198  if (OffImm == INT32_MIN)
1199  OffImm = 0;
1200  if (isSub) {
1201  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1202  } else if (AlwaysPrintImm0 || OffImm > 0) {
1203  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1204  }
1205  O << "]" << markup(">");
1206 }
1207 
1209  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1210  raw_ostream &O) {
1211  const MCOperand &MO1 = MI->getOperand(OpNum);
1212  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1213 
1214  O << markup("<mem:") << "[";
1215  printRegName(O, MO1.getReg());
1216  if (MO2.getImm()) {
1217  O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1218  << markup(">");
1219  }
1220  O << "]" << markup(">");
1221 }
1222 
1224  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1225  raw_ostream &O) {
1226  const MCOperand &MO1 = MI->getOperand(OpNum);
1227  int32_t OffImm = (int32_t)MO1.getImm();
1228  O << ", " << markup("<imm:");
1229  if (OffImm == INT32_MIN)
1230  O << "#-0";
1231  else if (OffImm < 0)
1232  O << "#-" << -OffImm;
1233  else
1234  O << "#" << OffImm;
1235  O << markup(">");
1236 }
1237 
1239  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1240  raw_ostream &O) {
1241  const MCOperand &MO1 = MI->getOperand(OpNum);
1242  int32_t OffImm = (int32_t)MO1.getImm();
1243 
1244  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1245 
1246  O << ", " << markup("<imm:");
1247  if (OffImm == INT32_MIN)
1248  O << "#-0";
1249  else if (OffImm < 0)
1250  O << "#-" << -OffImm;
1251  else
1252  O << "#" << OffImm;
1253  O << markup(">");
1254 }
1255 
1257  unsigned OpNum,
1258  const MCSubtargetInfo &STI,
1259  raw_ostream &O) {
1260  const MCOperand &MO1 = MI->getOperand(OpNum);
1261  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1262  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1263 
1264  O << markup("<mem:") << "[";
1265  printRegName(O, MO1.getReg());
1266 
1267  assert(MO2.getReg() && "Invalid so_reg load / store address!");
1268  O << ", ";
1269  printRegName(O, MO2.getReg());
1270 
1271  unsigned ShAmt = MO3.getImm();
1272  if (ShAmt) {
1273  assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1274  O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1275  }
1276  O << "]" << markup(">");
1277 }
1278 
1279 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1280  const MCSubtargetInfo &STI,
1281  raw_ostream &O) {
1282  const MCOperand &MO = MI->getOperand(OpNum);
1283  O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1284  << markup(">");
1285 }
1286 
1288  const MCSubtargetInfo &STI,
1289  raw_ostream &O) {
1290  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1291  unsigned EltBits;
1292  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1293  O << markup("<imm:") << "#0x";
1294  O.write_hex(Val);
1295  O << markup(">");
1296 }
1297 
1299  const MCSubtargetInfo &STI,
1300  raw_ostream &O) {
1301  unsigned Imm = MI->getOperand(OpNum).getImm();
1302  O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1303 }
1304 
1305 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1306  const MCSubtargetInfo &STI,
1307  raw_ostream &O) {
1308  unsigned Imm = MI->getOperand(OpNum).getImm();
1309  if (Imm == 0)
1310  return;
1311  assert(Imm <= 3 && "illegal ror immediate!");
1312  O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1313 }
1314 
1315 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1316  const MCSubtargetInfo &STI,
1317  raw_ostream &O) {
1318  MCOperand Op = MI->getOperand(OpNum);
1319 
1320  // Support for fixups (MCFixup)
1321  if (Op.isExpr())
1322  return printOperand(MI, OpNum, STI, O);
1323 
1324  unsigned Bits = Op.getImm() & 0xFF;
1325  unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1326 
1327  bool PrintUnsigned = false;
1328  switch (MI->getOpcode()) {
1329  case ARM::MOVi:
1330  // Movs to PC should be treated unsigned
1331  PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1332  break;
1333  case ARM::MSRi:
1334  // Movs to special registers should be treated unsigned
1335  PrintUnsigned = true;
1336  break;
1337  }
1338 
1339  int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1340  if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1341  // #rot has the least possible value
1342  O << "#" << markup("<imm:");
1343  if (PrintUnsigned)
1344  O << static_cast<uint32_t>(Rotated);
1345  else
1346  O << Rotated;
1347  O << markup(">");
1348  return;
1349  }
1350 
1351  // Explicit #bits, #rot implied
1352  O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1353  << Rot << markup(">");
1354 }
1355 
1356 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1357  const MCSubtargetInfo &STI, raw_ostream &O) {
1358  O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1359  << markup(">");
1360 }
1361 
1362 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1363  const MCSubtargetInfo &STI, raw_ostream &O) {
1364  O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1365  << markup(">");
1366 }
1367 
1368 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1369  const MCSubtargetInfo &STI,
1370  raw_ostream &O) {
1371  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1372 }
1373 
1374 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1375  const MCSubtargetInfo &STI,
1376  raw_ostream &O) {
1377  O << "{";
1378  printRegName(O, MI->getOperand(OpNum).getReg());
1379  O << "}";
1380 }
1381 
1382 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1383  const MCSubtargetInfo &STI,
1384  raw_ostream &O) {
1385  unsigned Reg = MI->getOperand(OpNum).getReg();
1386  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1387  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1388  O << "{";
1389  printRegName(O, Reg0);
1390  O << ", ";
1391  printRegName(O, Reg1);
1392  O << "}";
1393 }
1394 
1396  const MCSubtargetInfo &STI,
1397  raw_ostream &O) {
1398  unsigned Reg = MI->getOperand(OpNum).getReg();
1399  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1400  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1401  O << "{";
1402  printRegName(O, Reg0);
1403  O << ", ";
1404  printRegName(O, Reg1);
1405  O << "}";
1406 }
1407 
1408 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1409  const MCSubtargetInfo &STI,
1410  raw_ostream &O) {
1411  // Normally, it's not safe to use register enum values directly with
1412  // addition to get the next register, but for VFP registers, the
1413  // sort order is guaranteed because they're all of the form D<n>.
1414  O << "{";
1415  printRegName(O, MI->getOperand(OpNum).getReg());
1416  O << ", ";
1417  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1418  O << ", ";
1419  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1420  O << "}";
1421 }
1422 
1423 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1424  const MCSubtargetInfo &STI,
1425  raw_ostream &O) {
1426  // Normally, it's not safe to use register enum values directly with
1427  // addition to get the next register, but for VFP registers, the
1428  // sort order is guaranteed because they're all of the form D<n>.
1429  O << "{";
1430  printRegName(O, MI->getOperand(OpNum).getReg());
1431  O << ", ";
1432  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1433  O << ", ";
1434  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1435  O << ", ";
1436  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1437  O << "}";
1438 }
1439 
1441  unsigned OpNum,
1442  const MCSubtargetInfo &STI,
1443  raw_ostream &O) {
1444  O << "{";
1445  printRegName(O, MI->getOperand(OpNum).getReg());
1446  O << "[]}";
1447 }
1448 
1450  unsigned OpNum,
1451  const MCSubtargetInfo &STI,
1452  raw_ostream &O) {
1453  unsigned Reg = MI->getOperand(OpNum).getReg();
1454  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1455  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1456  O << "{";
1457  printRegName(O, Reg0);
1458  O << "[], ";
1459  printRegName(O, Reg1);
1460  O << "[]}";
1461 }
1462 
1464  unsigned OpNum,
1465  const MCSubtargetInfo &STI,
1466  raw_ostream &O) {
1467  // Normally, it's not safe to use register enum values directly with
1468  // addition to get the next register, but for VFP registers, the
1469  // sort order is guaranteed because they're all of the form D<n>.
1470  O << "{";
1471  printRegName(O, MI->getOperand(OpNum).getReg());
1472  O << "[], ";
1473  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1474  O << "[], ";
1475  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1476  O << "[]}";
1477 }
1478 
1480  unsigned OpNum,
1481  const MCSubtargetInfo &STI,
1482  raw_ostream &O) {
1483  // Normally, it's not safe to use register enum values directly with
1484  // addition to get the next register, but for VFP registers, the
1485  // sort order is guaranteed because they're all of the form D<n>.
1486  O << "{";
1487  printRegName(O, MI->getOperand(OpNum).getReg());
1488  O << "[], ";
1489  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1490  O << "[], ";
1491  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1492  O << "[], ";
1493  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1494  O << "[]}";
1495 }
1496 
1498  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1499  raw_ostream &O) {
1500  unsigned Reg = MI->getOperand(OpNum).getReg();
1501  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1502  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1503  O << "{";
1504  printRegName(O, Reg0);
1505  O << "[], ";
1506  printRegName(O, Reg1);
1507  O << "[]}";
1508 }
1509 
1511  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1512  raw_ostream &O) {
1513  // Normally, it's not safe to use register enum values directly with
1514  // addition to get the next register, but for VFP registers, the
1515  // sort order is guaranteed because they're all of the form D<n>.
1516  O << "{";
1517  printRegName(O, MI->getOperand(OpNum).getReg());
1518  O << "[], ";
1519  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1520  O << "[], ";
1521  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1522  O << "[]}";
1523 }
1524 
1526  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1527  raw_ostream &O) {
1528  // Normally, it's not safe to use register enum values directly with
1529  // addition to get the next register, but for VFP registers, the
1530  // sort order is guaranteed because they're all of the form D<n>.
1531  O << "{";
1532  printRegName(O, MI->getOperand(OpNum).getReg());
1533  O << "[], ";
1534  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1535  O << "[], ";
1536  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1537  O << "[], ";
1538  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1539  O << "[]}";
1540 }
1541 
1543  unsigned OpNum,
1544  const MCSubtargetInfo &STI,
1545  raw_ostream &O) {
1546  // Normally, it's not safe to use register enum values directly with
1547  // addition to get the next register, but for VFP registers, the
1548  // sort order is guaranteed because they're all of the form D<n>.
1549  O << "{";
1550  printRegName(O, MI->getOperand(OpNum).getReg());
1551  O << ", ";
1552  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1553  O << ", ";
1554  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1555  O << "}";
1556 }
1557 
1559  const MCSubtargetInfo &STI,
1560  raw_ostream &O) {
1561  // Normally, it's not safe to use register enum values directly with
1562  // addition to get the next register, but for VFP registers, the
1563  // sort order is guaranteed because they're all of the form D<n>.
1564  O << "{";
1565  printRegName(O, MI->getOperand(OpNum).getReg());
1566  O << ", ";
1567  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1568  O << ", ";
1569  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1570  O << ", ";
1571  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1572  O << "}";
1573 }
1574 
1575 template<int64_t Angle, int64_t Remainder>
1577  const MCSubtargetInfo &STI,
1578  raw_ostream &O) {
1579  unsigned Val = MI->getOperand(OpNo).getImm();
1580  O << "#" << (Val * Angle) + Remainder;
1581 }
1582 
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
iterator end()
Definition: MCInst.h:193
iterator begin()
Definition: MCInst.h:191
bool isImm() const
Definition: MCInst.h:58
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
SI Whole Quad Mode
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
unsigned Reg
unsigned getAM2IdxMode(unsigned AM2Opc)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:57
const char * getAMSubModeStr(AMSubMode Mode)
#define op(i)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits)
decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size...
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:33
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const char * getShiftOpcStr(ShiftOpc Op)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AMSubMode getAM4SubMode(unsigned Mode)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:99
static bool isStore(int Opcode)
float getFPImmFloat(unsigned Imm)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:95
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
int64_t getImm() const
Definition: MCInst.h:75
unsigned char getAM5Offset(unsigned AM5Opc)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM3Op(unsigned AM3Opc)
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:134
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getSORegOffset(unsigned Op)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
Definition: Constant.h:41
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
Definition: ARMBaseInfo.cpp:28
static const char * TraceSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:105
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
bool isExpr() const
Definition: MCInst.h:60
unsigned getNumOperands() const
Definition: MCInst.h:181
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:22
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:69
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:46
const char * getAddrOpcStr(AddrOpc Op)
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void setOpcode(unsigned Op)
Definition: MCInst.h:170
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
unsigned getAM2Offset(unsigned AM2Opc)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:77
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:453
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:37
ShiftOpc getSORegShOp(unsigned Op)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:45
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
bool UseMarkup
True if we are printing marked up assembly.
Definition: MCInstPrinter.h:50
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Constant expressions.
Definition: MCExpr.h:39
Binary expressions.
Definition: MCExpr.h:38
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5Op(unsigned AM5Opc)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getOpcode() const
Definition: MCInst.h:171
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:47
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)