LLVM  6.0.0svn
ARMInstPrinter.cpp
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1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an ARM MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstPrinter.h"
15 #include "Utils/ARMBaseInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMBaseRegisterInfo.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Casting.h"
31 #include <algorithm>
32 #include <cassert>
33 #include <cstdint>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "asm-printer"
38 
39 #define PRINT_ALIAS_INSTR
40 #include "ARMGenAsmWriter.inc"
41 
42 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
43 ///
44 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
45 static unsigned translateShiftImm(unsigned imm) {
46  // lsr #32 and asr #32 exist, but should be encoded as a 0.
47  assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
48 
49  if (imm == 0)
50  return 32;
51  return imm;
52 }
53 
54 /// Prints the shift value with an immediate value.
56  unsigned ShImm, bool UseMarkup) {
57  if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
58  return;
59  O << ", ";
60 
61  assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
62  O << getShiftOpcStr(ShOpc);
63 
64  if (ShOpc != ARM_AM::rrx) {
65  O << " ";
66  if (UseMarkup)
67  O << "<imm:";
68  O << "#" << translateShiftImm(ShImm);
69  if (UseMarkup)
70  O << ">";
71  }
72 }
73 
75  const MCRegisterInfo &MRI)
76  : MCInstPrinter(MAI, MII, MRI) {}
77 
78 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
79  OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
80 }
81 
83  StringRef Annot, const MCSubtargetInfo &STI) {
84  unsigned Opcode = MI->getOpcode();
85 
86  switch (Opcode) {
87  // Check for MOVs and print canonical forms, instead.
88  case ARM::MOVsr: {
89  // FIXME: Thumb variants?
90  const MCOperand &Dst = MI->getOperand(0);
91  const MCOperand &MO1 = MI->getOperand(1);
92  const MCOperand &MO2 = MI->getOperand(2);
93  const MCOperand &MO3 = MI->getOperand(3);
94 
96  printSBitModifierOperand(MI, 6, STI, O);
97  printPredicateOperand(MI, 4, STI, O);
98 
99  O << '\t';
100  printRegName(O, Dst.getReg());
101  O << ", ";
102  printRegName(O, MO1.getReg());
103 
104  O << ", ";
105  printRegName(O, MO2.getReg());
106  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
107  printAnnotation(O, Annot);
108  return;
109  }
110 
111  case ARM::MOVsi: {
112  // FIXME: Thumb variants?
113  const MCOperand &Dst = MI->getOperand(0);
114  const MCOperand &MO1 = MI->getOperand(1);
115  const MCOperand &MO2 = MI->getOperand(2);
116 
118  printSBitModifierOperand(MI, 5, STI, O);
119  printPredicateOperand(MI, 3, STI, O);
120 
121  O << '\t';
122  printRegName(O, Dst.getReg());
123  O << ", ";
124  printRegName(O, MO1.getReg());
125 
126  if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
127  printAnnotation(O, Annot);
128  return;
129  }
130 
131  O << ", " << markup("<imm:") << "#"
133  printAnnotation(O, Annot);
134  return;
135  }
136 
137  // A8.6.123 PUSH
138  case ARM::STMDB_UPD:
139  case ARM::t2STMDB_UPD:
140  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
141  // Should only print PUSH if there are at least two registers in the list.
142  O << '\t' << "push";
143  printPredicateOperand(MI, 2, STI, O);
144  if (Opcode == ARM::t2STMDB_UPD)
145  O << ".w";
146  O << '\t';
147  printRegisterList(MI, 4, STI, O);
148  printAnnotation(O, Annot);
149  return;
150  } else
151  break;
152 
153  case ARM::STR_PRE_IMM:
154  if (MI->getOperand(2).getReg() == ARM::SP &&
155  MI->getOperand(3).getImm() == -4) {
156  O << '\t' << "push";
157  printPredicateOperand(MI, 4, STI, O);
158  O << "\t{";
159  printRegName(O, MI->getOperand(1).getReg());
160  O << "}";
161  printAnnotation(O, Annot);
162  return;
163  } else
164  break;
165 
166  // A8.6.122 POP
167  case ARM::LDMIA_UPD:
168  case ARM::t2LDMIA_UPD:
169  if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
170  // Should only print POP if there are at least two registers in the list.
171  O << '\t' << "pop";
172  printPredicateOperand(MI, 2, STI, O);
173  if (Opcode == ARM::t2LDMIA_UPD)
174  O << ".w";
175  O << '\t';
176  printRegisterList(MI, 4, STI, O);
177  printAnnotation(O, Annot);
178  return;
179  } else
180  break;
181 
182  case ARM::LDR_POST_IMM:
183  if (MI->getOperand(2).getReg() == ARM::SP &&
184  MI->getOperand(4).getImm() == 4) {
185  O << '\t' << "pop";
186  printPredicateOperand(MI, 5, STI, O);
187  O << "\t{";
188  printRegName(O, MI->getOperand(0).getReg());
189  O << "}";
190  printAnnotation(O, Annot);
191  return;
192  } else
193  break;
194 
195  // A8.6.355 VPUSH
196  case ARM::VSTMSDB_UPD:
197  case ARM::VSTMDDB_UPD:
198  if (MI->getOperand(0).getReg() == ARM::SP) {
199  O << '\t' << "vpush";
200  printPredicateOperand(MI, 2, STI, O);
201  O << '\t';
202  printRegisterList(MI, 4, STI, O);
203  printAnnotation(O, Annot);
204  return;
205  } else
206  break;
207 
208  // A8.6.354 VPOP
209  case ARM::VLDMSIA_UPD:
210  case ARM::VLDMDIA_UPD:
211  if (MI->getOperand(0).getReg() == ARM::SP) {
212  O << '\t' << "vpop";
213  printPredicateOperand(MI, 2, STI, O);
214  O << '\t';
215  printRegisterList(MI, 4, STI, O);
216  printAnnotation(O, Annot);
217  return;
218  } else
219  break;
220 
221  case ARM::tLDMIA: {
222  bool Writeback = true;
223  unsigned BaseReg = MI->getOperand(0).getReg();
224  for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
225  if (MI->getOperand(i).getReg() == BaseReg)
226  Writeback = false;
227  }
228 
229  O << "\tldm";
230 
231  printPredicateOperand(MI, 1, STI, O);
232  O << '\t';
233  printRegName(O, BaseReg);
234  if (Writeback)
235  O << "!";
236  O << ", ";
237  printRegisterList(MI, 3, STI, O);
238  printAnnotation(O, Annot);
239  return;
240  }
241 
242  // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
243  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
244  // a single GPRPair reg operand is used in the .td file to replace the two
245  // GPRs. However, when decoding them, the two GRPs cannot be automatically
246  // expressed as a GPRPair, so we have to manually merge them.
247  // FIXME: We would really like to be able to tablegen'erate this.
248  case ARM::LDREXD:
249  case ARM::STREXD:
250  case ARM::LDAEXD:
251  case ARM::STLEXD: {
252  const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
253  bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
254  unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
255  if (MRC.contains(Reg)) {
256  MCInst NewMI;
257  MCOperand NewReg;
258  NewMI.setOpcode(Opcode);
259 
260  if (isStore)
261  NewMI.addOperand(MI->getOperand(0));
263  Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
264  NewMI.addOperand(NewReg);
265 
266  // Copy the rest operands into NewMI.
267  for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
268  NewMI.addOperand(MI->getOperand(i));
269  printInstruction(&NewMI, STI, O);
270  return;
271  }
272  break;
273  }
274  }
275 
276  if (!printAliasInstr(MI, STI, O))
277  printInstruction(MI, STI, O);
278 
279  printAnnotation(O, Annot);
280 }
281 
282 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
283  const MCSubtargetInfo &STI, raw_ostream &O) {
284  const MCOperand &Op = MI->getOperand(OpNo);
285  if (Op.isReg()) {
286  unsigned Reg = Op.getReg();
287  printRegName(O, Reg);
288  } else if (Op.isImm()) {
289  O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
290  } else {
291  assert(Op.isExpr() && "unknown operand kind in printOperand");
292  const MCExpr *Expr = Op.getExpr();
293  switch (Expr->getKind()) {
294  case MCExpr::Binary:
295  O << '#';
296  Expr->print(O, &MAI);
297  break;
298  case MCExpr::Constant: {
299  // If a symbolic branch target was added as a constant expression then
300  // print that address in hex. And only print 32 unsigned bits for the
301  // address.
302  const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
303  int64_t TargetAddress;
304  if (!Constant->evaluateAsAbsolute(TargetAddress)) {
305  O << '#';
306  Expr->print(O, &MAI);
307  } else {
308  O << "0x";
309  O.write_hex(static_cast<uint32_t>(TargetAddress));
310  }
311  break;
312  }
313  default:
314  // FIXME: Should we always treat this as if it is a constant literal and
315  // prefix it with '#'?
316  Expr->print(O, &MAI);
317  break;
318  }
319  }
320 }
321 
323  const MCSubtargetInfo &STI,
324  raw_ostream &O) {
325  const MCOperand &MO1 = MI->getOperand(OpNum);
326  if (MO1.isExpr()) {
327  MO1.getExpr()->print(O, &MAI);
328  return;
329  }
330 
331  O << markup("<mem:") << "[pc, ";
332 
333  int32_t OffImm = (int32_t)MO1.getImm();
334  bool isSub = OffImm < 0;
335 
336  // Special value for #-0. All others are normal.
337  if (OffImm == INT32_MIN)
338  OffImm = 0;
339  if (isSub) {
340  O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
341  } else {
342  O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
343  }
344  O << "]" << markup(">");
345 }
346 
347 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
348 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
349 // REG 0 0 - e.g. R5
350 // REG REG 0,SH_OPC - e.g. R5, ROR R3
351 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
352 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
353  const MCSubtargetInfo &STI,
354  raw_ostream &O) {
355  const MCOperand &MO1 = MI->getOperand(OpNum);
356  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
357  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
358 
359  printRegName(O, MO1.getReg());
360 
361  // Print the shift opc.
363  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
364  if (ShOpc == ARM_AM::rrx)
365  return;
366 
367  O << ' ';
368  printRegName(O, MO2.getReg());
369  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
370 }
371 
372 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
373  const MCSubtargetInfo &STI,
374  raw_ostream &O) {
375  const MCOperand &MO1 = MI->getOperand(OpNum);
376  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
377 
378  printRegName(O, MO1.getReg());
379 
380  // Print the shift opc.
383 }
384 
385 //===--------------------------------------------------------------------===//
386 // Addressing Mode #2
387 //===--------------------------------------------------------------------===//
388 
390  const MCSubtargetInfo &STI,
391  raw_ostream &O) {
392  const MCOperand &MO1 = MI->getOperand(Op);
393  const MCOperand &MO2 = MI->getOperand(Op + 1);
394  const MCOperand &MO3 = MI->getOperand(Op + 2);
395 
396  O << markup("<mem:") << "[";
397  printRegName(O, MO1.getReg());
398 
399  if (!MO2.getReg()) {
400  if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
401  O << ", " << markup("<imm:") << "#"
403  << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
404  }
405  O << "]" << markup(">");
406  return;
407  }
408 
409  O << ", ";
411  printRegName(O, MO2.getReg());
412 
415  O << "]" << markup(">");
416 }
417 
419  const MCSubtargetInfo &STI,
420  raw_ostream &O) {
421  const MCOperand &MO1 = MI->getOperand(Op);
422  const MCOperand &MO2 = MI->getOperand(Op + 1);
423  O << markup("<mem:") << "[";
424  printRegName(O, MO1.getReg());
425  O << ", ";
426  printRegName(O, MO2.getReg());
427  O << "]" << markup(">");
428 }
429 
431  const MCSubtargetInfo &STI,
432  raw_ostream &O) {
433  const MCOperand &MO1 = MI->getOperand(Op);
434  const MCOperand &MO2 = MI->getOperand(Op + 1);
435  O << markup("<mem:") << "[";
436  printRegName(O, MO1.getReg());
437  O << ", ";
438  printRegName(O, MO2.getReg());
439  O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
440 }
441 
443  const MCSubtargetInfo &STI,
444  raw_ostream &O) {
445  const MCOperand &MO1 = MI->getOperand(Op);
446 
447  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
448  printOperand(MI, Op, STI, O);
449  return;
450  }
451 
452 #ifndef NDEBUG
453  const MCOperand &MO3 = MI->getOperand(Op + 2);
454  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
455  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
456 #endif
457 
458  printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
459 }
460 
462  unsigned OpNum,
463  const MCSubtargetInfo &STI,
464  raw_ostream &O) {
465  const MCOperand &MO1 = MI->getOperand(OpNum);
466  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
467 
468  if (!MO1.getReg()) {
469  unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
470  O << markup("<imm:") << '#'
471  << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
472  << markup(">");
473  return;
474  }
475 
477  printRegName(O, MO1.getReg());
478 
481 }
482 
483 //===--------------------------------------------------------------------===//
484 // Addressing Mode #3
485 //===--------------------------------------------------------------------===//
486 
488  raw_ostream &O,
489  bool AlwaysPrintImm0) {
490  const MCOperand &MO1 = MI->getOperand(Op);
491  const MCOperand &MO2 = MI->getOperand(Op + 1);
492  const MCOperand &MO3 = MI->getOperand(Op + 2);
493 
494  O << markup("<mem:") << '[';
495  printRegName(O, MO1.getReg());
496 
497  if (MO2.getReg()) {
498  O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
499  printRegName(O, MO2.getReg());
500  O << ']' << markup(">");
501  return;
502  }
503 
504  // If the op is sub we have to print the immediate even if it is 0
505  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
507 
508  if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
509  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
510  << markup(">");
511  }
512  O << ']' << markup(">");
513 }
514 
515 template <bool AlwaysPrintImm0>
517  const MCSubtargetInfo &STI,
518  raw_ostream &O) {
519  const MCOperand &MO1 = MI->getOperand(Op);
520  if (!MO1.isReg()) { // For label symbolic references.
521  printOperand(MI, Op, STI, O);
522  return;
523  }
524 
527  "unexpected idxmode");
528  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
529 }
530 
532  unsigned OpNum,
533  const MCSubtargetInfo &STI,
534  raw_ostream &O) {
535  const MCOperand &MO1 = MI->getOperand(OpNum);
536  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
537 
538  if (MO1.getReg()) {
540  printRegName(O, MO1.getReg());
541  return;
542  }
543 
544  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
545  O << markup("<imm:") << '#'
546  << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
547  << markup(">");
548 }
549 
551  const MCSubtargetInfo &STI,
552  raw_ostream &O) {
553  const MCOperand &MO = MI->getOperand(OpNum);
554  unsigned Imm = MO.getImm();
555  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
556  << markup(">");
557 }
558 
560  const MCSubtargetInfo &STI,
561  raw_ostream &O) {
562  const MCOperand &MO1 = MI->getOperand(OpNum);
563  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
564 
565  O << (MO2.getImm() ? "" : "-");
566  printRegName(O, MO1.getReg());
567 }
568 
570  const MCSubtargetInfo &STI,
571  raw_ostream &O) {
572  const MCOperand &MO = MI->getOperand(OpNum);
573  unsigned Imm = MO.getImm();
574  O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
575  << markup(">");
576 }
577 
578 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
579  const MCSubtargetInfo &STI,
580  raw_ostream &O) {
583  O << ARM_AM::getAMSubModeStr(Mode);
584 }
585 
586 template <bool AlwaysPrintImm0>
587 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
588  const MCSubtargetInfo &STI,
589  raw_ostream &O) {
590  const MCOperand &MO1 = MI->getOperand(OpNum);
591  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
592 
593  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
594  printOperand(MI, OpNum, STI, O);
595  return;
596  }
597 
598  O << markup("<mem:") << "[";
599  printRegName(O, MO1.getReg());
600 
601  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
603  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
604  O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
605  << ImmOffs * 4 << markup(">");
606  }
607  O << "]" << markup(">");
608 }
609 
610 template <bool AlwaysPrintImm0>
612  const MCSubtargetInfo &STI,
613  raw_ostream &O) {
614  const MCOperand &MO1 = MI->getOperand(OpNum);
615  const MCOperand &MO2 = MI->getOperand(OpNum+1);
616 
617  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
618  printOperand(MI, OpNum, STI, O);
619  return;
620  }
621 
622  O << markup("<mem:") << "[";
623  printRegName(O, MO1.getReg());
624 
625  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
626  unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
627  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
628  O << ", "
629  << markup("<imm:")
630  << "#"
632  << ImmOffs * 2
633  << markup(">");
634  }
635  O << "]" << markup(">");
636 }
637 
638 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
639  const MCSubtargetInfo &STI,
640  raw_ostream &O) {
641  const MCOperand &MO1 = MI->getOperand(OpNum);
642  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
643 
644  O << markup("<mem:") << "[";
645  printRegName(O, MO1.getReg());
646  if (MO2.getImm()) {
647  O << ":" << (MO2.getImm() << 3);
648  }
649  O << "]" << markup(">");
650 }
651 
652 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
653  const MCSubtargetInfo &STI,
654  raw_ostream &O) {
655  const MCOperand &MO1 = MI->getOperand(OpNum);
656  O << markup("<mem:") << "[";
657  printRegName(O, MO1.getReg());
658  O << "]" << markup(">");
659 }
660 
662  unsigned OpNum,
663  const MCSubtargetInfo &STI,
664  raw_ostream &O) {
665  const MCOperand &MO = MI->getOperand(OpNum);
666  if (MO.getReg() == 0)
667  O << "!";
668  else {
669  O << ", ";
670  printRegName(O, MO.getReg());
671  }
672 }
673 
675  unsigned OpNum,
676  const MCSubtargetInfo &STI,
677  raw_ostream &O) {
678  const MCOperand &MO = MI->getOperand(OpNum);
679  uint32_t v = ~MO.getImm();
680  int32_t lsb = countTrailingZeros(v);
681  int32_t width = (32 - countLeadingZeros(v)) - lsb;
682  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
683  O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
684  << '#' << width << markup(">");
685 }
686 
687 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
688  const MCSubtargetInfo &STI,
689  raw_ostream &O) {
690  unsigned val = MI->getOperand(OpNum).getImm();
691  O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
692 }
693 
694 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
695  const MCSubtargetInfo &STI,
696  raw_ostream &O) {
697  unsigned val = MI->getOperand(OpNum).getImm();
699 }
700 
701 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
702  const MCSubtargetInfo &STI,
703  raw_ostream &O) {
704  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
705  bool isASR = (ShiftOp & (1 << 5)) != 0;
706  unsigned Amt = ShiftOp & 0x1f;
707  if (isASR) {
708  O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
709  << markup(">");
710  } else if (Amt) {
711  O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
712  }
713 }
714 
715 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
716  const MCSubtargetInfo &STI,
717  raw_ostream &O) {
718  unsigned Imm = MI->getOperand(OpNum).getImm();
719  if (Imm == 0)
720  return;
721  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
722  O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
723 }
724 
725 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
726  const MCSubtargetInfo &STI,
727  raw_ostream &O) {
728  unsigned Imm = MI->getOperand(OpNum).getImm();
729  // A shift amount of 32 is encoded as 0.
730  if (Imm == 0)
731  Imm = 32;
732  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
733  O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
734 }
735 
736 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
737  const MCSubtargetInfo &STI,
738  raw_ostream &O) {
739  assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
740  [&](const MCOperand &LHS, const MCOperand &RHS) {
741  return MRI.getEncodingValue(LHS.getReg()) <
742  MRI.getEncodingValue(RHS.getReg());
743  }));
744 
745  O << "{";
746  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
747  if (i != OpNum)
748  O << ", ";
749  printRegName(O, MI->getOperand(i).getReg());
750  }
751  O << "}";
752 }
753 
754 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
755  const MCSubtargetInfo &STI,
756  raw_ostream &O) {
757  unsigned Reg = MI->getOperand(OpNum).getReg();
758  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
759  O << ", ";
760  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
761 }
762 
763 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
764  const MCSubtargetInfo &STI,
765  raw_ostream &O) {
766  const MCOperand &Op = MI->getOperand(OpNum);
767  if (Op.getImm())
768  O << "be";
769  else
770  O << "le";
771 }
772 
773 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
774  const MCSubtargetInfo &STI, raw_ostream &O) {
775  const MCOperand &Op = MI->getOperand(OpNum);
776  O << ARM_PROC::IModToString(Op.getImm());
777 }
778 
779 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
780  const MCSubtargetInfo &STI, raw_ostream &O) {
781  const MCOperand &Op = MI->getOperand(OpNum);
782  unsigned IFlags = Op.getImm();
783  for (int i = 2; i >= 0; --i)
784  if (IFlags & (1 << i))
785  O << ARM_PROC::IFlagsToString(1 << i);
786 
787  if (IFlags == 0)
788  O << "none";
789 }
790 
791 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
792  const MCSubtargetInfo &STI,
793  raw_ostream &O) {
794  const MCOperand &Op = MI->getOperand(OpNum);
795  const FeatureBitset &FeatureBits = STI.getFeatureBits();
796  if (FeatureBits[ARM::FeatureMClass]) {
797 
798  unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
799  unsigned Opcode = MI->getOpcode();
800 
801  // For writes, handle extended mask bits if the DSP extension is present.
802  if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
804  if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
805  O << TheReg->Name;
806  return;
807  }
808  }
809 
810  // Handle the basic 8-bit mask.
811  SYSm &= 0xff;
812  if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
813  // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
814  // alias for MSR APSR_nzcvq.
816  if (TheReg) {
817  O << TheReg->Name;
818  return;
819  }
820  }
821 
823  if (TheReg) {
824  O << TheReg->Name;
825  return;
826  }
827 
828  llvm_unreachable("Unexpected mask value!");
829  return;
830  }
831 
832  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
833  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
834  unsigned SpecRegRBit = Op.getImm() >> 4;
835  unsigned Mask = Op.getImm() & 0xf;
836 
837  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
838  O << "APSR_";
839  switch (Mask) {
840  default:
841  llvm_unreachable("Unexpected mask value!");
842  case 4:
843  O << "g";
844  return;
845  case 8:
846  O << "nzcvq";
847  return;
848  case 12:
849  O << "nzcvqg";
850  return;
851  }
852  }
853 
854  if (SpecRegRBit)
855  O << "SPSR";
856  else
857  O << "CPSR";
858 
859  if (Mask) {
860  O << '_';
861  if (Mask & 8)
862  O << 'f';
863  if (Mask & 4)
864  O << 's';
865  if (Mask & 2)
866  O << 'x';
867  if (Mask & 1)
868  O << 'c';
869  }
870 }
871 
872 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
873  const MCSubtargetInfo &STI,
874  raw_ostream &O) {
875  uint32_t Banked = MI->getOperand(OpNum).getImm();
876  uint32_t R = (Banked & 0x20) >> 5;
877  uint32_t SysM = Banked & 0x1f;
878 
879  // Nothing much we can do about this, the encodings are specified in B9.2.3 of
880  // the ARM ARM v7C, and are all over the shop.
881  if (R) {
882  O << "SPSR_";
883 
884  switch (SysM) {
885  case 0x0e:
886  O << "fiq";
887  return;
888  case 0x10:
889  O << "irq";
890  return;
891  case 0x12:
892  O << "svc";
893  return;
894  case 0x14:
895  O << "abt";
896  return;
897  case 0x16:
898  O << "und";
899  return;
900  case 0x1c:
901  O << "mon";
902  return;
903  case 0x1e:
904  O << "hyp";
905  return;
906  default:
907  llvm_unreachable("Invalid banked SPSR register");
908  }
909  }
910 
911  assert(!R && "should have dealt with SPSR regs");
912  const char *RegNames[] = {
913  "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
914  "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
915  "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
916  "sp_abt", "lr_und", "sp_und", "", "", "", "",
917  "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
918  const char *Name = RegNames[SysM];
919  assert(Name[0] && "invalid banked register operand");
920 
921  O << Name;
922 }
923 
924 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
925  const MCSubtargetInfo &STI,
926  raw_ostream &O) {
928  // Handle the undefined 15 CC value here for printing so we don't abort().
929  if ((unsigned)CC == 15)
930  O << "<und>";
931  else if (CC != ARMCC::AL)
932  O << ARMCondCodeToString(CC);
933 }
934 
936  unsigned OpNum,
937  const MCSubtargetInfo &STI,
938  raw_ostream &O) {
940  O << ARMCondCodeToString(CC);
941 }
942 
944  const MCSubtargetInfo &STI,
945  raw_ostream &O) {
946  if (MI->getOperand(OpNum).getReg()) {
947  assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
948  "Expect ARM CPSR register!");
949  O << 's';
950  }
951 }
952 
953 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
954  const MCSubtargetInfo &STI,
955  raw_ostream &O) {
956  O << MI->getOperand(OpNum).getImm();
957 }
958 
959 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
960  const MCSubtargetInfo &STI,
961  raw_ostream &O) {
962  O << "p" << MI->getOperand(OpNum).getImm();
963 }
964 
965 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
966  const MCSubtargetInfo &STI,
967  raw_ostream &O) {
968  O << "c" << MI->getOperand(OpNum).getImm();
969 }
970 
971 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
972  const MCSubtargetInfo &STI,
973  raw_ostream &O) {
974  O << "{" << MI->getOperand(OpNum).getImm() << "}";
975 }
976 
977 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
978  const MCSubtargetInfo &STI, raw_ostream &O) {
979  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
980 }
981 
982 template <unsigned scale>
983 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
984  const MCSubtargetInfo &STI,
985  raw_ostream &O) {
986  const MCOperand &MO = MI->getOperand(OpNum);
987 
988  if (MO.isExpr()) {
989  MO.getExpr()->print(O, &MAI);
990  return;
991  }
992 
993  int32_t OffImm = (int32_t)MO.getImm() << scale;
994 
995  O << markup("<imm:");
996  if (OffImm == INT32_MIN)
997  O << "#-0";
998  else if (OffImm < 0)
999  O << "#-" << -OffImm;
1000  else
1001  O << "#" << OffImm;
1002  O << markup(">");
1003 }
1004 
1006  const MCSubtargetInfo &STI,
1007  raw_ostream &O) {
1008  O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1009  << markup(">");
1010 }
1011 
1012 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1013  const MCSubtargetInfo &STI,
1014  raw_ostream &O) {
1015  unsigned Imm = MI->getOperand(OpNum).getImm();
1016  O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1017  << markup(">");
1018 }
1019 
1020 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1021  const MCSubtargetInfo &STI,
1022  raw_ostream &O) {
1023  // (3 - the number of trailing zeros) is the number of then / else.
1024  unsigned Mask = MI->getOperand(OpNum).getImm();
1025  unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1026  unsigned CondBit0 = Firstcond & 1;
1027  unsigned NumTZ = countTrailingZeros(Mask);
1028  assert(NumTZ <= 3 && "Invalid IT mask!");
1029  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1030  bool T = ((Mask >> Pos) & 1) == CondBit0;
1031  if (T)
1032  O << 't';
1033  else
1034  O << 'e';
1035  }
1036 }
1037 
1039  const MCSubtargetInfo &STI,
1040  raw_ostream &O) {
1041  const MCOperand &MO1 = MI->getOperand(Op);
1042  const MCOperand &MO2 = MI->getOperand(Op + 1);
1043 
1044  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1045  printOperand(MI, Op, STI, O);
1046  return;
1047  }
1048 
1049  O << markup("<mem:") << "[";
1050  printRegName(O, MO1.getReg());
1051  if (unsigned RegNum = MO2.getReg()) {
1052  O << ", ";
1053  printRegName(O, RegNum);
1054  }
1055  O << "]" << markup(">");
1056 }
1057 
1059  unsigned Op,
1060  const MCSubtargetInfo &STI,
1061  raw_ostream &O,
1062  unsigned Scale) {
1063  const MCOperand &MO1 = MI->getOperand(Op);
1064  const MCOperand &MO2 = MI->getOperand(Op + 1);
1065 
1066  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1067  printOperand(MI, Op, STI, O);
1068  return;
1069  }
1070 
1071  O << markup("<mem:") << "[";
1072  printRegName(O, MO1.getReg());
1073  if (unsigned ImmOffs = MO2.getImm()) {
1074  O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1075  << markup(">");
1076  }
1077  O << "]" << markup(">");
1078 }
1079 
1081  unsigned Op,
1082  const MCSubtargetInfo &STI,
1083  raw_ostream &O) {
1084  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1085 }
1086 
1088  unsigned Op,
1089  const MCSubtargetInfo &STI,
1090  raw_ostream &O) {
1091  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1092 }
1093 
1095  unsigned Op,
1096  const MCSubtargetInfo &STI,
1097  raw_ostream &O) {
1098  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1099 }
1100 
1102  const MCSubtargetInfo &STI,
1103  raw_ostream &O) {
1104  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1105 }
1106 
1107 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1108 // register with shift forms.
1109 // REG 0 0 - e.g. R5
1110 // REG IMM, SH_OPC - e.g. R5, LSL #3
1111 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1112  const MCSubtargetInfo &STI,
1113  raw_ostream &O) {
1114  const MCOperand &MO1 = MI->getOperand(OpNum);
1115  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1116 
1117  unsigned Reg = MO1.getReg();
1118  printRegName(O, Reg);
1119 
1120  // Print the shift opc.
1121  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1124 }
1125 
1126 template <bool AlwaysPrintImm0>
1128  const MCSubtargetInfo &STI,
1129  raw_ostream &O) {
1130  const MCOperand &MO1 = MI->getOperand(OpNum);
1131  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1132 
1133  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1134  printOperand(MI, OpNum, STI, O);
1135  return;
1136  }
1137 
1138  O << markup("<mem:") << "[";
1139  printRegName(O, MO1.getReg());
1140 
1141  int32_t OffImm = (int32_t)MO2.getImm();
1142  bool isSub = OffImm < 0;
1143  // Special value for #-0. All others are normal.
1144  if (OffImm == INT32_MIN)
1145  OffImm = 0;
1146  if (isSub) {
1147  O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1148  } else if (AlwaysPrintImm0 || OffImm > 0) {
1149  O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1150  }
1151  O << "]" << markup(">");
1152 }
1153 
1154 template <bool AlwaysPrintImm0>
1156  unsigned OpNum,
1157  const MCSubtargetInfo &STI,
1158  raw_ostream &O) {
1159  const MCOperand &MO1 = MI->getOperand(OpNum);
1160  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1161 
1162  O << markup("<mem:") << "[";
1163  printRegName(O, MO1.getReg());
1164 
1165  int32_t OffImm = (int32_t)MO2.getImm();
1166  bool isSub = OffImm < 0;
1167  // Don't print +0.
1168  if (OffImm == INT32_MIN)
1169  OffImm = 0;
1170  if (isSub) {
1171  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1172  } else if (AlwaysPrintImm0 || OffImm > 0) {
1173  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1174  }
1175  O << "]" << markup(">");
1176 }
1177 
1178 template <bool AlwaysPrintImm0>
1180  unsigned OpNum,
1181  const MCSubtargetInfo &STI,
1182  raw_ostream &O) {
1183  const MCOperand &MO1 = MI->getOperand(OpNum);
1184  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1185 
1186  if (!MO1.isReg()) { // For label symbolic references.
1187  printOperand(MI, OpNum, STI, O);
1188  return;
1189  }
1190 
1191  O << markup("<mem:") << "[";
1192  printRegName(O, MO1.getReg());
1193 
1194  int32_t OffImm = (int32_t)MO2.getImm();
1195  bool isSub = OffImm < 0;
1196 
1197  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1198 
1199  // Don't print +0.
1200  if (OffImm == INT32_MIN)
1201  OffImm = 0;
1202  if (isSub) {
1203  O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1204  } else if (AlwaysPrintImm0 || OffImm > 0) {
1205  O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1206  }
1207  O << "]" << markup(">");
1208 }
1209 
1211  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1212  raw_ostream &O) {
1213  const MCOperand &MO1 = MI->getOperand(OpNum);
1214  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1215 
1216  O << markup("<mem:") << "[";
1217  printRegName(O, MO1.getReg());
1218  if (MO2.getImm()) {
1219  O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1220  << markup(">");
1221  }
1222  O << "]" << markup(">");
1223 }
1224 
1226  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1227  raw_ostream &O) {
1228  const MCOperand &MO1 = MI->getOperand(OpNum);
1229  int32_t OffImm = (int32_t)MO1.getImm();
1230  O << ", " << markup("<imm:");
1231  if (OffImm == INT32_MIN)
1232  O << "#-0";
1233  else if (OffImm < 0)
1234  O << "#-" << -OffImm;
1235  else
1236  O << "#" << OffImm;
1237  O << markup(">");
1238 }
1239 
1241  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1242  raw_ostream &O) {
1243  const MCOperand &MO1 = MI->getOperand(OpNum);
1244  int32_t OffImm = (int32_t)MO1.getImm();
1245 
1246  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1247 
1248  O << ", " << markup("<imm:");
1249  if (OffImm == INT32_MIN)
1250  O << "#-0";
1251  else if (OffImm < 0)
1252  O << "#-" << -OffImm;
1253  else
1254  O << "#" << OffImm;
1255  O << markup(">");
1256 }
1257 
1259  unsigned OpNum,
1260  const MCSubtargetInfo &STI,
1261  raw_ostream &O) {
1262  const MCOperand &MO1 = MI->getOperand(OpNum);
1263  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1264  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1265 
1266  O << markup("<mem:") << "[";
1267  printRegName(O, MO1.getReg());
1268 
1269  assert(MO2.getReg() && "Invalid so_reg load / store address!");
1270  O << ", ";
1271  printRegName(O, MO2.getReg());
1272 
1273  unsigned ShAmt = MO3.getImm();
1274  if (ShAmt) {
1275  assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1276  O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1277  }
1278  O << "]" << markup(">");
1279 }
1280 
1281 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1282  const MCSubtargetInfo &STI,
1283  raw_ostream &O) {
1284  const MCOperand &MO = MI->getOperand(OpNum);
1285  O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1286  << markup(">");
1287 }
1288 
1290  const MCSubtargetInfo &STI,
1291  raw_ostream &O) {
1292  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1293  unsigned EltBits;
1294  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1295  O << markup("<imm:") << "#0x";
1296  O.write_hex(Val);
1297  O << markup(">");
1298 }
1299 
1301  const MCSubtargetInfo &STI,
1302  raw_ostream &O) {
1303  unsigned Imm = MI->getOperand(OpNum).getImm();
1304  O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1305 }
1306 
1307 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1308  const MCSubtargetInfo &STI,
1309  raw_ostream &O) {
1310  unsigned Imm = MI->getOperand(OpNum).getImm();
1311  if (Imm == 0)
1312  return;
1313  assert(Imm <= 3 && "illegal ror immediate!");
1314  O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1315 }
1316 
1317 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1318  const MCSubtargetInfo &STI,
1319  raw_ostream &O) {
1320  MCOperand Op = MI->getOperand(OpNum);
1321 
1322  // Support for fixups (MCFixup)
1323  if (Op.isExpr())
1324  return printOperand(MI, OpNum, STI, O);
1325 
1326  unsigned Bits = Op.getImm() & 0xFF;
1327  unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1328 
1329  bool PrintUnsigned = false;
1330  switch (MI->getOpcode()) {
1331  case ARM::MOVi:
1332  // Movs to PC should be treated unsigned
1333  PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1334  break;
1335  case ARM::MSRi:
1336  // Movs to special registers should be treated unsigned
1337  PrintUnsigned = true;
1338  break;
1339  }
1340 
1341  int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1342  if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1343  // #rot has the least possible value
1344  O << "#" << markup("<imm:");
1345  if (PrintUnsigned)
1346  O << static_cast<uint32_t>(Rotated);
1347  else
1348  O << Rotated;
1349  O << markup(">");
1350  return;
1351  }
1352 
1353  // Explicit #bits, #rot implied
1354  O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1355  << Rot << markup(">");
1356 }
1357 
1358 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1359  const MCSubtargetInfo &STI, raw_ostream &O) {
1360  O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1361  << markup(">");
1362 }
1363 
1364 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1365  const MCSubtargetInfo &STI, raw_ostream &O) {
1366  O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1367  << markup(">");
1368 }
1369 
1370 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1371  const MCSubtargetInfo &STI,
1372  raw_ostream &O) {
1373  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1374 }
1375 
1376 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1377  const MCSubtargetInfo &STI,
1378  raw_ostream &O) {
1379  O << "{";
1380  printRegName(O, MI->getOperand(OpNum).getReg());
1381  O << "}";
1382 }
1383 
1384 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1385  const MCSubtargetInfo &STI,
1386  raw_ostream &O) {
1387  unsigned Reg = MI->getOperand(OpNum).getReg();
1388  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1389  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1390  O << "{";
1391  printRegName(O, Reg0);
1392  O << ", ";
1393  printRegName(O, Reg1);
1394  O << "}";
1395 }
1396 
1398  const MCSubtargetInfo &STI,
1399  raw_ostream &O) {
1400  unsigned Reg = MI->getOperand(OpNum).getReg();
1401  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1402  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1403  O << "{";
1404  printRegName(O, Reg0);
1405  O << ", ";
1406  printRegName(O, Reg1);
1407  O << "}";
1408 }
1409 
1410 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1411  const MCSubtargetInfo &STI,
1412  raw_ostream &O) {
1413  // Normally, it's not safe to use register enum values directly with
1414  // addition to get the next register, but for VFP registers, the
1415  // sort order is guaranteed because they're all of the form D<n>.
1416  O << "{";
1417  printRegName(O, MI->getOperand(OpNum).getReg());
1418  O << ", ";
1419  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1420  O << ", ";
1421  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1422  O << "}";
1423 }
1424 
1425 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1426  const MCSubtargetInfo &STI,
1427  raw_ostream &O) {
1428  // Normally, it's not safe to use register enum values directly with
1429  // addition to get the next register, but for VFP registers, the
1430  // sort order is guaranteed because they're all of the form D<n>.
1431  O << "{";
1432  printRegName(O, MI->getOperand(OpNum).getReg());
1433  O << ", ";
1434  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1435  O << ", ";
1436  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1437  O << ", ";
1438  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1439  O << "}";
1440 }
1441 
1443  unsigned OpNum,
1444  const MCSubtargetInfo &STI,
1445  raw_ostream &O) {
1446  O << "{";
1447  printRegName(O, MI->getOperand(OpNum).getReg());
1448  O << "[]}";
1449 }
1450 
1452  unsigned OpNum,
1453  const MCSubtargetInfo &STI,
1454  raw_ostream &O) {
1455  unsigned Reg = MI->getOperand(OpNum).getReg();
1456  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1457  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1458  O << "{";
1459  printRegName(O, Reg0);
1460  O << "[], ";
1461  printRegName(O, Reg1);
1462  O << "[]}";
1463 }
1464 
1466  unsigned OpNum,
1467  const MCSubtargetInfo &STI,
1468  raw_ostream &O) {
1469  // Normally, it's not safe to use register enum values directly with
1470  // addition to get the next register, but for VFP registers, the
1471  // sort order is guaranteed because they're all of the form D<n>.
1472  O << "{";
1473  printRegName(O, MI->getOperand(OpNum).getReg());
1474  O << "[], ";
1475  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1476  O << "[], ";
1477  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1478  O << "[]}";
1479 }
1480 
1482  unsigned OpNum,
1483  const MCSubtargetInfo &STI,
1484  raw_ostream &O) {
1485  // Normally, it's not safe to use register enum values directly with
1486  // addition to get the next register, but for VFP registers, the
1487  // sort order is guaranteed because they're all of the form D<n>.
1488  O << "{";
1489  printRegName(O, MI->getOperand(OpNum).getReg());
1490  O << "[], ";
1491  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1492  O << "[], ";
1493  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1494  O << "[], ";
1495  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1496  O << "[]}";
1497 }
1498 
1500  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1501  raw_ostream &O) {
1502  unsigned Reg = MI->getOperand(OpNum).getReg();
1503  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1504  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1505  O << "{";
1506  printRegName(O, Reg0);
1507  O << "[], ";
1508  printRegName(O, Reg1);
1509  O << "[]}";
1510 }
1511 
1513  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1514  raw_ostream &O) {
1515  // Normally, it's not safe to use register enum values directly with
1516  // addition to get the next register, but for VFP registers, the
1517  // sort order is guaranteed because they're all of the form D<n>.
1518  O << "{";
1519  printRegName(O, MI->getOperand(OpNum).getReg());
1520  O << "[], ";
1521  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1522  O << "[], ";
1523  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1524  O << "[]}";
1525 }
1526 
1528  const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1529  raw_ostream &O) {
1530  // Normally, it's not safe to use register enum values directly with
1531  // addition to get the next register, but for VFP registers, the
1532  // sort order is guaranteed because they're all of the form D<n>.
1533  O << "{";
1534  printRegName(O, MI->getOperand(OpNum).getReg());
1535  O << "[], ";
1536  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1537  O << "[], ";
1538  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1539  O << "[], ";
1540  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1541  O << "[]}";
1542 }
1543 
1545  unsigned OpNum,
1546  const MCSubtargetInfo &STI,
1547  raw_ostream &O) {
1548  // Normally, it's not safe to use register enum values directly with
1549  // addition to get the next register, but for VFP registers, the
1550  // sort order is guaranteed because they're all of the form D<n>.
1551  O << "{";
1552  printRegName(O, MI->getOperand(OpNum).getReg());
1553  O << ", ";
1554  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1555  O << ", ";
1556  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1557  O << "}";
1558 }
1559 
1561  const MCSubtargetInfo &STI,
1562  raw_ostream &O) {
1563  // Normally, it's not safe to use register enum values directly with
1564  // addition to get the next register, but for VFP registers, the
1565  // sort order is guaranteed because they're all of the form D<n>.
1566  O << "{";
1567  printRegName(O, MI->getOperand(OpNum).getReg());
1568  O << ", ";
1569  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1570  O << ", ";
1571  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1572  O << ", ";
1573  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1574  O << "}";
1575 }
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
iterator end()
Definition: MCInst.h:187
iterator begin()
Definition: MCInst.h:185
bool isImm() const
Definition: MCInst.h:59
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned char getAM3Offset(unsigned AM3Opc)
SI Whole Quad Mode
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:58
static const char * getShiftOpcStr(ShiftOpc Op)
#define op(i)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:181
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:36
static unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getAM3IdxMode(unsigned AM3Opc)
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Reg
All possible values of the reg field in the ModR/M byte.
static AMSubMode getAM4SubMode(unsigned Mode)
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static AddrOpc getAM5FP16Op(unsigned AM5Opc)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:97
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:96
static const char * getRegisterName(unsigned RegNo)
MCRegisterClass - Base class of TargetRegisterClass.
const char * Name
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static unsigned getAM2IdxMode(unsigned AM2Opc)
int64_t getImm() const
Definition: MCInst.h:76
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:184
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
Definition: Constant.h:42
static unsigned char getAM5Offset(unsigned AM5Opc)
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
Definition: ARMBaseInfo.cpp:31
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
bool isExpr() const
Definition: MCInst.h:61
unsigned getNumOperands() const
Definition: MCInst.h:175
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
Definition: ARMBaseInfo.cpp:25
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getAddrOpcStr(AddrOpc Op)
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:68
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:110
static AddrOpc getAM2Op(unsigned AM2Opc)
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void setOpcode(unsigned Op)
Definition: MCInst.h:167
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getAM2Offset(unsigned AM2Opc)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:173
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:141
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:421
static AddrOpc getAM3Op(unsigned AM3Opc)
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:101
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
static const char * getAMSubModeStr(AMSubMode Mode)
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
bool UseMarkup
True if we are printing marked up assembly.
Definition: MCInstPrinter.h:52
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
MCSubtargetInfo - Generic base class for all target subtargets.
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static AddrOpc getAM5Op(unsigned AM5Opc)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned char getAM5FP16Offset(unsigned AM5Opc)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getSORegOffset(unsigned Op)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Constant expressions.
Definition: MCExpr.h:40
Binary expressions.
Definition: MCExpr.h:39
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:177
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getOpcode() const
Definition: MCInst.h:168
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static float getFPImmFloat(unsigned Imm)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static ShiftOpc getSORegShOp(unsigned Op)
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:49
static uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits)
decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size...
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)