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ARMInstructionSelector.cpp
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1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetMachine.h"
21 #include "llvm/Support/Debug.h"
22 
23 #define DEBUG_TYPE "arm-isel"
24 
25 using namespace llvm;
26 
27 namespace {
28 
29 #define GET_GLOBALISEL_PREDICATE_BITSET
30 #include "ARMGenGlobalISel.inc"
31 #undef GET_GLOBALISEL_PREDICATE_BITSET
32 
33 class ARMInstructionSelector : public InstructionSelector {
34 public:
35  ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
36  const ARMRegisterBankInfo &RBI);
37 
38  bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
39  static const char *getName() { return DEBUG_TYPE; }
40 
41 private:
42  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
43 
44  struct CmpConstants;
45  struct InsertInfo;
46 
47  bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
48  MachineRegisterInfo &MRI) const;
49 
50  // Helper for inserting a comparison sequence that sets \p ResReg to either 1
51  // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
52  // \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
53  bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
54  ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
55  unsigned PrevRes) const;
56 
57  // Set \p DestReg to \p Constant.
58  void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
59 
60  bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61  bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62  bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
63 
64  // Check if the types match and both operands have the expected size and
65  // register bank.
66  bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
67  unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
68 
69  // Check if the register has the expected size and register bank.
70  bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
71  unsigned ExpectedRegBankID) const;
72 
73  const ARMBaseInstrInfo &TII;
74  const ARMBaseRegisterInfo &TRI;
75  const ARMBaseTargetMachine &TM;
76  const ARMRegisterBankInfo &RBI;
77  const ARMSubtarget &STI;
78 
79 #define GET_GLOBALISEL_PREDICATES_DECL
80 #include "ARMGenGlobalISel.inc"
81 #undef GET_GLOBALISEL_PREDICATES_DECL
82 
83 // We declare the temporaries used by selectImpl() in the class to minimize the
84 // cost of constructing placeholder values.
85 #define GET_GLOBALISEL_TEMPORARIES_DECL
86 #include "ARMGenGlobalISel.inc"
87 #undef GET_GLOBALISEL_TEMPORARIES_DECL
88 };
89 } // end anonymous namespace
90 
91 namespace llvm {
94  const ARMSubtarget &STI,
95  const ARMRegisterBankInfo &RBI) {
96  return new ARMInstructionSelector(TM, STI, RBI);
97 }
98 }
99 
100 const unsigned zero_reg = 0;
101 
102 #define GET_GLOBALISEL_IMPL
103 #include "ARMGenGlobalISel.inc"
104 #undef GET_GLOBALISEL_IMPL
105 
106 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
107  const ARMSubtarget &STI,
108  const ARMRegisterBankInfo &RBI)
109  : InstructionSelector(), TII(*STI.getInstrInfo()),
110  TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
112 #include "ARMGenGlobalISel.inc"
115 #include "ARMGenGlobalISel.inc"
117 {
118 }
119 
120 static const TargetRegisterClass *guessRegClass(unsigned Reg,
122  const TargetRegisterInfo &TRI,
123  const RegisterBankInfo &RBI) {
124  const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
125  assert(RegBank && "Can't get reg bank for virtual register");
126 
127  const unsigned Size = MRI.getType(Reg).getSizeInBits();
128  assert((RegBank->getID() == ARM::GPRRegBankID ||
129  RegBank->getID() == ARM::FPRRegBankID) &&
130  "Unsupported reg bank");
131 
132  if (RegBank->getID() == ARM::FPRRegBankID) {
133  if (Size == 32)
134  return &ARM::SPRRegClass;
135  else if (Size == 64)
136  return &ARM::DPRRegClass;
137  else if (Size == 128)
138  return &ARM::QPRRegClass;
139  else
140  llvm_unreachable("Unsupported destination size");
141  }
142 
143  return &ARM::GPRRegClass;
144 }
145 
147  MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
148  const RegisterBankInfo &RBI) {
149  unsigned DstReg = I.getOperand(0).getReg();
150  if (TargetRegisterInfo::isPhysicalRegister(DstReg))
151  return true;
152 
153  const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
154 
155  // No need to constrain SrcReg. It will get constrained when
156  // we hit another of its uses or its defs.
157  // Copies do not have constraints.
158  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
159  LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
160  << " operand\n");
161  return false;
162  }
163  return true;
164 }
165 
167  const ARMBaseInstrInfo &TII,
168  MachineRegisterInfo &MRI,
169  const TargetRegisterInfo &TRI,
170  const RegisterBankInfo &RBI) {
171  assert(TII.getSubtarget().hasVFP2() && "Can't select merge without VFP");
172 
173  // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
174  // into one DPR.
175  unsigned VReg0 = MIB->getOperand(0).getReg();
176  (void)VReg0;
177  assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
178  RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
179  "Unsupported operand for G_MERGE_VALUES");
180  unsigned VReg1 = MIB->getOperand(1).getReg();
181  (void)VReg1;
182  assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
183  RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
184  "Unsupported operand for G_MERGE_VALUES");
185  unsigned VReg2 = MIB->getOperand(2).getReg();
186  (void)VReg2;
187  assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
188  RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
189  "Unsupported operand for G_MERGE_VALUES");
190 
191  MIB->setDesc(TII.get(ARM::VMOVDRR));
192  MIB.add(predOps(ARMCC::AL));
193 
194  return true;
195 }
196 
198  const ARMBaseInstrInfo &TII,
199  MachineRegisterInfo &MRI,
200  const TargetRegisterInfo &TRI,
201  const RegisterBankInfo &RBI) {
202  assert(TII.getSubtarget().hasVFP2() && "Can't select unmerge without VFP");
203 
204  // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
205  // GPRs.
206  unsigned VReg0 = MIB->getOperand(0).getReg();
207  (void)VReg0;
208  assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
209  RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
210  "Unsupported operand for G_UNMERGE_VALUES");
211  unsigned VReg1 = MIB->getOperand(1).getReg();
212  (void)VReg1;
213  assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
214  RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
215  "Unsupported operand for G_UNMERGE_VALUES");
216  unsigned VReg2 = MIB->getOperand(2).getReg();
217  (void)VReg2;
218  assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
219  RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
220  "Unsupported operand for G_UNMERGE_VALUES");
221 
222  MIB->setDesc(TII.get(ARM::VMOVRRD));
223  MIB.add(predOps(ARMCC::AL));
224 
225  return true;
226 }
227 
228 /// Select the opcode for simple extensions (that translate to a single SXT/UXT
229 /// instruction). Extension operations more complicated than that should not
230 /// invoke this. Returns the original opcode if it doesn't know how to select a
231 /// better one.
232 static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
233  using namespace TargetOpcode;
234 
235  if (Size != 8 && Size != 16)
236  return Opc;
237 
238  if (Opc == G_SEXT)
239  return Size == 8 ? ARM::SXTB : ARM::SXTH;
240 
241  if (Opc == G_ZEXT)
242  return Size == 8 ? ARM::UXTB : ARM::UXTH;
243 
244  return Opc;
245 }
246 
247 /// Select the opcode for simple loads and stores. For types smaller than 32
248 /// bits, the value will be zero extended. Returns the original opcode if it
249 /// doesn't know how to select a better one.
250 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
251  unsigned Size) {
252  bool isStore = Opc == TargetOpcode::G_STORE;
253 
254  if (RegBank == ARM::GPRRegBankID) {
255  switch (Size) {
256  case 1:
257  case 8:
258  return isStore ? ARM::STRBi12 : ARM::LDRBi12;
259  case 16:
260  return isStore ? ARM::STRH : ARM::LDRH;
261  case 32:
262  return isStore ? ARM::STRi12 : ARM::LDRi12;
263  default:
264  return Opc;
265  }
266  }
267 
268  if (RegBank == ARM::FPRRegBankID) {
269  switch (Size) {
270  case 32:
271  return isStore ? ARM::VSTRS : ARM::VLDRS;
272  case 64:
273  return isStore ? ARM::VSTRD : ARM::VLDRD;
274  default:
275  return Opc;
276  }
277  }
278 
279  return Opc;
280 }
281 
282 // When lowering comparisons, we sometimes need to perform two compares instead
283 // of just one. Get the condition codes for both comparisons. If only one is
284 // needed, the second member of the pair is ARMCC::AL.
285 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
287  std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
288  switch (Pred) {
289  case CmpInst::FCMP_ONE:
290  Preds = {ARMCC::GT, ARMCC::MI};
291  break;
292  case CmpInst::FCMP_UEQ:
293  Preds = {ARMCC::EQ, ARMCC::VS};
294  break;
295  case CmpInst::ICMP_EQ:
296  case CmpInst::FCMP_OEQ:
297  Preds.first = ARMCC::EQ;
298  break;
299  case CmpInst::ICMP_SGT:
300  case CmpInst::FCMP_OGT:
301  Preds.first = ARMCC::GT;
302  break;
303  case CmpInst::ICMP_SGE:
304  case CmpInst::FCMP_OGE:
305  Preds.first = ARMCC::GE;
306  break;
307  case CmpInst::ICMP_UGT:
308  case CmpInst::FCMP_UGT:
309  Preds.first = ARMCC::HI;
310  break;
311  case CmpInst::FCMP_OLT:
312  Preds.first = ARMCC::MI;
313  break;
314  case CmpInst::ICMP_ULE:
315  case CmpInst::FCMP_OLE:
316  Preds.first = ARMCC::LS;
317  break;
318  case CmpInst::FCMP_ORD:
319  Preds.first = ARMCC::VC;
320  break;
321  case CmpInst::FCMP_UNO:
322  Preds.first = ARMCC::VS;
323  break;
324  case CmpInst::FCMP_UGE:
325  Preds.first = ARMCC::PL;
326  break;
327  case CmpInst::ICMP_SLT:
328  case CmpInst::FCMP_ULT:
329  Preds.first = ARMCC::LT;
330  break;
331  case CmpInst::ICMP_SLE:
332  case CmpInst::FCMP_ULE:
333  Preds.first = ARMCC::LE;
334  break;
335  case CmpInst::FCMP_UNE:
336  case CmpInst::ICMP_NE:
337  Preds.first = ARMCC::NE;
338  break;
339  case CmpInst::ICMP_UGE:
340  Preds.first = ARMCC::HS;
341  break;
342  case CmpInst::ICMP_ULT:
343  Preds.first = ARMCC::LO;
344  break;
345  default:
346  break;
347  }
348  assert(Preds.first != ARMCC::AL && "No comparisons needed?");
349  return Preds;
350 }
351 
353  CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank,
354  unsigned OpSize)
355  : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
356  OperandRegBankID(OpRegBank), OperandSize(OpSize) {}
357 
358  // The opcode used for performing the comparison.
359  const unsigned ComparisonOpcode;
360 
361  // The opcode used for reading the flags set by the comparison. May be
362  // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
363  const unsigned ReadFlagsOpcode;
364 
365  // The assumed register bank ID for the operands.
366  const unsigned OperandRegBankID;
367 
368  // The assumed size in bits for the operands.
369  const unsigned OperandSize;
370 };
371 
374  : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
375  DbgLoc(MIB->getDebugLoc()) {}
376 
379  const DebugLoc &DbgLoc;
380 };
381 
382 void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
383  unsigned Constant) const {
384  (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVi))
385  .addDef(DestReg)
386  .addImm(Constant)
388  .add(condCodeOp());
389 }
390 
391 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
392  unsigned LHSReg, unsigned RHSReg,
393  unsigned ExpectedSize,
394  unsigned ExpectedRegBankID) const {
395  return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
396  validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
397  validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
398 }
399 
400 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
401  unsigned ExpectedSize,
402  unsigned ExpectedRegBankID) const {
403  if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
404  LLVM_DEBUG(dbgs() << "Unexpected size for register");
405  return false;
406  }
407 
408  if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
409  LLVM_DEBUG(dbgs() << "Unexpected register bank for register");
410  return false;
411  }
412 
413  return true;
414 }
415 
416 bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
417  MachineInstrBuilder &MIB,
418  MachineRegisterInfo &MRI) const {
419  const InsertInfo I(MIB);
420 
421  auto ResReg = MIB->getOperand(0).getReg();
422  if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
423  return false;
424 
425  auto Cond =
426  static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
427  if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
428  putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
429  MIB->eraseFromParent();
430  return true;
431  }
432 
433  auto LHSReg = MIB->getOperand(2).getReg();
434  auto RHSReg = MIB->getOperand(3).getReg();
435  if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
436  Helper.OperandRegBankID))
437  return false;
438 
439  auto ARMConds = getComparePreds(Cond);
440  auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
441  putConstant(I, ZeroReg, 0);
442 
443  if (ARMConds.second == ARMCC::AL) {
444  // Simple case, we only need one comparison and we're done.
445  if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
446  ZeroReg))
447  return false;
448  } else {
449  // Not so simple, we need two successive comparisons.
450  auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
451  if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
452  RHSReg, ZeroReg))
453  return false;
454  if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
455  IntermediateRes))
456  return false;
457  }
458 
459  MIB->eraseFromParent();
460  return true;
461 }
462 
463 bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
464  unsigned ResReg,
465  ARMCC::CondCodes Cond,
466  unsigned LHSReg, unsigned RHSReg,
467  unsigned PrevRes) const {
468  // Perform the comparison.
469  auto CmpI =
470  BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
471  .addUse(LHSReg)
472  .addUse(RHSReg)
473  .add(predOps(ARMCC::AL));
474  if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
475  return false;
476 
477  // Read the comparison flags (if necessary).
478  if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
479  auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
480  TII.get(Helper.ReadFlagsOpcode))
481  .add(predOps(ARMCC::AL));
482  if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
483  return false;
484  }
485 
486  // Select either 1 or the previous result based on the value of the flags.
487  auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVCCi))
488  .addDef(ResReg)
489  .addUse(PrevRes)
490  .addImm(1)
491  .add(predOps(Cond, ARM::CPSR));
492  if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
493  return false;
494 
495  return true;
496 }
497 
498 bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
499  MachineRegisterInfo &MRI) const {
500  if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) {
501  LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n");
502  return false;
503  }
504 
505  auto GV = MIB->getOperand(1).getGlobal();
506  if (GV->isThreadLocal()) {
507  LLVM_DEBUG(dbgs() << "TLS variables not supported yet\n");
508  return false;
509  }
510 
511  auto &MBB = *MIB->getParent();
512  auto &MF = *MBB.getParent();
513 
514  bool UseMovt = STI.useMovt(MF);
515 
516  unsigned Size = TM.getPointerSize(0);
517  unsigned Alignment = 4;
518 
519  auto addOpsForConstantPoolLoad = [&MF, Alignment,
521  const GlobalValue *GV, bool IsSBREL) {
522  assert(MIB->getOpcode() == ARM::LDRi12 && "Unsupported instruction");
523  auto ConstPool = MF.getConstantPool();
524  auto CPIndex =
525  // For SB relative entries we need a target-specific constant pool.
526  // Otherwise, just use a regular constant pool entry.
527  IsSBREL
528  ? ConstPool->getConstantPoolIndex(
529  ARMConstantPoolConstant::Create(GV, ARMCP::SBREL), Alignment)
530  : ConstPool->getConstantPoolIndex(GV, Alignment);
531  MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
532  .addMemOperand(
533  MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
534  MachineMemOperand::MOLoad, Size, Alignment))
535  .addImm(0)
536  .add(predOps(ARMCC::AL));
537  };
538 
539  if (TM.isPositionIndependent()) {
540  bool Indirect = STI.isGVIndirectSymbol(GV);
541  // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
542  // support it yet. See PR28229.
543  unsigned Opc =
544  UseMovt && !STI.isTargetELF()
545  ? (Indirect ? ARM::MOV_ga_pcrel_ldr : ARM::MOV_ga_pcrel)
546  : (Indirect ? ARM::LDRLIT_ga_pcrel_ldr : ARM::LDRLIT_ga_pcrel);
547  MIB->setDesc(TII.get(Opc));
548 
550  if (STI.isTargetDarwin())
551  TargetFlags |= ARMII::MO_NONLAZY;
552  if (STI.isGVInGOT(GV))
553  TargetFlags |= ARMII::MO_GOT;
554  MIB->getOperand(1).setTargetFlags(TargetFlags);
555 
556  if (Indirect)
557  MIB.addMemOperand(MF.getMachineMemOperand(
558  MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad,
559  TM.getProgramPointerSize(), Alignment));
560 
561  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
562  }
563 
564  bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV);
565  if (STI.isROPI() && isReadOnly) {
566  unsigned Opc = UseMovt ? ARM::MOV_ga_pcrel : ARM::LDRLIT_ga_pcrel;
567  MIB->setDesc(TII.get(Opc));
568  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
569  }
570  if (STI.isRWPI() && !isReadOnly) {
571  auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
572  MachineInstrBuilder OffsetMIB;
573  if (UseMovt) {
574  OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
575  TII.get(ARM::MOVi32imm), Offset);
576  OffsetMIB.addGlobalAddress(GV, /*Offset*/ 0, ARMII::MO_SBREL);
577  } else {
578  // Load the offset from the constant pool.
579  OffsetMIB =
580  BuildMI(MBB, *MIB, MIB->getDebugLoc(), TII.get(ARM::LDRi12), Offset);
581  addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true);
582  }
583  if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
584  return false;
585 
586  // Add the offset to the SB register.
587  MIB->setDesc(TII.get(ARM::ADDrr));
588  MIB->RemoveOperand(1);
589  MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
590  .addReg(Offset)
591  .add(predOps(ARMCC::AL))
592  .add(condCodeOp());
593 
594  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
595  }
596 
597  if (STI.isTargetELF()) {
598  if (UseMovt) {
599  MIB->setDesc(TII.get(ARM::MOVi32imm));
600  } else {
601  // Load the global's address from the constant pool.
602  MIB->setDesc(TII.get(ARM::LDRi12));
603  MIB->RemoveOperand(1);
604  addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
605  }
606  } else if (STI.isTargetMachO()) {
607  if (UseMovt)
608  MIB->setDesc(TII.get(ARM::MOVi32imm));
609  else
610  MIB->setDesc(TII.get(ARM::LDRLIT_ga_abs));
611  } else {
612  LLVM_DEBUG(dbgs() << "Object format not supported yet\n");
613  return false;
614  }
615 
616  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
617 }
618 
619 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
620  MachineRegisterInfo &MRI) const {
621  auto &MBB = *MIB->getParent();
622  auto InsertBefore = std::next(MIB->getIterator());
623  auto &DbgLoc = MIB->getDebugLoc();
624 
625  // Compare the condition to 0.
626  auto CondReg = MIB->getOperand(1).getReg();
627  assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
628  "Unsupported types for select operation");
629  auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::CMPri))
630  .addUse(CondReg)
631  .addImm(0)
632  .add(predOps(ARMCC::AL));
633  if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
634  return false;
635 
636  // Move a value into the result register based on the result of the
637  // comparison.
638  auto ResReg = MIB->getOperand(0).getReg();
639  auto TrueReg = MIB->getOperand(2).getReg();
640  auto FalseReg = MIB->getOperand(3).getReg();
641  assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
642  validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
643  "Unsupported types for select operation");
644  auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVCCr))
645  .addDef(ResReg)
646  .addUse(TrueReg)
647  .addUse(FalseReg)
648  .add(predOps(ARMCC::EQ, ARM::CPSR));
649  if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
650  return false;
651 
652  MIB->eraseFromParent();
653  return true;
654 }
655 
656 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
657  MachineInstrBuilder &MIB) const {
658  MIB->setDesc(TII.get(ARM::MOVsr));
659  MIB.addImm(ShiftOpc);
661  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
662 }
663 
664 bool ARMInstructionSelector::select(MachineInstr &I,
665  CodeGenCoverage &CoverageInfo) const {
666  assert(I.getParent() && "Instruction should be in a basic block!");
667  assert(I.getParent()->getParent() && "Instruction should be in a function!");
668 
669  auto &MBB = *I.getParent();
670  auto &MF = *MBB.getParent();
671  auto &MRI = MF.getRegInfo();
672 
673  if (!isPreISelGenericOpcode(I.getOpcode())) {
674  if (I.isCopy())
675  return selectCopy(I, TII, MRI, TRI, RBI);
676 
677  return true;
678  }
679 
680  using namespace TargetOpcode;
681 
682  if (selectImpl(I, CoverageInfo))
683  return true;
684 
685  MachineInstrBuilder MIB{MF, I};
686  bool isSExt = false;
687 
688  switch (I.getOpcode()) {
689  case G_SEXT:
690  isSExt = true;
692  case G_ZEXT: {
693  LLT DstTy = MRI.getType(I.getOperand(0).getReg());
694  // FIXME: Smaller destination sizes coming soon!
695  if (DstTy.getSizeInBits() != 32) {
696  LLVM_DEBUG(dbgs() << "Unsupported destination size for extension");
697  return false;
698  }
699 
700  LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
701  unsigned SrcSize = SrcTy.getSizeInBits();
702  switch (SrcSize) {
703  case 1: {
704  // ZExt boils down to & 0x1; for SExt we also subtract that from 0
705  I.setDesc(TII.get(ARM::ANDri));
707 
708  if (isSExt) {
709  unsigned SExtResult = I.getOperand(0).getReg();
710 
711  // Use a new virtual register for the result of the AND
712  unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
713  I.getOperand(0).setReg(AndResult);
714 
715  auto InsertBefore = std::next(I.getIterator());
716  auto SubI =
717  BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
718  .addDef(SExtResult)
719  .addUse(AndResult)
720  .addImm(0)
722  .add(condCodeOp());
723  if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
724  return false;
725  }
726  break;
727  }
728  case 8:
729  case 16: {
730  unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
731  if (NewOpc == I.getOpcode())
732  return false;
733  I.setDesc(TII.get(NewOpc));
734  MIB.addImm(0).add(predOps(ARMCC::AL));
735  break;
736  }
737  default:
738  LLVM_DEBUG(dbgs() << "Unsupported source size for extension");
739  return false;
740  }
741  break;
742  }
743  case G_ANYEXT:
744  case G_TRUNC: {
745  // The high bits are undefined, so there's nothing special to do, just
746  // treat it as a copy.
747  auto SrcReg = I.getOperand(1).getReg();
748  auto DstReg = I.getOperand(0).getReg();
749 
750  const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
751  const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
752 
753  if (SrcRegBank.getID() == ARM::FPRRegBankID) {
754  // This should only happen in the obscure case where we have put a 64-bit
755  // integer into a D register. Get it out of there and keep only the
756  // interesting part.
757  assert(I.getOpcode() == G_TRUNC && "Unsupported operand for G_ANYEXT");
758  assert(DstRegBank.getID() == ARM::GPRRegBankID &&
759  "Unsupported combination of register banks");
760  assert(MRI.getType(SrcReg).getSizeInBits() == 64 && "Unsupported size");
761  assert(MRI.getType(DstReg).getSizeInBits() <= 32 && "Unsupported size");
762 
763  unsigned IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
764  auto InsertBefore = std::next(I.getIterator());
765  auto MovI =
766  BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD))
767  .addDef(DstReg)
768  .addDef(IgnoredBits)
769  .addUse(SrcReg)
770  .add(predOps(ARMCC::AL));
771  if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI))
772  return false;
773 
774  MIB->eraseFromParent();
775  return true;
776  }
777 
778  if (SrcRegBank.getID() != DstRegBank.getID()) {
779  LLVM_DEBUG(
780  dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
781  return false;
782  }
783 
784  if (SrcRegBank.getID() != ARM::GPRRegBankID) {
785  LLVM_DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
786  return false;
787  }
788 
789  I.setDesc(TII.get(COPY));
790  return selectCopy(I, TII, MRI, TRI, RBI);
791  }
792  case G_CONSTANT: {
793  if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) {
794  // Non-pointer constants should be handled by TableGen.
795  LLVM_DEBUG(dbgs() << "Unsupported constant type\n");
796  return false;
797  }
798 
799  auto &Val = I.getOperand(1);
800  if (Val.isCImm()) {
801  if (!Val.getCImm()->isZero()) {
802  LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
803  return false;
804  }
805  Val.ChangeToImmediate(0);
806  } else {
807  assert(Val.isImm() && "Unexpected operand for G_CONSTANT");
808  if (Val.getImm() != 0) {
809  LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
810  return false;
811  }
812  }
813 
814  I.setDesc(TII.get(ARM::MOVi));
816  break;
817  }
818  case G_INTTOPTR:
819  case G_PTRTOINT: {
820  auto SrcReg = I.getOperand(1).getReg();
821  auto DstReg = I.getOperand(0).getReg();
822 
823  const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
824  const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
825 
826  if (SrcRegBank.getID() != DstRegBank.getID()) {
827  LLVM_DEBUG(
828  dbgs()
829  << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
830  return false;
831  }
832 
833  if (SrcRegBank.getID() != ARM::GPRRegBankID) {
834  LLVM_DEBUG(
835  dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
836  return false;
837  }
838 
839  I.setDesc(TII.get(COPY));
840  return selectCopy(I, TII, MRI, TRI, RBI);
841  }
842  case G_SELECT:
843  return selectSelect(MIB, MRI);
844  case G_ICMP: {
845  CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END,
846  ARM::GPRRegBankID, 32);
847  return selectCmp(Helper, MIB, MRI);
848  }
849  case G_FCMP: {
850  assert(STI.hasVFP2() && "Can't select fcmp without VFP");
851 
852  unsigned OpReg = I.getOperand(2).getReg();
853  unsigned Size = MRI.getType(OpReg).getSizeInBits();
854 
855  if (Size == 64 && STI.isFPOnlySP()) {
856  LLVM_DEBUG(dbgs() << "Subtarget only supports single precision");
857  return false;
858  }
859  if (Size != 32 && Size != 64) {
860  LLVM_DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
861  return false;
862  }
863 
864  CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
865  ARM::FPRRegBankID, Size);
866  return selectCmp(Helper, MIB, MRI);
867  }
868  case G_LSHR:
869  return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
870  case G_ASHR:
871  return selectShift(ARM_AM::ShiftOpc::asr, MIB);
872  case G_SHL: {
873  return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
874  }
875  case G_GEP:
876  I.setDesc(TII.get(ARM::ADDrr));
878  break;
879  case G_FRAME_INDEX:
880  // Add 0 to the given frame index and hope it will eventually be folded into
881  // the user(s).
882  I.setDesc(TII.get(ARM::ADDri));
884  break;
885  case G_GLOBAL_VALUE:
886  return selectGlobal(MIB, MRI);
887  case G_STORE:
888  case G_LOAD: {
889  const auto &MemOp = **I.memoperands_begin();
890  if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
891  LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
892  return false;
893  }
894 
895  unsigned Reg = I.getOperand(0).getReg();
896  unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
897 
898  LLT ValTy = MRI.getType(Reg);
899  const auto ValSize = ValTy.getSizeInBits();
900 
901  assert((ValSize != 64 || STI.hasVFP2()) &&
902  "Don't know how to load/store 64-bit value without VFP");
903 
904  const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
905  if (NewOpc == G_LOAD || NewOpc == G_STORE)
906  return false;
907 
908  I.setDesc(TII.get(NewOpc));
909 
910  if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
911  // LDRH has a funny addressing mode (there's already a FIXME for it).
912  MIB.addReg(0);
913  MIB.addImm(0).add(predOps(ARMCC::AL));
914  break;
915  }
916  case G_MERGE_VALUES: {
917  if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
918  return false;
919  break;
920  }
921  case G_UNMERGE_VALUES: {
922  if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
923  return false;
924  break;
925  }
926  case G_BRCOND: {
927  if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
928  LLVM_DEBUG(dbgs() << "Unsupported condition register for G_BRCOND");
929  return false;
930  }
931 
932  // Set the flags.
933  auto Test = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::TSTri))
934  .addReg(I.getOperand(0).getReg())
935  .addImm(1)
936  .add(predOps(ARMCC::AL));
937  if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
938  return false;
939 
940  // Branch conditionally.
941  auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::Bcc))
942  .add(I.getOperand(1))
943  .add(predOps(ARMCC::NE, ARM::CPSR));
944  if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
945  return false;
946  I.eraseFromParent();
947  return true;
948  }
949  case G_PHI: {
950  I.setDesc(TII.get(PHI));
951 
952  unsigned DstReg = I.getOperand(0).getReg();
953  const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
954  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
955  break;
956  }
957 
958  return true;
959  }
960  default:
961  return false;
962  }
963 
964  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
965 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
static bool selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const unsigned zero_reg
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
#define DEBUG_TYPE
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
#define GET_GLOBALISEL_PREDICATES_INIT
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
Holds all the information related to register banks.
Definition: BitVector.h:938
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
Definition: ARMBaseInfo.h:261
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank, unsigned OpSize)
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
static StringRef getName(Value *V)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
bool hasVFP2() const
Definition: ARMSubtarget.h:561
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
static bool isStore(int Opcode)
This class provides the information for the target register banks.
const ARMSubtarget & getSubtarget() const
#define EQ(a, b)
Definition: regexec.c:112
static std::pair< ARMCC::CondCodes, ARMCC::CondCodes > getComparePreds(CmpInst::Predicate Pred)
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
This file declares the targeting of the RegisterBankInfo class for ARM.
This is an important base class in LLVM.
Definition: Constant.h:42
const GlobalValue * getGlobal() const
static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank, unsigned Size)
Select the opcode for simple loads and stores.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:685
static bool selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
self_iterator getIterator()
Definition: ilist_node.h:82
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:88
This class implements the register bank concept.
Definition: RegisterBank.h:29
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Section Relative (Windows TLS)
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
#define GET_GLOBALISEL_TEMPORARIES_INIT
uint32_t Size
Definition: Profile.cpp:47
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
static const Function * getParent(const Value *V)
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:279
const MachineBasicBlock::instr_iterator InsertBefore
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size)
Select the opcode for simple extensions (that translate to a single SXT/UXT instruction).
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
unsigned getPredicate() const