LLVM  9.0.0svn
ARMInstructionSelector.cpp
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1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMRegisterBankInfo.h"
14 #include "ARMSubtarget.h"
15 #include "ARMTargetMachine.h"
20 #include "llvm/Support/Debug.h"
21 
22 #define DEBUG_TYPE "arm-isel"
23 
24 using namespace llvm;
25 
26 namespace {
27 
28 #define GET_GLOBALISEL_PREDICATE_BITSET
29 #include "ARMGenGlobalISel.inc"
30 #undef GET_GLOBALISEL_PREDICATE_BITSET
31 
32 class ARMInstructionSelector : public InstructionSelector {
33 public:
34  ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
35  const ARMRegisterBankInfo &RBI);
36 
37  bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
38  static const char *getName() { return DEBUG_TYPE; }
39 
40 private:
41  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
42 
43  struct CmpConstants;
44  struct InsertInfo;
45 
46  bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
47  MachineRegisterInfo &MRI) const;
48 
49  // Helper for inserting a comparison sequence that sets \p ResReg to either 1
50  // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
51  // \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
52  bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
53  ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
54  unsigned PrevRes) const;
55 
56  // Set \p DestReg to \p Constant.
57  void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
58 
59  bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
60  bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61  bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
62 
63  // Check if the types match and both operands have the expected size and
64  // register bank.
65  bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
66  unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
67 
68  // Check if the register has the expected size and register bank.
69  bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
70  unsigned ExpectedRegBankID) const;
71 
72  const ARMBaseInstrInfo &TII;
73  const ARMBaseRegisterInfo &TRI;
74  const ARMBaseTargetMachine &TM;
75  const ARMRegisterBankInfo &RBI;
76  const ARMSubtarget &STI;
77 
78  // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
79  // uses "STI." in the code generated by TableGen. If we want to reuse some of
80  // the custom C++ predicates written for DAGISel, we need to have both around.
81  const ARMSubtarget *Subtarget = &STI;
82 
83  // Store the opcodes that we might need, so we don't have to check what kind
84  // of subtarget (ARM vs Thumb) we have all the time.
85  struct OpcodeCache {
86  unsigned ZEXT16;
87  unsigned SEXT16;
88 
89  unsigned ZEXT8;
90  unsigned SEXT8;
91 
92  // Used for implementing ZEXT/SEXT from i1
93  unsigned AND;
94  unsigned RSB;
95 
96  unsigned STORE32;
97  unsigned LOAD32;
98 
99  unsigned STORE16;
100  unsigned LOAD16;
101 
102  unsigned STORE8;
103  unsigned LOAD8;
104 
105  unsigned ADDrr;
106  unsigned ADDri;
107 
108  // Used for G_ICMP
109  unsigned CMPrr;
110  unsigned MOVi;
111  unsigned MOVCCi;
112 
113  // Used for G_SELECT
114  unsigned MOVCCr;
115 
116  unsigned TSTri;
117  unsigned Bcc;
118 
119  // Used for G_GLOBAL_VALUE
120  unsigned MOVi32imm;
121  unsigned ConstPoolLoad;
122  unsigned MOV_ga_pcrel;
123  unsigned LDRLIT_ga_pcrel;
124  unsigned LDRLIT_ga_abs;
125 
126  OpcodeCache(const ARMSubtarget &STI);
127  } const Opcodes;
128 
129  // Select the opcode for simple extensions (that translate to a single SXT/UXT
130  // instruction). Extension operations more complicated than that should not
131  // invoke this. Returns the original opcode if it doesn't know how to select a
132  // better one.
133  unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) const;
134 
135  // Select the opcode for simple loads and stores. Returns the original opcode
136  // if it doesn't know how to select a better one.
137  unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
138  unsigned Size) const;
139 
140  void renderVFPF32Imm(MachineInstrBuilder &New, const MachineInstr &Old) const;
141  void renderVFPF64Imm(MachineInstrBuilder &New, const MachineInstr &Old) const;
142 
143 #define GET_GLOBALISEL_PREDICATES_DECL
144 #include "ARMGenGlobalISel.inc"
145 #undef GET_GLOBALISEL_PREDICATES_DECL
146 
147 // We declare the temporaries used by selectImpl() in the class to minimize the
148 // cost of constructing placeholder values.
149 #define GET_GLOBALISEL_TEMPORARIES_DECL
150 #include "ARMGenGlobalISel.inc"
151 #undef GET_GLOBALISEL_TEMPORARIES_DECL
152 };
153 } // end anonymous namespace
154 
155 namespace llvm {
158  const ARMSubtarget &STI,
159  const ARMRegisterBankInfo &RBI) {
160  return new ARMInstructionSelector(TM, STI, RBI);
161 }
162 }
163 
164 const unsigned zero_reg = 0;
165 
166 #define GET_GLOBALISEL_IMPL
167 #include "ARMGenGlobalISel.inc"
168 #undef GET_GLOBALISEL_IMPL
169 
170 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
171  const ARMSubtarget &STI,
172  const ARMRegisterBankInfo &RBI)
173  : InstructionSelector(), TII(*STI.getInstrInfo()),
174  TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
176 #include "ARMGenGlobalISel.inc"
179 #include "ARMGenGlobalISel.inc"
181 {
182 }
183 
184 static const TargetRegisterClass *guessRegClass(unsigned Reg,
186  const TargetRegisterInfo &TRI,
187  const RegisterBankInfo &RBI) {
188  const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
189  assert(RegBank && "Can't get reg bank for virtual register");
190 
191  const unsigned Size = MRI.getType(Reg).getSizeInBits();
192  assert((RegBank->getID() == ARM::GPRRegBankID ||
193  RegBank->getID() == ARM::FPRRegBankID) &&
194  "Unsupported reg bank");
195 
196  if (RegBank->getID() == ARM::FPRRegBankID) {
197  if (Size == 32)
198  return &ARM::SPRRegClass;
199  else if (Size == 64)
200  return &ARM::DPRRegClass;
201  else if (Size == 128)
202  return &ARM::QPRRegClass;
203  else
204  llvm_unreachable("Unsupported destination size");
205  }
206 
207  return &ARM::GPRRegClass;
208 }
209 
211  MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
212  const RegisterBankInfo &RBI) {
213  unsigned DstReg = I.getOperand(0).getReg();
214  if (TargetRegisterInfo::isPhysicalRegister(DstReg))
215  return true;
216 
217  const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
218 
219  // No need to constrain SrcReg. It will get constrained when
220  // we hit another of its uses or its defs.
221  // Copies do not have constraints.
222  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
223  LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
224  << " operand\n");
225  return false;
226  }
227  return true;
228 }
229 
231  const ARMBaseInstrInfo &TII,
232  MachineRegisterInfo &MRI,
233  const TargetRegisterInfo &TRI,
234  const RegisterBankInfo &RBI) {
235  assert(TII.getSubtarget().hasVFP2() && "Can't select merge without VFP");
236 
237  // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
238  // into one DPR.
239  unsigned VReg0 = MIB->getOperand(0).getReg();
240  (void)VReg0;
241  assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
242  RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
243  "Unsupported operand for G_MERGE_VALUES");
244  unsigned VReg1 = MIB->getOperand(1).getReg();
245  (void)VReg1;
246  assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
247  RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
248  "Unsupported operand for G_MERGE_VALUES");
249  unsigned VReg2 = MIB->getOperand(2).getReg();
250  (void)VReg2;
251  assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
252  RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
253  "Unsupported operand for G_MERGE_VALUES");
254 
255  MIB->setDesc(TII.get(ARM::VMOVDRR));
256  MIB.add(predOps(ARMCC::AL));
257 
258  return true;
259 }
260 
262  const ARMBaseInstrInfo &TII,
263  MachineRegisterInfo &MRI,
264  const TargetRegisterInfo &TRI,
265  const RegisterBankInfo &RBI) {
266  assert(TII.getSubtarget().hasVFP2() && "Can't select unmerge without VFP");
267 
268  // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
269  // GPRs.
270  unsigned VReg0 = MIB->getOperand(0).getReg();
271  (void)VReg0;
272  assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
273  RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
274  "Unsupported operand for G_UNMERGE_VALUES");
275  unsigned VReg1 = MIB->getOperand(1).getReg();
276  (void)VReg1;
277  assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
278  RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
279  "Unsupported operand for G_UNMERGE_VALUES");
280  unsigned VReg2 = MIB->getOperand(2).getReg();
281  (void)VReg2;
282  assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
283  RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
284  "Unsupported operand for G_UNMERGE_VALUES");
285 
286  MIB->setDesc(TII.get(ARM::VMOVRRD));
287  MIB.add(predOps(ARMCC::AL));
288 
289  return true;
290 }
291 
292 ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
293  bool isThumb = STI.isThumb();
294 
295  using namespace TargetOpcode;
296 
297 #define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC
298  STORE_OPCODE(SEXT16, SXTH);
299  STORE_OPCODE(ZEXT16, UXTH);
300 
301  STORE_OPCODE(SEXT8, SXTB);
302  STORE_OPCODE(ZEXT8, UXTB);
303 
304  STORE_OPCODE(AND, ANDri);
305  STORE_OPCODE(RSB, RSBri);
306 
307  STORE_OPCODE(STORE32, STRi12);
308  STORE_OPCODE(LOAD32, LDRi12);
309 
310  // LDRH/STRH are special...
311  STORE16 = isThumb ? ARM::t2STRHi12 : ARM::STRH;
312  LOAD16 = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
313 
314  STORE_OPCODE(STORE8, STRBi12);
315  STORE_OPCODE(LOAD8, LDRBi12);
316 
317  STORE_OPCODE(ADDrr, ADDrr);
318  STORE_OPCODE(ADDri, ADDri);
319 
320  STORE_OPCODE(CMPrr, CMPrr);
321  STORE_OPCODE(MOVi, MOVi);
322  STORE_OPCODE(MOVCCi, MOVCCi);
323 
324  STORE_OPCODE(MOVCCr, MOVCCr);
325 
326  STORE_OPCODE(TSTri, TSTri);
327  STORE_OPCODE(Bcc, Bcc);
328 
329  STORE_OPCODE(MOVi32imm, MOVi32imm);
330  ConstPoolLoad = isThumb ? ARM::t2LDRpci : ARM::LDRi12;
331  STORE_OPCODE(MOV_ga_pcrel, MOV_ga_pcrel);
332  LDRLIT_ga_pcrel = isThumb ? ARM::tLDRLIT_ga_pcrel : ARM::LDRLIT_ga_pcrel;
333  LDRLIT_ga_abs = isThumb ? ARM::tLDRLIT_ga_abs : ARM::LDRLIT_ga_abs;
334 #undef MAP_OPCODE
335 }
336 
337 unsigned ARMInstructionSelector::selectSimpleExtOpc(unsigned Opc,
338  unsigned Size) const {
339  using namespace TargetOpcode;
340 
341  if (Size != 8 && Size != 16)
342  return Opc;
343 
344  if (Opc == G_SEXT)
345  return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
346 
347  if (Opc == G_ZEXT)
348  return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
349 
350  return Opc;
351 }
352 
353 unsigned ARMInstructionSelector::selectLoadStoreOpCode(unsigned Opc,
354  unsigned RegBank,
355  unsigned Size) const {
356  bool isStore = Opc == TargetOpcode::G_STORE;
357 
358  if (RegBank == ARM::GPRRegBankID) {
359  switch (Size) {
360  case 1:
361  case 8:
362  return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
363  case 16:
364  return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
365  case 32:
366  return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
367  default:
368  return Opc;
369  }
370  }
371 
372  if (RegBank == ARM::FPRRegBankID) {
373  switch (Size) {
374  case 32:
375  return isStore ? ARM::VSTRS : ARM::VLDRS;
376  case 64:
377  return isStore ? ARM::VSTRD : ARM::VLDRD;
378  default:
379  return Opc;
380  }
381  }
382 
383  return Opc;
384 }
385 
386 // When lowering comparisons, we sometimes need to perform two compares instead
387 // of just one. Get the condition codes for both comparisons. If only one is
388 // needed, the second member of the pair is ARMCC::AL.
389 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
391  std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
392  switch (Pred) {
393  case CmpInst::FCMP_ONE:
394  Preds = {ARMCC::GT, ARMCC::MI};
395  break;
396  case CmpInst::FCMP_UEQ:
397  Preds = {ARMCC::EQ, ARMCC::VS};
398  break;
399  case CmpInst::ICMP_EQ:
400  case CmpInst::FCMP_OEQ:
401  Preds.first = ARMCC::EQ;
402  break;
403  case CmpInst::ICMP_SGT:
404  case CmpInst::FCMP_OGT:
405  Preds.first = ARMCC::GT;
406  break;
407  case CmpInst::ICMP_SGE:
408  case CmpInst::FCMP_OGE:
409  Preds.first = ARMCC::GE;
410  break;
411  case CmpInst::ICMP_UGT:
412  case CmpInst::FCMP_UGT:
413  Preds.first = ARMCC::HI;
414  break;
415  case CmpInst::FCMP_OLT:
416  Preds.first = ARMCC::MI;
417  break;
418  case CmpInst::ICMP_ULE:
419  case CmpInst::FCMP_OLE:
420  Preds.first = ARMCC::LS;
421  break;
422  case CmpInst::FCMP_ORD:
423  Preds.first = ARMCC::VC;
424  break;
425  case CmpInst::FCMP_UNO:
426  Preds.first = ARMCC::VS;
427  break;
428  case CmpInst::FCMP_UGE:
429  Preds.first = ARMCC::PL;
430  break;
431  case CmpInst::ICMP_SLT:
432  case CmpInst::FCMP_ULT:
433  Preds.first = ARMCC::LT;
434  break;
435  case CmpInst::ICMP_SLE:
436  case CmpInst::FCMP_ULE:
437  Preds.first = ARMCC::LE;
438  break;
439  case CmpInst::FCMP_UNE:
440  case CmpInst::ICMP_NE:
441  Preds.first = ARMCC::NE;
442  break;
443  case CmpInst::ICMP_UGE:
444  Preds.first = ARMCC::HS;
445  break;
446  case CmpInst::ICMP_ULT:
447  Preds.first = ARMCC::LO;
448  break;
449  default:
450  break;
451  }
452  assert(Preds.first != ARMCC::AL && "No comparisons needed?");
453  return Preds;
454 }
455 
457  CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode,
458  unsigned OpRegBank, unsigned OpSize)
459  : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
460  SelectResultOpcode(SelectOpcode), OperandRegBankID(OpRegBank),
461  OperandSize(OpSize) {}
462 
463  // The opcode used for performing the comparison.
464  const unsigned ComparisonOpcode;
465 
466  // The opcode used for reading the flags set by the comparison. May be
467  // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
468  const unsigned ReadFlagsOpcode;
469 
470  // The opcode used for materializing the result of the comparison.
471  const unsigned SelectResultOpcode;
472 
473  // The assumed register bank ID for the operands.
474  const unsigned OperandRegBankID;
475 
476  // The assumed size in bits for the operands.
477  const unsigned OperandSize;
478 };
479 
482  : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
483  DbgLoc(MIB->getDebugLoc()) {}
484 
487  const DebugLoc &DbgLoc;
488 };
489 
490 void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
491  unsigned Constant) const {
492  (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Opcodes.MOVi))
493  .addDef(DestReg)
494  .addImm(Constant)
496  .add(condCodeOp());
497 }
498 
499 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
500  unsigned LHSReg, unsigned RHSReg,
501  unsigned ExpectedSize,
502  unsigned ExpectedRegBankID) const {
503  return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
504  validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
505  validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
506 }
507 
508 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
509  unsigned ExpectedSize,
510  unsigned ExpectedRegBankID) const {
511  if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
512  LLVM_DEBUG(dbgs() << "Unexpected size for register");
513  return false;
514  }
515 
516  if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
517  LLVM_DEBUG(dbgs() << "Unexpected register bank for register");
518  return false;
519  }
520 
521  return true;
522 }
523 
524 bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
525  MachineInstrBuilder &MIB,
526  MachineRegisterInfo &MRI) const {
527  const InsertInfo I(MIB);
528 
529  auto ResReg = MIB->getOperand(0).getReg();
530  if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
531  return false;
532 
533  auto Cond =
534  static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
535  if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
536  putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
537  MIB->eraseFromParent();
538  return true;
539  }
540 
541  auto LHSReg = MIB->getOperand(2).getReg();
542  auto RHSReg = MIB->getOperand(3).getReg();
543  if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
544  Helper.OperandRegBankID))
545  return false;
546 
547  auto ARMConds = getComparePreds(Cond);
548  auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
549  putConstant(I, ZeroReg, 0);
550 
551  if (ARMConds.second == ARMCC::AL) {
552  // Simple case, we only need one comparison and we're done.
553  if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
554  ZeroReg))
555  return false;
556  } else {
557  // Not so simple, we need two successive comparisons.
558  auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
559  if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
560  RHSReg, ZeroReg))
561  return false;
562  if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
563  IntermediateRes))
564  return false;
565  }
566 
567  MIB->eraseFromParent();
568  return true;
569 }
570 
571 bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
572  unsigned ResReg,
573  ARMCC::CondCodes Cond,
574  unsigned LHSReg, unsigned RHSReg,
575  unsigned PrevRes) const {
576  // Perform the comparison.
577  auto CmpI =
578  BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
579  .addUse(LHSReg)
580  .addUse(RHSReg)
581  .add(predOps(ARMCC::AL));
582  if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
583  return false;
584 
585  // Read the comparison flags (if necessary).
586  if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
587  auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
588  TII.get(Helper.ReadFlagsOpcode))
589  .add(predOps(ARMCC::AL));
590  if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
591  return false;
592  }
593 
594  // Select either 1 or the previous result based on the value of the flags.
595  auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
596  TII.get(Helper.SelectResultOpcode))
597  .addDef(ResReg)
598  .addUse(PrevRes)
599  .addImm(1)
600  .add(predOps(Cond, ARM::CPSR));
601  if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
602  return false;
603 
604  return true;
605 }
606 
607 bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
608  MachineRegisterInfo &MRI) const {
609  if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) {
610  LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n");
611  return false;
612  }
613 
614  auto GV = MIB->getOperand(1).getGlobal();
615  if (GV->isThreadLocal()) {
616  LLVM_DEBUG(dbgs() << "TLS variables not supported yet\n");
617  return false;
618  }
619 
620  auto &MBB = *MIB->getParent();
621  auto &MF = *MBB.getParent();
622 
623  bool UseMovt = STI.useMovt();
624 
625  unsigned Size = TM.getPointerSize(0);
626  unsigned Alignment = 4;
627 
628  auto addOpsForConstantPoolLoad = [&MF, Alignment,
630  const GlobalValue *GV, bool IsSBREL) {
631  assert((MIB->getOpcode() == ARM::LDRi12 ||
632  MIB->getOpcode() == ARM::t2LDRpci) &&
633  "Unsupported instruction");
634  auto ConstPool = MF.getConstantPool();
635  auto CPIndex =
636  // For SB relative entries we need a target-specific constant pool.
637  // Otherwise, just use a regular constant pool entry.
638  IsSBREL
639  ? ConstPool->getConstantPoolIndex(
640  ARMConstantPoolConstant::Create(GV, ARMCP::SBREL), Alignment)
641  : ConstPool->getConstantPoolIndex(GV, Alignment);
642  MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
643  .addMemOperand(MF.getMachineMemOperand(
644  MachinePointerInfo::getConstantPool(MF), MachineMemOperand::MOLoad,
645  Size, Alignment));
646  if (MIB->getOpcode() == ARM::LDRi12)
647  MIB.addImm(0);
648  MIB.add(predOps(ARMCC::AL));
649  };
650 
651  auto addGOTMemOperand = [this, &MF, Alignment](MachineInstrBuilder &MIB) {
652  MIB.addMemOperand(MF.getMachineMemOperand(
653  MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad,
654  TM.getProgramPointerSize(), Alignment));
655  };
656 
657  if (TM.isPositionIndependent()) {
658  bool Indirect = STI.isGVIndirectSymbol(GV);
659 
660  // For ARM mode, we have different pseudoinstructions for direct accesses
661  // and indirect accesses, and the ones for indirect accesses include the
662  // load from GOT. For Thumb mode, we use the same pseudoinstruction for both
663  // direct and indirect accesses, and we need to manually generate the load
664  // from GOT.
665  bool UseOpcodeThatLoads = Indirect && !STI.isThumb();
666 
667  // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
668  // support it yet. See PR28229.
669  unsigned Opc =
670  UseMovt && !STI.isTargetELF()
671  ? (UseOpcodeThatLoads ? (unsigned)ARM::MOV_ga_pcrel_ldr
672  : Opcodes.MOV_ga_pcrel)
673  : (UseOpcodeThatLoads ? (unsigned)ARM::LDRLIT_ga_pcrel_ldr
674  : Opcodes.LDRLIT_ga_pcrel);
675  MIB->setDesc(TII.get(Opc));
676 
678  if (STI.isTargetDarwin())
679  TargetFlags |= ARMII::MO_NONLAZY;
680  if (STI.isGVInGOT(GV))
681  TargetFlags |= ARMII::MO_GOT;
682  MIB->getOperand(1).setTargetFlags(TargetFlags);
683 
684  if (Indirect) {
685  if (!UseOpcodeThatLoads) {
686  auto ResultReg = MIB->getOperand(0).getReg();
687  auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
688 
689  MIB->getOperand(0).setReg(AddressReg);
690 
691  auto InsertBefore = std::next(MIB->getIterator());
692  auto MIBLoad = BuildMI(MBB, InsertBefore, MIB->getDebugLoc(),
693  TII.get(Opcodes.LOAD32))
694  .addDef(ResultReg)
695  .addReg(AddressReg)
696  .addImm(0)
697  .add(predOps(ARMCC::AL));
698  addGOTMemOperand(MIBLoad);
699 
700  if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI))
701  return false;
702  } else {
703  addGOTMemOperand(MIB);
704  }
705  }
706 
707  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
708  }
709 
710  bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV);
711  if (STI.isROPI() && isReadOnly) {
712  unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel;
713  MIB->setDesc(TII.get(Opc));
714  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
715  }
716  if (STI.isRWPI() && !isReadOnly) {
717  auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
718  MachineInstrBuilder OffsetMIB;
719  if (UseMovt) {
720  OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
721  TII.get(Opcodes.MOVi32imm), Offset);
722  OffsetMIB.addGlobalAddress(GV, /*Offset*/ 0, ARMII::MO_SBREL);
723  } else {
724  // Load the offset from the constant pool.
725  OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
726  TII.get(Opcodes.ConstPoolLoad), Offset);
727  addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true);
728  }
729  if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
730  return false;
731 
732  // Add the offset to the SB register.
733  MIB->setDesc(TII.get(Opcodes.ADDrr));
734  MIB->RemoveOperand(1);
735  MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
736  .addReg(Offset)
737  .add(predOps(ARMCC::AL))
738  .add(condCodeOp());
739 
740  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
741  }
742 
743  if (STI.isTargetELF()) {
744  if (UseMovt) {
745  MIB->setDesc(TII.get(Opcodes.MOVi32imm));
746  } else {
747  // Load the global's address from the constant pool.
748  MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
749  MIB->RemoveOperand(1);
750  addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
751  }
752  } else if (STI.isTargetMachO()) {
753  if (UseMovt)
754  MIB->setDesc(TII.get(Opcodes.MOVi32imm));
755  else
756  MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
757  } else {
758  LLVM_DEBUG(dbgs() << "Object format not supported yet\n");
759  return false;
760  }
761 
762  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
763 }
764 
765 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
766  MachineRegisterInfo &MRI) const {
767  auto &MBB = *MIB->getParent();
768  auto InsertBefore = std::next(MIB->getIterator());
769  auto &DbgLoc = MIB->getDebugLoc();
770 
771  // Compare the condition to 1.
772  auto CondReg = MIB->getOperand(1).getReg();
773  assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
774  "Unsupported types for select operation");
775  auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
776  .addUse(CondReg)
777  .addImm(1)
778  .add(predOps(ARMCC::AL));
779  if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
780  return false;
781 
782  // Move a value into the result register based on the result of the
783  // comparison.
784  auto ResReg = MIB->getOperand(0).getReg();
785  auto TrueReg = MIB->getOperand(2).getReg();
786  auto FalseReg = MIB->getOperand(3).getReg();
787  assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
788  validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
789  "Unsupported types for select operation");
790  auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr))
791  .addDef(ResReg)
792  .addUse(TrueReg)
793  .addUse(FalseReg)
794  .add(predOps(ARMCC::EQ, ARM::CPSR));
795  if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
796  return false;
797 
798  MIB->eraseFromParent();
799  return true;
800 }
801 
802 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
803  MachineInstrBuilder &MIB) const {
804  assert(!STI.isThumb() && "Unsupported subtarget");
805  MIB->setDesc(TII.get(ARM::MOVsr));
806  MIB.addImm(ShiftOpc);
808  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
809 }
810 
811 void ARMInstructionSelector::renderVFPF32Imm(
812  MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst) const {
813  assert(OldInst.getOpcode() == TargetOpcode::G_FCONSTANT &&
814  "Expected G_FCONSTANT");
815 
816  APFloat FPImmValue = OldInst.getOperand(1).getFPImm()->getValueAPF();
817  int FPImmEncoding = ARM_AM::getFP32Imm(FPImmValue);
818  assert(FPImmEncoding != -1 && "Invalid immediate value");
819 
820  NewInstBuilder.addImm(FPImmEncoding);
821 }
822 
823 void ARMInstructionSelector::renderVFPF64Imm(
824  MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst) const {
825  assert(OldInst.getOpcode() == TargetOpcode::G_FCONSTANT &&
826  "Expected G_FCONSTANT");
827 
828  APFloat FPImmValue = OldInst.getOperand(1).getFPImm()->getValueAPF();
829  int FPImmEncoding = ARM_AM::getFP64Imm(FPImmValue);
830  assert(FPImmEncoding != -1 && "Invalid immediate value");
831 
832  NewInstBuilder.addImm(FPImmEncoding);
833 }
834 
835 bool ARMInstructionSelector::select(MachineInstr &I,
836  CodeGenCoverage &CoverageInfo) const {
837  assert(I.getParent() && "Instruction should be in a basic block!");
838  assert(I.getParent()->getParent() && "Instruction should be in a function!");
839 
840  auto &MBB = *I.getParent();
841  auto &MF = *MBB.getParent();
842  auto &MRI = MF.getRegInfo();
843 
844  if (!isPreISelGenericOpcode(I.getOpcode())) {
845  if (I.isCopy())
846  return selectCopy(I, TII, MRI, TRI, RBI);
847 
848  return true;
849  }
850 
851  using namespace TargetOpcode;
852 
853  if (selectImpl(I, CoverageInfo))
854  return true;
855 
856  MachineInstrBuilder MIB{MF, I};
857  bool isSExt = false;
858 
859  switch (I.getOpcode()) {
860  case G_SEXT:
861  isSExt = true;
863  case G_ZEXT: {
864  LLT DstTy = MRI.getType(I.getOperand(0).getReg());
865  // FIXME: Smaller destination sizes coming soon!
866  if (DstTy.getSizeInBits() != 32) {
867  LLVM_DEBUG(dbgs() << "Unsupported destination size for extension");
868  return false;
869  }
870 
871  LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
872  unsigned SrcSize = SrcTy.getSizeInBits();
873  switch (SrcSize) {
874  case 1: {
875  // ZExt boils down to & 0x1; for SExt we also subtract that from 0
876  I.setDesc(TII.get(Opcodes.AND));
878 
879  if (isSExt) {
880  unsigned SExtResult = I.getOperand(0).getReg();
881 
882  // Use a new virtual register for the result of the AND
883  unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
884  I.getOperand(0).setReg(AndResult);
885 
886  auto InsertBefore = std::next(I.getIterator());
887  auto SubI =
888  BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB))
889  .addDef(SExtResult)
890  .addUse(AndResult)
891  .addImm(0)
893  .add(condCodeOp());
894  if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
895  return false;
896  }
897  break;
898  }
899  case 8:
900  case 16: {
901  unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
902  if (NewOpc == I.getOpcode())
903  return false;
904  I.setDesc(TII.get(NewOpc));
905  MIB.addImm(0).add(predOps(ARMCC::AL));
906  break;
907  }
908  default:
909  LLVM_DEBUG(dbgs() << "Unsupported source size for extension");
910  return false;
911  }
912  break;
913  }
914  case G_ANYEXT:
915  case G_TRUNC: {
916  // The high bits are undefined, so there's nothing special to do, just
917  // treat it as a copy.
918  auto SrcReg = I.getOperand(1).getReg();
919  auto DstReg = I.getOperand(0).getReg();
920 
921  const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
922  const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
923 
924  if (SrcRegBank.getID() == ARM::FPRRegBankID) {
925  // This should only happen in the obscure case where we have put a 64-bit
926  // integer into a D register. Get it out of there and keep only the
927  // interesting part.
928  assert(I.getOpcode() == G_TRUNC && "Unsupported operand for G_ANYEXT");
929  assert(DstRegBank.getID() == ARM::GPRRegBankID &&
930  "Unsupported combination of register banks");
931  assert(MRI.getType(SrcReg).getSizeInBits() == 64 && "Unsupported size");
932  assert(MRI.getType(DstReg).getSizeInBits() <= 32 && "Unsupported size");
933 
934  unsigned IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
935  auto InsertBefore = std::next(I.getIterator());
936  auto MovI =
937  BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD))
938  .addDef(DstReg)
939  .addDef(IgnoredBits)
940  .addUse(SrcReg)
941  .add(predOps(ARMCC::AL));
942  if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI))
943  return false;
944 
945  MIB->eraseFromParent();
946  return true;
947  }
948 
949  if (SrcRegBank.getID() != DstRegBank.getID()) {
950  LLVM_DEBUG(
951  dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
952  return false;
953  }
954 
955  if (SrcRegBank.getID() != ARM::GPRRegBankID) {
956  LLVM_DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
957  return false;
958  }
959 
960  I.setDesc(TII.get(COPY));
961  return selectCopy(I, TII, MRI, TRI, RBI);
962  }
963  case G_CONSTANT: {
964  if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) {
965  // Non-pointer constants should be handled by TableGen.
966  LLVM_DEBUG(dbgs() << "Unsupported constant type\n");
967  return false;
968  }
969 
970  auto &Val = I.getOperand(1);
971  if (Val.isCImm()) {
972  if (!Val.getCImm()->isZero()) {
973  LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
974  return false;
975  }
976  Val.ChangeToImmediate(0);
977  } else {
978  assert(Val.isImm() && "Unexpected operand for G_CONSTANT");
979  if (Val.getImm() != 0) {
980  LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
981  return false;
982  }
983  }
984 
985  assert(!STI.isThumb() && "Unsupported subtarget");
986  I.setDesc(TII.get(ARM::MOVi));
988  break;
989  }
990  case G_FCONSTANT: {
991  // Load from constant pool
992  unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8;
993  unsigned Alignment = Size;
994 
995  assert((Size == 4 || Size == 8) && "Unsupported FP constant type");
996  auto LoadOpcode = Size == 4 ? ARM::VLDRS : ARM::VLDRD;
997 
998  auto ConstPool = MF.getConstantPool();
999  auto CPIndex =
1000  ConstPool->getConstantPoolIndex(I.getOperand(1).getFPImm(), Alignment);
1001  MIB->setDesc(TII.get(LoadOpcode));
1002  MIB->RemoveOperand(1);
1003  MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
1004  .addMemOperand(
1005  MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
1006  MachineMemOperand::MOLoad, Size, Alignment))
1007  .addImm(0)
1008  .add(predOps(ARMCC::AL));
1009  break;
1010  }
1011  case G_INTTOPTR:
1012  case G_PTRTOINT: {
1013  auto SrcReg = I.getOperand(1).getReg();
1014  auto DstReg = I.getOperand(0).getReg();
1015 
1016  const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
1017  const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1018 
1019  if (SrcRegBank.getID() != DstRegBank.getID()) {
1020  LLVM_DEBUG(
1021  dbgs()
1022  << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
1023  return false;
1024  }
1025 
1026  if (SrcRegBank.getID() != ARM::GPRRegBankID) {
1027  LLVM_DEBUG(
1028  dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
1029  return false;
1030  }
1031 
1032  I.setDesc(TII.get(COPY));
1033  return selectCopy(I, TII, MRI, TRI, RBI);
1034  }
1035  case G_SELECT:
1036  return selectSelect(MIB, MRI);
1037  case G_ICMP: {
1038  CmpConstants Helper(Opcodes.CMPrr, ARM::INSTRUCTION_LIST_END,
1039  Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
1040  return selectCmp(Helper, MIB, MRI);
1041  }
1042  case G_FCMP: {
1043  assert(STI.hasVFP2() && "Can't select fcmp without VFP");
1044 
1045  unsigned OpReg = I.getOperand(2).getReg();
1046  unsigned Size = MRI.getType(OpReg).getSizeInBits();
1047 
1048  if (Size == 64 && STI.isFPOnlySP()) {
1049  LLVM_DEBUG(dbgs() << "Subtarget only supports single precision");
1050  return false;
1051  }
1052  if (Size != 32 && Size != 64) {
1053  LLVM_DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
1054  return false;
1055  }
1056 
1057  CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
1058  Opcodes.MOVCCi, ARM::FPRRegBankID, Size);
1059  return selectCmp(Helper, MIB, MRI);
1060  }
1061  case G_LSHR:
1062  return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
1063  case G_ASHR:
1064  return selectShift(ARM_AM::ShiftOpc::asr, MIB);
1065  case G_SHL: {
1066  return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
1067  }
1068  case G_GEP:
1069  I.setDesc(TII.get(Opcodes.ADDrr));
1070  MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
1071  break;
1072  case G_FRAME_INDEX:
1073  // Add 0 to the given frame index and hope it will eventually be folded into
1074  // the user(s).
1075  I.setDesc(TII.get(Opcodes.ADDri));
1076  MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
1077  break;
1078  case G_GLOBAL_VALUE:
1079  return selectGlobal(MIB, MRI);
1080  case G_STORE:
1081  case G_LOAD: {
1082  const auto &MemOp = **I.memoperands_begin();
1083  if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
1084  LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
1085  return false;
1086  }
1087 
1088  unsigned Reg = I.getOperand(0).getReg();
1089  unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
1090 
1091  LLT ValTy = MRI.getType(Reg);
1092  const auto ValSize = ValTy.getSizeInBits();
1093 
1094  assert((ValSize != 64 || STI.hasVFP2()) &&
1095  "Don't know how to load/store 64-bit value without VFP");
1096 
1097  const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
1098  if (NewOpc == G_LOAD || NewOpc == G_STORE)
1099  return false;
1100 
1101  if (ValSize == 1 && NewOpc == Opcodes.STORE8) {
1102  // Before storing a 1-bit value, make sure to clear out any unneeded bits.
1103  unsigned OriginalValue = I.getOperand(0).getReg();
1104 
1105  unsigned ValueToStore = MRI.createVirtualRegister(&ARM::GPRRegClass);
1106  I.getOperand(0).setReg(ValueToStore);
1107 
1108  auto InsertBefore = I.getIterator();
1109  auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND))
1110  .addDef(ValueToStore)
1111  .addUse(OriginalValue)
1112  .addImm(1)
1113  .add(predOps(ARMCC::AL))
1114  .add(condCodeOp());
1115  if (!constrainSelectedInstRegOperands(*AndI, TII, TRI, RBI))
1116  return false;
1117  }
1118 
1119  I.setDesc(TII.get(NewOpc));
1120 
1121  if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
1122  // LDRH has a funny addressing mode (there's already a FIXME for it).
1123  MIB.addReg(0);
1124  MIB.addImm(0).add(predOps(ARMCC::AL));
1125  break;
1126  }
1127  case G_MERGE_VALUES: {
1128  if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
1129  return false;
1130  break;
1131  }
1132  case G_UNMERGE_VALUES: {
1133  if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
1134  return false;
1135  break;
1136  }
1137  case G_BRCOND: {
1138  if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
1139  LLVM_DEBUG(dbgs() << "Unsupported condition register for G_BRCOND");
1140  return false;
1141  }
1142 
1143  // Set the flags.
1144  auto Test =
1145  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
1146  .addReg(I.getOperand(0).getReg())
1147  .addImm(1)
1148  .add(predOps(ARMCC::AL));
1149  if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
1150  return false;
1151 
1152  // Branch conditionally.
1153  auto Branch =
1154  BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
1155  .add(I.getOperand(1))
1156  .add(predOps(ARMCC::NE, ARM::CPSR));
1157  if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
1158  return false;
1159  I.eraseFromParent();
1160  return true;
1161  }
1162  case G_PHI: {
1163  I.setDesc(TII.get(PHI));
1164 
1165  unsigned DstReg = I.getOperand(0).getReg();
1166  const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
1167  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1168  break;
1169  }
1170 
1171  return true;
1172  }
1173  default:
1174  return false;
1175  }
1176 
1177  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1178 }
bool useMovt() const
const MachineInstrBuilder & add(const MachineOperand &MO) const
static bool selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
bool isThumb() const
Definition: ARMSubtarget.h:717
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const unsigned zero_reg
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
unsigned getReg() const
getReg - Returns the register number.
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:500
unsigned Reg
static uint64_t selectImpl(uint64_t CandidateMask, uint64_t &NextInSequenceMask)
#define DEBUG_TYPE
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
#define GET_GLOBALISEL_PREDICATES_INIT
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
static bool isThumb(const MCSubtargetInfo &STI)
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
bool isFPOnlySP() const
Definition: ARMSubtarget.h:604
bool isTargetELF() const
Definition: ARMSubtarget.h:662
Holds all the information related to register banks.
Definition: BitVector.h:937
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
Definition: ARMBaseInfo.h:260
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
static StringRef getName(Value *V)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool hasVFP2() const
Definition: ARMSubtarget.h:572
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
static bool isStore(int Opcode)
This class provides the information for the target register banks.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:652
const ARMSubtarget & getSubtarget() const
#define EQ(a, b)
Definition: regexec.c:112
bool isReadOnly(const GlobalValue *GV) const
static std::pair< ARMCC::CondCodes, ARMCC::CondCodes > getComparePreds(CmpInst::Predicate Pred)
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
static int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
This file declares the targeting of the RegisterBankInfo class for ARM.
This is an important base class in LLVM.
Definition: Constant.h:41
#define STORE_OPCODE(VAR, OPC)
const GlobalValue * getGlobal() const
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
static bool selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
self_iterator getIterator()
Definition: ilist_node.h:81
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:50
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode, unsigned OpRegBank, unsigned OpSize)
const APFloat & getValueAPF() const
Definition: Constants.h:302
static int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:87
This class implements the register bank concept.
Definition: RegisterBank.h:28
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isROPI() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Section Relative (Windows TLS)
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
#define GET_GLOBALISEL_TEMPORARIES_INIT
uint32_t Size
Definition: Profile.cpp:46
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isTargetMachO() const
Definition: ARMSubtarget.h:663
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
static const Function * getParent(const Value *V)
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:278
bool isRWPI() const
const MachineBasicBlock::instr_iterator InsertBefore
unsigned getReg(unsigned Idx)
Get the register for the operand index.
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
unsigned getPredicate() const