LLVM  8.0.0svn
ARMInstructionSelector.cpp
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1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetMachine.h"
21 #include "llvm/Support/Debug.h"
22 
23 #define DEBUG_TYPE "arm-isel"
24 
25 using namespace llvm;
26 
27 namespace {
28 
29 #define GET_GLOBALISEL_PREDICATE_BITSET
30 #include "ARMGenGlobalISel.inc"
31 #undef GET_GLOBALISEL_PREDICATE_BITSET
32 
33 class ARMInstructionSelector : public InstructionSelector {
34 public:
35  ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
36  const ARMRegisterBankInfo &RBI);
37 
38  bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
39  static const char *getName() { return DEBUG_TYPE; }
40 
41 private:
42  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
43 
44  struct CmpConstants;
45  struct InsertInfo;
46 
47  bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
48  MachineRegisterInfo &MRI) const;
49 
50  // Helper for inserting a comparison sequence that sets \p ResReg to either 1
51  // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
52  // \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
53  bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
54  ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
55  unsigned PrevRes) const;
56 
57  // Set \p DestReg to \p Constant.
58  void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
59 
60  bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61  bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62  bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
63 
64  // Check if the types match and both operands have the expected size and
65  // register bank.
66  bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
67  unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
68 
69  // Check if the register has the expected size and register bank.
70  bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
71  unsigned ExpectedRegBankID) const;
72 
73  const ARMBaseInstrInfo &TII;
74  const ARMBaseRegisterInfo &TRI;
75  const ARMBaseTargetMachine &TM;
76  const ARMRegisterBankInfo &RBI;
77  const ARMSubtarget &STI;
78 
79 #define GET_GLOBALISEL_PREDICATES_DECL
80 #include "ARMGenGlobalISel.inc"
81 #undef GET_GLOBALISEL_PREDICATES_DECL
82 
83 // We declare the temporaries used by selectImpl() in the class to minimize the
84 // cost of constructing placeholder values.
85 #define GET_GLOBALISEL_TEMPORARIES_DECL
86 #include "ARMGenGlobalISel.inc"
87 #undef GET_GLOBALISEL_TEMPORARIES_DECL
88 };
89 } // end anonymous namespace
90 
91 namespace llvm {
94  const ARMSubtarget &STI,
95  const ARMRegisterBankInfo &RBI) {
96  return new ARMInstructionSelector(TM, STI, RBI);
97 }
98 }
99 
100 const unsigned zero_reg = 0;
101 
102 #define GET_GLOBALISEL_IMPL
103 #include "ARMGenGlobalISel.inc"
104 #undef GET_GLOBALISEL_IMPL
105 
106 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
107  const ARMSubtarget &STI,
108  const ARMRegisterBankInfo &RBI)
109  : InstructionSelector(), TII(*STI.getInstrInfo()),
110  TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
112 #include "ARMGenGlobalISel.inc"
115 #include "ARMGenGlobalISel.inc"
117 {
118 }
119 
120 static const TargetRegisterClass *guessRegClass(unsigned Reg,
122  const TargetRegisterInfo &TRI,
123  const RegisterBankInfo &RBI) {
124  const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
125  assert(RegBank && "Can't get reg bank for virtual register");
126 
127  const unsigned Size = MRI.getType(Reg).getSizeInBits();
128  assert((RegBank->getID() == ARM::GPRRegBankID ||
129  RegBank->getID() == ARM::FPRRegBankID) &&
130  "Unsupported reg bank");
131 
132  if (RegBank->getID() == ARM::FPRRegBankID) {
133  if (Size == 32)
134  return &ARM::SPRRegClass;
135  else if (Size == 64)
136  return &ARM::DPRRegClass;
137  else if (Size == 128)
138  return &ARM::QPRRegClass;
139  else
140  llvm_unreachable("Unsupported destination size");
141  }
142 
143  return &ARM::GPRRegClass;
144 }
145 
147  MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
148  const RegisterBankInfo &RBI) {
149  unsigned DstReg = I.getOperand(0).getReg();
150  if (TargetRegisterInfo::isPhysicalRegister(DstReg))
151  return true;
152 
153  const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
154 
155  // No need to constrain SrcReg. It will get constrained when
156  // we hit another of its uses or its defs.
157  // Copies do not have constraints.
158  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
159  LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
160  << " operand\n");
161  return false;
162  }
163  return true;
164 }
165 
167  const ARMBaseInstrInfo &TII,
168  MachineRegisterInfo &MRI,
169  const TargetRegisterInfo &TRI,
170  const RegisterBankInfo &RBI) {
171  assert(TII.getSubtarget().hasVFP2() && "Can't select merge without VFP");
172 
173  // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
174  // into one DPR.
175  unsigned VReg0 = MIB->getOperand(0).getReg();
176  (void)VReg0;
177  assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
178  RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
179  "Unsupported operand for G_MERGE_VALUES");
180  unsigned VReg1 = MIB->getOperand(1).getReg();
181  (void)VReg1;
182  assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
183  RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
184  "Unsupported operand for G_MERGE_VALUES");
185  unsigned VReg2 = MIB->getOperand(2).getReg();
186  (void)VReg2;
187  assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
188  RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
189  "Unsupported operand for G_MERGE_VALUES");
190 
191  MIB->setDesc(TII.get(ARM::VMOVDRR));
192  MIB.add(predOps(ARMCC::AL));
193 
194  return true;
195 }
196 
198  const ARMBaseInstrInfo &TII,
199  MachineRegisterInfo &MRI,
200  const TargetRegisterInfo &TRI,
201  const RegisterBankInfo &RBI) {
202  assert(TII.getSubtarget().hasVFP2() && "Can't select unmerge without VFP");
203 
204  // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
205  // GPRs.
206  unsigned VReg0 = MIB->getOperand(0).getReg();
207  (void)VReg0;
208  assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
209  RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
210  "Unsupported operand for G_UNMERGE_VALUES");
211  unsigned VReg1 = MIB->getOperand(1).getReg();
212  (void)VReg1;
213  assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
214  RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
215  "Unsupported operand for G_UNMERGE_VALUES");
216  unsigned VReg2 = MIB->getOperand(2).getReg();
217  (void)VReg2;
218  assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
219  RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
220  "Unsupported operand for G_UNMERGE_VALUES");
221 
222  MIB->setDesc(TII.get(ARM::VMOVRRD));
223  MIB.add(predOps(ARMCC::AL));
224 
225  return true;
226 }
227 
228 /// Select the opcode for simple extensions (that translate to a single SXT/UXT
229 /// instruction). Extension operations more complicated than that should not
230 /// invoke this. Returns the original opcode if it doesn't know how to select a
231 /// better one.
232 static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size, bool isThumb) {
233  using namespace TargetOpcode;
234 
235  if (Size != 8 && Size != 16)
236  return Opc;
237 
238  if (Opc == G_SEXT)
239  return isThumb ? Size == 8 ? ARM::t2SXTB : ARM::t2SXTH
240  : Size == 8 ? ARM::SXTB : ARM::SXTH;
241 
242  if (Opc == G_ZEXT)
243  return isThumb ? Size == 8 ? ARM::t2UXTB : ARM::t2UXTH
244  : Size == 8 ? ARM::UXTB : ARM::UXTH;
245 
246  return Opc;
247 }
248 
249 /// Select the opcode for simple loads and stores. For types smaller than 32
250 /// bits, the value will be zero extended. Returns the original opcode if it
251 /// doesn't know how to select a better one.
252 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
253  unsigned Size, bool isThumb) {
254  bool isStore = Opc == TargetOpcode::G_STORE;
255 
256  if (RegBank == ARM::GPRRegBankID) {
257  if (isThumb)
258  switch (Size) {
259  case 1:
260  case 8:
261  return isStore ? ARM::t2STRBi12 : ARM::t2LDRBi12;
262  case 16:
263  return isStore ? ARM::t2STRHi12 : ARM::t2LDRHi12;
264  case 32:
265  return isStore ? ARM::t2STRi12 : ARM::t2LDRi12;
266  default:
267  return Opc;
268  }
269 
270  switch (Size) {
271  case 1:
272  case 8:
273  return isStore ? ARM::STRBi12 : ARM::LDRBi12;
274  case 16:
275  return isStore ? ARM::STRH : ARM::LDRH;
276  case 32:
277  return isStore ? ARM::STRi12 : ARM::LDRi12;
278  default:
279  return Opc;
280  }
281  }
282 
283  if (RegBank == ARM::FPRRegBankID) {
284  switch (Size) {
285  case 32:
286  return isStore ? ARM::VSTRS : ARM::VLDRS;
287  case 64:
288  return isStore ? ARM::VSTRD : ARM::VLDRD;
289  default:
290  return Opc;
291  }
292  }
293 
294  return Opc;
295 }
296 
297 // When lowering comparisons, we sometimes need to perform two compares instead
298 // of just one. Get the condition codes for both comparisons. If only one is
299 // needed, the second member of the pair is ARMCC::AL.
300 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
302  std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
303  switch (Pred) {
304  case CmpInst::FCMP_ONE:
305  Preds = {ARMCC::GT, ARMCC::MI};
306  break;
307  case CmpInst::FCMP_UEQ:
308  Preds = {ARMCC::EQ, ARMCC::VS};
309  break;
310  case CmpInst::ICMP_EQ:
311  case CmpInst::FCMP_OEQ:
312  Preds.first = ARMCC::EQ;
313  break;
314  case CmpInst::ICMP_SGT:
315  case CmpInst::FCMP_OGT:
316  Preds.first = ARMCC::GT;
317  break;
318  case CmpInst::ICMP_SGE:
319  case CmpInst::FCMP_OGE:
320  Preds.first = ARMCC::GE;
321  break;
322  case CmpInst::ICMP_UGT:
323  case CmpInst::FCMP_UGT:
324  Preds.first = ARMCC::HI;
325  break;
326  case CmpInst::FCMP_OLT:
327  Preds.first = ARMCC::MI;
328  break;
329  case CmpInst::ICMP_ULE:
330  case CmpInst::FCMP_OLE:
331  Preds.first = ARMCC::LS;
332  break;
333  case CmpInst::FCMP_ORD:
334  Preds.first = ARMCC::VC;
335  break;
336  case CmpInst::FCMP_UNO:
337  Preds.first = ARMCC::VS;
338  break;
339  case CmpInst::FCMP_UGE:
340  Preds.first = ARMCC::PL;
341  break;
342  case CmpInst::ICMP_SLT:
343  case CmpInst::FCMP_ULT:
344  Preds.first = ARMCC::LT;
345  break;
346  case CmpInst::ICMP_SLE:
347  case CmpInst::FCMP_ULE:
348  Preds.first = ARMCC::LE;
349  break;
350  case CmpInst::FCMP_UNE:
351  case CmpInst::ICMP_NE:
352  Preds.first = ARMCC::NE;
353  break;
354  case CmpInst::ICMP_UGE:
355  Preds.first = ARMCC::HS;
356  break;
357  case CmpInst::ICMP_ULT:
358  Preds.first = ARMCC::LO;
359  break;
360  default:
361  break;
362  }
363  assert(Preds.first != ARMCC::AL && "No comparisons needed?");
364  return Preds;
365 }
366 
368  CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank,
369  unsigned OpSize)
370  : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
371  OperandRegBankID(OpRegBank), OperandSize(OpSize) {}
372 
373  // The opcode used for performing the comparison.
374  const unsigned ComparisonOpcode;
375 
376  // The opcode used for reading the flags set by the comparison. May be
377  // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
378  const unsigned ReadFlagsOpcode;
379 
380  // The assumed register bank ID for the operands.
381  const unsigned OperandRegBankID;
382 
383  // The assumed size in bits for the operands.
384  const unsigned OperandSize;
385 };
386 
389  : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
390  DbgLoc(MIB->getDebugLoc()) {}
391 
394  const DebugLoc &DbgLoc;
395 };
396 
397 void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
398  unsigned Constant) const {
399  (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVi))
400  .addDef(DestReg)
401  .addImm(Constant)
403  .add(condCodeOp());
404 }
405 
406 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
407  unsigned LHSReg, unsigned RHSReg,
408  unsigned ExpectedSize,
409  unsigned ExpectedRegBankID) const {
410  return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
411  validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
412  validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
413 }
414 
415 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
416  unsigned ExpectedSize,
417  unsigned ExpectedRegBankID) const {
418  if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
419  LLVM_DEBUG(dbgs() << "Unexpected size for register");
420  return false;
421  }
422 
423  if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
424  LLVM_DEBUG(dbgs() << "Unexpected register bank for register");
425  return false;
426  }
427 
428  return true;
429 }
430 
431 bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
432  MachineInstrBuilder &MIB,
433  MachineRegisterInfo &MRI) const {
434  const InsertInfo I(MIB);
435 
436  auto ResReg = MIB->getOperand(0).getReg();
437  if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
438  return false;
439 
440  auto Cond =
441  static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
442  if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
443  putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
444  MIB->eraseFromParent();
445  return true;
446  }
447 
448  auto LHSReg = MIB->getOperand(2).getReg();
449  auto RHSReg = MIB->getOperand(3).getReg();
450  if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
451  Helper.OperandRegBankID))
452  return false;
453 
454  auto ARMConds = getComparePreds(Cond);
455  auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
456  putConstant(I, ZeroReg, 0);
457 
458  if (ARMConds.second == ARMCC::AL) {
459  // Simple case, we only need one comparison and we're done.
460  if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
461  ZeroReg))
462  return false;
463  } else {
464  // Not so simple, we need two successive comparisons.
465  auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
466  if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
467  RHSReg, ZeroReg))
468  return false;
469  if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
470  IntermediateRes))
471  return false;
472  }
473 
474  MIB->eraseFromParent();
475  return true;
476 }
477 
478 bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
479  unsigned ResReg,
480  ARMCC::CondCodes Cond,
481  unsigned LHSReg, unsigned RHSReg,
482  unsigned PrevRes) const {
483  // Perform the comparison.
484  auto CmpI =
485  BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
486  .addUse(LHSReg)
487  .addUse(RHSReg)
488  .add(predOps(ARMCC::AL));
489  if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
490  return false;
491 
492  // Read the comparison flags (if necessary).
493  if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
494  auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
495  TII.get(Helper.ReadFlagsOpcode))
496  .add(predOps(ARMCC::AL));
497  if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
498  return false;
499  }
500 
501  // Select either 1 or the previous result based on the value of the flags.
502  auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVCCi))
503  .addDef(ResReg)
504  .addUse(PrevRes)
505  .addImm(1)
506  .add(predOps(Cond, ARM::CPSR));
507  if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
508  return false;
509 
510  return true;
511 }
512 
513 bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
514  MachineRegisterInfo &MRI) const {
515  if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) {
516  LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n");
517  return false;
518  }
519 
520  auto GV = MIB->getOperand(1).getGlobal();
521  if (GV->isThreadLocal()) {
522  LLVM_DEBUG(dbgs() << "TLS variables not supported yet\n");
523  return false;
524  }
525 
526  auto &MBB = *MIB->getParent();
527  auto &MF = *MBB.getParent();
528 
529  bool UseMovt = STI.useMovt(MF);
530 
531  unsigned Size = TM.getPointerSize(0);
532  unsigned Alignment = 4;
533 
534  auto addOpsForConstantPoolLoad = [&MF, Alignment,
536  const GlobalValue *GV, bool IsSBREL) {
537  assert(MIB->getOpcode() == ARM::LDRi12 && "Unsupported instruction");
538  auto ConstPool = MF.getConstantPool();
539  auto CPIndex =
540  // For SB relative entries we need a target-specific constant pool.
541  // Otherwise, just use a regular constant pool entry.
542  IsSBREL
543  ? ConstPool->getConstantPoolIndex(
544  ARMConstantPoolConstant::Create(GV, ARMCP::SBREL), Alignment)
545  : ConstPool->getConstantPoolIndex(GV, Alignment);
546  MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
547  .addMemOperand(
548  MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
549  MachineMemOperand::MOLoad, Size, Alignment))
550  .addImm(0)
551  .add(predOps(ARMCC::AL));
552  };
553 
554  if (TM.isPositionIndependent()) {
555  bool Indirect = STI.isGVIndirectSymbol(GV);
556  // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
557  // support it yet. See PR28229.
558  unsigned Opc =
559  UseMovt && !STI.isTargetELF()
560  ? (Indirect ? ARM::MOV_ga_pcrel_ldr : ARM::MOV_ga_pcrel)
561  : (Indirect ? ARM::LDRLIT_ga_pcrel_ldr : ARM::LDRLIT_ga_pcrel);
562  MIB->setDesc(TII.get(Opc));
563 
565  if (STI.isTargetDarwin())
566  TargetFlags |= ARMII::MO_NONLAZY;
567  if (STI.isGVInGOT(GV))
568  TargetFlags |= ARMII::MO_GOT;
569  MIB->getOperand(1).setTargetFlags(TargetFlags);
570 
571  if (Indirect)
572  MIB.addMemOperand(MF.getMachineMemOperand(
573  MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad,
574  TM.getProgramPointerSize(), Alignment));
575 
576  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
577  }
578 
579  bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV);
580  if (STI.isROPI() && isReadOnly) {
581  unsigned Opc = UseMovt ? ARM::MOV_ga_pcrel : ARM::LDRLIT_ga_pcrel;
582  MIB->setDesc(TII.get(Opc));
583  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
584  }
585  if (STI.isRWPI() && !isReadOnly) {
586  auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
587  MachineInstrBuilder OffsetMIB;
588  if (UseMovt) {
589  OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
590  TII.get(ARM::MOVi32imm), Offset);
591  OffsetMIB.addGlobalAddress(GV, /*Offset*/ 0, ARMII::MO_SBREL);
592  } else {
593  // Load the offset from the constant pool.
594  OffsetMIB =
595  BuildMI(MBB, *MIB, MIB->getDebugLoc(), TII.get(ARM::LDRi12), Offset);
596  addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true);
597  }
598  if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
599  return false;
600 
601  // Add the offset to the SB register.
602  MIB->setDesc(TII.get(ARM::ADDrr));
603  MIB->RemoveOperand(1);
604  MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
605  .addReg(Offset)
606  .add(predOps(ARMCC::AL))
607  .add(condCodeOp());
608 
609  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
610  }
611 
612  if (STI.isTargetELF()) {
613  if (UseMovt) {
614  MIB->setDesc(TII.get(ARM::MOVi32imm));
615  } else {
616  // Load the global's address from the constant pool.
617  MIB->setDesc(TII.get(ARM::LDRi12));
618  MIB->RemoveOperand(1);
619  addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
620  }
621  } else if (STI.isTargetMachO()) {
622  if (UseMovt)
623  MIB->setDesc(TII.get(ARM::MOVi32imm));
624  else
625  MIB->setDesc(TII.get(ARM::LDRLIT_ga_abs));
626  } else {
627  LLVM_DEBUG(dbgs() << "Object format not supported yet\n");
628  return false;
629  }
630 
631  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
632 }
633 
634 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
635  MachineRegisterInfo &MRI) const {
636  auto &MBB = *MIB->getParent();
637  auto InsertBefore = std::next(MIB->getIterator());
638  auto &DbgLoc = MIB->getDebugLoc();
639 
640  // Compare the condition to 0.
641  auto CondReg = MIB->getOperand(1).getReg();
642  assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
643  "Unsupported types for select operation");
644  auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::CMPri))
645  .addUse(CondReg)
646  .addImm(0)
647  .add(predOps(ARMCC::AL));
648  if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
649  return false;
650 
651  // Move a value into the result register based on the result of the
652  // comparison.
653  auto ResReg = MIB->getOperand(0).getReg();
654  auto TrueReg = MIB->getOperand(2).getReg();
655  auto FalseReg = MIB->getOperand(3).getReg();
656  assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
657  validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
658  "Unsupported types for select operation");
659  auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVCCr))
660  .addDef(ResReg)
661  .addUse(TrueReg)
662  .addUse(FalseReg)
663  .add(predOps(ARMCC::EQ, ARM::CPSR));
664  if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
665  return false;
666 
667  MIB->eraseFromParent();
668  return true;
669 }
670 
671 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
672  MachineInstrBuilder &MIB) const {
673  MIB->setDesc(TII.get(ARM::MOVsr));
674  MIB.addImm(ShiftOpc);
676  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
677 }
678 
679 bool ARMInstructionSelector::select(MachineInstr &I,
680  CodeGenCoverage &CoverageInfo) const {
681  assert(I.getParent() && "Instruction should be in a basic block!");
682  assert(I.getParent()->getParent() && "Instruction should be in a function!");
683 
684  auto &MBB = *I.getParent();
685  auto &MF = *MBB.getParent();
686  auto &MRI = MF.getRegInfo();
687 
688  if (!isPreISelGenericOpcode(I.getOpcode())) {
689  if (I.isCopy())
690  return selectCopy(I, TII, MRI, TRI, RBI);
691 
692  return true;
693  }
694 
695  using namespace TargetOpcode;
696 
697  if (selectImpl(I, CoverageInfo))
698  return true;
699 
700  MachineInstrBuilder MIB{MF, I};
701  bool isSExt = false;
702 
703  switch (I.getOpcode()) {
704  case G_SEXT:
705  isSExt = true;
707  case G_ZEXT: {
708  LLT DstTy = MRI.getType(I.getOperand(0).getReg());
709  // FIXME: Smaller destination sizes coming soon!
710  if (DstTy.getSizeInBits() != 32) {
711  LLVM_DEBUG(dbgs() << "Unsupported destination size for extension");
712  return false;
713  }
714 
715  LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
716  unsigned SrcSize = SrcTy.getSizeInBits();
717  switch (SrcSize) {
718  case 1: {
719  // ZExt boils down to & 0x1; for SExt we also subtract that from 0
720  I.setDesc(TII.get(STI.isThumb() ? ARM::t2ANDri : ARM::ANDri));
722 
723  if (isSExt) {
724  unsigned SExtResult = I.getOperand(0).getReg();
725 
726  // Use a new virtual register for the result of the AND
727  unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
728  I.getOperand(0).setReg(AndResult);
729 
730  auto InsertBefore = std::next(I.getIterator());
731  auto SubI = BuildMI(MBB, InsertBefore, I.getDebugLoc(),
732  TII.get(STI.isThumb() ? ARM::t2RSBri : ARM::RSBri))
733  .addDef(SExtResult)
734  .addUse(AndResult)
735  .addImm(0)
737  .add(condCodeOp());
738  if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
739  return false;
740  }
741  break;
742  }
743  case 8:
744  case 16: {
745  unsigned NewOpc =
746  selectSimpleExtOpc(I.getOpcode(), SrcSize, STI.isThumb());
747  if (NewOpc == I.getOpcode())
748  return false;
749  I.setDesc(TII.get(NewOpc));
750  MIB.addImm(0).add(predOps(ARMCC::AL));
751  break;
752  }
753  default:
754  LLVM_DEBUG(dbgs() << "Unsupported source size for extension");
755  return false;
756  }
757  break;
758  }
759  case G_ANYEXT:
760  case G_TRUNC: {
761  // The high bits are undefined, so there's nothing special to do, just
762  // treat it as a copy.
763  auto SrcReg = I.getOperand(1).getReg();
764  auto DstReg = I.getOperand(0).getReg();
765 
766  const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
767  const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
768 
769  if (SrcRegBank.getID() == ARM::FPRRegBankID) {
770  // This should only happen in the obscure case where we have put a 64-bit
771  // integer into a D register. Get it out of there and keep only the
772  // interesting part.
773  assert(I.getOpcode() == G_TRUNC && "Unsupported operand for G_ANYEXT");
774  assert(DstRegBank.getID() == ARM::GPRRegBankID &&
775  "Unsupported combination of register banks");
776  assert(MRI.getType(SrcReg).getSizeInBits() == 64 && "Unsupported size");
777  assert(MRI.getType(DstReg).getSizeInBits() <= 32 && "Unsupported size");
778 
779  unsigned IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
780  auto InsertBefore = std::next(I.getIterator());
781  auto MovI =
782  BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD))
783  .addDef(DstReg)
784  .addDef(IgnoredBits)
785  .addUse(SrcReg)
786  .add(predOps(ARMCC::AL));
787  if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI))
788  return false;
789 
790  MIB->eraseFromParent();
791  return true;
792  }
793 
794  if (SrcRegBank.getID() != DstRegBank.getID()) {
795  LLVM_DEBUG(
796  dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
797  return false;
798  }
799 
800  if (SrcRegBank.getID() != ARM::GPRRegBankID) {
801  LLVM_DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
802  return false;
803  }
804 
805  I.setDesc(TII.get(COPY));
806  return selectCopy(I, TII, MRI, TRI, RBI);
807  }
808  case G_CONSTANT: {
809  if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) {
810  // Non-pointer constants should be handled by TableGen.
811  LLVM_DEBUG(dbgs() << "Unsupported constant type\n");
812  return false;
813  }
814 
815  auto &Val = I.getOperand(1);
816  if (Val.isCImm()) {
817  if (!Val.getCImm()->isZero()) {
818  LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
819  return false;
820  }
821  Val.ChangeToImmediate(0);
822  } else {
823  assert(Val.isImm() && "Unexpected operand for G_CONSTANT");
824  if (Val.getImm() != 0) {
825  LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n");
826  return false;
827  }
828  }
829 
830  I.setDesc(TII.get(ARM::MOVi));
832  break;
833  }
834  case G_INTTOPTR:
835  case G_PTRTOINT: {
836  auto SrcReg = I.getOperand(1).getReg();
837  auto DstReg = I.getOperand(0).getReg();
838 
839  const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
840  const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
841 
842  if (SrcRegBank.getID() != DstRegBank.getID()) {
843  LLVM_DEBUG(
844  dbgs()
845  << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
846  return false;
847  }
848 
849  if (SrcRegBank.getID() != ARM::GPRRegBankID) {
850  LLVM_DEBUG(
851  dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
852  return false;
853  }
854 
855  I.setDesc(TII.get(COPY));
856  return selectCopy(I, TII, MRI, TRI, RBI);
857  }
858  case G_SELECT:
859  return selectSelect(MIB, MRI);
860  case G_ICMP: {
861  CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END,
862  ARM::GPRRegBankID, 32);
863  return selectCmp(Helper, MIB, MRI);
864  }
865  case G_FCMP: {
866  assert(STI.hasVFP2() && "Can't select fcmp without VFP");
867 
868  unsigned OpReg = I.getOperand(2).getReg();
869  unsigned Size = MRI.getType(OpReg).getSizeInBits();
870 
871  if (Size == 64 && STI.isFPOnlySP()) {
872  LLVM_DEBUG(dbgs() << "Subtarget only supports single precision");
873  return false;
874  }
875  if (Size != 32 && Size != 64) {
876  LLVM_DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
877  return false;
878  }
879 
880  CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
881  ARM::FPRRegBankID, Size);
882  return selectCmp(Helper, MIB, MRI);
883  }
884  case G_LSHR:
885  return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
886  case G_ASHR:
887  return selectShift(ARM_AM::ShiftOpc::asr, MIB);
888  case G_SHL: {
889  return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
890  }
891  case G_GEP:
892  I.setDesc(TII.get(ARM::ADDrr));
894  break;
895  case G_FRAME_INDEX:
896  // Add 0 to the given frame index and hope it will eventually be folded into
897  // the user(s).
898  I.setDesc(TII.get(ARM::ADDri));
900  break;
901  case G_GLOBAL_VALUE:
902  return selectGlobal(MIB, MRI);
903  case G_STORE:
904  case G_LOAD: {
905  const auto &MemOp = **I.memoperands_begin();
906  if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
907  LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
908  return false;
909  }
910 
911  unsigned Reg = I.getOperand(0).getReg();
912  unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
913 
914  LLT ValTy = MRI.getType(Reg);
915  const auto ValSize = ValTy.getSizeInBits();
916 
917  assert((ValSize != 64 || STI.hasVFP2()) &&
918  "Don't know how to load/store 64-bit value without VFP");
919 
920  const auto NewOpc =
921  selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize, STI.isThumb());
922  if (NewOpc == G_LOAD || NewOpc == G_STORE)
923  return false;
924 
925  I.setDesc(TII.get(NewOpc));
926 
927  if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
928  // LDRH has a funny addressing mode (there's already a FIXME for it).
929  MIB.addReg(0);
930  MIB.addImm(0).add(predOps(ARMCC::AL));
931  break;
932  }
933  case G_MERGE_VALUES: {
934  if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
935  return false;
936  break;
937  }
938  case G_UNMERGE_VALUES: {
939  if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
940  return false;
941  break;
942  }
943  case G_BRCOND: {
944  if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
945  LLVM_DEBUG(dbgs() << "Unsupported condition register for G_BRCOND");
946  return false;
947  }
948 
949  // Set the flags.
950  auto Test = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::TSTri))
951  .addReg(I.getOperand(0).getReg())
952  .addImm(1)
953  .add(predOps(ARMCC::AL));
954  if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
955  return false;
956 
957  // Branch conditionally.
958  auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::Bcc))
959  .add(I.getOperand(1))
960  .add(predOps(ARMCC::NE, ARM::CPSR));
961  if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
962  return false;
963  I.eraseFromParent();
964  return true;
965  }
966  case G_PHI: {
967  I.setDesc(TII.get(PHI));
968 
969  unsigned DstReg = I.getOperand(0).getReg();
970  const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
971  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
972  break;
973  }
974 
975  return true;
976  }
977  default:
978  return false;
979  }
980 
981  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
982 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
static bool selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
const unsigned zero_reg
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank, unsigned Size, bool isThumb)
Select the opcode for simple loads and stores.
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
#define DEBUG_TYPE
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
#define GET_GLOBALISEL_PREDICATES_INIT
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
static bool isThumb(const MCSubtargetInfo &STI)
Holds all the information related to register banks.
Definition: BitVector.h:938
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
Definition: ARMBaseInfo.h:261
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank, unsigned OpSize)
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
static StringRef getName(Value *V)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
bool hasVFP2() const
Definition: ARMSubtarget.h:567
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
static bool isStore(int Opcode)
This class provides the information for the target register banks.
const ARMSubtarget & getSubtarget() const
#define EQ(a, b)
Definition: regexec.c:112
static std::pair< ARMCC::CondCodes, ARMCC::CondCodes > getComparePreds(CmpInst::Predicate Pred)
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
This file declares the targeting of the RegisterBankInfo class for ARM.
This is an important base class in LLVM.
Definition: Constant.h:42
const GlobalValue * getGlobal() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:642
static bool selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
self_iterator getIterator()
Definition: ilist_node.h:82
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:88
This class implements the register bank concept.
Definition: RegisterBank.h:29
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Section Relative (Windows TLS)
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
#define GET_GLOBALISEL_TEMPORARIES_INIT
uint32_t Size
Definition: Profile.cpp:47
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
static const Function * getParent(const Value *V)
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:279
const MachineBasicBlock::instr_iterator InsertBefore
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size, bool isThumb)
Select the opcode for simple extensions (that translate to a single SXT/UXT instruction).
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
unsigned getPredicate() const