LLVM  9.0.0svn
ARMLegalizerInfo.cpp
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1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMLegalizerInfo.h"
14 #include "ARMCallLowering.h"
15 #include "ARMSubtarget.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Type.h"
23 
24 using namespace llvm;
25 using namespace LegalizeActions;
26 
27 /// FIXME: The following static functions are SizeChangeStrategy functions
28 /// that are meant to temporarily mimic the behaviour of the old legalization
29 /// based on doubling/halving non-legal types as closely as possible. This is
30 /// not entirly possible as only legalizing the types that are exactly a power
31 /// of 2 times the size of the legal types would require specifying all those
32 /// sizes explicitly.
33 /// In practice, not specifying those isn't a problem, and the below functions
34 /// should disappear quickly as we add support for legalizing non-power-of-2
35 /// sized types further.
36 static void
39  for (unsigned i = 0; i < v.size(); ++i) {
40  result.push_back(v[i]);
41  if (i + 1 < v[i].first && i + 1 < v.size() &&
42  v[i + 1].first != v[i].first + 1)
43  result.push_back({v[i].first + 1, Unsupported});
44  }
45 }
46 
49  assert(v.size() >= 1);
50  assert(v[0].first > 17);
52  {8, WidenScalar},
53  {9, Unsupported},
54  {16, WidenScalar},
55  {17, Unsupported}};
57  auto Largest = result.back().first;
58  result.push_back({Largest + 1, Unsupported});
59  return result;
60 }
61 
62 static bool AEABI(const ARMSubtarget &ST) {
63  return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
64 }
65 
67  using namespace TargetOpcode;
68 
69  const LLT p0 = LLT::pointer(0, 32);
70 
71  const LLT s1 = LLT::scalar(1);
72  const LLT s8 = LLT::scalar(8);
73  const LLT s16 = LLT::scalar(16);
74  const LLT s32 = LLT::scalar(32);
75  const LLT s64 = LLT::scalar(64);
76 
77  if (ST.isThumb1Only()) {
78  // Thumb1 is not supported yet.
79  computeTables();
80  verify(*ST.getInstrInfo());
81  return;
82  }
83 
84  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
85  .legalForCartesianProduct({s32}, {s1, s8, s16});
86 
87  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
88  .legalFor({s32})
89  .minScalar(0, s32);
90 
91  getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
92  .legalFor({{s32, s32}})
93  .clampScalar(1, s32, s32);
94 
95  bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
96  (ST.isThumb() && ST.hasDivideInThumbMode());
97  if (HasHWDivide)
98  getActionDefinitionsBuilder({G_SDIV, G_UDIV})
99  .legalFor({s32})
100  .clampScalar(0, s32, s32);
101  else
102  getActionDefinitionsBuilder({G_SDIV, G_UDIV})
103  .libcallFor({s32})
104  .clampScalar(0, s32, s32);
105 
106  for (unsigned Op : {G_SREM, G_UREM}) {
107  setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
108  if (HasHWDivide)
109  setAction({Op, s32}, Lower);
110  else if (AEABI(ST))
111  setAction({Op, s32}, Custom);
112  else
113  setAction({Op, s32}, Libcall);
114  }
115 
116  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
117  getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
118 
119  getActionDefinitionsBuilder(G_CONSTANT)
120  .legalFor({s32, p0})
121  .clampScalar(0, s32, s32);
122 
123  getActionDefinitionsBuilder(G_ICMP)
124  .legalForCartesianProduct({s1}, {s32, p0})
125  .minScalar(1, s32);
126 
127  getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
128  {s1});
129 
130  // We're keeping these builders around because we'll want to add support for
131  // floating point to them.
132  auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE})
133  .legalForTypesWithMemDesc({{s1, p0, 8, 8},
134  {s8, p0, 8, 8},
135  {s16, p0, 16, 8},
136  {s32, p0, 32, 8},
137  {p0, p0, 32, 8}})
138  .unsupportedIfMemSizeNotPow2();
139 
140  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
141  getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
142 
143  auto &PhiBuilder =
144  getActionDefinitionsBuilder(G_PHI)
145  .legalFor({s32, p0})
146  .minScalar(0, s32);
147 
148  getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
149 
150  getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
151 
152  if (!ST.useSoftFloat() && ST.hasVFP2()) {
153  getActionDefinitionsBuilder(
154  {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
155  .legalFor({s32, s64});
156 
157  LoadStoreBuilder
158  .legalForTypesWithMemDesc({{s64, p0, 64, 32}})
159  .maxScalar(0, s32);
160  PhiBuilder.legalFor({s64});
161 
162  getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
163  {s32, s64});
164 
165  getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
166  getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
167 
168  getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
169  getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
170 
171  getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
172  .legalForCartesianProduct({s32}, {s32, s64});
173  getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
174  .legalForCartesianProduct({s32, s64}, {s32});
175  } else {
176  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
177  .libcallFor({s32, s64});
178 
179  LoadStoreBuilder.maxScalar(0, s32);
180 
181  for (auto Ty : {s32, s64})
182  setAction({G_FNEG, Ty}, Lower);
183 
184  getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
185 
186  getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
187  {s32, s64});
188 
189  if (AEABI(ST))
190  setFCmpLibcallsAEABI();
191  else
192  setFCmpLibcallsGNU();
193 
194  getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
195  getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
196 
197  getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
198  .libcallForCartesianProduct({s32}, {s32, s64});
199  getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
200  .libcallForCartesianProduct({s32, s64}, {s32});
201  }
202 
203  if (!ST.useSoftFloat() && ST.hasVFP4())
204  getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
205  else
206  getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
207 
208  getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
209 
210  if (ST.hasV5TOps()) {
211  getActionDefinitionsBuilder(G_CTLZ)
212  .legalFor({s32, s32})
213  .clampScalar(1, s32, s32)
214  .clampScalar(0, s32, s32);
215  getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
216  .lowerFor({s32, s32})
217  .clampScalar(1, s32, s32)
218  .clampScalar(0, s32, s32);
219  } else {
220  getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
221  .libcallFor({s32, s32})
222  .clampScalar(1, s32, s32)
223  .clampScalar(0, s32, s32);
224  getActionDefinitionsBuilder(G_CTLZ)
225  .lowerFor({s32, s32})
226  .clampScalar(1, s32, s32)
227  .clampScalar(0, s32, s32);
228  }
229 
230  computeTables();
231  verify(*ST.getInstrInfo());
232 }
233 
234 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
235  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
236  // default-initialized.
237  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
238  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
239  {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
240  FCmp32Libcalls[CmpInst::FCMP_OGE] = {
241  {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
242  FCmp32Libcalls[CmpInst::FCMP_OGT] = {
243  {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
244  FCmp32Libcalls[CmpInst::FCMP_OLE] = {
245  {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
246  FCmp32Libcalls[CmpInst::FCMP_OLT] = {
247  {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
248  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
249  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
250  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
251  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
252  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
253  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
254  FCmp32Libcalls[CmpInst::FCMP_UNO] = {
255  {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
256  FCmp32Libcalls[CmpInst::FCMP_ONE] = {
257  {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
258  {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
259  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
260  {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
261  {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
262 
263  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
264  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
265  {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
266  FCmp64Libcalls[CmpInst::FCMP_OGE] = {
267  {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
268  FCmp64Libcalls[CmpInst::FCMP_OGT] = {
269  {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
270  FCmp64Libcalls[CmpInst::FCMP_OLE] = {
271  {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
272  FCmp64Libcalls[CmpInst::FCMP_OLT] = {
273  {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
274  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
275  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
276  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
277  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
278  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
279  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
280  FCmp64Libcalls[CmpInst::FCMP_UNO] = {
281  {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
282  FCmp64Libcalls[CmpInst::FCMP_ONE] = {
283  {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
284  {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
285  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
286  {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
287  {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
288 }
289 
290 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
291  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
292  // default-initialized.
293  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
294  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
295  FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
296  FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
297  FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
298  FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
299  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
300  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
301  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
302  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
303  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
304  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
305  FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
306  FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
307  {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
308  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
309  {RTLIB::UO_F32, CmpInst::ICMP_NE}};
310 
311  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
312  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
313  FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
314  FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
315  FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
316  FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
317  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
318  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
319  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
320  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
321  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
322  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
323  FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
324  FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
325  {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
326  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
327  {RTLIB::UO_F64, CmpInst::ICMP_NE}};
328 }
329 
331 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
332  unsigned Size) const {
333  assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
334  if (Size == 32)
335  return FCmp32Libcalls[Predicate];
336  if (Size == 64)
337  return FCmp64Libcalls[Predicate];
338  llvm_unreachable("Unsupported size for FCmp predicate");
339 }
340 
343  MachineIRBuilder &MIRBuilder,
344  GISelChangeObserver &Observer) const {
345  using namespace TargetOpcode;
346 
347  MIRBuilder.setInstr(MI);
348  LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
349 
350  switch (MI.getOpcode()) {
351  default:
352  return false;
353  case G_SREM:
354  case G_UREM: {
355  unsigned OriginalResult = MI.getOperand(0).getReg();
356  auto Size = MRI.getType(OriginalResult).getSizeInBits();
357  if (Size != 32)
358  return false;
359 
360  auto Libcall =
361  MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
362 
363  // Our divmod libcalls return a struct containing the quotient and the
364  // remainder. We need to create a virtual register for it.
365  Type *ArgTy = Type::getInt32Ty(Ctx);
366  StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
367  auto RetVal = MRI.createGenericVirtualRegister(
368  getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
369 
370  auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
371  {{MI.getOperand(1).getReg(), ArgTy},
372  {MI.getOperand(2).getReg(), ArgTy}});
374  return false;
375 
376  // The remainder is the second result of divmod. Split the return value into
377  // a new, unused register for the quotient and the destination of the
378  // original instruction for the remainder.
379  MIRBuilder.buildUnmerge(
380  {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
381  RetVal);
382  break;
383  }
384  case G_FCMP: {
385  assert(MRI.getType(MI.getOperand(2).getReg()) ==
386  MRI.getType(MI.getOperand(3).getReg()) &&
387  "Mismatched operands for G_FCMP");
388  auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
389 
390  auto OriginalResult = MI.getOperand(0).getReg();
391  auto Predicate =
392  static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
393  auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
394 
395  if (Libcalls.empty()) {
398  "Predicate needs libcalls, but none specified");
399  MIRBuilder.buildConstant(OriginalResult,
400  Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
401  MI.eraseFromParent();
402  return true;
403  }
404 
405  assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
406  auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
407  auto *RetTy = Type::getInt32Ty(Ctx);
408 
410  for (auto Libcall : Libcalls) {
411  auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
412  auto Status =
413  createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
414  {{MI.getOperand(2).getReg(), ArgTy},
415  {MI.getOperand(3).getReg(), ArgTy}});
416 
418  return false;
419 
420  auto ProcessedResult =
421  Libcalls.size() == 1
422  ? OriginalResult
423  : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
424 
425  // We have a result, but we need to transform it into a proper 1-bit 0 or
426  // 1, taking into account the different peculiarities of the values
427  // returned by the comparison functions.
428  CmpInst::Predicate ResultPred = Libcall.Predicate;
429  if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
430  // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
431  // to keep the types consistent.
432  MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
433  } else {
434  // We need to compare against 0.
435  assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
436  auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
437  MIRBuilder.buildConstant(Zero, 0);
438  MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
439  }
440  Results.push_back(ProcessedResult);
441  }
442 
443  if (Results.size() != 1) {
444  assert(Results.size() == 2 && "Unexpected number of results");
445  MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
446  }
447  break;
448  }
449  case G_FCONSTANT: {
450  // Convert to integer constants, while preserving the binary representation.
451  auto AsInteger =
453  MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
454  *ConstantInt::get(Ctx, AsInteger));
455  break;
456  }
457  }
458 
459  MI.eraseFromParent();
460  return true;
461 }
size_t size() const
Definition: Function.h:663
bool isFPPredicate() const
Definition: InstrTypes.h:738
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:677
static Type * getDoubleTy(LLVMContext &C)
Definition: Type.cpp:164
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
bool isThumb() const
Definition: ARMSubtarget.h:717
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:589
The operation should be implemented in terms of a wider scalar base-type.
Definition: LegalizerInfo.h:57
void push_back(const T &Elt)
Definition: SmallVector.h:211
unsigned getReg() const
getReg - Returns the register number.
static bool AEABI(const ARMSubtarget &ST)
std::vector< SizeAndAction > SizeAndActionsVec
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:652
Function Alias Analysis Results
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:662
bool isThumb1Only() const
Definition: ARMSubtarget.h:719
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:682
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:496
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:657
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:656
static Type * getFloatTy(LLVMContext &C)
Definition: Type.cpp:163
const ConstantFP * getFPImm() const
Class to represent struct types.
Definition: DerivedTypes.h:232
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:653
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
This operation is completely unsupported on the target.
Definition: LegalizerInfo.h:85
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:341
LegalizerHelper::LegalizeResult createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, const CallLowering::ArgInfo &Result, ArrayRef< CallLowering::ArgInfo > Args)
Helper function that creates the given libcall.
bool hasVFP2() const
Definition: ARMSubtarget.h:572
MachineFunction & getMF()
Getter for the function we currently build.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
The operation itself must be expressed in terms of simpler actions on this target.
Definition: LegalizerInfo.h:72
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static LegalizerInfo::SizeAndActionsVec widen_8_16(const LegalizerInfo::SizeAndActionsVec &v)
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:590
Abstract class that contains various methods for clients to notify about changes. ...
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
This file declares the targeting of the Machinelegalizer class for ARM.
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
ARMLegalizerInfo(const ARMSubtarget &ST)
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:655
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:663
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:661
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
signed greater than
Definition: InstrTypes.h:673
unsigned first
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
const APFloat & getValueAPF() const
Definition: Constants.h:302
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:650
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
bool useSoftFloat() const
Definition: ARMSubtarget.h:716
bool isTargetAEABI() const
Definition: ARMSubtarget.h:672
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:660
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
The operation should be implemented as a call to some kind of runtime support library.
Definition: LegalizerInfo.h:77
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
signed less than
Definition: InstrTypes.h:675
The target wants to do something special with this combination of operand and type.
Definition: LegalizerInfo.h:81
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isIntPredicate() const
Definition: InstrTypes.h:739
signed less or equal
Definition: InstrTypes.h:676
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Instruction has been legalized and the MachineFunction changed.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, GISelChangeObserver &Observer) const override
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:654
static void addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, const LegalizerInfo::SizeAndActionsVec &v)
FIXME: The following static functions are SizeChangeStrategy functions that are meant to temporarily ...
uint32_t Size
Definition: Profile.cpp:46
bool hasV5TOps() const
Definition: ARMSubtarget.h:539
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:658
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:649
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:659
bool hasVFP4() const
Definition: ARMSubtarget.h:574
IRTranslator LLVM IR MI
APInt bitcastToAPInt() const
Definition: APFloat.h:1093
This file describes how to lower LLVM calls to machine code calls.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:651
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:648
signed greater or equal
Definition: InstrTypes.h:674
unsigned getPredicate() const