LLVM  6.0.0svn
ARMLegalizerInfo.cpp
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1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the Machinelegalizer class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMLegalizerInfo.h"
15 #include "ARMCallLowering.h"
16 #include "ARMSubtarget.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/IR/Type.h"
24 
25 using namespace llvm;
26 
27 /// FIXME: The following static functions are SizeChangeStrategy functions
28 /// that are meant to temporarily mimic the behaviour of the old legalization
29 /// based on doubling/halving non-legal types as closely as possible. This is
30 /// not entirly possible as only legalizing the types that are exactly a power
31 /// of 2 times the size of the legal types would require specifying all those
32 /// sizes explicitly.
33 /// In practice, not specifying those isn't a problem, and the below functions
34 /// should disappear quickly as we add support for legalizing non-power-of-2
35 /// sized types further.
36 static void
39  for (unsigned i = 0; i < v.size(); ++i) {
40  result.push_back(v[i]);
41  if (i + 1 < v[i].first && i + 1 < v.size() &&
42  v[i + 1].first != v[i].first + 1)
43  result.push_back({v[i].first + 1, LegalizerInfo::Unsupported});
44  }
45 }
46 
49  assert(v.size() >= 1);
50  assert(v[0].first > 17);
56  auto Largest = result.back().first;
57  result.push_back({Largest + 1, LegalizerInfo::Unsupported});
58  return result;
59 }
60 
63  assert(v.size() >= 1);
64  assert(v[0].first > 17);
70  auto Largest = result.back().first;
71  result.push_back({Largest + 1, LegalizerInfo::Unsupported});
72  return result;
73 }
74 
75 static bool AEABI(const ARMSubtarget &ST) {
76  return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
77 }
78 
80  using namespace TargetOpcode;
81 
82  const LLT p0 = LLT::pointer(0, 32);
83 
84  const LLT s1 = LLT::scalar(1);
85  const LLT s8 = LLT::scalar(8);
86  const LLT s16 = LLT::scalar(16);
87  const LLT s32 = LLT::scalar(32);
88  const LLT s64 = LLT::scalar(64);
89 
90  setAction({G_GLOBAL_VALUE, p0}, Legal);
91  setAction({G_FRAME_INDEX, p0}, Legal);
92 
93  for (unsigned Op : {G_LOAD, G_STORE}) {
94  for (auto Ty : {s1, s8, s16, s32, p0})
95  setAction({Op, Ty}, Legal);
96  setAction({Op, 1, p0}, Legal);
97  }
98 
99  for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
100  if (Op != G_ADD)
103  setAction({Op, s32}, Legal);
104  }
105 
106  for (unsigned Op : {G_SDIV, G_UDIV}) {
109  if (ST.hasDivideInARMMode())
110  setAction({Op, s32}, Legal);
111  else
112  setAction({Op, s32}, Libcall);
113  }
114 
115  for (unsigned Op : {G_SREM, G_UREM}) {
117  if (ST.hasDivideInARMMode())
118  setAction({Op, s32}, Lower);
119  else if (AEABI(ST))
120  setAction({Op, s32}, Custom);
121  else
122  setAction({Op, s32}, Libcall);
123  }
124 
125  for (unsigned Op : {G_SEXT, G_ZEXT, G_ANYEXT}) {
126  setAction({Op, s32}, Legal);
127  }
128 
129  for (unsigned Op : {G_ASHR, G_LSHR, G_SHL})
130  setAction({Op, s32}, Legal);
131 
132  setAction({G_GEP, p0}, Legal);
133  setAction({G_GEP, 1, s32}, Legal);
134 
135  setAction({G_SELECT, s32}, Legal);
136  setAction({G_SELECT, p0}, Legal);
137  setAction({G_SELECT, 1, s1}, Legal);
138 
139  setAction({G_BRCOND, s1}, Legal);
140 
141  setAction({G_CONSTANT, s32}, Legal);
143 
144  setAction({G_ICMP, s1}, Legal);
147  for (auto Ty : {s32, p0})
148  setAction({G_ICMP, 1, Ty}, Legal);
149 
150  if (!ST.useSoftFloat() && ST.hasVFP2()) {
151  for (unsigned BinOp : {G_FADD, G_FSUB})
152  for (auto Ty : {s32, s64})
153  setAction({BinOp, Ty}, Legal);
154 
155  setAction({G_LOAD, s64}, Legal);
156  setAction({G_STORE, s64}, Legal);
157 
158  setAction({G_FCMP, s1}, Legal);
159  setAction({G_FCMP, 1, s32}, Legal);
160  setAction({G_FCMP, 1, s64}, Legal);
161  } else {
162  for (unsigned BinOp : {G_FADD, G_FSUB})
163  for (auto Ty : {s32, s64})
164  setAction({BinOp, Ty}, Libcall);
165 
166  setAction({G_FCMP, s1}, Legal);
167  setAction({G_FCMP, 1, s32}, Custom);
168  setAction({G_FCMP, 1, s64}, Custom);
169 
170  if (AEABI(ST))
171  setFCmpLibcallsAEABI();
172  else
173  setFCmpLibcallsGNU();
174  }
175 
176  for (unsigned Op : {G_FREM, G_FPOW})
177  for (auto Ty : {s32, s64})
178  setAction({Op, Ty}, Libcall);
179 
180  computeTables();
181 }
182 
183 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
184  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
185  // default-initialized.
186  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
187  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
188  {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
189  FCmp32Libcalls[CmpInst::FCMP_OGE] = {
190  {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
191  FCmp32Libcalls[CmpInst::FCMP_OGT] = {
192  {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
193  FCmp32Libcalls[CmpInst::FCMP_OLE] = {
194  {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
195  FCmp32Libcalls[CmpInst::FCMP_OLT] = {
196  {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
197  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
198  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
199  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
200  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
201  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
202  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
203  FCmp32Libcalls[CmpInst::FCMP_UNO] = {
204  {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
205  FCmp32Libcalls[CmpInst::FCMP_ONE] = {
206  {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
207  {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
208  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
209  {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
210  {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
211 
212  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
213  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
214  {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
215  FCmp64Libcalls[CmpInst::FCMP_OGE] = {
216  {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
217  FCmp64Libcalls[CmpInst::FCMP_OGT] = {
218  {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
219  FCmp64Libcalls[CmpInst::FCMP_OLE] = {
220  {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
221  FCmp64Libcalls[CmpInst::FCMP_OLT] = {
222  {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
223  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
224  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
225  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
226  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
227  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
228  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
229  FCmp64Libcalls[CmpInst::FCMP_UNO] = {
230  {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
231  FCmp64Libcalls[CmpInst::FCMP_ONE] = {
232  {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
233  {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
234  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
235  {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
236  {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
237 }
238 
239 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
240  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
241  // default-initialized.
242  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
243  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
244  FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
245  FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
246  FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
247  FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
248  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
249  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
250  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
251  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
252  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
253  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
254  FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
255  FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
256  {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
257  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
258  {RTLIB::UO_F32, CmpInst::ICMP_NE}};
259 
260  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
261  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
262  FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
263  FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
264  FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
265  FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
266  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
267  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
268  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
269  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
270  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
271  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
272  FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
273  FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
274  {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
275  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
276  {RTLIB::UO_F64, CmpInst::ICMP_NE}};
277 }
278 
280 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
281  unsigned Size) const {
282  assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
283  if (Size == 32)
284  return FCmp32Libcalls[Predicate];
285  if (Size == 64)
286  return FCmp64Libcalls[Predicate];
287  llvm_unreachable("Unsupported size for FCmp predicate");
288 }
289 
292  MachineIRBuilder &MIRBuilder) const {
293  using namespace TargetOpcode;
294 
295  MIRBuilder.setInstr(MI);
296 
297  switch (MI.getOpcode()) {
298  default:
299  return false;
300  case G_SREM:
301  case G_UREM: {
302  unsigned OriginalResult = MI.getOperand(0).getReg();
303  auto Size = MRI.getType(OriginalResult).getSizeInBits();
304  if (Size != 32)
305  return false;
306 
307  auto Libcall =
308  MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
309 
310  // Our divmod libcalls return a struct containing the quotient and the
311  // remainder. We need to create a virtual register for it.
312  auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
313  Type *ArgTy = Type::getInt32Ty(Ctx);
314  StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
315  auto RetVal = MRI.createGenericVirtualRegister(
316  getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
317 
318  auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
319  {{MI.getOperand(1).getReg(), ArgTy},
320  {MI.getOperand(2).getReg(), ArgTy}});
321  if (Status != LegalizerHelper::Legalized)
322  return false;
323 
324  // The remainder is the second result of divmod. Split the return value into
325  // a new, unused register for the quotient and the destination of the
326  // original instruction for the remainder.
327  MIRBuilder.buildUnmerge(
328  {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
329  RetVal);
330  break;
331  }
332  case G_FCMP: {
333  assert(MRI.getType(MI.getOperand(2).getReg()) ==
334  MRI.getType(MI.getOperand(3).getReg()) &&
335  "Mismatched operands for G_FCMP");
336  auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
337 
338  auto OriginalResult = MI.getOperand(0).getReg();
339  auto Predicate =
340  static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
341  auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
342 
343  if (Libcalls.empty()) {
346  "Predicate needs libcalls, but none specified");
347  MIRBuilder.buildConstant(OriginalResult,
348  Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
349  MI.eraseFromParent();
350  return true;
351  }
352 
353  auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
354  assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
355  auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
356  auto *RetTy = Type::getInt32Ty(Ctx);
357 
359  for (auto Libcall : Libcalls) {
360  auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
361  auto Status =
362  createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
363  {{MI.getOperand(2).getReg(), ArgTy},
364  {MI.getOperand(3).getReg(), ArgTy}});
365 
366  if (Status != LegalizerHelper::Legalized)
367  return false;
368 
369  auto ProcessedResult =
370  Libcalls.size() == 1
371  ? OriginalResult
372  : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
373 
374  // We have a result, but we need to transform it into a proper 1-bit 0 or
375  // 1, taking into account the different peculiarities of the values
376  // returned by the comparison functions.
377  CmpInst::Predicate ResultPred = Libcall.Predicate;
378  if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
379  // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
380  // to keep the types consistent.
381  MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
382  } else {
383  // We need to compare against 0.
384  assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
385  auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
386  MIRBuilder.buildConstant(Zero, 0);
387  MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
388  }
389  Results.push_back(ProcessedResult);
390  }
391 
392  if (Results.size() != 1) {
393  assert(Results.size() == 2 && "Unexpected number of results");
394  MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
395  }
396  break;
397  }
398  }
399 
400  MI.eraseFromParent();
401  return true;
402 }
size_t size() const
Definition: Function.h:593
bool isFPPredicate() const
Definition: InstrTypes.h:944
void push_back(const T &Elt)
Definition: SmallVector.h:212
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:626
static Type * getDoubleTy(LLVMContext &C)
Definition: Type.cpp:165
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getReg() const
getReg - Returns the register number.
static bool AEABI(const ARMSubtarget &ST)
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:859
Function Alias Analysis Results
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:869
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res<def> = G_TRUNC Op.
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:631
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:864
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:863
static SizeAndActionsVec widenToLargerTypesUnsupportedOtherwise(const SizeAndActionsVec &v)
static Type * getFloatTy(LLVMContext &C)
Definition: Type.cpp:164
Class to represent struct types.
Definition: DerivedTypes.h:201
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:860
std::vector< SizeAndAction > SizeAndActionsVec
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:336
LegalizerHelper::LegalizeResult createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, const CallLowering::ArgInfo &Result, ArrayRef< CallLowering::ArgInfo > Args)
Helper function that creates the given libcall.
bool hasVFP2() const
Definition: ARMSubtarget.h:529
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
MachineFunction & getMF()
Getter for the function we currently build.
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const override
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static LegalizerInfo::SizeAndActionsVec widen_8_16(const LegalizerInfo::SizeAndActionsVec &v)
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:545
The target wants to do something special with this combination of operand and type.
Definition: LegalizerInfo.h:93
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This file declares the targeting of the Machinelegalizer class for ARM.
Helper class to build MachineInstr.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:853
ARMLegalizerInfo(const ARMSubtarget &ST)
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:862
MachineInstrBuilder buildOr(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res<def> = G_OR Op0, Op1.
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:870
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:868
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
signed greater than
Definition: InstrTypes.h:880
unsigned first
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:857
The operation should be implemented as a call to some kind of runtime support library.
Definition: LegalizerInfo.h:89
bool useSoftFloat() const
Definition: ARMSubtarget.h:671
bool isTargetAEABI() const
Definition: ARMSubtarget.h:621
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:867
The operation should be implemented in terms of a wider scalar base-type.
Definition: LegalizerInfo.h:69
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
signed less than
Definition: InstrTypes.h:882
static LegalizerInfo::SizeAndActionsVec widen_1_8_16(const LegalizerInfo::SizeAndActionsVec &v)
bool isIntPredicate() const
Definition: InstrTypes.h:945
signed less or equal
Definition: InstrTypes.h:883
The operation itself must be expressed in terms of simpler actions on this target.
Definition: LegalizerInfo.h:84
The operation is expected to be selectable directly by the target, and no transformation is necessary...
Definition: LegalizerInfo.h:59
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
Instruction has been legalized and the MachineFunction changed.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, const unsigned TypeIdx, SizeChangeStrategy S)
The setAction calls record the non-size-changing legalization actions to take on specificly-sized typ...
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:861
static void addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, const LegalizerInfo::SizeAndActionsVec &v)
FIXME: The following static functions are SizeChangeStrategy functions that are meant to temporarily ...
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:865
MachineInstrBuilder buildUnmerge(ArrayRef< unsigned > Res, unsigned Op)
Build and insert Res0<def>, ...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:856
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:866
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
This operation is completely unsupported on the target.
Definition: LegalizerInfo.h:97
IRTranslator LLVM IR MI
This file describes how to lower LLVM calls to machine code calls.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:858
void setAction(const InstrAspect &Aspect, LegalizeAction Action)
More friendly way to set an action for common types that have an LLT representation.
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:855
signed greater or equal
Definition: InstrTypes.h:881
unsigned getPredicate() const