LLVM  9.0.0svn
ARMLegalizerInfo.cpp
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1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for ARM.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMLegalizerInfo.h"
14 #include "ARMCallLowering.h"
15 #include "ARMSubtarget.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Type.h"
23 
24 using namespace llvm;
25 using namespace LegalizeActions;
26 
27 /// FIXME: The following static functions are SizeChangeStrategy functions
28 /// that are meant to temporarily mimic the behaviour of the old legalization
29 /// based on doubling/halving non-legal types as closely as possible. This is
30 /// not entirly possible as only legalizing the types that are exactly a power
31 /// of 2 times the size of the legal types would require specifying all those
32 /// sizes explicitly.
33 /// In practice, not specifying those isn't a problem, and the below functions
34 /// should disappear quickly as we add support for legalizing non-power-of-2
35 /// sized types further.
36 static void
39  for (unsigned i = 0; i < v.size(); ++i) {
40  result.push_back(v[i]);
41  if (i + 1 < v[i].first && i + 1 < v.size() &&
42  v[i + 1].first != v[i].first + 1)
43  result.push_back({v[i].first + 1, Unsupported});
44  }
45 }
46 
49  assert(v.size() >= 1);
50  assert(v[0].first > 17);
52  {8, WidenScalar},
53  {9, Unsupported},
54  {16, WidenScalar},
55  {17, Unsupported}};
57  auto Largest = result.back().first;
58  result.push_back({Largest + 1, Unsupported});
59  return result;
60 }
61 
62 static bool AEABI(const ARMSubtarget &ST) {
63  return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
64 }
65 
67  using namespace TargetOpcode;
68 
69  const LLT p0 = LLT::pointer(0, 32);
70 
71  const LLT s1 = LLT::scalar(1);
72  const LLT s8 = LLT::scalar(8);
73  const LLT s16 = LLT::scalar(16);
74  const LLT s32 = LLT::scalar(32);
75  const LLT s64 = LLT::scalar(64);
76 
77  if (ST.isThumb1Only()) {
78  // Thumb1 is not supported yet.
79  computeTables();
80  verify(*ST.getInstrInfo());
81  return;
82  }
83 
84  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
85  .legalForCartesianProduct({s32}, {s1, s8, s16});
86 
87  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
88  .legalFor({s32})
89  .minScalar(0, s32);
90 
91  getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
92  .legalFor({{s32, s32}})
93  .clampScalar(1, s32, s32);
94 
95  bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
96  (ST.isThumb() && ST.hasDivideInThumbMode());
97  if (HasHWDivide)
98  getActionDefinitionsBuilder({G_SDIV, G_UDIV})
99  .legalFor({s32})
100  .clampScalar(0, s32, s32);
101  else
102  getActionDefinitionsBuilder({G_SDIV, G_UDIV})
103  .libcallFor({s32})
104  .clampScalar(0, s32, s32);
105 
106  for (unsigned Op : {G_SREM, G_UREM}) {
107  setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
108  if (HasHWDivide)
109  setAction({Op, s32}, Lower);
110  else if (AEABI(ST))
111  setAction({Op, s32}, Custom);
112  else
113  setAction({Op, s32}, Libcall);
114  }
115 
116  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
117  getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
118 
119  getActionDefinitionsBuilder(G_CONSTANT)
120  .legalFor({s32, p0})
121  .clampScalar(0, s32, s32);
122 
123  getActionDefinitionsBuilder(G_ICMP)
124  .legalForCartesianProduct({s1}, {s32, p0})
125  .minScalar(1, s32);
126 
127  getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0},
128  {s1});
129 
130  // We're keeping these builders around because we'll want to add support for
131  // floating point to them.
132  auto &LoadStoreBuilder =
133  getActionDefinitionsBuilder({G_LOAD, G_STORE})
134  .legalForTypesWithMemDesc({
135  {s1, p0, 8, 8},
136  {s8, p0, 8, 8},
137  {s16, p0, 16, 8},
138  {s32, p0, 32, 8},
139  {p0, p0, 32, 8}});
140 
141  getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
142 
143  getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
144 
145  if (ST.isThumb()) {
146  // FIXME: merge with the code for non-Thumb.
147  computeTables();
148  verify(*ST.getInstrInfo());
149  return;
150  }
151 
152  getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
153  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
154 
155  if (ST.hasV5TOps()) {
156  getActionDefinitionsBuilder(G_CTLZ)
157  .legalFor({s32, s32})
158  .clampScalar(1, s32, s32)
159  .clampScalar(0, s32, s32);
160  getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
161  .lowerFor({s32, s32})
162  .clampScalar(1, s32, s32)
163  .clampScalar(0, s32, s32);
164  } else {
165  getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
166  .libcallFor({s32, s32})
167  .clampScalar(1, s32, s32)
168  .clampScalar(0, s32, s32);
169  getActionDefinitionsBuilder(G_CTLZ)
170  .lowerFor({s32, s32})
171  .clampScalar(1, s32, s32)
172  .clampScalar(0, s32, s32);
173  }
174 
175  // We're keeping these builders around because we'll want to add support for
176  // floating point to them.
177  auto &PhiBuilder =
178  getActionDefinitionsBuilder(G_PHI).legalFor({s32, p0}).minScalar(0, s32);
179 
180  if (!ST.useSoftFloat() && ST.hasVFP2()) {
181  getActionDefinitionsBuilder(
182  {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
183  .legalFor({s32, s64});
184 
185  LoadStoreBuilder.legalFor({{s64, p0}});
186  PhiBuilder.legalFor({s64});
187 
188  getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
189  {s32, s64});
190 
191  getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
192  getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
193 
194  getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
195  getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
196 
197  getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
198  .legalForCartesianProduct({s32}, {s32, s64});
199  getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
200  .legalForCartesianProduct({s32, s64}, {s32});
201  } else {
202  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
203  .libcallFor({s32, s64});
204 
205  LoadStoreBuilder.maxScalar(0, s32);
206 
207  for (auto Ty : {s32, s64})
208  setAction({G_FNEG, Ty}, Lower);
209 
210  getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
211 
212  getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
213  {s32, s64});
214 
215  if (AEABI(ST))
216  setFCmpLibcallsAEABI();
217  else
218  setFCmpLibcallsGNU();
219 
220  getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
221  getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
222 
223  getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
224  .libcallForCartesianProduct({s32}, {s32, s64});
225  getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
226  .libcallForCartesianProduct({s32, s64}, {s32});
227  }
228 
229  if (!ST.useSoftFloat() && ST.hasVFP4())
230  getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
231  else
232  getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
233 
234  getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
235 
236  computeTables();
237  verify(*ST.getInstrInfo());
238 }
239 
240 void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
241  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
242  // default-initialized.
243  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
244  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
245  {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
246  FCmp32Libcalls[CmpInst::FCMP_OGE] = {
247  {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
248  FCmp32Libcalls[CmpInst::FCMP_OGT] = {
249  {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
250  FCmp32Libcalls[CmpInst::FCMP_OLE] = {
251  {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
252  FCmp32Libcalls[CmpInst::FCMP_OLT] = {
253  {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
254  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
255  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
256  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
257  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
258  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
259  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
260  FCmp32Libcalls[CmpInst::FCMP_UNO] = {
261  {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
262  FCmp32Libcalls[CmpInst::FCMP_ONE] = {
263  {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
264  {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
265  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
266  {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
267  {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
268 
269  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
270  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
271  {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
272  FCmp64Libcalls[CmpInst::FCMP_OGE] = {
273  {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
274  FCmp64Libcalls[CmpInst::FCMP_OGT] = {
275  {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
276  FCmp64Libcalls[CmpInst::FCMP_OLE] = {
277  {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
278  FCmp64Libcalls[CmpInst::FCMP_OLT] = {
279  {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
280  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
281  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
282  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
283  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
284  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
285  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
286  FCmp64Libcalls[CmpInst::FCMP_UNO] = {
287  {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
288  FCmp64Libcalls[CmpInst::FCMP_ONE] = {
289  {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
290  {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
291  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
292  {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
293  {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
294 }
295 
296 void ARMLegalizerInfo::setFCmpLibcallsGNU() {
297  // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
298  // default-initialized.
299  FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
300  FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
301  FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
302  FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
303  FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
304  FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
305  FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
306  FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
307  FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
308  FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
309  FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
310  FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
311  FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
312  FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
313  {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
314  FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
315  {RTLIB::UO_F32, CmpInst::ICMP_NE}};
316 
317  FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
318  FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
319  FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
320  FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
321  FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
322  FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
323  FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
324  FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
325  FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
326  FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
327  FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
328  FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
329  FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
330  FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
331  {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
332  FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
333  {RTLIB::UO_F64, CmpInst::ICMP_NE}};
334 }
335 
337 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
338  unsigned Size) const {
339  assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
340  if (Size == 32)
341  return FCmp32Libcalls[Predicate];
342  if (Size == 64)
343  return FCmp64Libcalls[Predicate];
344  llvm_unreachable("Unsupported size for FCmp predicate");
345 }
346 
349  MachineIRBuilder &MIRBuilder,
350  GISelChangeObserver &Observer) const {
351  using namespace TargetOpcode;
352 
353  MIRBuilder.setInstr(MI);
354  LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
355 
356  switch (MI.getOpcode()) {
357  default:
358  return false;
359  case G_SREM:
360  case G_UREM: {
361  unsigned OriginalResult = MI.getOperand(0).getReg();
362  auto Size = MRI.getType(OriginalResult).getSizeInBits();
363  if (Size != 32)
364  return false;
365 
366  auto Libcall =
367  MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
368 
369  // Our divmod libcalls return a struct containing the quotient and the
370  // remainder. We need to create a virtual register for it.
371  Type *ArgTy = Type::getInt32Ty(Ctx);
372  StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
373  auto RetVal = MRI.createGenericVirtualRegister(
374  getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
375 
376  auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
377  {{MI.getOperand(1).getReg(), ArgTy},
378  {MI.getOperand(2).getReg(), ArgTy}});
380  return false;
381 
382  // The remainder is the second result of divmod. Split the return value into
383  // a new, unused register for the quotient and the destination of the
384  // original instruction for the remainder.
385  MIRBuilder.buildUnmerge(
386  {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
387  RetVal);
388  break;
389  }
390  case G_FCMP: {
391  assert(MRI.getType(MI.getOperand(2).getReg()) ==
392  MRI.getType(MI.getOperand(3).getReg()) &&
393  "Mismatched operands for G_FCMP");
394  auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
395 
396  auto OriginalResult = MI.getOperand(0).getReg();
397  auto Predicate =
398  static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
399  auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
400 
401  if (Libcalls.empty()) {
404  "Predicate needs libcalls, but none specified");
405  MIRBuilder.buildConstant(OriginalResult,
406  Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
407  MI.eraseFromParent();
408  return true;
409  }
410 
411  assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
412  auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
413  auto *RetTy = Type::getInt32Ty(Ctx);
414 
416  for (auto Libcall : Libcalls) {
417  auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
418  auto Status =
419  createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
420  {{MI.getOperand(2).getReg(), ArgTy},
421  {MI.getOperand(3).getReg(), ArgTy}});
422 
424  return false;
425 
426  auto ProcessedResult =
427  Libcalls.size() == 1
428  ? OriginalResult
429  : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
430 
431  // We have a result, but we need to transform it into a proper 1-bit 0 or
432  // 1, taking into account the different peculiarities of the values
433  // returned by the comparison functions.
434  CmpInst::Predicate ResultPred = Libcall.Predicate;
435  if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
436  // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
437  // to keep the types consistent.
438  MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
439  } else {
440  // We need to compare against 0.
441  assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
442  auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
443  MIRBuilder.buildConstant(Zero, 0);
444  MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
445  }
446  Results.push_back(ProcessedResult);
447  }
448 
449  if (Results.size() != 1) {
450  assert(Results.size() == 2 && "Unexpected number of results");
451  MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
452  }
453  break;
454  }
455  case G_FCONSTANT: {
456  // Convert to integer constants, while preserving the binary representation.
457  auto AsInteger =
459  MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
460  *ConstantInt::get(Ctx, AsInteger));
461  break;
462  }
463  }
464 
465  MI.eraseFromParent();
466  return true;
467 }
size_t size() const
Definition: Function.h:660
bool isFPPredicate() const
Definition: InstrTypes.h:738
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:676
static Type * getDoubleTy(LLVMContext &C)
Definition: Type.cpp:164
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
bool isThumb() const
Definition: ARMSubtarget.h:716
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:588
The operation should be implemented in terms of a wider scalar base-type.
Definition: LegalizerInfo.h:57
void push_back(const T &Elt)
Definition: SmallVector.h:211
unsigned getReg() const
getReg - Returns the register number.
static bool AEABI(const ARMSubtarget &ST)
std::vector< SizeAndAction > SizeAndActionsVec
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:652
Function Alias Analysis Results
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:662
bool isThumb1Only() const
Definition: ARMSubtarget.h:718
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:681
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:495
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:657
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:656
static Type * getFloatTy(LLVMContext &C)
Definition: Type.cpp:163
const ConstantFP * getFPImm() const
Class to represent struct types.
Definition: DerivedTypes.h:232
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:653
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
This operation is completely unsupported on the target.
Definition: LegalizerInfo.h:85
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:341
LegalizerHelper::LegalizeResult createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, const CallLowering::ArgInfo &Result, ArrayRef< CallLowering::ArgInfo > Args)
Helper function that creates the given libcall.
bool hasVFP2() const
Definition: ARMSubtarget.h:571
MachineFunction & getMF()
Getter for the function we currently build.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
The operation itself must be expressed in terms of simpler actions on this target.
Definition: LegalizerInfo.h:72
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static LegalizerInfo::SizeAndActionsVec widen_8_16(const LegalizerInfo::SizeAndActionsVec &v)
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:589
Abstract class that contains various methods for clients to notify about changes. ...
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
This file declares the targeting of the Machinelegalizer class for ARM.
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
ARMLegalizerInfo(const ARMSubtarget &ST)
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:655
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:663
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:661
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
signed greater than
Definition: InstrTypes.h:673
unsigned first
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
const APFloat & getValueAPF() const
Definition: Constants.h:302
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:650
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
bool useSoftFloat() const
Definition: ARMSubtarget.h:715
bool isTargetAEABI() const
Definition: ARMSubtarget.h:671
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:660
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
The operation should be implemented as a call to some kind of runtime support library.
Definition: LegalizerInfo.h:77
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
signed less than
Definition: InstrTypes.h:675
The target wants to do something special with this combination of operand and type.
Definition: LegalizerInfo.h:81
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:621
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isIntPredicate() const
Definition: InstrTypes.h:739
signed less or equal
Definition: InstrTypes.h:676
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Instruction has been legalized and the MachineFunction changed.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder, GISelChangeObserver &Observer) const override
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:654
static void addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, const LegalizerInfo::SizeAndActionsVec &v)
FIXME: The following static functions are SizeChangeStrategy functions that are meant to temporarily ...
uint32_t Size
Definition: Profile.cpp:46
bool hasV5TOps() const
Definition: ARMSubtarget.h:538
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:658
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:649
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:659
bool hasVFP4() const
Definition: ARMSubtarget.h:573
IRTranslator LLVM IR MI
APInt bitcastToAPInt() const
Definition: APFloat.h:1093
This file describes how to lower LLVM calls to machine code calls.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:651
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:648
signed greater or equal
Definition: InstrTypes.h:674
unsigned getPredicate() const