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ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMMCTargetDesc.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMMCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
31 
32 using namespace llvm;
33 
34 #define GET_REGINFO_MC_DESC
35 #include "ARMGenRegisterInfo.inc"
36 
38  std::string &Info) {
39  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
40  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
41  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
42  // Checks for the deprecated CP15ISB encoding:
43  // mcr p15, #0, rX, c7, c5, #4
44  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
45  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
46  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
47  Info = "deprecated since v7, use 'isb'";
48  return true;
49  }
50 
51  // Checks for the deprecated CP15DSB encoding:
52  // mcr p15, #0, rX, c7, c10, #4
53  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
54  Info = "deprecated since v7, use 'dsb'";
55  return true;
56  }
57  }
58  // Checks for the deprecated CP15DMB encoding:
59  // mcr p15, #0, rX, c7, c10, #5
60  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
61  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
62  Info = "deprecated since v7, use 'dmb'";
63  return true;
64  }
65  }
66  return false;
67 }
68 
69 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
70  std::string &Info) {
71  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
72  MI.getOperand(1).getImm() != 8) {
73  Info = "applying IT instruction to more than one subsequent instruction is "
74  "deprecated";
75  return true;
76  }
77 
78  return false;
79 }
80 
82  std::string &Info) {
83  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
84  "cannot predicate thumb instructions");
85 
86  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
87  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
88  assert(MI.getOperand(OI).isReg() && "expected register");
89  if (MI.getOperand(OI).getReg() == ARM::SP ||
90  MI.getOperand(OI).getReg() == ARM::PC) {
91  Info = "use of SP or PC in the list is deprecated";
92  return true;
93  }
94  }
95  return false;
96 }
97 
99  std::string &Info) {
100  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
101  "cannot predicate thumb instructions");
102 
103  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
104  bool ListContainsPC = false, ListContainsLR = false;
105  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
106  assert(MI.getOperand(OI).isReg() && "expected register");
107  switch (MI.getOperand(OI).getReg()) {
108  default:
109  break;
110  case ARM::LR:
111  ListContainsLR = true;
112  break;
113  case ARM::PC:
114  ListContainsPC = true;
115  break;
116  case ARM::SP:
117  Info = "use of SP in the list is deprecated";
118  return true;
119  }
120  }
121 
122  if (ListContainsPC && ListContainsLR) {
123  Info = "use of LR and PC simultaneously in the list is deprecated";
124  return true;
125  }
126 
127  return false;
128 }
129 
130 #define GET_INSTRINFO_MC_DESC
131 #include "ARMGenInstrInfo.inc"
132 
133 #define GET_SUBTARGETINFO_MC_DESC
134 #include "ARMGenSubtargetInfo.inc"
135 
136 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
137  std::string ARMArchFeature;
138 
140  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
141  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
142 
143  if (TT.isThumb()) {
144  if (!ARMArchFeature.empty())
145  ARMArchFeature += ",";
146  ARMArchFeature += "+thumb-mode,+v4t";
147  }
148 
149  if (TT.isOSNaCl()) {
150  if (!ARMArchFeature.empty())
151  ARMArchFeature += ",";
152  ARMArchFeature += "+nacl-trap";
153  }
154 
155  if (TT.isOSWindows()) {
156  if (!ARMArchFeature.empty())
157  ARMArchFeature += ",";
158  ARMArchFeature += "+noarm";
159  }
160 
161  return ARMArchFeature;
162 }
163 
165  StringRef CPU, StringRef FS) {
166  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
167  if (!FS.empty()) {
168  if (!ArchFS.empty())
169  ArchFS = (Twine(ArchFS) + "," + FS).str();
170  else
171  ArchFS = FS;
172  }
173 
174  return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
175 }
176 
178  MCInstrInfo *X = new MCInstrInfo();
179  InitARMMCInstrInfo(X);
180  return X;
181 }
182 
185  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
186  return X;
187 }
188 
190  const Triple &TheTriple) {
191  MCAsmInfo *MAI;
192  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
193  MAI = new ARMMCAsmInfoDarwin(TheTriple);
194  else if (TheTriple.isWindowsMSVCEnvironment())
195  MAI = new ARMCOFFMCAsmInfoMicrosoft();
196  else if (TheTriple.isOSWindows())
197  MAI = new ARMCOFFMCAsmInfoGNU();
198  else
199  MAI = new ARMELFMCAsmInfo(TheTriple);
200 
201  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
203 
204  return MAI;
205 }
206 
208  std::unique_ptr<MCAsmBackend> &&MAB,
209  std::unique_ptr<MCObjectWriter> &&OW,
210  std::unique_ptr<MCCodeEmitter> &&Emitter,
211  bool RelaxAll) {
212  return createARMELFStreamer(
213  Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
214  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb));
215 }
216 
217 static MCStreamer *
218 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
219  std::unique_ptr<MCObjectWriter> &&OW,
220  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
221  bool DWARFMustBeAtTheEnd) {
222  return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
223  std::move(Emitter), false, DWARFMustBeAtTheEnd);
224 }
225 
227  unsigned SyntaxVariant,
228  const MCAsmInfo &MAI,
229  const MCInstrInfo &MII,
230  const MCRegisterInfo &MRI) {
231  if (SyntaxVariant == 0)
232  return new ARMInstPrinter(MAI, MII, MRI);
233  return nullptr;
234 }
235 
237  MCContext &Ctx) {
238  if (TT.isOSBinFormatMachO())
239  return createARMMachORelocationInfo(Ctx);
240  // Default to the stock relocation info.
241  return llvm::createMCRelocationInfo(TT, Ctx);
242 }
243 
244 namespace {
245 
246 class ARMMCInstrAnalysis : public MCInstrAnalysis {
247 public:
248  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
249 
250  bool isUnconditionalBranch(const MCInst &Inst) const override {
251  // BCCs with the "always" predicate are unconditional branches.
252  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
253  return true;
255  }
256 
257  bool isConditionalBranch(const MCInst &Inst) const override {
258  // BCCs with the "always" predicate are unconditional branches.
259  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
260  return false;
262  }
263 
264  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
265  uint64_t Size, uint64_t &Target) const override {
266  // We only handle PCRel branches for now.
267  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
268  return false;
269 
270  int64_t Imm = Inst.getOperand(0).getImm();
271  Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
272  return true;
273  }
274 };
275 
276 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
277 public:
278  ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
279 
280  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
281  uint64_t Size, uint64_t &Target) const override {
282  // We only handle PCRel branches for now.
283  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
284  return false;
285 
286  int64_t Imm = Inst.getOperand(0).getImm();
287  Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
288  return true;
289  }
290 };
291 
292 }
293 
295  return new ARMMCInstrAnalysis(Info);
296 }
297 
299  return new ThumbMCInstrAnalysis(Info);
300 }
301 
302 // Force static initialization.
303 extern "C" void LLVMInitializeARMTargetMC() {
306  // Register the MC asm info.
308 
309  // Register the MC instruction info.
311 
312  // Register the MC register info.
314 
315  // Register the MC subtarget info.
318 
322 
323  // Register the obj target streamer.
326 
327  // Register the asm streamer.
329 
330  // Register the null TargetStreamer.
332 
333  // Register the MCInstPrinter.
335 
336  // Register the MC relocation info.
338  }
339 
340  // Register the MC instruction analyzer.
341  for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
345 
346  for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
349  }
350  for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
353  }
354 }
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:471
bool isImm() const
Definition: MCInst.h:59
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static MCInstrAnalysis * createThumbMCInstrAnalysis(const MCInstrInfo *Info)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCInstrInfo * createARMMCInstrInfo()
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
unsigned Reg
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:568
virtual bool isConditionalBranch(const MCInst &Inst) const
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
bool isReg() const
Definition: MCInst.h:58
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Target & getTheThumbLETarget()
void LLVMInitializeARMTargetMC()
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const FeatureBitset & getFeatureBits() const
StringRef getArchName(ArchKind AK)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheARMBETarget()
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Target & getTheThumbBETarget()
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:286
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:601
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:563
int64_t getImm() const
Definition: MCInst.h:76
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Streaming machine code generation interface.
Definition: MCStreamer.h:183
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
Create MCExprs from relocations found in an object file.
unsigned getNumOperands() const
Definition: MCInst.h:184
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:599
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:958
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static bool isUnconditionalBranch(TerminatorInst *Term)
Definition: ADCE.cpp:209
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:44
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:40
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:650
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
uint32_t Size
Definition: Profile.cpp:47
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
ArchKind parseArch(StringRef Arch)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Target & getTheARMLETarget()
unsigned getOpcode() const
Definition: MCInst.h:174
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:524
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)