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ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides ARM specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMMCTargetDesc.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMMCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
30 
31 using namespace llvm;
32 
33 #define GET_REGINFO_MC_DESC
34 #include "ARMGenRegisterInfo.inc"
35 
37  std::string &Info) {
38  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
39  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
40  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
41  // Checks for the deprecated CP15ISB encoding:
42  // mcr p15, #0, rX, c7, c5, #4
43  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
44  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
45  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
46  Info = "deprecated since v7, use 'isb'";
47  return true;
48  }
49 
50  // Checks for the deprecated CP15DSB encoding:
51  // mcr p15, #0, rX, c7, c10, #4
52  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
53  Info = "deprecated since v7, use 'dsb'";
54  return true;
55  }
56  }
57  // Checks for the deprecated CP15DMB encoding:
58  // mcr p15, #0, rX, c7, c10, #5
59  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
60  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
61  Info = "deprecated since v7, use 'dmb'";
62  return true;
63  }
64  }
65  return false;
66 }
67 
68 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
69  std::string &Info) {
70  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
71  MI.getOperand(1).getImm() != 8) {
72  Info = "applying IT instruction to more than one subsequent instruction is "
73  "deprecated";
74  return true;
75  }
76 
77  return false;
78 }
79 
81  std::string &Info) {
82  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
83  "cannot predicate thumb instructions");
84 
85  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
86  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
87  assert(MI.getOperand(OI).isReg() && "expected register");
88  if (MI.getOperand(OI).getReg() == ARM::SP ||
89  MI.getOperand(OI).getReg() == ARM::PC) {
90  Info = "use of SP or PC in the list is deprecated";
91  return true;
92  }
93  }
94  return false;
95 }
96 
98  std::string &Info) {
99  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
100  "cannot predicate thumb instructions");
101 
102  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
103  bool ListContainsPC = false, ListContainsLR = false;
104  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
105  assert(MI.getOperand(OI).isReg() && "expected register");
106  switch (MI.getOperand(OI).getReg()) {
107  default:
108  break;
109  case ARM::LR:
110  ListContainsLR = true;
111  break;
112  case ARM::PC:
113  ListContainsPC = true;
114  break;
115  case ARM::SP:
116  Info = "use of SP in the list is deprecated";
117  return true;
118  }
119  }
120 
121  if (ListContainsPC && ListContainsLR) {
122  Info = "use of LR and PC simultaneously in the list is deprecated";
123  return true;
124  }
125 
126  return false;
127 }
128 
129 #define GET_INSTRINFO_MC_DESC
130 #include "ARMGenInstrInfo.inc"
131 
132 #define GET_SUBTARGETINFO_MC_DESC
133 #include "ARMGenSubtargetInfo.inc"
134 
135 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
136  std::string ARMArchFeature;
137 
139  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
140  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
141 
142  if (TT.isThumb()) {
143  if (ARMArchFeature.empty())
144  ARMArchFeature = "+thumb-mode,+v4t";
145  else
146  ARMArchFeature += ",+thumb-mode,+v4t";
147  }
148 
149  if (TT.isOSNaCl()) {
150  if (ARMArchFeature.empty())
151  ARMArchFeature = "+nacl-trap";
152  else
153  ARMArchFeature += ",+nacl-trap";
154  }
155 
156  return ARMArchFeature;
157 }
158 
160  StringRef CPU, StringRef FS) {
161  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
162  if (!FS.empty()) {
163  if (!ArchFS.empty())
164  ArchFS = (Twine(ArchFS) + "," + FS).str();
165  else
166  ArchFS = FS;
167  }
168 
169  return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
170 }
171 
173  MCInstrInfo *X = new MCInstrInfo();
174  InitARMMCInstrInfo(X);
175  return X;
176 }
177 
180  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
181  return X;
182 }
183 
185  const Triple &TheTriple) {
186  MCAsmInfo *MAI;
187  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
188  MAI = new ARMMCAsmInfoDarwin(TheTriple);
189  else if (TheTriple.isWindowsMSVCEnvironment())
190  MAI = new ARMCOFFMCAsmInfoMicrosoft();
191  else if (TheTriple.isOSWindows())
192  MAI = new ARMCOFFMCAsmInfoGNU();
193  else
194  MAI = new ARMELFMCAsmInfo(TheTriple);
195 
196  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
198 
199  return MAI;
200 }
201 
203  std::unique_ptr<MCAsmBackend> &&MAB,
204  raw_pwrite_stream &OS,
205  std::unique_ptr<MCCodeEmitter> &&Emitter,
206  bool RelaxAll) {
207  return createARMELFStreamer(
208  Ctx, std::move(MAB), OS, std::move(Emitter), false,
209  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb));
210 }
211 
212 static MCStreamer *
213 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
214  raw_pwrite_stream &OS,
215  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
216  bool DWARFMustBeAtTheEnd) {
217  return createMachOStreamer(Ctx, std::move(MAB), OS, std::move(Emitter), false,
218  DWARFMustBeAtTheEnd);
219 }
220 
222  unsigned SyntaxVariant,
223  const MCAsmInfo &MAI,
224  const MCInstrInfo &MII,
225  const MCRegisterInfo &MRI) {
226  if (SyntaxVariant == 0)
227  return new ARMInstPrinter(MAI, MII, MRI);
228  return nullptr;
229 }
230 
232  MCContext &Ctx) {
233  if (TT.isOSBinFormatMachO())
234  return createARMMachORelocationInfo(Ctx);
235  // Default to the stock relocation info.
236  return llvm::createMCRelocationInfo(TT, Ctx);
237 }
238 
239 namespace {
240 
241 class ARMMCInstrAnalysis : public MCInstrAnalysis {
242 public:
243  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
244 
245  bool isUnconditionalBranch(const MCInst &Inst) const override {
246  // BCCs with the "always" predicate are unconditional branches.
247  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
248  return true;
250  }
251 
252  bool isConditionalBranch(const MCInst &Inst) const override {
253  // BCCs with the "always" predicate are unconditional branches.
254  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
255  return false;
257  }
258 
259  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
260  uint64_t Size, uint64_t &Target) const override {
261  // We only handle PCRel branches for now.
262  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
263  return false;
264 
265  int64_t Imm = Inst.getOperand(0).getImm();
266  Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
267  return true;
268  }
269 };
270 
271 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
272 public:
273  ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
274 
275  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
276  uint64_t Size, uint64_t &Target) const override {
277  // We only handle PCRel branches for now.
278  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
279  return false;
280 
281  int64_t Imm = Inst.getOperand(0).getImm();
282  Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
283  return true;
284  }
285 };
286 
287 }
288 
290  return new ARMMCInstrAnalysis(Info);
291 }
292 
294  return new ThumbMCInstrAnalysis(Info);
295 }
296 
297 // Force static initialization.
298 extern "C" void LLVMInitializeARMTargetMC() {
301  // Register the MC asm info.
303 
304  // Register the MC instruction info.
306 
307  // Register the MC register info.
309 
310  // Register the MC subtarget info.
313 
317 
318  // Register the obj target streamer.
321 
322  // Register the asm streamer.
324 
325  // Register the null TargetStreamer.
327 
328  // Register the MCInstPrinter.
330 
331  // Register the MC relocation info.
333  }
334 
335  // Register the MC instruction analyzer.
336  for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
340 
341  // Register the MC Code Emitter
346 
347  // Register the asm backend.
356 }
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, raw_pwrite_stream &OS, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
bool isImm() const
Definition: MCInst.h:59
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static MCInstrAnalysis * createThumbMCInstrAnalysis(const MCInstrInfo *Info)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCInstrInfo * createARMMCInstrInfo()
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
MCAsmBackend * createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, raw_pwrite_stream &OS, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
virtual bool isConditionalBranch(const MCInst &Inst) const
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
bool isReg() const
Definition: MCInst.h:58
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Target & getTheThumbLETarget()
void LLVMInitializeARMTargetMC()
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
StringRef getArchName(ArchKind AK)
Reg
All possible values of the reg field in the ModR/M byte.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheARMBETarget()
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:59
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Target & getTheThumbBETarget()
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:582
cl::opt< bool > RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, " "relax all fixups in the emitted object file"))
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
int64_t getImm() const
Definition: MCInst.h:76
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Streaming machine code generation interface.
Definition: MCStreamer.h:169
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:377
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, raw_pwrite_stream &OS, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Takes ownership of TAB and CE.
Create MCExprs from relocations found in an object file.
unsigned getNumOperands() const
Definition: MCInst.h:182
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:940
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, raw_pwrite_stream &OS, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
MCAsmBackend * createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
static bool isUnconditionalBranch(TerminatorInst *Term)
Definition: ADCE.cpp:208
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
OperandType
Types of operands to CF instructions.
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:649
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
MCSubtargetInfo - Generic base class for all target subtargets.
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
ArchKind parseArch(StringRef Arch)
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:337
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Target & getTheARMLETarget()
unsigned getOpcode() const
Definition: MCInst.h:172
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:523
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, raw_pwrite_stream &OS, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb)