LLVM  9.0.0svn
ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMBaseInfo.h"
15 #include "ARMMCAsmInfo.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCELFStreamer.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
30 
31 using namespace llvm;
32 
33 #define GET_REGINFO_MC_DESC
34 #include "ARMGenRegisterInfo.inc"
35 
37  std::string &Info) {
38  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
39  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
40  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
41  // Checks for the deprecated CP15ISB encoding:
42  // mcr p15, #0, rX, c7, c5, #4
43  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
44  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
45  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
46  Info = "deprecated since v7, use 'isb'";
47  return true;
48  }
49 
50  // Checks for the deprecated CP15DSB encoding:
51  // mcr p15, #0, rX, c7, c10, #4
52  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
53  Info = "deprecated since v7, use 'dsb'";
54  return true;
55  }
56  }
57  // Checks for the deprecated CP15DMB encoding:
58  // mcr p15, #0, rX, c7, c10, #5
59  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
60  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
61  Info = "deprecated since v7, use 'dmb'";
62  return true;
63  }
64  }
65  return false;
66 }
67 
68 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
69  std::string &Info) {
70  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
71  MI.getOperand(1).getImm() != 8) {
72  Info = "applying IT instruction to more than one subsequent instruction is "
73  "deprecated";
74  return true;
75  }
76 
77  return false;
78 }
79 
81  std::string &Info) {
82  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
83  "cannot predicate thumb instructions");
84 
85  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
86  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
87  assert(MI.getOperand(OI).isReg() && "expected register");
88  if (MI.getOperand(OI).getReg() == ARM::SP ||
89  MI.getOperand(OI).getReg() == ARM::PC) {
90  Info = "use of SP or PC in the list is deprecated";
91  return true;
92  }
93  }
94  return false;
95 }
96 
98  std::string &Info) {
99  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
100  "cannot predicate thumb instructions");
101 
102  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
103  bool ListContainsPC = false, ListContainsLR = false;
104  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
105  assert(MI.getOperand(OI).isReg() && "expected register");
106  switch (MI.getOperand(OI).getReg()) {
107  default:
108  break;
109  case ARM::LR:
110  ListContainsLR = true;
111  break;
112  case ARM::PC:
113  ListContainsPC = true;
114  break;
115  case ARM::SP:
116  Info = "use of SP in the list is deprecated";
117  return true;
118  }
119  }
120 
121  if (ListContainsPC && ListContainsLR) {
122  Info = "use of LR and PC simultaneously in the list is deprecated";
123  return true;
124  }
125 
126  return false;
127 }
128 
129 #define GET_INSTRINFO_MC_DESC
130 #include "ARMGenInstrInfo.inc"
131 
132 #define GET_SUBTARGETINFO_MC_DESC
133 #include "ARMGenSubtargetInfo.inc"
134 
135 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
136  std::string ARMArchFeature;
137 
139  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
140  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
141 
142  if (TT.isThumb()) {
143  if (!ARMArchFeature.empty())
144  ARMArchFeature += ",";
145  ARMArchFeature += "+thumb-mode,+v4t";
146  }
147 
148  if (TT.isOSNaCl()) {
149  if (!ARMArchFeature.empty())
150  ARMArchFeature += ",";
151  ARMArchFeature += "+nacl-trap";
152  }
153 
154  if (TT.isOSWindows()) {
155  if (!ARMArchFeature.empty())
156  ARMArchFeature += ",";
157  ARMArchFeature += "+noarm";
158  }
159 
160  return ARMArchFeature;
161 }
162 
164  StringRef CPU, StringRef FS) {
165  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
166  if (!FS.empty()) {
167  if (!ArchFS.empty())
168  ArchFS = (Twine(ArchFS) + "," + FS).str();
169  else
170  ArchFS = FS;
171  }
172 
173  return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
174 }
175 
177  MCInstrInfo *X = new MCInstrInfo();
178  InitARMMCInstrInfo(X);
179  return X;
180 }
181 
184  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
185  return X;
186 }
187 
189  const Triple &TheTriple) {
190  MCAsmInfo *MAI;
191  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
192  MAI = new ARMMCAsmInfoDarwin(TheTriple);
193  else if (TheTriple.isWindowsMSVCEnvironment())
194  MAI = new ARMCOFFMCAsmInfoMicrosoft();
195  else if (TheTriple.isOSWindows())
196  MAI = new ARMCOFFMCAsmInfoGNU();
197  else
198  MAI = new ARMELFMCAsmInfo(TheTriple);
199 
200  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
202 
203  return MAI;
204 }
205 
207  std::unique_ptr<MCAsmBackend> &&MAB,
208  std::unique_ptr<MCObjectWriter> &&OW,
209  std::unique_ptr<MCCodeEmitter> &&Emitter,
210  bool RelaxAll) {
211  return createARMELFStreamer(
212  Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
213  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb));
214 }
215 
216 static MCStreamer *
217 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
218  std::unique_ptr<MCObjectWriter> &&OW,
219  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
220  bool DWARFMustBeAtTheEnd) {
221  return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
222  std::move(Emitter), false, DWARFMustBeAtTheEnd);
223 }
224 
226  unsigned SyntaxVariant,
227  const MCAsmInfo &MAI,
228  const MCInstrInfo &MII,
229  const MCRegisterInfo &MRI) {
230  if (SyntaxVariant == 0)
231  return new ARMInstPrinter(MAI, MII, MRI);
232  return nullptr;
233 }
234 
236  MCContext &Ctx) {
237  if (TT.isOSBinFormatMachO())
238  return createARMMachORelocationInfo(Ctx);
239  // Default to the stock relocation info.
240  return llvm::createMCRelocationInfo(TT, Ctx);
241 }
242 
243 namespace {
244 
245 class ARMMCInstrAnalysis : public MCInstrAnalysis {
246 public:
247  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
248 
249  bool isUnconditionalBranch(const MCInst &Inst) const override {
250  // BCCs with the "always" predicate are unconditional branches.
251  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
252  return true;
254  }
255 
256  bool isConditionalBranch(const MCInst &Inst) const override {
257  // BCCs with the "always" predicate are unconditional branches.
258  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
259  return false;
261  }
262 
263  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
264  uint64_t Size, uint64_t &Target) const override {
265  // We only handle PCRel branches for now.
266  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
267  return false;
268 
269  int64_t Imm = Inst.getOperand(0).getImm();
270  Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
271  return true;
272  }
273 };
274 
275 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
276 public:
277  ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
278 
279  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
280  uint64_t Size, uint64_t &Target) const override {
281  // We only handle PCRel branches for now.
282  if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
283  return false;
284 
285  int64_t Imm = Inst.getOperand(0).getImm();
286  Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
287  return true;
288  }
289 };
290 
291 }
292 
294  return new ARMMCInstrAnalysis(Info);
295 }
296 
298  return new ThumbMCInstrAnalysis(Info);
299 }
300 
301 // Force static initialization.
302 extern "C" void LLVMInitializeARMTargetMC() {
305  // Register the MC asm info.
307 
308  // Register the MC instruction info.
310 
311  // Register the MC register info.
313 
314  // Register the MC subtarget info.
317 
321 
322  // Register the obj target streamer.
325 
326  // Register the asm streamer.
328 
329  // Register the null TargetStreamer.
331 
332  // Register the MCInstPrinter.
334 
335  // Register the MC relocation info.
337  }
338 
339  // Register the MC instruction analyzer.
340  for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
344 
345  for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
348  }
349  for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
352  }
353 }
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
bool isImm() const
Definition: MCInst.h:58
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static MCInstrAnalysis * createThumbMCInstrAnalysis(const MCInstrInfo *Info)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCInstrInfo * createARMMCInstrInfo()
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
unsigned Reg
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:570
virtual bool isConditionalBranch(const MCInst &Inst) const
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
bool isReg() const
Definition: MCInst.h:57
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Target & getTheThumbLETarget()
void LLVMInitializeARMTargetMC()
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const FeatureBitset & getFeatureBits() const
StringRef getArchName(ArchKind AK)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheARMBETarget()
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Target & getTheThumbBETarget()
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:600
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:208
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:527
int64_t getImm() const
Definition: MCInst.h:75
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Streaming machine code generation interface.
Definition: MCStreamer.h:188
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
Create MCExprs from relocations found in an object file.
unsigned getNumOperands() const
Definition: MCInst.h:181
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:612
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:966
ArchKind parseArch(StringRef Arch)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:663
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
uint32_t Size
Definition: Profile.cpp:46
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Target & getTheARMLETarget()
unsigned getOpcode() const
Definition: MCInst.h:171
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:537
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)