LLVM 19.0.0git
ARMMCTargetDesc.h
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1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides ARM specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15
17#include "llvm/MC/MCInstrDesc.h"
18#include <memory>
19#include <string>
20
21namespace llvm {
22class formatted_raw_ostream;
23class MCAsmBackend;
24class MCCodeEmitter;
25class MCContext;
26class MCInstrInfo;
27class MCInstPrinter;
28class MCObjectTargetWriter;
29class MCObjectWriter;
30class MCRegisterInfo;
31class MCSubtargetInfo;
32class MCStreamer;
33class MCTargetOptions;
34class MCRelocationInfo;
35class MCTargetStreamer;
36class StringRef;
37class Target;
38class Triple;
39
40namespace ARM_MC {
41std::string ParseARMTriple(const Triple &TT, StringRef CPU);
43
44bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
45bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
46
47template<class Inst>
48bool isLDMBaseRegInList(const Inst &MI) {
49 auto BaseReg = MI.getOperand(0).getReg();
50 for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
51 const auto &Op = MI.getOperand(I);
52 if (Op.isReg() && Op.getReg() == BaseReg)
53 return true;
54 }
55 return false;
56}
57
59 int64_t Imm);
60
61/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
62/// do not need to go through TargetRegistry.
64 StringRef FS);
65}
66
67MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
68MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
69 formatted_raw_ostream &OS,
70 MCInstPrinter *InstPrint,
71 bool isVerboseAsm);
72MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
73 const MCSubtargetInfo &STI);
74MCTargetStreamer *createARMObjectTargetELFStreamer(MCStreamer &S);
75MCTargetStreamer *createARMObjectTargetWinCOFFStreamer(MCStreamer &S);
76
77MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
78 MCContext &Ctx);
79
80MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
81 MCContext &Ctx);
82
83MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
84 const MCRegisterInfo &MRI,
85 const MCTargetOptions &Options);
86
87MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
88 const MCRegisterInfo &MRI,
89 const MCTargetOptions &Options);
90
91// Construct a PE/COFF machine code streamer which will generate a PE/COFF
92// object file.
93MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
94 std::unique_ptr<MCAsmBackend> &&MAB,
95 std::unique_ptr<MCObjectWriter> &&OW,
96 std::unique_ptr<MCCodeEmitter> &&Emitter,
97 bool RelaxAll,
98 bool IncrementalLinkerCompatible);
99
100/// Construct an ELF Mach-O object writer.
101std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
102
103/// Construct an ARM Mach-O object writer.
104std::unique_ptr<MCObjectTargetWriter>
105createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
106 uint32_t CPUSubtype);
107
108/// Construct an ARM PE/COFF object writer.
109std::unique_ptr<MCObjectTargetWriter>
111
112/// Construct ARM Mach-O relocation info.
113MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
114
115namespace ARM {
119};
120inline bool isVpred(OperandType op) {
121 return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
122}
123inline bool isVpred(uint8_t op) {
124 return isVpred(static_cast<OperandType>(op));
125}
126
127bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);
128
129} // end namespace ARM
130
131} // End llvm namespace
132
133// Defines symbolic names for ARM registers. This defines a mapping from
134// register name to register number.
135//
136#define GET_REGINFO_ENUM
137#include "ARMGenRegisterInfo.inc"
138
139// Defines symbolic names for the ARM instructions.
140//
141#define GET_INSTRINFO_ENUM
142#define GET_INSTRINFO_MC_HELPER_DECLS
143#include "ARMGenInstrInfo.inc"
144
145#define GET_SUBTARGETINFO_ENUM
146#include "ARMGenSubtargetInfo.inc"
147
148#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
dxil DXContainer Global Emitter
uint64_t Addr
#define op(i)
IRTranslator LLVM IR MI
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
raw_pwrite_stream & OS
This class represents an Operation in the Expression.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isLDMBaseRegInList(const Inst &MI)
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
bool isVpred(OperandType op)
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an ARM Mach-O object writer.
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
MCTargetStreamer * createARMObjectTargetELFStreamer(MCStreamer &S)
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
std::unique_ptr< MCObjectTargetWriter > createARMELFObjectWriter(uint8_t OSABI)
Construct an ELF Mach-O object writer.
MCTargetStreamer * createARMObjectTargetWinCOFFStreamer(MCStreamer &S)
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
std::unique_ptr< MCObjectTargetWriter > createARMWinCOFFObjectWriter()
Construct an ARM PE/COFF object writer.
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)