22 #define GET_TARGET_REGBANK_IMPL 23 #include "ARMGenRegisterBank.inc" 50 unsigned Start,
unsigned Length,
59 "Wrong mapping for GPR");
62 "Wrong mapping for SPR");
65 "Wrong mapping for DPR");
101 "Wrong value mapping for 3 GPR ops instruction");
104 "Wrong value mapping for 3 GPR ops instruction");
107 "Wrong value mapping for 3 GPR ops instruction");
111 "Wrong value mapping for 3 SPR ops instruction");
114 "Wrong value mapping for 3 SPR ops instruction");
117 "Wrong value mapping for 3 SPR ops instruction");
121 "Wrong value mapping for 3 DPR ops instruction");
124 "Wrong value mapping for 3 DPR ops instruction");
127 "Wrong value mapping for 3 DPR ops instruction");
135 static bool AlreadyInit =
false;
147 assert(&ARM::GPRRegBank == &RBGPR &&
"The order in RegBanks is messed up");
151 "Subclass not added?");
153 "Subclass not added?");
155 "Subclass not added?");
157 "Subclass not added?");
159 "Subclass not added?");
161 "Subclass not added?");
163 "Subclass not added?");
164 assert(RBGPR.
getSize() == 32 &&
"GPRs should hold up to 32-bit");
176 switch (RC.
getID()) {
178 case GPRnopcRegClassID:
179 case GPRspRegClassID:
180 case tGPR_and_tcGPRRegClassID:
183 case SPR_8RegClassID:
185 case DPR_8RegClassID:
207 using namespace TargetOpcode;
372 "Mismatched operand sizes for G_FCMP");
375 assert((Size == 32 || Size == 64) &&
"Unsupported size for G_FCMP");
381 FPRValueMapping, FPRValueMapping});
384 case G_MERGE_VALUES: {
399 case G_UNMERGE_VALUES: {
426 for (
unsigned i = 0; i < NumOperands; i++) {
427 for (
const auto &Mapping : OperandsMapping[i]) {
429 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
431 "Trying to use floating point register bank on target without vfp");
static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, RegisterBankInfo::PartialMapping *BreakDown)
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
Compute iterated dominance frontiers using a linear time algorithm.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getReg() const
getReg - Returns the register number.
setjmp/longjmp based exceptions
static void checkValueMappings()
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getID() const
Return the register class ID number.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned const MachineRegisterInfo * MRI
This file declares the targeting of the RegisterBankInfo class for ARM.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
RegisterBankInfo::ValueMapping ValueMappings[]
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
RegisterBankInfo::PartialMapping PartMappings[]
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isValid() const
Check whether this object is valid.
ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
static void checkPartialMappings()
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
This class implements the register bank concept.
Helper struct that represents how a value is mapped through different register banks.
static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)
const MachineBasicBlock * getParent() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
unsigned NumBreakDowns
Number of partial mapping to break down this value.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
const MachineOperand & getOperand(unsigned i) const
unsigned getID() const
Get the identifier of this register bank.