LLVM  8.0.0svn
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16 
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMISelLowering.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSchedule.h"
33 #include <memory>
34 #include <string>
35 
36 #define GET_SUBTARGETINFO_HEADER
37 #include "ARMGenSubtargetInfo.inc"
38 
39 namespace llvm {
40 
41 class ARMBaseTargetMachine;
42 class GlobalValue;
43 class StringRef;
44 
46 protected:
49 
75  };
78 
82  };
83  enum ARMArchEnum {
114  };
115 
116 public:
117  /// What kind of timing do load multiple/store multiple instructions have.
119  /// Can load/store 2 registers/cycle.
121  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
122  /// is not 64-bit aligned.
124  /// Can load/store 1 register/cycle.
126  /// Can load/store 1 register/cycle, but needs an extra cycle for address
127  /// computation and potentially also for register writeback.
129  };
130 
131 protected:
132  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
134 
135  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
137 
138  /// ARMArch - ARM architecture
140 
141  /// HasV4TOps, HasV5TOps, HasV5TEOps,
142  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
143  /// Specify whether target support specific ARM ISA variants.
144  bool HasV4TOps = false;
145  bool HasV5TOps = false;
146  bool HasV5TEOps = false;
147  bool HasV6Ops = false;
148  bool HasV6MOps = false;
149  bool HasV6KOps = false;
150  bool HasV6T2Ops = false;
151  bool HasV7Ops = false;
152  bool HasV8Ops = false;
153  bool HasV8_1aOps = false;
154  bool HasV8_2aOps = false;
155  bool HasV8_3aOps = false;
156  bool HasV8_4aOps = false;
157  bool HasV8_5aOps = false;
158  bool HasV8MBaselineOps = false;
159  bool HasV8MMainlineOps = false;
160 
161  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
162  /// floating point ISAs are supported.
163  bool HasVFPv2 = false;
164  bool HasVFPv3 = false;
165  bool HasVFPv4 = false;
166  bool HasFPARMv8 = false;
167  bool HasNEON = false;
168 
169  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
170  bool HasDotProd = false;
171 
172  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
173  /// specified. Use the method useNEONForSinglePrecisionFP() to
174  /// determine if NEON should actually be used.
176 
177  /// UseMulOps - True if non-microcoded fused integer multiply-add and
178  /// multiply-subtract instructions should be used.
179  bool UseMulOps = false;
180 
181  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
182  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
183  bool SlowFPVMLx = false;
184 
185  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
186  /// forwarding to allow mul + mla being issued back to back.
187  bool HasVMLxForwarding = false;
188 
189  /// SlowFPBrcc - True if floating point compare + branch is slow.
190  bool SlowFPBrcc = false;
191 
192  /// InThumbMode - True if compiling for Thumb, false for ARM.
193  bool InThumbMode = false;
194 
195  /// UseSoftFloat - True if we're using software floating point features.
196  bool UseSoftFloat = false;
197 
198  /// UseMISched - True if MachineScheduler should be used for this subtarget.
199  bool UseMISched = false;
200 
201  /// DisablePostRAScheduler - False if scheduling should happen again after
202  /// register allocation.
204 
205  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
206  bool UseAA = false;
207 
208  /// HasThumb2 - True if Thumb2 instructions are supported.
209  bool HasThumb2 = false;
210 
211  /// NoARM - True if subtarget does not support ARM mode execution.
212  bool NoARM = false;
213 
214  /// ReserveR9 - True if R9 is not available as a general purpose register.
215  bool ReserveR9 = false;
216 
217  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
218  /// 32-bit imms (including global addresses).
219  bool NoMovt = false;
220 
221  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
222  /// must be able to synthesize call stubs for interworking between ARM and
223  /// Thumb.
224  bool SupportsTailCall = false;
225 
226  /// HasFP16 - True if subtarget supports half-precision FP conversions
227  bool HasFP16 = false;
228 
229  /// HasFullFP16 - True if subtarget supports half-precision FP operations
230  bool HasFullFP16 = false;
231 
232  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
233  bool HasFP16FML = false;
234 
235  /// HasD16 - True if subtarget is limited to 16 double precision
236  /// FP registers for VFPv3.
237  bool HasD16 = false;
238 
239  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
241 
242  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
244 
245  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
246  /// instructions.
247  bool HasDataBarrier = false;
248 
249  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
250  /// instruction.
251  bool HasFullDataBarrier = false;
252 
253  /// HasV7Clrex - True if the subtarget supports CLREX instructions
254  bool HasV7Clrex = false;
255 
256  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
257  /// instructions
258  bool HasAcquireRelease = false;
259 
260  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
261  /// over 16-bit ones.
262  bool Pref32BitThumb = false;
263 
264  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
265  /// that partially update CPSR and add false dependency on the previous
266  /// CPSR setting instruction.
268 
269  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
270  /// for instructions updating CPSR. Enabled for Cortex-A57.
272 
273  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
274  /// movs with shifter operand (i.e. asr, lsl, lsr).
276 
277  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
278  /// avoid issue "normal" call instructions to callees which do not return.
279  bool HasRetAddrStack = false;
280 
281  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
282  /// a branch predictor or not changes the expected cost of taking a branch
283  /// which affects the choice of whether to use predicated instructions.
284  bool HasBranchPredictor = true;
285 
286  /// HasMPExtension - True if the subtarget supports Multiprocessing
287  /// extension (ARMv7 only).
288  bool HasMPExtension = false;
289 
290  /// HasVirtualization - True if the subtarget supports the Virtualization
291  /// extension.
292  bool HasVirtualization = false;
293 
294  /// FPOnlySP - If true, the floating point unit only supports single
295  /// precision.
296  bool FPOnlySP = false;
297 
298  /// If true, the processor supports the Performance Monitor Extensions. These
299  /// include a generic cycle-counter as well as more fine-grained (often
300  /// implementation-specific) events.
301  bool HasPerfMon = false;
302 
303  /// HasTrustZone - if true, processor supports TrustZone security extensions
304  bool HasTrustZone = false;
305 
306  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
307  bool Has8MSecExt = false;
308 
309  /// HasSHA2 - if true, processor supports SHA1 and SHA256
310  bool HasSHA2 = false;
311 
312  /// HasAES - if true, processor supports AES
313  bool HasAES = false;
314 
315  /// HasCrypto - if true, processor supports Cryptography extensions
316  bool HasCrypto = false;
317 
318  /// HasCRC - if true, processor supports CRC instructions
319  bool HasCRC = false;
320 
321  /// HasRAS - if true, the processor supports RAS extensions
322  bool HasRAS = false;
323 
324  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
325  /// particularly effective at zeroing a VFP register.
326  bool HasZeroCycleZeroing = false;
327 
328  /// HasFPAO - if true, processor does positive address offset computation faster
329  bool HasFPAO = false;
330 
331  /// HasFuseAES - if true, processor executes back to back AES instruction
332  /// pairs faster.
333  bool HasFuseAES = false;
334 
335  /// HasFuseLiterals - if true, processor executes back to back
336  /// bottom and top halves of literal generation faster.
337  bool HasFuseLiterals = false;
338 
339  /// If true, if conversion may decide to leave some instructions unpredicated.
341 
342  /// If true, VMOV will be favored over VGETLNi32.
343  bool HasSlowVGETLNi32 = false;
344 
345  /// If true, VMOV will be favored over VDUP.
346  bool HasSlowVDUP32 = false;
347 
348  /// If true, VMOVSR will be favored over VMOVDRR.
349  bool PreferVMOVSR = false;
350 
351  /// If true, ISHST barriers will be used for Release semantics.
352  bool PreferISHST = false;
353 
354  /// If true, a VLDM/VSTM starting with an odd register number is considered to
355  /// take more microops than single VLDRS/VSTRS.
356  bool SlowOddRegister = false;
357 
358  /// If true, loading into a D subregister will be penalized.
359  bool SlowLoadDSubregister = false;
360 
361  /// If true, use a wider stride when allocating VFP registers.
362  bool UseWideStrideVFP = false;
363 
364  /// If true, the AGU and NEON/FPU units are multiplexed.
365  bool HasMuxedUnits = false;
366 
367  /// If true, VMOVS will never be widened to VMOVD.
368  bool DontWidenVMOVS = false;
369 
370  /// If true, splat a register between VFP and NEON instructions.
371  bool SplatVFPToNeon = false;
372 
373  /// If true, run the MLx expansion pass.
374  bool ExpandMLx = false;
375 
376  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
377  bool HasVMLxHazards = false;
378 
379  // If true, read thread pointer from coprocessor register.
380  bool ReadTPHard = false;
381 
382  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
383  bool UseNEONForFPMovs = false;
384 
385  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
386  bool CheckVLDnAlign = false;
387 
388  /// If true, VFP instructions are not pipelined.
389  bool NonpipelinedVFP = false;
390 
391  /// StrictAlign - If true, the subtarget disallows unaligned memory
392  /// accesses for some types. For details, see
393  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
394  bool StrictAlign = false;
395 
396  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
397  /// blocks to conform to ARMv8 rule.
398  bool RestrictIT = false;
399 
400  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
401  /// and such) instructions.
402  bool HasDSP = false;
403 
404  /// NaCl TRAP instruction is generated instead of the regular TRAP.
405  bool UseNaClTrap = false;
406 
407  /// Generate calls via indirect call instructions.
408  bool GenLongCalls = false;
409 
410  /// Generate code that does not contain data access to code sections.
411  bool GenExecuteOnly = false;
412 
413  /// Target machine allowed unsafe FP math (such as use of NEON fp)
414  bool UnsafeFPMath = false;
415 
416  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
417  bool UseSjLjEH = false;
418 
419  /// Has speculation barrier
420  bool HasSpecCtrl = false;
421 
422  /// Implicitly convert an instruction to a different one if its immediates
423  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
424  bool NegativeImmediates = true;
425 
426  /// stackAlignment - The minimum alignment known to hold of the stack frame on
427  /// entry to the function and which must be maintained by every function.
428  unsigned stackAlignment = 4;
429 
430  /// CPUString - String name of used CPU.
431  std::string CPUString;
432 
433  unsigned MaxInterleaveFactor = 1;
434 
435  /// Clearance before partial register updates (in number of instructions)
437 
438  /// What kind of timing do load multiple/store multiple have (double issue,
439  /// single issue etc).
441 
442  /// The adjustment that we need to apply to get the operand latency from the
443  /// operand cycle returned by the itinerary data for pre-ISel operands.
445 
446  /// What alignment is preferred for loop bodies, in log2(bytes).
447  unsigned PrefLoopAlignment = 0;
448 
449  /// IsLittle - The target is Little Endian
450  bool IsLittle;
451 
452  /// TargetTriple - What processor and OS we're targeting.
454 
455  /// SchedModel - Processor specific instruction costs.
457 
458  /// Selected instruction itineraries (one entry per itinerary class.)
460 
461  /// Options passed via command line that could influence the target
463 
465 
466 public:
467  /// This constructor initializes the data members to match that
468  /// of the specified triple.
469  ///
470  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
471  const ARMBaseTargetMachine &TM, bool IsLittle);
472 
473  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
474  /// that still makes it profitable to inline the call.
475  unsigned getMaxInlineSizeThreshold() const {
476  return 64;
477  }
478 
479  /// ParseSubtargetFeatures - Parses features string setting specified
480  /// subtarget options. Definition of function is auto generated by tblgen.
482 
483  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
484  /// so that we can use initializer lists for subtarget initialization.
486 
487  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
488  return &TSInfo;
489  }
490 
491  const ARMBaseInstrInfo *getInstrInfo() const override {
492  return InstrInfo.get();
493  }
494 
495  const ARMTargetLowering *getTargetLowering() const override {
496  return &TLInfo;
497  }
498 
499  const ARMFrameLowering *getFrameLowering() const override {
500  return FrameLowering.get();
501  }
502 
503  const ARMBaseRegisterInfo *getRegisterInfo() const override {
504  return &InstrInfo->getRegisterInfo();
505  }
506 
507  const CallLowering *getCallLowering() const override;
508  const InstructionSelector *getInstructionSelector() const override;
509  const LegalizerInfo *getLegalizerInfo() const override;
510  const RegisterBankInfo *getRegBankInfo() const override;
511 
512 private:
513  ARMSelectionDAGInfo TSInfo;
514  // Either Thumb1FrameLowering or ARMFrameLowering.
515  std::unique_ptr<ARMFrameLowering> FrameLowering;
516  // Either Thumb1InstrInfo or Thumb2InstrInfo.
517  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
518  ARMTargetLowering TLInfo;
519 
520  /// GlobalISel related APIs.
521  std::unique_ptr<CallLowering> CallLoweringInfo;
522  std::unique_ptr<InstructionSelector> InstSelector;
523  std::unique_ptr<LegalizerInfo> Legalizer;
524  std::unique_ptr<RegisterBankInfo> RegBankInfo;
525 
526  void initializeEnvironment();
527  void initSubtargetFeatures(StringRef CPU, StringRef FS);
528  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
529 
530 public:
531  void computeIssueWidth();
532 
533  bool hasV4TOps() const { return HasV4TOps; }
534  bool hasV5TOps() const { return HasV5TOps; }
535  bool hasV5TEOps() const { return HasV5TEOps; }
536  bool hasV6Ops() const { return HasV6Ops; }
537  bool hasV6MOps() const { return HasV6MOps; }
538  bool hasV6KOps() const { return HasV6KOps; }
539  bool hasV6T2Ops() const { return HasV6T2Ops; }
540  bool hasV7Ops() const { return HasV7Ops; }
541  bool hasV8Ops() const { return HasV8Ops; }
542  bool hasV8_1aOps() const { return HasV8_1aOps; }
543  bool hasV8_2aOps() const { return HasV8_2aOps; }
544  bool hasV8_3aOps() const { return HasV8_3aOps; }
545  bool hasV8_4aOps() const { return HasV8_4aOps; }
546  bool hasV8_5aOps() const { return HasV8_5aOps; }
547  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
548  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
549 
550  /// @{
551  /// These functions are obsolete, please consider adding subtarget features
552  /// or properties instead of calling them.
553  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
554  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
555  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
556  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
557  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
558  bool isSwift() const { return ARMProcFamily == Swift; }
559  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
560  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
561  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
562  bool isKrait() const { return ARMProcFamily == Krait; }
563  /// @}
564 
565  bool hasARMOps() const { return !NoARM; }
566 
567  bool hasVFP2() const { return HasVFPv2; }
568  bool hasVFP3() const { return HasVFPv3; }
569  bool hasVFP4() const { return HasVFPv4; }
570  bool hasFPARMv8() const { return HasFPARMv8; }
571  bool hasNEON() const { return HasNEON; }
572  bool hasSHA2() const { return HasSHA2; }
573  bool hasAES() const { return HasAES; }
574  bool hasCrypto() const { return HasCrypto; }
575  bool hasDotProd() const { return HasDotProd; }
576  bool hasCRC() const { return HasCRC; }
577  bool hasRAS() const { return HasRAS; }
578  bool hasVirtualization() const { return HasVirtualization; }
579 
582  }
583 
586  bool hasDataBarrier() const { return HasDataBarrier; }
587  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
588  bool hasV7Clrex() const { return HasV7Clrex; }
589  bool hasAcquireRelease() const { return HasAcquireRelease; }
590 
591  bool hasAnyDataBarrier() const {
592  return HasDataBarrier || (hasV6Ops() && !isThumb());
593  }
594 
595  bool useMulOps() const { return UseMulOps; }
596  bool useFPVMLx() const { return !SlowFPVMLx; }
597  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
598  bool isFPBrccSlow() const { return SlowFPBrcc; }
599  bool isFPOnlySP() const { return FPOnlySP; }
600  bool hasPerfMon() const { return HasPerfMon; }
601  bool hasTrustZone() const { return HasTrustZone; }
602  bool has8MSecExt() const { return Has8MSecExt; }
603  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
604  bool hasFPAO() const { return HasFPAO; }
606  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
607  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
608  bool preferVMOVSR() const { return PreferVMOVSR; }
609  bool preferISHSTBarriers() const { return PreferISHST; }
610  bool expandMLx() const { return ExpandMLx; }
611  bool hasVMLxHazards() const { return HasVMLxHazards; }
612  bool hasSlowOddRegister() const { return SlowOddRegister; }
614  bool useWideStrideVFP() const { return UseWideStrideVFP; }
615  bool hasMuxedUnits() const { return HasMuxedUnits; }
616  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
617  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
618  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
619  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
620  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
621  bool prefers32BitThumb() const { return Pref32BitThumb; }
625  bool hasRetAddrStack() const { return HasRetAddrStack; }
626  bool hasBranchPredictor() const { return HasBranchPredictor; }
627  bool hasMPExtension() const { return HasMPExtension; }
628  bool hasDSP() const { return HasDSP; }
629  bool useNaClTrap() const { return UseNaClTrap; }
630  bool useSjLjEH() const { return UseSjLjEH; }
631  bool hasSpecCtrl() const { return HasSpecCtrl; }
632  bool genLongCalls() const { return GenLongCalls; }
633  bool genExecuteOnly() const { return GenExecuteOnly; }
634 
635  bool hasFP16() const { return HasFP16; }
636  bool hasD16() const { return HasD16; }
637  bool hasFullFP16() const { return HasFullFP16; }
638  bool hasFP16FML() const { return HasFP16FML; }
639 
640  bool hasFuseAES() const { return HasFuseAES; }
641  bool hasFuseLiterals() const { return HasFuseLiterals; }
642  /// Return true if the CPU supports any kind of instruction fusion.
643  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
644 
645  const Triple &getTargetTriple() const { return TargetTriple; }
646 
647  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
648  bool isTargetIOS() const { return TargetTriple.isiOS(); }
649  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
650  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
651  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
652  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
653  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
654  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
655 
656  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
657  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
658  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
659 
660  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
661  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
662  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
663  // even for GNUEABI, so we can make a distinction here and still conform to
664  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
665  // FIXME: The Darwin exception is temporary, while we move users to
666  // "*-*-*-macho" triples as quickly as possible.
667  bool isTargetAEABI() const {
668  return (TargetTriple.getEnvironment() == Triple::EABI ||
669  TargetTriple.getEnvironment() == Triple::EABIHF) &&
671  }
672  bool isTargetGNUAEABI() const {
673  return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
674  TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
676  }
677  bool isTargetMuslAEABI() const {
678  return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
679  TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
681  }
682 
683  // ARM Targets that support EHABI exception handling standard
684  // Darwin uses SjLj. Other targets might need more checks.
685  bool isTargetEHABICompatible() const {
686  return (TargetTriple.getEnvironment() == Triple::EABI ||
687  TargetTriple.getEnvironment() == Triple::GNUEABI ||
688  TargetTriple.getEnvironment() == Triple::MuslEABI ||
689  TargetTriple.getEnvironment() == Triple::EABIHF ||
690  TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
691  TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
692  isTargetAndroid()) &&
694  }
695 
696  bool isTargetHardFloat() const;
697 
698  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
699 
700  bool isXRaySupported() const override;
701 
702  bool isAPCS_ABI() const;
703  bool isAAPCS_ABI() const;
704  bool isAAPCS16_ABI() const;
705 
706  bool isROPI() const;
707  bool isRWPI() const;
708 
709  bool useMachineScheduler() const { return UseMISched; }
711  bool useSoftFloat() const { return UseSoftFloat; }
712  bool isThumb() const { return InThumbMode; }
713  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
714  bool isThumb2() const { return InThumbMode && HasThumb2; }
715  bool hasThumb2() const { return HasThumb2; }
716  bool isMClass() const { return ARMProcClass == MClass; }
717  bool isRClass() const { return ARMProcClass == RClass; }
718  bool isAClass() const { return ARMProcClass == AClass; }
719  bool isReadTPHard() const { return ReadTPHard; }
720 
721  bool isR9Reserved() const {
722  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
723  }
724 
725  bool useR7AsFramePointer() const {
726  return isTargetDarwin() || (!isTargetWindows() && isThumb());
727  }
728 
729  /// Returns true if the frame setup is split into two separate pushes (first
730  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
731  /// to lr. This is always required on Thumb1-only targets, as the push and
732  /// pop instructions can't access the high registers.
733  bool splitFramePushPop(const MachineFunction &MF) const {
734  return (useR7AsFramePointer() &&
736  isThumb1Only();
737  }
738 
739  bool useStride4VFPs(const MachineFunction &MF) const;
740 
741  bool useMovt(const MachineFunction &MF) const;
742 
743  bool supportsTailCall() const { return SupportsTailCall; }
744 
745  bool allowsUnalignedMem() const { return !StrictAlign; }
746 
747  bool restrictIT() const { return RestrictIT; }
748 
749  const std::string & getCPUString() const { return CPUString; }
750 
751  bool isLittle() const { return IsLittle; }
752 
753  unsigned getMispredictionPenalty() const;
754 
755  /// Returns true if machine scheduler should be enabled.
756  bool enableMachineScheduler() const override;
757 
758  /// True for some subtargets at > -O0.
759  bool enablePostRAScheduler() const override;
760 
761  /// Enable use of alias analysis during code generation (during MI
762  /// scheduling, DAGCombine, etc.).
763  bool useAA() const override { return UseAA; }
764 
765  // enableAtomicExpand- True if we need to expand our atomics.
766  bool enableAtomicExpand() const override;
767 
768  /// getInstrItins - Return the instruction itineraries based on subtarget
769  /// selection.
770  const InstrItineraryData *getInstrItineraryData() const override {
771  return &InstrItins;
772  }
773 
774  /// getStackAlignment - Returns the minimum alignment known to hold of the
775  /// stack frame on entry to the function and which must be maintained by every
776  /// function for this subtarget.
777  unsigned getStackAlignment() const { return stackAlignment; }
778 
779  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
780 
782 
784  return LdStMultipleTiming;
785  }
786 
789  }
790 
791  /// True if the GV will be accessed via an indirect symbol.
792  bool isGVIndirectSymbol(const GlobalValue *GV) const;
793 
794  /// Returns the constant pool modifier needed to access the GV.
795  bool isGVInGOT(const GlobalValue *GV) const;
796 
797  /// True if fast-isel is used.
798  bool useFastISel() const;
799 
800  /// Returns the correct return opcode for the current feature set.
801  /// Use BX if available to allow mixing thumb/arm code, but fall back
802  /// to plain mov pc,lr on ARMv4.
803  unsigned getReturnOpcode() const {
804  if (isThumb())
805  return ARM::tBX_RET;
806  if (hasV4TOps())
807  return ARM::BX_RET;
808  return ARM::MOVPCLR;
809  }
810 
811  /// Allow movt+movw for PIC global address calculation.
812  /// ELF does not have GOT relocations for movt+movw.
813  /// ROPI does not use GOT.
815  return isROPI() || !isTargetELF();
816  }
817 
818  unsigned getPrefLoopAlignment() const {
819  return PrefLoopAlignment;
820  }
821 };
822 
823 } // end namespace llvm
824 
825 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:219
bool hasV5TEOps() const
Definition: ARMSubtarget.h:535
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
bool hasCRC() const
Definition: ARMSubtarget.h:576
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:383
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:672
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:543
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:428
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:374
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:453
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:619
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:622
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:284
bool hasRAS() const
Definition: ARMSubtarget.h:577
bool HasSpecCtrl
Has speculation barrier.
Definition: ARMSubtarget.h:420
bool hasSHA2() const
Definition: ARMSubtarget.h:572
bool isThumb() const
Definition: ARMSubtarget.h:712
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:584
bool SplatVFPToNeon
If true, splat a register between VFP and NEON instructions.
Definition: ARMSubtarget.h:371
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:183
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:359
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:487
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:592
bool hasV4TOps() const
Definition: ARMSubtarget.h:533
bool isLittle() const
Definition: ARMSubtarget.h:751
bool useFastISel() const
True if fast-isel is used.
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:626
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:279
bool isTargetNaCl() const
Definition: ARMSubtarget.h:652
bool hasFuseAES() const
Definition: ARMSubtarget.h:640
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:495
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:230
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:240
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:346
bool preferVMOVSR() const
Definition: ARMSubtarget.h:608
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:571
bool hasV7Ops() const
Definition: ARMSubtarget.h:540
bool hasV8_5aOps() const
Definition: ARMSubtarget.h:546
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:621
bool isCortexA5() const
Definition: ARMSubtarget.h:553
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:465
bool hasVFP3() const
Definition: ARMSubtarget.h:568
bool isTargetCOFF() const
Definition: ARMSubtarget.h:656
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:163
bool useNaClTrap() const
Definition: ARMSubtarget.h:629
bool UseAA
UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
Definition: ARMSubtarget.h:206
bool hasV6Ops() const
Definition: ARMSubtarget.h:536
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:243
bool hasDotProd() const
Definition: ARMSubtarget.h:575
bool isThumb1Only() const
Definition: ARMSubtarget.h:713
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:677
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:589
const LegalizerInfo * getLegalizerInfo() const override
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:624
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:464
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:408
bool isTargetHardFloat() const
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:653
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:224
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:607
bool isFPOnlySP() const
Definition: ARMSubtarget.h:599
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:365
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:343
bool isRClass() const
Definition: ARMSubtarget.h:717
bool genExecuteOnly() const
Definition: ARMSubtarget.h:633
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:779
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:179
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:491
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:547
bool isTargetELF() const
Definition: ARMSubtarget.h:657
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:125
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:307
Holds all the information related to register banks.
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:322
bool hasARMOps() const
Definition: ARMSubtarget.h:565
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:356
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:326
bool hasV8_4aOps() const
Definition: ARMSubtarget.h:545
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:394
bool hasV8Ops() const
Definition: ARMSubtarget.h:541
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:209
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:333
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:414
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:618
bool hasPerfMon() const
Definition: ARMSubtarget.h:600
bool hasFuseLiterals() const
Definition: ARMSubtarget.h:641
bool useStride4VFPs(const MachineFunction &MF) const
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:368
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool hasVFP2() const
Definition: ARMSubtarget.h:567
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:349
bool isReadTPHard() const
Definition: ARMSubtarget.h:719
bool isCortexM3() const
Definition: ARMSubtarget.h:559
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:262
bool isCortexR5() const
Definition: ARMSubtarget.h:561
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:450
bool hasDSP() const
Definition: ARMSubtarget.h:628
bool useFPVMLx() const
Definition: ARMSubtarget.h:596
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:475
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:733
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:587
bool useMovt(const MachineFunction &MF) const
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:118
bool enableAtomicExpand() const override
bool hasVirtualization() const
Definition: ARMSubtarget.h:578
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:123
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:615
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isXRaySupported() const override
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:685
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:212
bool HasFuseLiterals
HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generatio...
Definition: ARMSubtarget.h:337
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:580
bool hasFPAO() const
Definition: ARMSubtarget.h:604
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:781
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:539
bool isTargetDarwin() const
Definition: ARMSubtarget.h:647
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:444
bool HasAES
HasAES - if true, processor supports AES.
Definition: ARMSubtarget.h:313
bool hasV6MOps() const
Definition: ARMSubtarget.h:537
Itinerary data supplied by a subtarget to be used by a target.
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:455
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:424
bool isOSNetBSD() const
Definition: Triple.h:482
bool isAClass() const
Definition: ARMSubtarget.h:718
bool hasFP16() const
Definition: ARMSubtarget.h:635
bool hasD16() const
Definition: ARMSubtarget.h:636
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:725
bool isR9Reserved() const
Definition: ARMSubtarget.h:721
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:301
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:606
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:585
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:650
bool hasCrypto() const
Definition: ARMSubtarget.h:574
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:566
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:275
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:319
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:605
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:402
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:254
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:609
bool hasV6KOps() const
Definition: ARMSubtarget.h:538
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:292
bool has8MSecExt() const
Definition: ARMSubtarget.h:602
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:777
bool restrictIT() const
Definition: ARMSubtarget.h:747
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:133
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:398
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:597
bool isMClass() const
Definition: ARMSubtarget.h:716
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:340
bool isWatchABI() const
Definition: Triple.h:469
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:199
bool useMachineScheduler() const
Definition: ARMSubtarget.h:709
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:144
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:187
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:649
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:203
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:377
bool hasFPARMv8() const
Definition: ARMSubtarget.h:570
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:316
bool useMulOps() const
Definition: ARMSubtarget.h:595
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:620
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:613
unsigned getMispredictionPenalty() const
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:288
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:745
bool hasTrustZone() const
Definition: ARMSubtarget.h:601
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:499
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:612
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:602
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:170
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
bool useSjLjEH() const
Definition: ARMSubtarget.h:630
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:389
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:783
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasV7Clrex() const
Definition: ARMSubtarget.h:588
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:614
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:227
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:304
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:193
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool hasAES() const
Definition: ARMSubtarget.h:573
const std::string & getCPUString() const
Definition: ARMSubtarget.h:749
bool isCortexA9() const
Definition: ARMSubtarget.h:556
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useSoftFloat() const
Definition: ARMSubtarget.h:711
bool isTargetAEABI() const
Definition: ARMSubtarget.h:667
bool isTargetLinux() const
Definition: ARMSubtarget.h:651
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:770
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:598
const InstructionSelector * getInstructionSelector() const override
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:623
bool isTargetAndroid() const
Definition: ARMSubtarget.h:698
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:139
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:814
bool hasMPExtension() const
Definition: ARMSubtarget.h:627
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:576
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
Definition: ARMSubtarget.h:296
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:136
bool hasNEON() const
Definition: ARMSubtarget.h:571
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:307
bool UseWideStrideVFP
If true, use a wider stride when allocating VFP registers.
Definition: ARMSubtarget.h:362
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:411
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:405
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR...
Definition: ARMSubtarget.h:271
unsigned getPrefLoopAlignment() const
Definition: ARMSubtarget.h:818
unsigned PrefLoopAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:447
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:456
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:352
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:710
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:462
bool genLongCalls() const
Definition: ARMSubtarget.h:632
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool UseSoftFloat
UseSoftFloat - True if we&#39;re using software floating point features.
Definition: ARMSubtarget.h:196
bool isROPI() const
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:803
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:597
bool expandMLx() const
Definition: ARMSubtarget.h:610
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:542
Provides the logic to select generic machine instructions.
bool isThumb2() const
Definition: ARMSubtarget.h:714
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:645
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:603
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:625
bool isTargetIOS() const
Definition: ARMSubtarget.h:648
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:215
bool hasSpecCtrl() const
Definition: ARMSubtarget.h:631
TargetOptions Options
Definition: TargetMachine.h:97
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:459
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:175
bool isCortexA7() const
Definition: ARMSubtarget.h:554
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:503
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:617
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:436
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:787
bool hasV5TOps() const
Definition: ARMSubtarget.h:534
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool HasFP16FML
HasFP16FML - True if subtarget supports half-precision FP fml operations.
Definition: ARMSubtarget.h:233
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:611
bool isTargetMachO() const
Definition: ARMSubtarget.h:658
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:190
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:440
bool isKrait() const
Definition: ARMSubtarget.h:562
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:237
bool isSwift() const
Definition: ARMSubtarget.h:558
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool supportsTailCall() const
Definition: ARMSubtarget.h:743
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:128
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:267
bool isCortexA8() const
Definition: ARMSubtarget.h:555
This file describes how to lower LLVM calls to machine code calls.
bool hasVFP4() const
Definition: ARMSubtarget.h:569
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:625
bool isRWPI() const
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:548
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:120
bool isTargetWindows() const
Definition: ARMSubtarget.h:654
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction. ...
Definition: ARMSubtarget.h:251
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:431
bool isCortexA15() const
Definition: ARMSubtarget.h:557
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:258
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:643
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:591
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition: ARMSubtarget.h:763
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:329
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:247
bool isAAPCS_ABI() const
bool hasDataBarrier() const
Definition: ARMSubtarget.h:586
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:242
bool hasFP16FML() const
Definition: ARMSubtarget.h:638
bool hasThumb2() const
Definition: ARMSubtarget.h:715
bool isLikeA9() const
Definition: ARMSubtarget.h:560
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:386
bool HasSHA2
HasSHA2 - if true, processor supports SHA1 and SHA256.
Definition: ARMSubtarget.h:310
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:417
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:616
bool hasFullFP16() const
Definition: ARMSubtarget.h:637
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:433
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:544