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ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the ARM specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMISelLowering.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
30 #include "llvm/MC/MCSchedule.h"
32 #include <memory>
33 #include <string>
34 
35 #define GET_SUBTARGETINFO_HEADER
36 #include "ARMGenSubtargetInfo.inc"
37 
38 namespace llvm {
39 
40 class ARMBaseTargetMachine;
41 class GlobalValue;
42 class StringRef;
43 
45 protected:
48 
75  };
78 
82  };
83  enum ARMArchEnum {
115  };
116 
117 public:
118  /// What kind of timing do load multiple/store multiple instructions have.
120  /// Can load/store 2 registers/cycle.
122  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
123  /// is not 64-bit aligned.
125  /// Can load/store 1 register/cycle.
127  /// Can load/store 1 register/cycle, but needs an extra cycle for address
128  /// computation and potentially also for register writeback.
130  };
131 
132 protected:
133  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
135 
136  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
138 
139  /// ARMArch - ARM architecture
141 
142  /// HasV4TOps, HasV5TOps, HasV5TEOps,
143  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
144  /// Specify whether target support specific ARM ISA variants.
145  bool HasV4TOps = false;
146  bool HasV5TOps = false;
147  bool HasV5TEOps = false;
148  bool HasV6Ops = false;
149  bool HasV6MOps = false;
150  bool HasV6KOps = false;
151  bool HasV6T2Ops = false;
152  bool HasV7Ops = false;
153  bool HasV8Ops = false;
154  bool HasV8_1aOps = false;
155  bool HasV8_2aOps = false;
156  bool HasV8_3aOps = false;
157  bool HasV8_4aOps = false;
158  bool HasV8_5aOps = false;
159  bool HasV8MBaselineOps = false;
160  bool HasV8MMainlineOps = false;
161  bool HasV8_1MMainlineOps = false;
162  bool HasMVEIntegerOps = false;
163  bool HasMVEFloatOps = false;
164 
165  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
166  /// floating point ISAs are supported.
167  bool HasVFPv2 = false;
168  bool HasVFPv3 = false;
169  bool HasVFPv4 = false;
170  bool HasFPARMv8 = false;
171  bool HasNEON = false;
172  bool HasFPRegs = false;
173  bool HasFPRegs16 = false;
174  bool HasFPRegs64 = false;
175 
176  /// Versions of the VFP flags restricted to single precision, or to
177  /// 16 d-registers, or both.
178  bool HasVFPv2SP = false;
179  bool HasVFPv3SP = false;
180  bool HasVFPv4SP = false;
181  bool HasFPARMv8SP = false;
182  bool HasVFPv2D16 = false;
183  bool HasVFPv3D16 = false;
184  bool HasVFPv4D16 = false;
185  bool HasFPARMv8D16 = false;
186  bool HasVFPv2D16SP = false;
187  bool HasVFPv3D16SP = false;
188  bool HasVFPv4D16SP = false;
189  bool HasFPARMv8D16SP = false;
190 
191  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
192  bool HasDotProd = false;
193 
194  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
195  /// specified. Use the method useNEONForSinglePrecisionFP() to
196  /// determine if NEON should actually be used.
198 
199  /// UseMulOps - True if non-microcoded fused integer multiply-add and
200  /// multiply-subtract instructions should be used.
201  bool UseMulOps = false;
202 
203  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
204  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
205  bool SlowFPVMLx = false;
206 
207  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
208  /// forwarding to allow mul + mla being issued back to back.
209  bool HasVMLxForwarding = false;
210 
211  /// SlowFPBrcc - True if floating point compare + branch is slow.
212  bool SlowFPBrcc = false;
213 
214  /// InThumbMode - True if compiling for Thumb, false for ARM.
215  bool InThumbMode = false;
216 
217  /// UseSoftFloat - True if we're using software floating point features.
218  bool UseSoftFloat = false;
219 
220  /// UseMISched - True if MachineScheduler should be used for this subtarget.
221  bool UseMISched = false;
222 
223  /// DisablePostRAScheduler - False if scheduling should happen again after
224  /// register allocation.
226 
227  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
228  bool UseAA = false;
229 
230  /// HasThumb2 - True if Thumb2 instructions are supported.
231  bool HasThumb2 = false;
232 
233  /// NoARM - True if subtarget does not support ARM mode execution.
234  bool NoARM = false;
235 
236  /// ReserveR9 - True if R9 is not available as a general purpose register.
237  bool ReserveR9 = false;
238 
239  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
240  /// 32-bit imms (including global addresses).
241  bool NoMovt = false;
242 
243  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
244  /// must be able to synthesize call stubs for interworking between ARM and
245  /// Thumb.
246  bool SupportsTailCall = false;
247 
248  /// HasFP16 - True if subtarget supports half-precision FP conversions
249  bool HasFP16 = false;
250 
251  /// HasFullFP16 - True if subtarget supports half-precision FP operations
252  bool HasFullFP16 = false;
253 
254  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
255  bool HasFP16FML = false;
256 
257  /// HasD32 - True if subtarget has the full 32 double precision
258  /// FP registers for VFPv3.
259  bool HasD32 = false;
260 
261  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
263 
264  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
266 
267  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
268  /// instructions.
269  bool HasDataBarrier = false;
270 
271  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
272  /// instruction.
273  bool HasFullDataBarrier = false;
274 
275  /// HasV7Clrex - True if the subtarget supports CLREX instructions
276  bool HasV7Clrex = false;
277 
278  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
279  /// instructions
280  bool HasAcquireRelease = false;
281 
282  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
283  /// over 16-bit ones.
284  bool Pref32BitThumb = false;
285 
286  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
287  /// that partially update CPSR and add false dependency on the previous
288  /// CPSR setting instruction.
290 
291  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
292  /// for instructions updating CPSR. Enabled for Cortex-A57.
294 
295  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
296  /// movs with shifter operand (i.e. asr, lsl, lsr).
298 
299  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
300  /// avoid issue "normal" call instructions to callees which do not return.
301  bool HasRetAddrStack = false;
302 
303  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
304  /// a branch predictor or not changes the expected cost of taking a branch
305  /// which affects the choice of whether to use predicated instructions.
306  bool HasBranchPredictor = true;
307 
308  /// HasMPExtension - True if the subtarget supports Multiprocessing
309  /// extension (ARMv7 only).
310  bool HasMPExtension = false;
311 
312  /// HasVirtualization - True if the subtarget supports the Virtualization
313  /// extension.
314  bool HasVirtualization = false;
315 
316  /// HasFP64 - If true, the floating point unit supports double
317  /// precision.
318  bool HasFP64 = false;
319 
320  /// If true, the processor supports the Performance Monitor Extensions. These
321  /// include a generic cycle-counter as well as more fine-grained (often
322  /// implementation-specific) events.
323  bool HasPerfMon = false;
324 
325  /// HasTrustZone - if true, processor supports TrustZone security extensions
326  bool HasTrustZone = false;
327 
328  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
329  bool Has8MSecExt = false;
330 
331  /// HasSHA2 - if true, processor supports SHA1 and SHA256
332  bool HasSHA2 = false;
333 
334  /// HasAES - if true, processor supports AES
335  bool HasAES = false;
336 
337  /// HasCrypto - if true, processor supports Cryptography extensions
338  bool HasCrypto = false;
339 
340  /// HasCRC - if true, processor supports CRC instructions
341  bool HasCRC = false;
342 
343  /// HasRAS - if true, the processor supports RAS extensions
344  bool HasRAS = false;
345 
346  /// HasLOB - if true, the processor supports the Low Overhead Branch extension
347  bool HasLOB = false;
348 
349  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
350  /// particularly effective at zeroing a VFP register.
351  bool HasZeroCycleZeroing = false;
352 
353  /// HasFPAO - if true, processor does positive address offset computation faster
354  bool HasFPAO = false;
355 
356  /// HasFuseAES - if true, processor executes back to back AES instruction
357  /// pairs faster.
358  bool HasFuseAES = false;
359 
360  /// HasFuseLiterals - if true, processor executes back to back
361  /// bottom and top halves of literal generation faster.
362  bool HasFuseLiterals = false;
363 
364  /// If true, if conversion may decide to leave some instructions unpredicated.
366 
367  /// If true, VMOV will be favored over VGETLNi32.
368  bool HasSlowVGETLNi32 = false;
369 
370  /// If true, VMOV will be favored over VDUP.
371  bool HasSlowVDUP32 = false;
372 
373  /// If true, VMOVSR will be favored over VMOVDRR.
374  bool PreferVMOVSR = false;
375 
376  /// If true, ISHST barriers will be used for Release semantics.
377  bool PreferISHST = false;
378 
379  /// If true, a VLDM/VSTM starting with an odd register number is considered to
380  /// take more microops than single VLDRS/VSTRS.
381  bool SlowOddRegister = false;
382 
383  /// If true, loading into a D subregister will be penalized.
384  bool SlowLoadDSubregister = false;
385 
386  /// If true, use a wider stride when allocating VFP registers.
387  bool UseWideStrideVFP = false;
388 
389  /// If true, the AGU and NEON/FPU units are multiplexed.
390  bool HasMuxedUnits = false;
391 
392  /// If true, VMOVS will never be widened to VMOVD.
393  bool DontWidenVMOVS = false;
394 
395  /// If true, splat a register between VFP and NEON instructions.
396  bool SplatVFPToNeon = false;
397 
398  /// If true, run the MLx expansion pass.
399  bool ExpandMLx = false;
400 
401  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
402  bool HasVMLxHazards = false;
403 
404  // If true, read thread pointer from coprocessor register.
405  bool ReadTPHard = false;
406 
407  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
408  bool UseNEONForFPMovs = false;
409 
410  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
411  bool CheckVLDnAlign = false;
412 
413  /// If true, VFP instructions are not pipelined.
414  bool NonpipelinedVFP = false;
415 
416  /// StrictAlign - If true, the subtarget disallows unaligned memory
417  /// accesses for some types. For details, see
418  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
419  bool StrictAlign = false;
420 
421  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
422  /// blocks to conform to ARMv8 rule.
423  bool RestrictIT = false;
424 
425  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
426  /// and such) instructions.
427  bool HasDSP = false;
428 
429  /// NaCl TRAP instruction is generated instead of the regular TRAP.
430  bool UseNaClTrap = false;
431 
432  /// Generate calls via indirect call instructions.
433  bool GenLongCalls = false;
434 
435  /// Generate code that does not contain data access to code sections.
436  bool GenExecuteOnly = false;
437 
438  /// Target machine allowed unsafe FP math (such as use of NEON fp)
439  bool UnsafeFPMath = false;
440 
441  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
442  bool UseSjLjEH = false;
443 
444  /// Has speculation barrier
445  bool HasSB = false;
446 
447  /// Implicitly convert an instruction to a different one if its immediates
448  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
449  bool NegativeImmediates = true;
450 
451  /// stackAlignment - The minimum alignment known to hold of the stack frame on
452  /// entry to the function and which must be maintained by every function.
453  unsigned stackAlignment = 4;
454 
455  /// CPUString - String name of used CPU.
456  std::string CPUString;
457 
458  unsigned MaxInterleaveFactor = 1;
459 
460  /// Clearance before partial register updates (in number of instructions)
462 
463  /// What kind of timing do load multiple/store multiple have (double issue,
464  /// single issue etc).
466 
467  /// The adjustment that we need to apply to get the operand latency from the
468  /// operand cycle returned by the itinerary data for pre-ISel operands.
470 
471  /// What alignment is preferred for loop bodies, in log2(bytes).
472  unsigned PrefLoopAlignment = 0;
473 
474  /// OptMinSize - True if we're optimising for minimum code size, equal to
475  /// the function attribute.
476  bool OptMinSize = false;
477 
478  /// IsLittle - The target is Little Endian
479  bool IsLittle;
480 
481  /// TargetTriple - What processor and OS we're targeting.
483 
484  /// SchedModel - Processor specific instruction costs.
486 
487  /// Selected instruction itineraries (one entry per itinerary class.)
489 
490  /// Options passed via command line that could influence the target
492 
494 
495 public:
496  /// This constructor initializes the data members to match that
497  /// of the specified triple.
498  ///
499  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
500  const ARMBaseTargetMachine &TM, bool IsLittle,
501  bool MinSize = false);
502 
503  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
504  /// that still makes it profitable to inline the call.
505  unsigned getMaxInlineSizeThreshold() const {
506  return 64;
507  }
508 
509  /// ParseSubtargetFeatures - Parses features string setting specified
510  /// subtarget options. Definition of function is auto generated by tblgen.
512 
513  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
514  /// so that we can use initializer lists for subtarget initialization.
516 
517  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
518  return &TSInfo;
519  }
520 
521  const ARMBaseInstrInfo *getInstrInfo() const override {
522  return InstrInfo.get();
523  }
524 
525  const ARMTargetLowering *getTargetLowering() const override {
526  return &TLInfo;
527  }
528 
529  const ARMFrameLowering *getFrameLowering() const override {
530  return FrameLowering.get();
531  }
532 
533  const ARMBaseRegisterInfo *getRegisterInfo() const override {
534  return &InstrInfo->getRegisterInfo();
535  }
536 
537  const CallLowering *getCallLowering() const override;
538  const InstructionSelector *getInstructionSelector() const override;
539  const LegalizerInfo *getLegalizerInfo() const override;
540  const RegisterBankInfo *getRegBankInfo() const override;
541 
542 private:
543  ARMSelectionDAGInfo TSInfo;
544  // Either Thumb1FrameLowering or ARMFrameLowering.
545  std::unique_ptr<ARMFrameLowering> FrameLowering;
546  // Either Thumb1InstrInfo or Thumb2InstrInfo.
547  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
548  ARMTargetLowering TLInfo;
549 
550  /// GlobalISel related APIs.
551  std::unique_ptr<CallLowering> CallLoweringInfo;
552  std::unique_ptr<InstructionSelector> InstSelector;
553  std::unique_ptr<LegalizerInfo> Legalizer;
554  std::unique_ptr<RegisterBankInfo> RegBankInfo;
555 
556  void initializeEnvironment();
557  void initSubtargetFeatures(StringRef CPU, StringRef FS);
558  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
559 
560 public:
561  void computeIssueWidth();
562 
563  bool hasV4TOps() const { return HasV4TOps; }
564  bool hasV5TOps() const { return HasV5TOps; }
565  bool hasV5TEOps() const { return HasV5TEOps; }
566  bool hasV6Ops() const { return HasV6Ops; }
567  bool hasV6MOps() const { return HasV6MOps; }
568  bool hasV6KOps() const { return HasV6KOps; }
569  bool hasV6T2Ops() const { return HasV6T2Ops; }
570  bool hasV7Ops() const { return HasV7Ops; }
571  bool hasV8Ops() const { return HasV8Ops; }
572  bool hasV8_1aOps() const { return HasV8_1aOps; }
573  bool hasV8_2aOps() const { return HasV8_2aOps; }
574  bool hasV8_3aOps() const { return HasV8_3aOps; }
575  bool hasV8_4aOps() const { return HasV8_4aOps; }
576  bool hasV8_5aOps() const { return HasV8_5aOps; }
577  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
578  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
579  bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
580  bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
581  bool hasMVEFloatOps() const { return HasMVEFloatOps; }
582  bool hasFPRegs() const { return HasFPRegs; }
583  bool hasFPRegs16() const { return HasFPRegs16; }
584  bool hasFPRegs64() const { return HasFPRegs64; }
585 
586  /// @{
587  /// These functions are obsolete, please consider adding subtarget features
588  /// or properties instead of calling them.
589  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
590  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
591  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
592  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
593  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
594  bool isSwift() const { return ARMProcFamily == Swift; }
595  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
596  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
597  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
598  bool isKrait() const { return ARMProcFamily == Krait; }
599  /// @}
600 
601  bool hasARMOps() const { return !NoARM; }
602 
603  bool hasVFP2Base() const { return HasVFPv2D16SP; }
604  bool hasVFP3Base() const { return HasVFPv3D16SP; }
605  bool hasVFP4Base() const { return HasVFPv4D16SP; }
606  bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
607  bool hasNEON() const { return HasNEON; }
608  bool hasSHA2() const { return HasSHA2; }
609  bool hasAES() const { return HasAES; }
610  bool hasCrypto() const { return HasCrypto; }
611  bool hasDotProd() const { return HasDotProd; }
612  bool hasCRC() const { return HasCRC; }
613  bool hasRAS() const { return HasRAS; }
614  bool hasLOB() const { return HasLOB; }
615  bool hasVirtualization() const { return HasVirtualization; }
616 
619  }
620 
623  bool hasDataBarrier() const { return HasDataBarrier; }
624  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
625  bool hasV7Clrex() const { return HasV7Clrex; }
626  bool hasAcquireRelease() const { return HasAcquireRelease; }
627 
628  bool hasAnyDataBarrier() const {
629  return HasDataBarrier || (hasV6Ops() && !isThumb());
630  }
631 
632  bool useMulOps() const { return UseMulOps; }
633  bool useFPVMLx() const { return !SlowFPVMLx; }
634  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
635  bool isFPBrccSlow() const { return SlowFPBrcc; }
636  bool hasFP64() const { return HasFP64; }
637  bool hasPerfMon() const { return HasPerfMon; }
638  bool hasTrustZone() const { return HasTrustZone; }
639  bool has8MSecExt() const { return Has8MSecExt; }
640  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
641  bool hasFPAO() const { return HasFPAO; }
643  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
644  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
645  bool preferVMOVSR() const { return PreferVMOVSR; }
646  bool preferISHSTBarriers() const { return PreferISHST; }
647  bool expandMLx() const { return ExpandMLx; }
648  bool hasVMLxHazards() const { return HasVMLxHazards; }
649  bool hasSlowOddRegister() const { return SlowOddRegister; }
651  bool useWideStrideVFP() const { return UseWideStrideVFP; }
652  bool hasMuxedUnits() const { return HasMuxedUnits; }
653  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
654  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
655  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
656  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
657  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
658  bool prefers32BitThumb() const { return Pref32BitThumb; }
662  bool hasRetAddrStack() const { return HasRetAddrStack; }
663  bool hasBranchPredictor() const { return HasBranchPredictor; }
664  bool hasMPExtension() const { return HasMPExtension; }
665  bool hasDSP() const { return HasDSP; }
666  bool useNaClTrap() const { return UseNaClTrap; }
667  bool useSjLjEH() const { return UseSjLjEH; }
668  bool hasSB() const { return HasSB; }
669  bool genLongCalls() const { return GenLongCalls; }
670  bool genExecuteOnly() const { return GenExecuteOnly; }
671 
672  bool hasFP16() const { return HasFP16; }
673  bool hasD32() const { return HasD32; }
674  bool hasFullFP16() const { return HasFullFP16; }
675  bool hasFP16FML() const { return HasFP16FML; }
676 
677  bool hasFuseAES() const { return HasFuseAES; }
678  bool hasFuseLiterals() const { return HasFuseLiterals; }
679  /// Return true if the CPU supports any kind of instruction fusion.
680  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
681 
682  const Triple &getTargetTriple() const { return TargetTriple; }
683 
684  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
685  bool isTargetIOS() const { return TargetTriple.isiOS(); }
686  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
687  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
688  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
689  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
690  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
691  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
692 
693  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
694  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
695  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
696 
697  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
698  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
699  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
700  // even for GNUEABI, so we can make a distinction here and still conform to
701  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
702  // FIXME: The Darwin exception is temporary, while we move users to
703  // "*-*-*-macho" triples as quickly as possible.
704  bool isTargetAEABI() const {
705  return (TargetTriple.getEnvironment() == Triple::EABI ||
706  TargetTriple.getEnvironment() == Triple::EABIHF) &&
708  }
709  bool isTargetGNUAEABI() const {
710  return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
711  TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
713  }
714  bool isTargetMuslAEABI() const {
715  return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
716  TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
718  }
719 
720  // ARM Targets that support EHABI exception handling standard
721  // Darwin uses SjLj. Other targets might need more checks.
722  bool isTargetEHABICompatible() const {
723  return (TargetTriple.getEnvironment() == Triple::EABI ||
724  TargetTriple.getEnvironment() == Triple::GNUEABI ||
725  TargetTriple.getEnvironment() == Triple::MuslEABI ||
726  TargetTriple.getEnvironment() == Triple::EABIHF ||
727  TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
728  TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
729  isTargetAndroid()) &&
731  }
732 
733  bool isTargetHardFloat() const;
734 
735  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
736 
737  bool isXRaySupported() const override;
738 
739  bool isAPCS_ABI() const;
740  bool isAAPCS_ABI() const;
741  bool isAAPCS16_ABI() const;
742 
743  bool isROPI() const;
744  bool isRWPI() const;
745 
746  bool useMachineScheduler() const { return UseMISched; }
748  bool useSoftFloat() const { return UseSoftFloat; }
749  bool isThumb() const { return InThumbMode; }
750  bool hasMinSize() const { return OptMinSize; }
751  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
752  bool isThumb2() const { return InThumbMode && HasThumb2; }
753  bool hasThumb2() const { return HasThumb2; }
754  bool isMClass() const { return ARMProcClass == MClass; }
755  bool isRClass() const { return ARMProcClass == RClass; }
756  bool isAClass() const { return ARMProcClass == AClass; }
757  bool isReadTPHard() const { return ReadTPHard; }
758 
759  bool isR9Reserved() const {
760  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
761  }
762 
763  bool useR7AsFramePointer() const {
764  return isTargetDarwin() || (!isTargetWindows() && isThumb());
765  }
766 
767  /// Returns true if the frame setup is split into two separate pushes (first
768  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
769  /// to lr. This is always required on Thumb1-only targets, as the push and
770  /// pop instructions can't access the high registers.
771  bool splitFramePushPop(const MachineFunction &MF) const {
772  return (useR7AsFramePointer() &&
774  isThumb1Only();
775  }
776 
777  bool useStride4VFPs() const;
778 
779  bool useMovt() const;
780 
781  bool supportsTailCall() const { return SupportsTailCall; }
782 
783  bool allowsUnalignedMem() const { return !StrictAlign; }
784 
785  bool restrictIT() const { return RestrictIT; }
786 
787  const std::string & getCPUString() const { return CPUString; }
788 
789  bool isLittle() const { return IsLittle; }
790 
791  unsigned getMispredictionPenalty() const;
792 
793  /// Returns true if machine scheduler should be enabled.
794  bool enableMachineScheduler() const override;
795 
796  /// True for some subtargets at > -O0.
797  bool enablePostRAScheduler() const override;
798 
799  /// Enable use of alias analysis during code generation (during MI
800  /// scheduling, DAGCombine, etc.).
801  bool useAA() const override { return UseAA; }
802 
803  // enableAtomicExpand- True if we need to expand our atomics.
804  bool enableAtomicExpand() const override;
805 
806  /// getInstrItins - Return the instruction itineraries based on subtarget
807  /// selection.
808  const InstrItineraryData *getInstrItineraryData() const override {
809  return &InstrItins;
810  }
811 
812  /// getStackAlignment - Returns the minimum alignment known to hold of the
813  /// stack frame on entry to the function and which must be maintained by every
814  /// function for this subtarget.
815  unsigned getStackAlignment() const { return stackAlignment; }
816 
817  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
818 
820 
822  return LdStMultipleTiming;
823  }
824 
827  }
828 
829  /// True if the GV will be accessed via an indirect symbol.
830  bool isGVIndirectSymbol(const GlobalValue *GV) const;
831 
832  /// Returns the constant pool modifier needed to access the GV.
833  bool isGVInGOT(const GlobalValue *GV) const;
834 
835  /// True if fast-isel is used.
836  bool useFastISel() const;
837 
838  /// Returns the correct return opcode for the current feature set.
839  /// Use BX if available to allow mixing thumb/arm code, but fall back
840  /// to plain mov pc,lr on ARMv4.
841  unsigned getReturnOpcode() const {
842  if (isThumb())
843  return ARM::tBX_RET;
844  if (hasV4TOps())
845  return ARM::BX_RET;
846  return ARM::MOVPCLR;
847  }
848 
849  /// Allow movt+movw for PIC global address calculation.
850  /// ELF does not have GOT relocations for movt+movw.
851  /// ROPI does not use GOT.
853  return isROPI() || !isTargetELF();
854  }
855 
856  unsigned getPrefLoopAlignment() const {
857  return PrefLoopAlignment;
858  }
859 
861  unsigned PhysReg) const override;
862  unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
863 };
864 
865 } // end namespace llvm
866 
867 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:241
bool hasV5TEOps() const
Definition: ARMSubtarget.h:565
bool useMovt() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
bool hasCRC() const
Definition: ARMSubtarget.h:612
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:408
bool hasD32() const
Definition: ARMSubtarget.h:673
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:709
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:573
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:453
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:399
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:482
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:656
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:659
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:306
bool hasRAS() const
Definition: ARMSubtarget.h:613
bool hasSHA2() const
Definition: ARMSubtarget.h:608
bool isThumb() const
Definition: ARMSubtarget.h:749
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:621
bool SplatVFPToNeon
If true, splat a register between VFP and NEON instructions.
Definition: ARMSubtarget.h:396
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:205
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:384
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:517
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
bool hasV4TOps() const
Definition: ARMSubtarget.h:563
bool isLittle() const
Definition: ARMSubtarget.h:789
bool useFastISel() const
True if fast-isel is used.
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:663
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:301
bool isTargetNaCl() const
Definition: ARMSubtarget.h:689
bool hasFuseAES() const
Definition: ARMSubtarget.h:677
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:525
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:252
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:262
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:371
bool preferVMOVSR() const
Definition: ARMSubtarget.h:645
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:581
bool hasV7Ops() const
Definition: ARMSubtarget.h:570
bool hasV8_5aOps() const
Definition: ARMSubtarget.h:576
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:658
bool isCortexA5() const
Definition: ARMSubtarget.h:589
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:472
bool isTargetCOFF() const
Definition: ARMSubtarget.h:693
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:167
bool useNaClTrap() const
Definition: ARMSubtarget.h:666
bool OptMinSize
OptMinSize - True if we&#39;re optimising for minimum code size, equal to the function attribute...
Definition: ARMSubtarget.h:476
bool HasFP64
HasFP64 - If true, the floating point unit supports double precision.
Definition: ARMSubtarget.h:318
bool UseAA
UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
Definition: ARMSubtarget.h:228
bool hasV6Ops() const
Definition: ARMSubtarget.h:566
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:265
bool hasDotProd() const
Definition: ARMSubtarget.h:611
bool isThumb1Only() const
Definition: ARMSubtarget.h:751
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:714
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:626
const LegalizerInfo * getLegalizerInfo() const override
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:661
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:493
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:433
bool isTargetHardFloat() const
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:690
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:246
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:644
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:390
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:368
bool isRClass() const
Definition: ARMSubtarget.h:755
bool genExecuteOnly() const
Definition: ARMSubtarget.h:670
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:817
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:201
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:521
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:577
bool isTargetELF() const
Definition: ARMSubtarget.h:694
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:126
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:329
Holds all the information related to register banks.
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:344
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool hasARMOps() const
Definition: ARMSubtarget.h:601
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:381
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:351
bool hasV8_4aOps() const
Definition: ARMSubtarget.h:575
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:419
bool hasV8Ops() const
Definition: ARMSubtarget.h:571
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:231
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:358
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:439
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:655
bool hasPerfMon() const
Definition: ARMSubtarget.h:637
bool hasFuseLiterals() const
Definition: ARMSubtarget.h:678
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:393
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:374
bool isReadTPHard() const
Definition: ARMSubtarget.h:757
bool isCortexM3() const
Definition: ARMSubtarget.h:595
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:284
bool isCortexR5() const
Definition: ARMSubtarget.h:597
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:479
bool hasDSP() const
Definition: ARMSubtarget.h:665
bool useFPVMLx() const
Definition: ARMSubtarget.h:633
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:505
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:771
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:624
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:119
bool enableAtomicExpand() const override
bool hasVirtualization() const
Definition: ARMSubtarget.h:615
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:124
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:652
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isXRaySupported() const override
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:722
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:234
bool HasFuseLiterals
HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generatio...
Definition: ARMSubtarget.h:362
bool HasSB
Has speculation barrier.
Definition: ARMSubtarget.h:445
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:617
bool hasFPAO() const
Definition: ARMSubtarget.h:641
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:819
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:569
bool isTargetDarwin() const
Definition: ARMSubtarget.h:684
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:469
bool HasAES
HasAES - if true, processor supports AES.
Definition: ARMSubtarget.h:335
bool hasV6MOps() const
Definition: ARMSubtarget.h:567
Itinerary data supplied by a subtarget to be used by a target.
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
bool hasV8_1MMainlineOps() const
Definition: ARMSubtarget.h:579
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:449
bool isOSNetBSD() const
Definition: Triple.h:493
bool isAClass() const
Definition: ARMSubtarget.h:756
bool hasFP16() const
Definition: ARMSubtarget.h:672
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:763
bool hasSB() const
Definition: ARMSubtarget.h:668
bool isR9Reserved() const
Definition: ARMSubtarget.h:759
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:323
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:643
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:622
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:687
bool HasD32
HasD32 - True if subtarget has the full 32 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:259
bool hasCrypto() const
Definition: ARMSubtarget.h:610
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:297
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:341
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:642
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:427
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:276
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:646
bool hasV6KOps() const
Definition: ARMSubtarget.h:568
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:314
bool has8MSecExt() const
Definition: ARMSubtarget.h:639
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:815
bool restrictIT() const
Definition: ARMSubtarget.h:785
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:134
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:423
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
bool isMClass() const
Definition: ARMSubtarget.h:754
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:365
bool isWatchABI() const
Definition: Triple.h:476
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:221
bool useMachineScheduler() const
Definition: ARMSubtarget.h:746
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:145
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:209
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:686
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:225
bool HasVFPv2SP
Versions of the VFP flags restricted to single precision, or to 16 d-registers, or both...
Definition: ARMSubtarget.h:178
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:402
bool hasFPRegs16() const
Definition: ARMSubtarget.h:583
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:338
bool useMulOps() const
Definition: ARMSubtarget.h:632
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:657
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:650
unsigned getMispredictionPenalty() const
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool hasVFP2Base() const
Definition: ARMSubtarget.h:603
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:310
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:783
bool hasTrustZone() const
Definition: ARMSubtarget.h:638
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:529
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:649
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:192
bool isAPCS_ABI() const
bool hasVFP3Base() const
Definition: ARMSubtarget.h:604
const CallLowering * getCallLowering() const override
bool useSjLjEH() const
Definition: ARMSubtarget.h:667
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:414
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:821
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool hasV7Clrex() const
Definition: ARMSubtarget.h:625
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:651
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:249
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:326
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:215
bool hasAES() const
Definition: ARMSubtarget.h:609
const std::string & getCPUString() const
Definition: ARMSubtarget.h:787
bool isCortexA9() const
Definition: ARMSubtarget.h:592
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasFP64() const
Definition: ARMSubtarget.h:636
bool useSoftFloat() const
Definition: ARMSubtarget.h:748
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:606
bool isTargetAEABI() const
Definition: ARMSubtarget.h:704
bool isTargetLinux() const
Definition: ARMSubtarget.h:688
bool hasVFP4Base() const
Definition: ARMSubtarget.h:605
bool hasMVEFloatOps() const
Definition: ARMSubtarget.h:581
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:808
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:635
const InstructionSelector * getInstructionSelector() const override
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:660
bool isTargetAndroid() const
Definition: ARMSubtarget.h:735
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:140
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:852
bool hasMPExtension() const
Definition: ARMSubtarget.h:664
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:137
bool hasNEON() const
Definition: ARMSubtarget.h:607
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
bool UseWideStrideVFP
If true, use a wider stride when allocating VFP registers.
Definition: ARMSubtarget.h:387
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:436
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:430
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR...
Definition: ARMSubtarget.h:293
unsigned getPrefLoopAlignment() const
Definition: ARMSubtarget.h:856
bool hasFPRegs64() const
Definition: ARMSubtarget.h:584
unsigned PrefLoopAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:472
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:485
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:377
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:747
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:491
bool genLongCalls() const
Definition: ARMSubtarget.h:669
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool useStride4VFPs() const
bool UseSoftFloat
UseSoftFloat - True if we&#39;re using software floating point features.
Definition: ARMSubtarget.h:218
bool isROPI() const
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:841
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:634
bool expandMLx() const
Definition: ARMSubtarget.h:647
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:572
Provides the logic to select generic machine instructions.
bool isThumb2() const
Definition: ARMSubtarget.h:752
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:682
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:640
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:662
bool isTargetIOS() const
Definition: ARMSubtarget.h:685
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:237
TargetOptions Options
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:488
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:197
bool isCortexA7() const
Definition: ARMSubtarget.h:590
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:533
bool hasLOB() const
Definition: ARMSubtarget.h:614
bool hasFPRegs() const
Definition: ARMSubtarget.h:582
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:654
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:461
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:825
bool hasV5TOps() const
Definition: ARMSubtarget.h:564
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool HasFP16FML
HasFP16FML - True if subtarget supports half-precision FP fml operations.
Definition: ARMSubtarget.h:255
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:648
bool hasMinSize() const
Definition: ARMSubtarget.h:750
bool isTargetMachO() const
Definition: ARMSubtarget.h:695
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:212
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:465
bool isKrait() const
Definition: ARMSubtarget.h:598
bool isSwift() const
Definition: ARMSubtarget.h:594
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool supportsTailCall() const
Definition: ARMSubtarget.h:781
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:129
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:289
bool isCortexA8() const
Definition: ARMSubtarget.h:591
This file describes how to lower LLVM calls to machine code calls.
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:580
bool isRWPI() const
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:578
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:121
bool isTargetWindows() const
Definition: ARMSubtarget.h:691
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction. ...
Definition: ARMSubtarget.h:273
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:456
bool isCortexA15() const
Definition: ARMSubtarget.h:593
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:280
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:680
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:628
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition: ARMSubtarget.h:801
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:354
bool HasLOB
HasLOB - if true, the processor supports the Low Overhead Branch extension.
Definition: ARMSubtarget.h:347
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:269
bool isAAPCS_ABI() const
bool hasDataBarrier() const
Definition: ARMSubtarget.h:623
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
bool hasFP16FML() const
Definition: ARMSubtarget.h:675
bool hasThumb2() const
Definition: ARMSubtarget.h:753
bool isLikeA9() const
Definition: ARMSubtarget.h:596
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:411
bool HasSHA2
HasSHA2 - if true, processor supports SHA1 and SHA256.
Definition: ARMSubtarget.h:332
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:442
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:653
bool hasFullFP16() const
Definition: ARMSubtarget.h:674
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:458
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:574