LLVM 19.0.0git
ARMSubtarget.h
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1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
19#include "ARMFrameLowering.h"
20#include "ARMISelLowering.h"
22#include "ARMSelectionDAGInfo.h"
31#include "llvm/MC/MCSchedule.h"
35#include <bitset>
36#include <memory>
37#include <string>
38
39#define GET_SUBTARGETINFO_HEADER
40#include "ARMGenSubtargetInfo.inc"
41
42namespace llvm {
43
44class ARMBaseTargetMachine;
45class GlobalValue;
46class StringRef;
47
49protected:
52
90 Swift
91 };
94
97 RClass
98 };
137 };
138
139public:
140 /// What kind of timing do load multiple/store multiple instructions have.
142 /// Can load/store 2 registers/cycle.
144 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
145 /// is not 64-bit aligned.
147 /// Can load/store 1 register/cycle.
149 /// Can load/store 1 register/cycle, but needs an extra cycle for address
150 /// computation and potentially also for register writeback.
152 };
153
154protected:
155// Bool members corresponding to the SubtargetFeatures defined in tablegen
156#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
157 bool ATTRIBUTE = DEFAULT;
158#include "ARMGenSubtargetInfo.inc"
159
160 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
162
163 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
165
166 /// ARMArch - ARM architecture
168
169 /// UseMulOps - True if non-microcoded fused integer multiply-add and
170 /// multiply-subtract instructions should be used.
171 bool UseMulOps = false;
172
173 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
174 /// must be able to synthesize call stubs for interworking between ARM and
175 /// Thumb.
176 bool SupportsTailCall = false;
177
178 /// RestrictIT - If true, the subtarget disallows generation of complex IT
179 /// blocks.
180 bool RestrictIT = false;
181
182 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
183 bool UseSjLjEH = false;
184
185 /// stackAlignment - The minimum alignment known to hold of the stack frame on
186 /// entry to the function and which must be maintained by every function.
188
189 /// CPUString - String name of used CPU.
190 std::string CPUString;
191
193
194 /// Clearance before partial register updates (in number of instructions)
196
197 /// What kind of timing do load multiple/store multiple have (double issue,
198 /// single issue etc).
200
201 /// The adjustment that we need to apply to get the operand latency from the
202 /// operand cycle returned by the itinerary data for pre-ISel operands.
204
205 /// What alignment is preferred for loop bodies and functions, in log2(bytes).
207
208 /// The cost factor for MVE instructions, representing the multiple beats an
209 // instruction can take. The default is 2, (set in initSubtargetFeatures so
210 // that we can use subtarget features less than 2).
212
213 /// OptMinSize - True if we're optimising for minimum code size, equal to
214 /// the function attribute.
215 bool OptMinSize = false;
216
217 /// IsLittle - The target is Little Endian
219
220 /// TargetTriple - What processor and OS we're targeting.
222
223 /// SchedModel - Processor specific instruction costs.
225
226 /// Selected instruction itineraries (one entry per itinerary class.)
228
229 /// Options passed via command line that could influence the target
231
233
234public:
235 /// This constructor initializes the data members to match that
236 /// of the specified triple.
237 ///
238 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
239 const ARMBaseTargetMachine &TM, bool IsLittle,
240 bool MinSize = false);
241
242 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
243 /// that still makes it profitable to inline the call.
244 unsigned getMaxInlineSizeThreshold() const {
245 return 64;
246 }
247
248 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
249 /// that still makes it profitable to inline a llvm.memcpy as a Tail
250 /// Predicated loop.
251 /// This threshold should only be used for constant size inputs.
252 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
253
254 /// ParseSubtargetFeatures - Parses features string setting specified
255 /// subtarget options. Definition of function is auto generated by tblgen.
257
258 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
259 /// so that we can use initializer lists for subtarget initialization.
261
262 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
263 return &TSInfo;
264 }
265
266 const ARMBaseInstrInfo *getInstrInfo() const override {
267 return InstrInfo.get();
268 }
269
270 const ARMTargetLowering *getTargetLowering() const override {
271 return &TLInfo;
272 }
273
274 const ARMFrameLowering *getFrameLowering() const override {
275 return FrameLowering.get();
276 }
277
278 const ARMBaseRegisterInfo *getRegisterInfo() const override {
279 return &InstrInfo->getRegisterInfo();
280 }
281
282 /// The correct instructions have been implemented to initialize undef
283 /// registers, therefore the ARM Architecture is supported by the Init Undef
284 /// Pass. This will return true as the pass needs to be supported for all
285 /// types of instructions. The pass will then perform more checks to ensure it
286 /// should be applying the Pseudo Instructions.
287 bool supportsInitUndef() const override { return true; }
288
289 const CallLowering *getCallLowering() const override;
291 const LegalizerInfo *getLegalizerInfo() const override;
292 const RegisterBankInfo *getRegBankInfo() const override;
293
294private:
295 ARMSelectionDAGInfo TSInfo;
296 // Either Thumb1FrameLowering or ARMFrameLowering.
297 std::unique_ptr<ARMFrameLowering> FrameLowering;
298 // Either Thumb1InstrInfo or Thumb2InstrInfo.
299 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
300 ARMTargetLowering TLInfo;
301
302 /// GlobalISel related APIs.
303 std::unique_ptr<CallLowering> CallLoweringInfo;
304 std::unique_ptr<InstructionSelector> InstSelector;
305 std::unique_ptr<LegalizerInfo> Legalizer;
306 std::unique_ptr<RegisterBankInfo> RegBankInfo;
307
308 void initializeEnvironment();
309 void initSubtargetFeatures(StringRef CPU, StringRef FS);
310 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
311
312 std::bitset<8> CoprocCDE = {};
313public:
314// Getters for SubtargetFeatures defined in tablegen
315#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
316 bool GETTER() const { return ATTRIBUTE; }
317#include "ARMGenSubtargetInfo.inc"
318
319 /// @{
320 /// These functions are obsolete, please consider adding subtarget features
321 /// or properties instead of calling them.
322 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
323 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
324 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
325 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
326 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
327 bool isSwift() const { return ARMProcFamily == Swift; }
328 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
329 bool isCortexM7() const { return ARMProcFamily == CortexM7; }
330 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
331 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
332 bool isKrait() const { return ARMProcFamily == Krait; }
333 /// @}
334
335 bool hasARMOps() const { return !NoARM; }
336
338 return hasNEON() && hasNEONForFP();
339 }
340
341 bool hasVFP2Base() const { return hasVFPv2SP(); }
342 bool hasVFP3Base() const { return hasVFPv3D16SP(); }
343 bool hasVFP4Base() const { return hasVFPv4D16SP(); }
344 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }
345
346 bool hasAnyDataBarrier() const {
347 return HasDataBarrier || (hasV6Ops() && !isThumb());
348 }
349
350 bool useMulOps() const { return UseMulOps; }
351 bool useFPVMLx() const { return !SlowFPVMLx; }
352 bool useFPVFMx() const {
353 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
354 }
355 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
356 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
357 bool useSjLjEH() const { return UseSjLjEH; }
358 bool hasBaseDSP() const {
359 if (isThumb())
360 return hasThumb2() && hasDSP();
361 else
362 return hasV5TEOps();
363 }
364
365 /// Return true if the CPU supports any kind of instruction fusion.
366 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
367
368 const Triple &getTargetTriple() const { return TargetTriple; }
369
370 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
371 bool isTargetIOS() const { return TargetTriple.isiOS(); }
372 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
373 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
374 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
375 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
376 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
377 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
378 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
379
380 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
381 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
383
384 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
385 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
386 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
387 // even for GNUEABI, so we can make a distinction here and still conform to
388 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
389 // FIXME: The Darwin exception is temporary, while we move users to
390 // "*-*-*-macho" triples as quickly as possible.
391 bool isTargetAEABI() const {
395 }
396 bool isTargetGNUAEABI() const {
400 }
401 bool isTargetMuslAEABI() const {
406 }
407
408 // ARM Targets that support EHABI exception handling standard
409 // Darwin uses SjLj. Other targets might need more checks.
412 }
413
414 bool isTargetHardFloat() const;
415
416 bool isReadTPSoft() const {
417 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());
418 }
419
420 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
421
422 bool isXRaySupported() const override;
423
424 bool isAPCS_ABI() const;
425 bool isAAPCS_ABI() const;
426 bool isAAPCS16_ABI() const;
427
428 bool isROPI() const;
429 bool isRWPI() const;
430
431 bool useMachineScheduler() const { return UseMISched; }
432 bool useMachinePipeliner() const { return UseMIPipeliner; }
433 bool hasMinSize() const { return OptMinSize; }
434 bool isThumb1Only() const { return isThumb() && !hasThumb2(); }
435 bool isThumb2() const { return isThumb() && hasThumb2(); }
436 bool isMClass() const { return ARMProcClass == MClass; }
437 bool isRClass() const { return ARMProcClass == RClass; }
438 bool isAClass() const { return ARMProcClass == AClass; }
439
440 bool isR9Reserved() const {
441 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
442 }
443
445 if (isTargetDarwin() ||
446 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
447 return ARM::R7;
448 return ARM::R11;
449 }
450
451 /// Returns true if the frame setup is split into two separate pushes (first
452 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
453 /// to lr. This is always required on Thumb1-only targets, as the push and
454 /// pop instructions can't access the high registers.
455 bool splitFramePushPop(const MachineFunction &MF) const {
457 return true;
458 return (getFramePointerReg() == ARM::R7 &&
460 isThumb1Only();
461 }
462
463 bool splitFramePointerPush(const MachineFunction &MF) const;
464
465 bool useStride4VFPs() const;
466
467 bool useMovt() const;
468
469 bool supportsTailCall() const { return SupportsTailCall; }
470
471 bool allowsUnalignedMem() const { return !StrictAlign; }
472
473 bool restrictIT() const { return RestrictIT; }
474
475 const std::string & getCPUString() const { return CPUString; }
476
477 bool isLittle() const { return IsLittle; }
478
479 unsigned getMispredictionPenalty() const;
480
481 /// Returns true if machine scheduler should be enabled.
482 bool enableMachineScheduler() const override;
483
484 /// Returns true if machine pipeliner should be enabled.
485 bool enableMachinePipeliner() const override;
486 bool useDFAforSMS() const override;
487
488 /// True for some subtargets at > -O0.
489 bool enablePostRAScheduler() const override;
490
491 /// True for some subtargets at > -O0.
492 bool enablePostRAMachineScheduler() const override;
493
494 /// Check whether this subtarget wants to use subregister liveness.
495 bool enableSubRegLiveness() const override;
496
497 /// Enable use of alias analysis during code generation (during MI
498 /// scheduling, DAGCombine, etc.).
499 bool useAA() const override { return true; }
500
501 /// getInstrItins - Return the instruction itineraries based on subtarget
502 /// selection.
504 return &InstrItins;
505 }
506
507 /// getStackAlignment - Returns the minimum alignment known to hold of the
508 /// stack frame on entry to the function and which must be maintained by every
509 /// function for this subtarget.
511
512 // Returns the required alignment for LDRD/STRD instructions
514 return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8);
515 }
516
517 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
518
520
522 return LdStMultipleTiming;
523 }
524
527 }
528
529 /// True if the GV will be accessed via an indirect symbol.
530 bool isGVIndirectSymbol(const GlobalValue *GV) const;
531
532 /// Returns the constant pool modifier needed to access the GV.
533 bool isGVInGOT(const GlobalValue *GV) const;
534
535 /// True if fast-isel is used.
536 bool useFastISel() const;
537
538 /// Returns the correct return opcode for the current feature set.
539 /// Use BX if available to allow mixing thumb/arm code, but fall back
540 /// to plain mov pc,lr on ARMv4.
541 unsigned getReturnOpcode() const {
542 if (isThumb())
543 return ARM::tBX_RET;
544 if (hasV4TOps())
545 return ARM::BX_RET;
546 return ARM::MOVPCLR;
547 }
548
549 /// Allow movt+movw for PIC global address calculation.
550 /// ELF does not have GOT relocations for movt+movw.
551 /// ROPI does not use GOT.
553 return isROPI() || !isTargetELF();
554 }
555
557
558 unsigned
561 return 1;
562 return MVEVectorCostFactor;
563 }
564
566 unsigned PhysReg) const override;
567 unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
568};
569
570} // end namespace llvm
571
572#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
static bool isThumb(const MCSubtargetInfo &STI)
This file describes how to lower LLVM calls to machine code calls.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Interface for Targets to specify which operations they can successfully select and how the others sho...
This pass exposes codegen information to IR-level passes.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool useFastISel() const
True if fast-isel is used.
bool isTargetMachO() const
Definition: ARMSubtarget.h:382
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:366
bool isCortexA7() const
Definition: ARMSubtarget.h:323
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:218
bool useMovt() const
bool isSwift() const
Definition: ARMSubtarget.h:327
bool isTargetAEABI() const
Definition: ARMSubtarget.h:391
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:199
bool hasARMOps() const
Definition: ARMSubtarget.h:335
bool supportsTailCall() const
Definition: ARMSubtarget.h:469
bool supportsInitUndef() const override
The correct instructions have been implemented to initialize undef registers, therefore the ARM Archi...
Definition: ARMSubtarget.h:287
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:368
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:183
bool hasVFP4Base() const
Definition: ARMSubtarget.h:343
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:192
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:232
bool isRClass() const
Definition: ARMSubtarget.h:437
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:521
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:266
bool useFPVMLx() const
Definition: ARMSubtarget.h:351
bool isThumb1Only() const
Definition: ARMSubtarget.h:434
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:161
bool useFPVFMx() const
Definition: ARMSubtarget.h:352
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:167
bool isCortexM7() const
Definition: ARMSubtarget.h:329
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:344
bool isAClass() const
Definition: ARMSubtarget.h:438
bool isThumb2() const
Definition: ARMSubtarget.h:435
bool useDFAforSMS() const override
bool isReadTPSoft() const
Definition: ARMSubtarget.h:416
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:164
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool isAAPCS16_ABI() const
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:444
bool isTargetWindows() const
Definition: ARMSubtarget.h:378
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:410
bool isCortexR5() const
Definition: ARMSubtarget.h:331
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:211
bool hasBaseDSP() const
Definition: ARMSubtarget.h:358
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:270
bool useSjLjEH() const
Definition: ARMSubtarget.h:357
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:224
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:190
unsigned getMispredictionPenalty() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:221
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isLikeA9() const
Definition: ARMSubtarget.h:330
bool isTargetDarwin() const
Definition: ARMSubtarget.h:370
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:278
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:227
bool useStride4VFPs() const
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:215
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:541
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:180
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:510
bool isKrait() const
Definition: ARMSubtarget.h:332
bool isCortexA5() const
Definition: ARMSubtarget.h:322
bool hasVFP2Base() const
Definition: ARMSubtarget.h:341
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies and functions, in log2(bytes).
Definition: ARMSubtarget.h:206
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: ARMSubtarget.h:499
bool isTargetAndroid() const
Definition: ARMSubtarget.h:420
bool isROPI() const
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:187
unsigned getMaxMemcpyTPInlineSizeThreshold() const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...
Definition: ARMSubtarget.h:252
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:195
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
bool isTargetCOFF() const
Definition: ARMSubtarget.h:380
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:455
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:244
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:396
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:262
const std::string & getCPUString() const
Definition: ARMSubtarget.h:475
InstructionSelector * getInstructionSelector() const override
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:517
bool hasVFP3Base() const
Definition: ARMSubtarget.h:342
bool isR9Reserved() const
Definition: ARMSubtarget.h:440
bool isAPCS_ABI() const
bool useFPVFMx64() const
Definition: ARMSubtarget.h:356
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:519
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:377
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:372
bool isXRaySupported() const override
const CallLowering * getCallLowering() const override
bool hasMinSize() const
Definition: ARMSubtarget.h:433
bool splitFramePointerPush(const MachineFunction &MF) const
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isTargetIOS() const
Definition: ARMSubtarget.h:371
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:337
bool isTargetNaCl() const
Definition: ARMSubtarget.h:376
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:503
bool isCortexM3() const
Definition: ARMSubtarget.h:328
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:373
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:552
bool isCortexA8() const
Definition: ARMSubtarget.h:324
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:171
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:230
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:141
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:146
@ SingleIssue
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:148
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:143
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:151
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:346
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:432
bool isTargetDriverKit() const
Definition: ARMSubtarget.h:374
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:525
bool isAAPCS_ABI() const
bool useMachineScheduler() const
Definition: ARMSubtarget.h:431
bool isCortexA15() const
Definition: ARMSubtarget.h:326
bool isRWPI() const
bool isLittle() const
Definition: ARMSubtarget.h:477
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:471
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:401
const LegalizerInfo * getLegalizerInfo() const override
bool isTargetLinux() const
Definition: ARMSubtarget.h:375
bool isCortexA9() const
Definition: ARMSubtarget.h:325
bool useFPVFMx16() const
Definition: ARMSubtarget.h:355
bool isMClass() const
Definition: ARMSubtarget.h:436
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:176
unsigned getPrefLoopLogAlignment() const
Definition: ARMSubtarget.h:556
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:203
bool isTargetHardFloat() const
bool useMulOps() const
Definition: ARMSubtarget.h:350
bool isTargetELF() const
Definition: ARMSubtarget.h:381
bool restrictIT() const
Definition: ARMSubtarget.h:473
unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const
Definition: ARMSubtarget.h:559
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:274
Align getDualLoadStoreAlignment() const
Definition: ARMSubtarget.h:513
Itinerary data supplied by a subtarget to be used by a target.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetCostKind
The kind of cost model.
@ TCK_CodeSize
Instruction code size.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:657
bool isWatchABI() const
Definition: Triple.h:529
@ MuslEABIHF
Definition: Triple.h:251
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:537
bool isTargetEHABICompatible() const
Tests whether the target supports the EHABI exception handling standard.
Definition: Triple.h:847
bool isOSNetBSD() const
Definition: Triple.h:560
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:753
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:716
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:708
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:378
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:608
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:662
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:542
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:525
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:515
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:703
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:253