LLVM  7.0.0svn
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16 
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMISelLowering.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSchedule.h"
33 #include <memory>
34 #include <string>
35 
36 #define GET_SUBTARGETINFO_HEADER
37 #include "ARMGenSubtargetInfo.inc"
38 
39 namespace llvm {
40 
41 class ARMBaseTargetMachine;
42 class GlobalValue;
43 class StringRef;
44 
46 protected:
49 
75  };
78 
82  };
83  enum ARMArchEnum {
112  };
113 
114 public:
115  /// What kind of timing do load multiple/store multiple instructions have.
117  /// Can load/store 2 registers/cycle.
119  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
120  /// is not 64-bit aligned.
122  /// Can load/store 1 register/cycle.
124  /// Can load/store 1 register/cycle, but needs an extra cycle for address
125  /// computation and potentially also for register writeback.
127  };
128 
129 protected:
130  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
132 
133  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
135 
136  /// ARMArch - ARM architecture
138 
139  /// HasV4TOps, HasV5TOps, HasV5TEOps,
140  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
141  /// Specify whether target support specific ARM ISA variants.
142  bool HasV4TOps = false;
143  bool HasV5TOps = false;
144  bool HasV5TEOps = false;
145  bool HasV6Ops = false;
146  bool HasV6MOps = false;
147  bool HasV6KOps = false;
148  bool HasV6T2Ops = false;
149  bool HasV7Ops = false;
150  bool HasV8Ops = false;
151  bool HasV8_1aOps = false;
152  bool HasV8_2aOps = false;
153  bool HasV8_3aOps = false;
154  bool HasV8MBaselineOps = false;
155  bool HasV8MMainlineOps = false;
156 
157  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
158  /// floating point ISAs are supported.
159  bool HasVFPv2 = false;
160  bool HasVFPv3 = false;
161  bool HasVFPv4 = false;
162  bool HasFPARMv8 = false;
163  bool HasNEON = false;
164 
165  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
166  bool HasDotProd = false;
167 
168  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
169  /// specified. Use the method useNEONForSinglePrecisionFP() to
170  /// determine if NEON should actually be used.
172 
173  /// UseMulOps - True if non-microcoded fused integer multiply-add and
174  /// multiply-subtract instructions should be used.
175  bool UseMulOps = false;
176 
177  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
178  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
179  bool SlowFPVMLx = false;
180 
181  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
182  /// forwarding to allow mul + mla being issued back to back.
183  bool HasVMLxForwarding = false;
184 
185  /// SlowFPBrcc - True if floating point compare + branch is slow.
186  bool SlowFPBrcc = false;
187 
188  /// InThumbMode - True if compiling for Thumb, false for ARM.
189  bool InThumbMode = false;
190 
191  /// UseSoftFloat - True if we're using software floating point features.
192  bool UseSoftFloat = false;
193 
194  /// UseMISched - True if MachineScheduler should be used for this subtarget.
195  bool UseMISched = false;
196 
197  /// DisablePostRAScheduler - False if scheduling should happen again after
198  /// register allocation.
200 
201  /// HasThumb2 - True if Thumb2 instructions are supported.
202  bool HasThumb2 = false;
203 
204  /// NoARM - True if subtarget does not support ARM mode execution.
205  bool NoARM = false;
206 
207  /// ReserveR9 - True if R9 is not available as a general purpose register.
208  bool ReserveR9 = false;
209 
210  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
211  /// 32-bit imms (including global addresses).
212  bool NoMovt = false;
213 
214  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
215  /// must be able to synthesize call stubs for interworking between ARM and
216  /// Thumb.
217  bool SupportsTailCall = false;
218 
219  /// HasFP16 - True if subtarget supports half-precision FP conversions
220  bool HasFP16 = false;
221 
222  /// HasFullFP16 - True if subtarget supports half-precision FP operations
223  bool HasFullFP16 = false;
224 
225  /// HasD16 - True if subtarget is limited to 16 double precision
226  /// FP registers for VFPv3.
227  bool HasD16 = false;
228 
229  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
231 
232  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
234 
235  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
236  /// instructions.
237  bool HasDataBarrier = false;
238 
239  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
240  /// instruction.
241  bool HasFullDataBarrier = false;
242 
243  /// HasV7Clrex - True if the subtarget supports CLREX instructions
244  bool HasV7Clrex = false;
245 
246  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
247  /// instructions
248  bool HasAcquireRelease = false;
249 
250  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
251  /// over 16-bit ones.
252  bool Pref32BitThumb = false;
253 
254  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
255  /// that partially update CPSR and add false dependency on the previous
256  /// CPSR setting instruction.
258 
259  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
260  /// for instructions updating CPSR. Enabled for Cortex-A57.
262 
263  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
264  /// movs with shifter operand (i.e. asr, lsl, lsr).
266 
267  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
268  /// avoid issue "normal" call instructions to callees which do not return.
269  bool HasRetAddrStack = false;
270 
271  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
272  /// a branch predictor or not changes the expected cost of taking a branch
273  /// which affects the choice of whether to use predicated instructions.
274  bool HasBranchPredictor = true;
275 
276  /// HasMPExtension - True if the subtarget supports Multiprocessing
277  /// extension (ARMv7 only).
278  bool HasMPExtension = false;
279 
280  /// HasVirtualization - True if the subtarget supports the Virtualization
281  /// extension.
282  bool HasVirtualization = false;
283 
284  /// FPOnlySP - If true, the floating point unit only supports single
285  /// precision.
286  bool FPOnlySP = false;
287 
288  /// If true, the processor supports the Performance Monitor Extensions. These
289  /// include a generic cycle-counter as well as more fine-grained (often
290  /// implementation-specific) events.
291  bool HasPerfMon = false;
292 
293  /// HasTrustZone - if true, processor supports TrustZone security extensions
294  bool HasTrustZone = false;
295 
296  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
297  bool Has8MSecExt = false;
298 
299  /// HasCrypto - if true, processor supports Cryptography extensions
300  bool HasCrypto = false;
301 
302  /// HasCRC - if true, processor supports CRC instructions
303  bool HasCRC = false;
304 
305  /// HasRAS - if true, the processor supports RAS extensions
306  bool HasRAS = false;
307 
308  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
309  /// particularly effective at zeroing a VFP register.
310  bool HasZeroCycleZeroing = false;
311 
312  /// HasFPAO - if true, processor does positive address offset computation faster
313  bool HasFPAO = false;
314 
315  /// HasFuseAES - if true, processor executes back to back AES instruction
316  /// pairs faster.
317  bool HasFuseAES = false;
318 
319  /// If true, if conversion may decide to leave some instructions unpredicated.
321 
322  /// If true, VMOV will be favored over VGETLNi32.
323  bool HasSlowVGETLNi32 = false;
324 
325  /// If true, VMOV will be favored over VDUP.
326  bool HasSlowVDUP32 = false;
327 
328  /// If true, VMOVSR will be favored over VMOVDRR.
329  bool PreferVMOVSR = false;
330 
331  /// If true, ISHST barriers will be used for Release semantics.
332  bool PreferISHST = false;
333 
334  /// If true, a VLDM/VSTM starting with an odd register number is considered to
335  /// take more microops than single VLDRS/VSTRS.
336  bool SlowOddRegister = false;
337 
338  /// If true, loading into a D subregister will be penalized.
339  bool SlowLoadDSubregister = false;
340 
341  /// If true, the AGU and NEON/FPU units are multiplexed.
342  bool HasMuxedUnits = false;
343 
344  /// If true, VMOVS will never be widened to VMOVD
345  bool DontWidenVMOVS = false;
346 
347  /// If true, run the MLx expansion pass.
348  bool ExpandMLx = false;
349 
350  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
351  bool HasVMLxHazards = false;
352 
353  // If true, read thread pointer from coprocessor register.
354  bool ReadTPHard = false;
355 
356  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
357  bool UseNEONForFPMovs = false;
358 
359  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
360  bool CheckVLDnAlign = false;
361 
362  /// If true, VFP instructions are not pipelined.
363  bool NonpipelinedVFP = false;
364 
365  /// StrictAlign - If true, the subtarget disallows unaligned memory
366  /// accesses for some types. For details, see
367  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
368  bool StrictAlign = false;
369 
370  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
371  /// blocks to conform to ARMv8 rule.
372  bool RestrictIT = false;
373 
374  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
375  /// and such) instructions.
376  bool HasDSP = false;
377 
378  /// NaCl TRAP instruction is generated instead of the regular TRAP.
379  bool UseNaClTrap = false;
380 
381  /// Generate calls via indirect call instructions.
382  bool GenLongCalls = false;
383 
384  /// Generate code that does not contain data access to code sections.
385  bool GenExecuteOnly = false;
386 
387  /// Target machine allowed unsafe FP math (such as use of NEON fp)
388  bool UnsafeFPMath = false;
389 
390  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
391  bool UseSjLjEH = false;
392 
393  /// Implicitly convert an instruction to a different one if its immediates
394  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
395  bool NegativeImmediates = true;
396 
397  /// stackAlignment - The minimum alignment known to hold of the stack frame on
398  /// entry to the function and which must be maintained by every function.
399  unsigned stackAlignment = 4;
400 
401  /// CPUString - String name of used CPU.
402  std::string CPUString;
403 
404  unsigned MaxInterleaveFactor = 1;
405 
406  /// Clearance before partial register updates (in number of instructions)
408 
409  /// What kind of timing do load multiple/store multiple have (double issue,
410  /// single issue etc).
412 
413  /// The adjustment that we need to apply to get the operand latency from the
414  /// operand cycle returned by the itinerary data for pre-ISel operands.
416 
417  /// IsLittle - The target is Little Endian
418  bool IsLittle;
419 
420  /// TargetTriple - What processor and OS we're targeting.
422 
423  /// SchedModel - Processor specific instruction costs.
425 
426  /// Selected instruction itineraries (one entry per itinerary class.)
428 
429  /// Options passed via command line that could influence the target
431 
433 
434 public:
435  /// This constructor initializes the data members to match that
436  /// of the specified triple.
437  ///
438  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
439  const ARMBaseTargetMachine &TM, bool IsLittle);
440 
441  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
442  /// that still makes it profitable to inline the call.
443  unsigned getMaxInlineSizeThreshold() const {
444  return 64;
445  }
446 
447  /// ParseSubtargetFeatures - Parses features string setting specified
448  /// subtarget options. Definition of function is auto generated by tblgen.
450 
451  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
452  /// so that we can use initializer lists for subtarget initialization.
454 
455  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
456  return &TSInfo;
457  }
458 
459  const ARMBaseInstrInfo *getInstrInfo() const override {
460  return InstrInfo.get();
461  }
462 
463  const ARMTargetLowering *getTargetLowering() const override {
464  return &TLInfo;
465  }
466 
467  const ARMFrameLowering *getFrameLowering() const override {
468  return FrameLowering.get();
469  }
470 
471  const ARMBaseRegisterInfo *getRegisterInfo() const override {
472  return &InstrInfo->getRegisterInfo();
473  }
474 
475  const CallLowering *getCallLowering() const override;
476  const InstructionSelector *getInstructionSelector() const override;
477  const LegalizerInfo *getLegalizerInfo() const override;
478  const RegisterBankInfo *getRegBankInfo() const override;
479 
480 private:
481  ARMSelectionDAGInfo TSInfo;
482  // Either Thumb1FrameLowering or ARMFrameLowering.
483  std::unique_ptr<ARMFrameLowering> FrameLowering;
484  // Either Thumb1InstrInfo or Thumb2InstrInfo.
485  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
486  ARMTargetLowering TLInfo;
487 
488  /// GlobalISel related APIs.
489  std::unique_ptr<CallLowering> CallLoweringInfo;
490  std::unique_ptr<InstructionSelector> InstSelector;
491  std::unique_ptr<LegalizerInfo> Legalizer;
492  std::unique_ptr<RegisterBankInfo> RegBankInfo;
493 
494  void initializeEnvironment();
495  void initSubtargetFeatures(StringRef CPU, StringRef FS);
496  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
497 
498 public:
499  void computeIssueWidth();
500 
501  bool hasV4TOps() const { return HasV4TOps; }
502  bool hasV5TOps() const { return HasV5TOps; }
503  bool hasV5TEOps() const { return HasV5TEOps; }
504  bool hasV6Ops() const { return HasV6Ops; }
505  bool hasV6MOps() const { return HasV6MOps; }
506  bool hasV6KOps() const { return HasV6KOps; }
507  bool hasV6T2Ops() const { return HasV6T2Ops; }
508  bool hasV7Ops() const { return HasV7Ops; }
509  bool hasV8Ops() const { return HasV8Ops; }
510  bool hasV8_1aOps() const { return HasV8_1aOps; }
511  bool hasV8_2aOps() const { return HasV8_2aOps; }
512  bool hasV8_3aOps() const { return HasV8_3aOps; }
513  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
514  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
515 
516  /// @{
517  /// These functions are obsolete, please consider adding subtarget features
518  /// or properties instead of calling them.
519  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
520  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
521  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
522  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
523  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
524  bool isSwift() const { return ARMProcFamily == Swift; }
525  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
526  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
527  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
528  bool isKrait() const { return ARMProcFamily == Krait; }
529  /// @}
530 
531  bool hasARMOps() const { return !NoARM; }
532 
533  bool hasVFP2() const { return HasVFPv2; }
534  bool hasVFP3() const { return HasVFPv3; }
535  bool hasVFP4() const { return HasVFPv4; }
536  bool hasFPARMv8() const { return HasFPARMv8; }
537  bool hasNEON() const { return HasNEON; }
538  bool hasCrypto() const { return HasCrypto; }
539  bool hasDotProd() const { return HasDotProd; }
540  bool hasCRC() const { return HasCRC; }
541  bool hasRAS() const { return HasRAS; }
542  bool hasVirtualization() const { return HasVirtualization; }
543 
546  }
547 
550  bool hasDataBarrier() const { return HasDataBarrier; }
551  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
552  bool hasV7Clrex() const { return HasV7Clrex; }
553  bool hasAcquireRelease() const { return HasAcquireRelease; }
554 
555  bool hasAnyDataBarrier() const {
556  return HasDataBarrier || (hasV6Ops() && !isThumb());
557  }
558 
559  bool useMulOps() const { return UseMulOps; }
560  bool useFPVMLx() const { return !SlowFPVMLx; }
561  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
562  bool isFPBrccSlow() const { return SlowFPBrcc; }
563  bool isFPOnlySP() const { return FPOnlySP; }
564  bool hasPerfMon() const { return HasPerfMon; }
565  bool hasTrustZone() const { return HasTrustZone; }
566  bool has8MSecExt() const { return Has8MSecExt; }
567  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
568  bool hasFPAO() const { return HasFPAO; }
570  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
571  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
572  bool preferVMOVSR() const { return PreferVMOVSR; }
573  bool preferISHSTBarriers() const { return PreferISHST; }
574  bool expandMLx() const { return ExpandMLx; }
575  bool hasVMLxHazards() const { return HasVMLxHazards; }
576  bool hasSlowOddRegister() const { return SlowOddRegister; }
578  bool hasMuxedUnits() const { return HasMuxedUnits; }
579  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
580  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
581  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
582  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
583  bool prefers32BitThumb() const { return Pref32BitThumb; }
587  bool hasRetAddrStack() const { return HasRetAddrStack; }
588  bool hasBranchPredictor() const { return HasBranchPredictor; }
589  bool hasMPExtension() const { return HasMPExtension; }
590  bool hasDSP() const { return HasDSP; }
591  bool useNaClTrap() const { return UseNaClTrap; }
592  bool useSjLjEH() const { return UseSjLjEH; }
593  bool genLongCalls() const { return GenLongCalls; }
594  bool genExecuteOnly() const { return GenExecuteOnly; }
595 
596  bool hasFP16() const { return HasFP16; }
597  bool hasD16() const { return HasD16; }
598  bool hasFullFP16() const { return HasFullFP16; }
599 
600  bool hasFuseAES() const { return HasFuseAES; }
601  /// Return true if the CPU supports any kind of instruction fusion.
602  bool hasFusion() const { return hasFuseAES(); }
603 
604  const Triple &getTargetTriple() const { return TargetTriple; }
605 
606  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
607  bool isTargetIOS() const { return TargetTriple.isiOS(); }
608  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
609  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
610  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
611  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
612  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
613  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
614 
615  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
616  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
617  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
618 
619  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
620  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
621  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
622  // even for GNUEABI, so we can make a distinction here and still conform to
623  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
624  // FIXME: The Darwin exception is temporary, while we move users to
625  // "*-*-*-macho" triples as quickly as possible.
626  bool isTargetAEABI() const {
627  return (TargetTriple.getEnvironment() == Triple::EABI ||
628  TargetTriple.getEnvironment() == Triple::EABIHF) &&
630  }
631  bool isTargetGNUAEABI() const {
632  return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
633  TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
635  }
636  bool isTargetMuslAEABI() const {
637  return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
638  TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
640  }
641 
642  // ARM Targets that support EHABI exception handling standard
643  // Darwin uses SjLj. Other targets might need more checks.
644  bool isTargetEHABICompatible() const {
645  return (TargetTriple.getEnvironment() == Triple::EABI ||
646  TargetTriple.getEnvironment() == Triple::GNUEABI ||
647  TargetTriple.getEnvironment() == Triple::MuslEABI ||
648  TargetTriple.getEnvironment() == Triple::EABIHF ||
649  TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
650  TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
651  isTargetAndroid()) &&
653  }
654 
655  bool isTargetHardFloat() const {
656  // FIXME: this is invalid for WindowsCE
657  return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
658  TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
659  TargetTriple.getEnvironment() == Triple::EABIHF ||
661  }
662 
663  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
664 
665  bool isXRaySupported() const override;
666 
667  bool isAPCS_ABI() const;
668  bool isAAPCS_ABI() const;
669  bool isAAPCS16_ABI() const;
670 
671  bool isROPI() const;
672  bool isRWPI() const;
673 
674  bool useMachineScheduler() const { return UseMISched; }
676  bool useSoftFloat() const { return UseSoftFloat; }
677  bool isThumb() const { return InThumbMode; }
678  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
679  bool isThumb2() const { return InThumbMode && HasThumb2; }
680  bool hasThumb2() const { return HasThumb2; }
681  bool isMClass() const { return ARMProcClass == MClass; }
682  bool isRClass() const { return ARMProcClass == RClass; }
683  bool isAClass() const { return ARMProcClass == AClass; }
684  bool isReadTPHard() const { return ReadTPHard; }
685 
686  bool isR9Reserved() const {
687  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
688  }
689 
690  bool useR7AsFramePointer() const {
691  return isTargetDarwin() || (!isTargetWindows() && isThumb());
692  }
693 
694  /// Returns true if the frame setup is split into two separate pushes (first
695  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
696  /// to lr. This is always required on Thumb1-only targets, as the push and
697  /// pop instructions can't access the high registers.
698  bool splitFramePushPop(const MachineFunction &MF) const {
699  return (useR7AsFramePointer() &&
701  isThumb1Only();
702  }
703 
704  bool useStride4VFPs(const MachineFunction &MF) const;
705 
706  bool useMovt(const MachineFunction &MF) const;
707 
708  bool supportsTailCall() const { return SupportsTailCall; }
709 
710  bool allowsUnalignedMem() const { return !StrictAlign; }
711 
712  bool restrictIT() const { return RestrictIT; }
713 
714  const std::string & getCPUString() const { return CPUString; }
715 
716  bool isLittle() const { return IsLittle; }
717 
718  unsigned getMispredictionPenalty() const;
719 
720  /// Returns true if machine scheduler should be enabled.
721  bool enableMachineScheduler() const override;
722 
723  /// True for some subtargets at > -O0.
724  bool enablePostRAScheduler() const override;
725 
726  // enableAtomicExpand- True if we need to expand our atomics.
727  bool enableAtomicExpand() const override;
728 
729  /// getInstrItins - Return the instruction itineraries based on subtarget
730  /// selection.
731  const InstrItineraryData *getInstrItineraryData() const override {
732  return &InstrItins;
733  }
734 
735  /// getStackAlignment - Returns the minimum alignment known to hold of the
736  /// stack frame on entry to the function and which must be maintained by every
737  /// function for this subtarget.
738  unsigned getStackAlignment() const { return stackAlignment; }
739 
740  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
741 
743 
745  return LdStMultipleTiming;
746  }
747 
750  }
751 
752  /// True if the GV will be accessed via an indirect symbol.
753  bool isGVIndirectSymbol(const GlobalValue *GV) const;
754 
755  /// Returns the constant pool modifier needed to access the GV.
756  bool isGVInGOT(const GlobalValue *GV) const;
757 
758  /// True if fast-isel is used.
759  bool useFastISel() const;
760 
761  /// Returns the correct return opcode for the current feature set.
762  /// Use BX if available to allow mixing thumb/arm code, but fall back
763  /// to plain mov pc,lr on ARMv4.
764  unsigned getReturnOpcode() const {
765  if (isThumb())
766  return ARM::tBX_RET;
767  if (hasV4TOps())
768  return ARM::BX_RET;
769  return ARM::MOVPCLR;
770  }
771 
772  /// Allow movt+movw for PIC global address calculation.
773  /// ELF does not have GOT relocations for movt+movw.
774  /// ROPI does not use GOT.
776  return isROPI() || !isTargetELF();
777  }
778 };
779 
780 } // end namespace llvm
781 
782 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:212
bool hasV5TEOps() const
Definition: ARMSubtarget.h:503
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:468
bool hasCRC() const
Definition: ARMSubtarget.h:540
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:357
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:631
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:511
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:399
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:348
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:421
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:581
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:584
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:274
bool hasRAS() const
Definition: ARMSubtarget.h:541
bool isThumb() const
Definition: ARMSubtarget.h:677
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:548
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:179
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:339
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:455
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
bool hasV4TOps() const
Definition: ARMSubtarget.h:501
bool isLittle() const
Definition: ARMSubtarget.h:716
bool useFastISel() const
True if fast-isel is used.
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:588
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:269
bool isTargetHardFloat() const
Definition: ARMSubtarget.h:655
bool isTargetNaCl() const
Definition: ARMSubtarget.h:611
bool hasFuseAES() const
Definition: ARMSubtarget.h:600
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:463
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:223
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:230
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:326
bool preferVMOVSR() const
Definition: ARMSubtarget.h:572
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:565
bool hasV7Ops() const
Definition: ARMSubtarget.h:508
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:583
bool isCortexA5() const
Definition: ARMSubtarget.h:519
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:459
bool hasVFP3() const
Definition: ARMSubtarget.h:534
bool isTargetCOFF() const
Definition: ARMSubtarget.h:615
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:159
bool useNaClTrap() const
Definition: ARMSubtarget.h:591
bool hasV6Ops() const
Definition: ARMSubtarget.h:504
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:233
bool hasDotProd() const
Definition: ARMSubtarget.h:539
bool isThumb1Only() const
Definition: ARMSubtarget.h:678
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:636
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:553
const LegalizerInfo * getLegalizerInfo() const override
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:586
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:432
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:382
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:612
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:217
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:571
bool isFPOnlySP() const
Definition: ARMSubtarget.h:563
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:342
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:323
bool isRClass() const
Definition: ARMSubtarget.h:682
bool genExecuteOnly() const
Definition: ARMSubtarget.h:594
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:740
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:175
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:459
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:513
bool isTargetELF() const
Definition: ARMSubtarget.h:616
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:123
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:297
Holds all the information related to register banks.
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:306
bool hasARMOps() const
Definition: ARMSubtarget.h:531
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:336
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:310
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:368
bool hasV8Ops() const
Definition: ARMSubtarget.h:509
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:202
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:317
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:388
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:580
bool hasPerfMon() const
Definition: ARMSubtarget.h:564
bool useStride4VFPs(const MachineFunction &MF) const
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:345
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool hasVFP2() const
Definition: ARMSubtarget.h:533
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:329
bool isReadTPHard() const
Definition: ARMSubtarget.h:684
bool isCortexM3() const
Definition: ARMSubtarget.h:525
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:252
bool isCortexR5() const
Definition: ARMSubtarget.h:527
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:418
bool hasDSP() const
Definition: ARMSubtarget.h:590
bool useFPVMLx() const
Definition: ARMSubtarget.h:560
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:443
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:698
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:551
bool useMovt(const MachineFunction &MF) const
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:116
bool enableAtomicExpand() const override
bool hasVirtualization() const
Definition: ARMSubtarget.h:542
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:121
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:578
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isXRaySupported() const override
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:644
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:205
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:544
bool hasFPAO() const
Definition: ARMSubtarget.h:568
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:742
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:507
bool isTargetDarwin() const
Definition: ARMSubtarget.h:606
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:415
bool hasV6MOps() const
Definition: ARMSubtarget.h:505
Itinerary data supplied by a subtarget to be used by a target.
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:449
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:395
bool isOSNetBSD() const
Definition: Triple.h:476
bool isAClass() const
Definition: ARMSubtarget.h:683
bool hasFP16() const
Definition: ARMSubtarget.h:596
bool hasD16() const
Definition: ARMSubtarget.h:597
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:690
bool isR9Reserved() const
Definition: ARMSubtarget.h:686
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:291
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:570
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:549
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:609
bool hasCrypto() const
Definition: ARMSubtarget.h:538
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:560
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:265
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:303
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:569
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:376
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:244
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:573
bool hasV6KOps() const
Definition: ARMSubtarget.h:506
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:282
bool has8MSecExt() const
Definition: ARMSubtarget.h:566
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:738
bool restrictIT() const
Definition: ARMSubtarget.h:712
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:131
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:372
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:591
bool isMClass() const
Definition: ARMSubtarget.h:681
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:320
bool isWatchABI() const
Definition: Triple.h:463
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:195
bool useMachineScheduler() const
Definition: ARMSubtarget.h:674
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:142
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:183
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:608
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:199
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:351
bool hasFPARMv8() const
Definition: ARMSubtarget.h:536
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:300
bool useMulOps() const
Definition: ARMSubtarget.h:559
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:582
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:577
unsigned getMispredictionPenalty() const
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:278
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:710
bool hasTrustZone() const
Definition: ARMSubtarget.h:565
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:467
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:576
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:596
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:166
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
bool useSjLjEH() const
Definition: ARMSubtarget.h:592
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:363
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:744
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasV7Clrex() const
Definition: ARMSubtarget.h:552
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:220
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:294
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:189
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
const std::string & getCPUString() const
Definition: ARMSubtarget.h:714
bool isCortexA9() const
Definition: ARMSubtarget.h:522
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useSoftFloat() const
Definition: ARMSubtarget.h:676
bool isTargetAEABI() const
Definition: ARMSubtarget.h:626
bool isTargetLinux() const
Definition: ARMSubtarget.h:610
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:731
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:562
const InstructionSelector * getInstructionSelector() const override
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:585
bool isTargetAndroid() const
Definition: ARMSubtarget.h:663
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:137
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:775
bool hasMPExtension() const
Definition: ARMSubtarget.h:589
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:570
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
Definition: ARMSubtarget.h:286
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:134
bool hasNEON() const
Definition: ARMSubtarget.h:537
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:301
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:385
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:379
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR...
Definition: ARMSubtarget.h:261
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:424
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:332
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:675
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:430
bool genLongCalls() const
Definition: ARMSubtarget.h:593
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool UseSoftFloat
UseSoftFloat - True if we&#39;re using software floating point features.
Definition: ARMSubtarget.h:192
bool isROPI() const
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:764
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:561
bool expandMLx() const
Definition: ARMSubtarget.h:574
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:510
Provides the logic to select generic machine instructions.
bool isThumb2() const
Definition: ARMSubtarget.h:679
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:604
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:567
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:587
bool isTargetIOS() const
Definition: ARMSubtarget.h:607
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:208
TargetOptions Options
Definition: TargetMachine.h:98
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:427
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:171
bool isCortexA7() const
Definition: ARMSubtarget.h:520
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:471
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:407
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:748
bool hasV5TOps() const
Definition: ARMSubtarget.h:502
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:575
bool isTargetMachO() const
Definition: ARMSubtarget.h:617
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:186
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:411
bool isKrait() const
Definition: ARMSubtarget.h:528
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:227
bool isSwift() const
Definition: ARMSubtarget.h:524
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool supportsTailCall() const
Definition: ARMSubtarget.h:708
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:126
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:257
bool isCortexA8() const
Definition: ARMSubtarget.h:521
This file describes how to lower LLVM calls to machine code calls.
bool hasVFP4() const
Definition: ARMSubtarget.h:535
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:619
bool isRWPI() const
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:514
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:118
bool isTargetWindows() const
Definition: ARMSubtarget.h:613
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction. ...
Definition: ARMSubtarget.h:241
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:402
bool isCortexA15() const
Definition: ARMSubtarget.h:523
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:248
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:602
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:555
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:313
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:237
bool isAAPCS_ABI() const
bool hasDataBarrier() const
Definition: ARMSubtarget.h:550
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:247
bool hasThumb2() const
Definition: ARMSubtarget.h:680
bool isLikeA9() const
Definition: ARMSubtarget.h:526
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:360
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:391
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:579
bool hasFullFP16() const
Definition: ARMSubtarget.h:598
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:404
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:512