LLVM  8.0.0svn
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16 
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBaseRegisterInfo.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMISelLowering.h"
22 #include "ARMSelectionDAGInfo.h"
23 #include "llvm/ADT/Triple.h"
31 #include "llvm/MC/MCSchedule.h"
33 #include <memory>
34 #include <string>
35 
36 #define GET_SUBTARGETINFO_HEADER
37 #include "ARMGenSubtargetInfo.inc"
38 
39 namespace llvm {
40 
41 class ARMBaseTargetMachine;
42 class GlobalValue;
43 class StringRef;
44 
46 protected:
49 
75  };
78 
82  };
83  enum ARMArchEnum {
113  };
114 
115 public:
116  /// What kind of timing do load multiple/store multiple instructions have.
118  /// Can load/store 2 registers/cycle.
120  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
121  /// is not 64-bit aligned.
123  /// Can load/store 1 register/cycle.
125  /// Can load/store 1 register/cycle, but needs an extra cycle for address
126  /// computation and potentially also for register writeback.
128  };
129 
130 protected:
131  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
133 
134  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
136 
137  /// ARMArch - ARM architecture
139 
140  /// HasV4TOps, HasV5TOps, HasV5TEOps,
141  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
142  /// Specify whether target support specific ARM ISA variants.
143  bool HasV4TOps = false;
144  bool HasV5TOps = false;
145  bool HasV5TEOps = false;
146  bool HasV6Ops = false;
147  bool HasV6MOps = false;
148  bool HasV6KOps = false;
149  bool HasV6T2Ops = false;
150  bool HasV7Ops = false;
151  bool HasV8Ops = false;
152  bool HasV8_1aOps = false;
153  bool HasV8_2aOps = false;
154  bool HasV8_3aOps = false;
155  bool HasV8_4aOps = false;
156  bool HasV8MBaselineOps = false;
157  bool HasV8MMainlineOps = false;
158 
159  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
160  /// floating point ISAs are supported.
161  bool HasVFPv2 = false;
162  bool HasVFPv3 = false;
163  bool HasVFPv4 = false;
164  bool HasFPARMv8 = false;
165  bool HasNEON = false;
166 
167  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
168  bool HasDotProd = false;
169 
170  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
171  /// specified. Use the method useNEONForSinglePrecisionFP() to
172  /// determine if NEON should actually be used.
174 
175  /// UseMulOps - True if non-microcoded fused integer multiply-add and
176  /// multiply-subtract instructions should be used.
177  bool UseMulOps = false;
178 
179  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
180  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
181  bool SlowFPVMLx = false;
182 
183  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
184  /// forwarding to allow mul + mla being issued back to back.
185  bool HasVMLxForwarding = false;
186 
187  /// SlowFPBrcc - True if floating point compare + branch is slow.
188  bool SlowFPBrcc = false;
189 
190  /// InThumbMode - True if compiling for Thumb, false for ARM.
191  bool InThumbMode = false;
192 
193  /// UseSoftFloat - True if we're using software floating point features.
194  bool UseSoftFloat = false;
195 
196  /// UseMISched - True if MachineScheduler should be used for this subtarget.
197  bool UseMISched = false;
198 
199  /// DisablePostRAScheduler - False if scheduling should happen again after
200  /// register allocation.
202 
203  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
204  bool UseAA = false;
205 
206  /// HasThumb2 - True if Thumb2 instructions are supported.
207  bool HasThumb2 = false;
208 
209  /// NoARM - True if subtarget does not support ARM mode execution.
210  bool NoARM = false;
211 
212  /// ReserveR9 - True if R9 is not available as a general purpose register.
213  bool ReserveR9 = false;
214 
215  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
216  /// 32-bit imms (including global addresses).
217  bool NoMovt = false;
218 
219  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
220  /// must be able to synthesize call stubs for interworking between ARM and
221  /// Thumb.
222  bool SupportsTailCall = false;
223 
224  /// HasFP16 - True if subtarget supports half-precision FP conversions
225  bool HasFP16 = false;
226 
227  /// HasFullFP16 - True if subtarget supports half-precision FP operations
228  bool HasFullFP16 = false;
229 
230  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
231  bool HasFP16FML = false;
232 
233  /// HasD16 - True if subtarget is limited to 16 double precision
234  /// FP registers for VFPv3.
235  bool HasD16 = false;
236 
237  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
239 
240  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
242 
243  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
244  /// instructions.
245  bool HasDataBarrier = false;
246 
247  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
248  /// instruction.
249  bool HasFullDataBarrier = false;
250 
251  /// HasV7Clrex - True if the subtarget supports CLREX instructions
252  bool HasV7Clrex = false;
253 
254  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
255  /// instructions
256  bool HasAcquireRelease = false;
257 
258  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
259  /// over 16-bit ones.
260  bool Pref32BitThumb = false;
261 
262  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
263  /// that partially update CPSR and add false dependency on the previous
264  /// CPSR setting instruction.
266 
267  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
268  /// for instructions updating CPSR. Enabled for Cortex-A57.
270 
271  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
272  /// movs with shifter operand (i.e. asr, lsl, lsr).
274 
275  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
276  /// avoid issue "normal" call instructions to callees which do not return.
277  bool HasRetAddrStack = false;
278 
279  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
280  /// a branch predictor or not changes the expected cost of taking a branch
281  /// which affects the choice of whether to use predicated instructions.
282  bool HasBranchPredictor = true;
283 
284  /// HasMPExtension - True if the subtarget supports Multiprocessing
285  /// extension (ARMv7 only).
286  bool HasMPExtension = false;
287 
288  /// HasVirtualization - True if the subtarget supports the Virtualization
289  /// extension.
290  bool HasVirtualization = false;
291 
292  /// FPOnlySP - If true, the floating point unit only supports single
293  /// precision.
294  bool FPOnlySP = false;
295 
296  /// If true, the processor supports the Performance Monitor Extensions. These
297  /// include a generic cycle-counter as well as more fine-grained (often
298  /// implementation-specific) events.
299  bool HasPerfMon = false;
300 
301  /// HasTrustZone - if true, processor supports TrustZone security extensions
302  bool HasTrustZone = false;
303 
304  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
305  bool Has8MSecExt = false;
306 
307  /// HasSHA2 - if true, processor supports SHA1 and SHA256
308  bool HasSHA2 = false;
309 
310  /// HasAES - if true, processor supports AES
311  bool HasAES = false;
312 
313  /// HasCrypto - if true, processor supports Cryptography extensions
314  bool HasCrypto = false;
315 
316  /// HasCRC - if true, processor supports CRC instructions
317  bool HasCRC = false;
318 
319  /// HasRAS - if true, the processor supports RAS extensions
320  bool HasRAS = false;
321 
322  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
323  /// particularly effective at zeroing a VFP register.
324  bool HasZeroCycleZeroing = false;
325 
326  /// HasFPAO - if true, processor does positive address offset computation faster
327  bool HasFPAO = false;
328 
329  /// HasFuseAES - if true, processor executes back to back AES instruction
330  /// pairs faster.
331  bool HasFuseAES = false;
332 
333  /// HasFuseLiterals - if true, processor executes back to back
334  /// bottom and top halves of literal generation faster.
335  bool HasFuseLiterals = false;
336 
337  /// If true, if conversion may decide to leave some instructions unpredicated.
339 
340  /// If true, VMOV will be favored over VGETLNi32.
341  bool HasSlowVGETLNi32 = false;
342 
343  /// If true, VMOV will be favored over VDUP.
344  bool HasSlowVDUP32 = false;
345 
346  /// If true, VMOVSR will be favored over VMOVDRR.
347  bool PreferVMOVSR = false;
348 
349  /// If true, ISHST barriers will be used for Release semantics.
350  bool PreferISHST = false;
351 
352  /// If true, a VLDM/VSTM starting with an odd register number is considered to
353  /// take more microops than single VLDRS/VSTRS.
354  bool SlowOddRegister = false;
355 
356  /// If true, loading into a D subregister will be penalized.
357  bool SlowLoadDSubregister = false;
358 
359  /// If true, use a wider stride when allocating VFP registers.
360  bool UseWideStrideVFP = false;
361 
362  /// If true, the AGU and NEON/FPU units are multiplexed.
363  bool HasMuxedUnits = false;
364 
365  /// If true, VMOVS will never be widened to VMOVD.
366  bool DontWidenVMOVS = false;
367 
368  /// If true, splat a register between VFP and NEON instructions.
369  bool SplatVFPToNeon = false;
370 
371  /// If true, run the MLx expansion pass.
372  bool ExpandMLx = false;
373 
374  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
375  bool HasVMLxHazards = false;
376 
377  // If true, read thread pointer from coprocessor register.
378  bool ReadTPHard = false;
379 
380  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
381  bool UseNEONForFPMovs = false;
382 
383  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
384  bool CheckVLDnAlign = false;
385 
386  /// If true, VFP instructions are not pipelined.
387  bool NonpipelinedVFP = false;
388 
389  /// StrictAlign - If true, the subtarget disallows unaligned memory
390  /// accesses for some types. For details, see
391  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
392  bool StrictAlign = false;
393 
394  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
395  /// blocks to conform to ARMv8 rule.
396  bool RestrictIT = false;
397 
398  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
399  /// and such) instructions.
400  bool HasDSP = false;
401 
402  /// NaCl TRAP instruction is generated instead of the regular TRAP.
403  bool UseNaClTrap = false;
404 
405  /// Generate calls via indirect call instructions.
406  bool GenLongCalls = false;
407 
408  /// Generate code that does not contain data access to code sections.
409  bool GenExecuteOnly = false;
410 
411  /// Target machine allowed unsafe FP math (such as use of NEON fp)
412  bool UnsafeFPMath = false;
413 
414  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
415  bool UseSjLjEH = false;
416 
417  /// Implicitly convert an instruction to a different one if its immediates
418  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
419  bool NegativeImmediates = true;
420 
421  /// stackAlignment - The minimum alignment known to hold of the stack frame on
422  /// entry to the function and which must be maintained by every function.
423  unsigned stackAlignment = 4;
424 
425  /// CPUString - String name of used CPU.
426  std::string CPUString;
427 
428  unsigned MaxInterleaveFactor = 1;
429 
430  /// Clearance before partial register updates (in number of instructions)
432 
433  /// What kind of timing do load multiple/store multiple have (double issue,
434  /// single issue etc).
436 
437  /// The adjustment that we need to apply to get the operand latency from the
438  /// operand cycle returned by the itinerary data for pre-ISel operands.
440 
441  /// What alignment is preferred for loop bodies, in log2(bytes).
442  unsigned PrefLoopAlignment = 0;
443 
444  /// IsLittle - The target is Little Endian
445  bool IsLittle;
446 
447  /// TargetTriple - What processor and OS we're targeting.
449 
450  /// SchedModel - Processor specific instruction costs.
452 
453  /// Selected instruction itineraries (one entry per itinerary class.)
455 
456  /// Options passed via command line that could influence the target
458 
460 
461 public:
462  /// This constructor initializes the data members to match that
463  /// of the specified triple.
464  ///
465  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
466  const ARMBaseTargetMachine &TM, bool IsLittle);
467 
468  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
469  /// that still makes it profitable to inline the call.
470  unsigned getMaxInlineSizeThreshold() const {
471  return 64;
472  }
473 
474  /// ParseSubtargetFeatures - Parses features string setting specified
475  /// subtarget options. Definition of function is auto generated by tblgen.
477 
478  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
479  /// so that we can use initializer lists for subtarget initialization.
481 
482  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
483  return &TSInfo;
484  }
485 
486  const ARMBaseInstrInfo *getInstrInfo() const override {
487  return InstrInfo.get();
488  }
489 
490  const ARMTargetLowering *getTargetLowering() const override {
491  return &TLInfo;
492  }
493 
494  const ARMFrameLowering *getFrameLowering() const override {
495  return FrameLowering.get();
496  }
497 
498  const ARMBaseRegisterInfo *getRegisterInfo() const override {
499  return &InstrInfo->getRegisterInfo();
500  }
501 
502  const CallLowering *getCallLowering() const override;
503  const InstructionSelector *getInstructionSelector() const override;
504  const LegalizerInfo *getLegalizerInfo() const override;
505  const RegisterBankInfo *getRegBankInfo() const override;
506 
507 private:
508  ARMSelectionDAGInfo TSInfo;
509  // Either Thumb1FrameLowering or ARMFrameLowering.
510  std::unique_ptr<ARMFrameLowering> FrameLowering;
511  // Either Thumb1InstrInfo or Thumb2InstrInfo.
512  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
513  ARMTargetLowering TLInfo;
514 
515  /// GlobalISel related APIs.
516  std::unique_ptr<CallLowering> CallLoweringInfo;
517  std::unique_ptr<InstructionSelector> InstSelector;
518  std::unique_ptr<LegalizerInfo> Legalizer;
519  std::unique_ptr<RegisterBankInfo> RegBankInfo;
520 
521  void initializeEnvironment();
522  void initSubtargetFeatures(StringRef CPU, StringRef FS);
523  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
524 
525 public:
526  void computeIssueWidth();
527 
528  bool hasV4TOps() const { return HasV4TOps; }
529  bool hasV5TOps() const { return HasV5TOps; }
530  bool hasV5TEOps() const { return HasV5TEOps; }
531  bool hasV6Ops() const { return HasV6Ops; }
532  bool hasV6MOps() const { return HasV6MOps; }
533  bool hasV6KOps() const { return HasV6KOps; }
534  bool hasV6T2Ops() const { return HasV6T2Ops; }
535  bool hasV7Ops() const { return HasV7Ops; }
536  bool hasV8Ops() const { return HasV8Ops; }
537  bool hasV8_1aOps() const { return HasV8_1aOps; }
538  bool hasV8_2aOps() const { return HasV8_2aOps; }
539  bool hasV8_3aOps() const { return HasV8_3aOps; }
540  bool hasV8_4aOps() const { return HasV8_4aOps; }
541  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
542  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
543 
544  /// @{
545  /// These functions are obsolete, please consider adding subtarget features
546  /// or properties instead of calling them.
547  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
548  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
549  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
550  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
551  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
552  bool isSwift() const { return ARMProcFamily == Swift; }
553  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
554  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
555  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
556  bool isKrait() const { return ARMProcFamily == Krait; }
557  /// @}
558 
559  bool hasARMOps() const { return !NoARM; }
560 
561  bool hasVFP2() const { return HasVFPv2; }
562  bool hasVFP3() const { return HasVFPv3; }
563  bool hasVFP4() const { return HasVFPv4; }
564  bool hasFPARMv8() const { return HasFPARMv8; }
565  bool hasNEON() const { return HasNEON; }
566  bool hasSHA2() const { return HasSHA2; }
567  bool hasAES() const { return HasAES; }
568  bool hasCrypto() const { return HasCrypto; }
569  bool hasDotProd() const { return HasDotProd; }
570  bool hasCRC() const { return HasCRC; }
571  bool hasRAS() const { return HasRAS; }
572  bool hasVirtualization() const { return HasVirtualization; }
573 
576  }
577 
580  bool hasDataBarrier() const { return HasDataBarrier; }
581  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
582  bool hasV7Clrex() const { return HasV7Clrex; }
583  bool hasAcquireRelease() const { return HasAcquireRelease; }
584 
585  bool hasAnyDataBarrier() const {
586  return HasDataBarrier || (hasV6Ops() && !isThumb());
587  }
588 
589  bool useMulOps() const { return UseMulOps; }
590  bool useFPVMLx() const { return !SlowFPVMLx; }
591  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
592  bool isFPBrccSlow() const { return SlowFPBrcc; }
593  bool isFPOnlySP() const { return FPOnlySP; }
594  bool hasPerfMon() const { return HasPerfMon; }
595  bool hasTrustZone() const { return HasTrustZone; }
596  bool has8MSecExt() const { return Has8MSecExt; }
597  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
598  bool hasFPAO() const { return HasFPAO; }
600  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
601  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
602  bool preferVMOVSR() const { return PreferVMOVSR; }
603  bool preferISHSTBarriers() const { return PreferISHST; }
604  bool expandMLx() const { return ExpandMLx; }
605  bool hasVMLxHazards() const { return HasVMLxHazards; }
606  bool hasSlowOddRegister() const { return SlowOddRegister; }
608  bool useWideStrideVFP() const { return UseWideStrideVFP; }
609  bool hasMuxedUnits() const { return HasMuxedUnits; }
610  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
611  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
612  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
613  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
614  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
615  bool prefers32BitThumb() const { return Pref32BitThumb; }
619  bool hasRetAddrStack() const { return HasRetAddrStack; }
620  bool hasBranchPredictor() const { return HasBranchPredictor; }
621  bool hasMPExtension() const { return HasMPExtension; }
622  bool hasDSP() const { return HasDSP; }
623  bool useNaClTrap() const { return UseNaClTrap; }
624  bool useSjLjEH() const { return UseSjLjEH; }
625  bool genLongCalls() const { return GenLongCalls; }
626  bool genExecuteOnly() const { return GenExecuteOnly; }
627 
628  bool hasFP16() const { return HasFP16; }
629  bool hasD16() const { return HasD16; }
630  bool hasFullFP16() const { return HasFullFP16; }
631  bool hasFP16FML() const { return HasFP16FML; }
632 
633  bool hasFuseAES() const { return HasFuseAES; }
634  bool hasFuseLiterals() const { return HasFuseLiterals; }
635  /// Return true if the CPU supports any kind of instruction fusion.
636  bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
637 
638  const Triple &getTargetTriple() const { return TargetTriple; }
639 
640  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
641  bool isTargetIOS() const { return TargetTriple.isiOS(); }
642  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
643  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
644  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
645  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
646  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
647  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
648 
649  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
650  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
651  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
652 
653  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
654  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
655  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
656  // even for GNUEABI, so we can make a distinction here and still conform to
657  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
658  // FIXME: The Darwin exception is temporary, while we move users to
659  // "*-*-*-macho" triples as quickly as possible.
660  bool isTargetAEABI() const {
661  return (TargetTriple.getEnvironment() == Triple::EABI ||
662  TargetTriple.getEnvironment() == Triple::EABIHF) &&
664  }
665  bool isTargetGNUAEABI() const {
666  return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
667  TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
669  }
670  bool isTargetMuslAEABI() const {
671  return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
672  TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
674  }
675 
676  // ARM Targets that support EHABI exception handling standard
677  // Darwin uses SjLj. Other targets might need more checks.
678  bool isTargetEHABICompatible() const {
679  return (TargetTriple.getEnvironment() == Triple::EABI ||
680  TargetTriple.getEnvironment() == Triple::GNUEABI ||
681  TargetTriple.getEnvironment() == Triple::MuslEABI ||
682  TargetTriple.getEnvironment() == Triple::EABIHF ||
683  TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
684  TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
685  isTargetAndroid()) &&
687  }
688 
689  bool isTargetHardFloat() const;
690 
691  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
692 
693  bool isXRaySupported() const override;
694 
695  bool isAPCS_ABI() const;
696  bool isAAPCS_ABI() const;
697  bool isAAPCS16_ABI() const;
698 
699  bool isROPI() const;
700  bool isRWPI() const;
701 
702  bool useMachineScheduler() const { return UseMISched; }
704  bool useSoftFloat() const { return UseSoftFloat; }
705  bool isThumb() const { return InThumbMode; }
706  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
707  bool isThumb2() const { return InThumbMode && HasThumb2; }
708  bool hasThumb2() const { return HasThumb2; }
709  bool isMClass() const { return ARMProcClass == MClass; }
710  bool isRClass() const { return ARMProcClass == RClass; }
711  bool isAClass() const { return ARMProcClass == AClass; }
712  bool isReadTPHard() const { return ReadTPHard; }
713 
714  bool isR9Reserved() const {
715  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
716  }
717 
718  bool useR7AsFramePointer() const {
719  return isTargetDarwin() || (!isTargetWindows() && isThumb());
720  }
721 
722  /// Returns true if the frame setup is split into two separate pushes (first
723  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
724  /// to lr. This is always required on Thumb1-only targets, as the push and
725  /// pop instructions can't access the high registers.
726  bool splitFramePushPop(const MachineFunction &MF) const {
727  return (useR7AsFramePointer() &&
729  isThumb1Only();
730  }
731 
732  bool useStride4VFPs(const MachineFunction &MF) const;
733 
734  bool useMovt(const MachineFunction &MF) const;
735 
736  bool supportsTailCall() const { return SupportsTailCall; }
737 
738  bool allowsUnalignedMem() const { return !StrictAlign; }
739 
740  bool restrictIT() const { return RestrictIT; }
741 
742  const std::string & getCPUString() const { return CPUString; }
743 
744  bool isLittle() const { return IsLittle; }
745 
746  unsigned getMispredictionPenalty() const;
747 
748  /// Returns true if machine scheduler should be enabled.
749  bool enableMachineScheduler() const override;
750 
751  /// True for some subtargets at > -O0.
752  bool enablePostRAScheduler() const override;
753 
754  /// Enable use of alias analysis during code generation (during MI
755  /// scheduling, DAGCombine, etc.).
756  bool useAA() const override { return UseAA; }
757 
758  // enableAtomicExpand- True if we need to expand our atomics.
759  bool enableAtomicExpand() const override;
760 
761  /// getInstrItins - Return the instruction itineraries based on subtarget
762  /// selection.
763  const InstrItineraryData *getInstrItineraryData() const override {
764  return &InstrItins;
765  }
766 
767  /// getStackAlignment - Returns the minimum alignment known to hold of the
768  /// stack frame on entry to the function and which must be maintained by every
769  /// function for this subtarget.
770  unsigned getStackAlignment() const { return stackAlignment; }
771 
772  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
773 
775 
777  return LdStMultipleTiming;
778  }
779 
782  }
783 
784  /// True if the GV will be accessed via an indirect symbol.
785  bool isGVIndirectSymbol(const GlobalValue *GV) const;
786 
787  /// Returns the constant pool modifier needed to access the GV.
788  bool isGVInGOT(const GlobalValue *GV) const;
789 
790  /// True if fast-isel is used.
791  bool useFastISel() const;
792 
793  /// Returns the correct return opcode for the current feature set.
794  /// Use BX if available to allow mixing thumb/arm code, but fall back
795  /// to plain mov pc,lr on ARMv4.
796  unsigned getReturnOpcode() const {
797  if (isThumb())
798  return ARM::tBX_RET;
799  if (hasV4TOps())
800  return ARM::BX_RET;
801  return ARM::MOVPCLR;
802  }
803 
804  /// Allow movt+movw for PIC global address calculation.
805  /// ELF does not have GOT relocations for movt+movw.
806  /// ROPI does not use GOT.
808  return isROPI() || !isTargetELF();
809  }
810 
811  unsigned getPrefLoopAlignment() const {
812  return PrefLoopAlignment;
813  }
814 };
815 
816 } // end namespace llvm
817 
818 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:217
bool hasV5TEOps() const
Definition: ARMSubtarget.h:530
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:471
bool hasCRC() const
Definition: ARMSubtarget.h:570
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:381
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:665
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:538
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:423
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:372
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
Definition: ARMSubtarget.h:448
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:613
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:616
bool HasBranchPredictor
HasBranchPredictor - True if the subtarget has a branch predictor.
Definition: ARMSubtarget.h:282
bool hasRAS() const
Definition: ARMSubtarget.h:571
bool hasSHA2() const
Definition: ARMSubtarget.h:566
bool isThumb() const
Definition: ARMSubtarget.h:705
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasDivideInThumbMode() const
Definition: ARMSubtarget.h:578
bool SplatVFPToNeon
If true, splat a register between VFP and NEON instructions.
Definition: ARMSubtarget.h:369
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:181
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:357
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:482
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:589
bool hasV4TOps() const
Definition: ARMSubtarget.h:528
bool isLittle() const
Definition: ARMSubtarget.h:744
bool useFastISel() const
True if fast-isel is used.
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:620
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:277
bool isTargetNaCl() const
Definition: ARMSubtarget.h:645
bool hasFuseAES() const
Definition: ARMSubtarget.h:633
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:490
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:228
bool HasHardwareDivideInThumb
HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.
Definition: ARMSubtarget.h:238
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:344
bool preferVMOVSR() const
Definition: ARMSubtarget.h:602
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:568
bool hasV7Ops() const
Definition: ARMSubtarget.h:535
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:615
bool isCortexA5() const
Definition: ARMSubtarget.h:547
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:462
bool hasVFP3() const
Definition: ARMSubtarget.h:562
bool isTargetCOFF() const
Definition: ARMSubtarget.h:649
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:161
bool useNaClTrap() const
Definition: ARMSubtarget.h:623
bool UseAA
UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
Definition: ARMSubtarget.h:204
bool hasV6Ops() const
Definition: ARMSubtarget.h:531
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:241
bool hasDotProd() const
Definition: ARMSubtarget.h:569
bool isThumb1Only() const
Definition: ARMSubtarget.h:706
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:670
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:583
const LegalizerInfo * getLegalizerInfo() const override
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:618
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:459
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:406
bool isTargetHardFloat() const
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:646
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:222
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:601
bool isFPOnlySP() const
Definition: ARMSubtarget.h:593
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:363
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:341
bool isRClass() const
Definition: ARMSubtarget.h:710
bool genExecuteOnly() const
Definition: ARMSubtarget.h:626
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:772
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:177
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:486
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:541
bool isTargetELF() const
Definition: ARMSubtarget.h:650
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:124
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:305
Holds all the information related to register banks.
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:320
bool hasARMOps() const
Definition: ARMSubtarget.h:559
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:354
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:324
bool hasV8_4aOps() const
Definition: ARMSubtarget.h:540
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:392
bool hasV8Ops() const
Definition: ARMSubtarget.h:536
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:207
bool HasFuseAES
HasFuseAES - if true, processor executes back to back AES instruction pairs faster.
Definition: ARMSubtarget.h:331
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:412
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:612
bool hasPerfMon() const
Definition: ARMSubtarget.h:594
bool hasFuseLiterals() const
Definition: ARMSubtarget.h:634
bool useStride4VFPs(const MachineFunction &MF) const
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:366
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool hasVFP2() const
Definition: ARMSubtarget.h:561
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:347
bool isReadTPHard() const
Definition: ARMSubtarget.h:712
bool isCortexM3() const
Definition: ARMSubtarget.h:553
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:260
bool isCortexR5() const
Definition: ARMSubtarget.h:555
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:445
bool hasDSP() const
Definition: ARMSubtarget.h:622
bool useFPVMLx() const
Definition: ARMSubtarget.h:590
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:470
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:726
bool hasFullDataBarrier() const
Definition: ARMSubtarget.h:581
bool useMovt(const MachineFunction &MF) const
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:117
bool enableAtomicExpand() const override
bool hasVirtualization() const
Definition: ARMSubtarget.h:572
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:122
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:609
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isXRaySupported() const override
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:678
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:210
bool HasFuseLiterals
HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generatio...
Definition: ARMSubtarget.h:335
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:574
bool hasFPAO() const
Definition: ARMSubtarget.h:598
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:774
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:534
bool isTargetDarwin() const
Definition: ARMSubtarget.h:640
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:439
bool HasAES
HasAES - if true, processor supports AES.
Definition: ARMSubtarget.h:311
bool hasV6MOps() const
Definition: ARMSubtarget.h:532
Itinerary data supplied by a subtarget to be used by a target.
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:452
bool NegativeImmediates
Implicitly convert an instruction to a different one if its immediates cannot be encoded.
Definition: ARMSubtarget.h:419
bool isOSNetBSD() const
Definition: Triple.h:479
bool isAClass() const
Definition: ARMSubtarget.h:711
bool hasFP16() const
Definition: ARMSubtarget.h:628
bool hasD16() const
Definition: ARMSubtarget.h:629
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:718
bool isR9Reserved() const
Definition: ARMSubtarget.h:714
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:299
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:600
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:579
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:643
bool hasCrypto() const
Definition: ARMSubtarget.h:568
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:563
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:273
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:317
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:599
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:400
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:252
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:603
bool hasV6KOps() const
Definition: ARMSubtarget.h:533
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:290
bool has8MSecExt() const
Definition: ARMSubtarget.h:596
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:770
bool restrictIT() const
Definition: ARMSubtarget.h:740
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:132
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:396
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:594
bool isMClass() const
Definition: ARMSubtarget.h:709
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:338
bool isWatchABI() const
Definition: Triple.h:466
bool UseMISched
UseMISched - True if MachineScheduler should be used for this subtarget.
Definition: ARMSubtarget.h:197
bool useMachineScheduler() const
Definition: ARMSubtarget.h:702
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:143
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:185
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:642
bool DisablePostRAScheduler
DisablePostRAScheduler - False if scheduling should happen again after register allocation.
Definition: ARMSubtarget.h:201
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:375
bool hasFPARMv8() const
Definition: ARMSubtarget.h:564
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:314
bool useMulOps() const
Definition: ARMSubtarget.h:589
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:614
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:607
unsigned getMispredictionPenalty() const
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:286
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:738
bool hasTrustZone() const
Definition: ARMSubtarget.h:595
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:494
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:606
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:599
bool HasDotProd
HasDotProd - True if the ARMv8.2A dot product instructions are supported.
Definition: ARMSubtarget.h:168
bool isAPCS_ABI() const
const CallLowering * getCallLowering() const override
bool useSjLjEH() const
Definition: ARMSubtarget.h:624
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:387
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:776
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasV7Clrex() const
Definition: ARMSubtarget.h:582
bool useWideStrideVFP() const
Definition: ARMSubtarget.h:608
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:225
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:302
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:191
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool hasAES() const
Definition: ARMSubtarget.h:567
const std::string & getCPUString() const
Definition: ARMSubtarget.h:742
bool isCortexA9() const
Definition: ARMSubtarget.h:550
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useSoftFloat() const
Definition: ARMSubtarget.h:704
bool isTargetAEABI() const
Definition: ARMSubtarget.h:660
bool isTargetLinux() const
Definition: ARMSubtarget.h:644
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:763
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:592
const InstructionSelector * getInstructionSelector() const override
bool cheapPredicableCPSRDef() const
Definition: ARMSubtarget.h:617
bool isTargetAndroid() const
Definition: ARMSubtarget.h:691
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:138
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:807
bool hasMPExtension() const
Definition: ARMSubtarget.h:621
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:573
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
Definition: ARMSubtarget.h:294
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:135
bool hasNEON() const
Definition: ARMSubtarget.h:565
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:304
bool UseWideStrideVFP
If true, use a wider stride when allocating VFP registers.
Definition: ARMSubtarget.h:360
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:409
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:403
bool CheapPredicableCPSRDef
CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR...
Definition: ARMSubtarget.h:269
unsigned getPrefLoopAlignment() const
Definition: ARMSubtarget.h:811
unsigned PrefLoopAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:442
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:451
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:350
bool disablePostRAScheduler() const
Definition: ARMSubtarget.h:703
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:457
bool genLongCalls() const
Definition: ARMSubtarget.h:625
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool UseSoftFloat
UseSoftFloat - True if we&#39;re using software floating point features.
Definition: ARMSubtarget.h:194
bool isROPI() const
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:796
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:591
bool expandMLx() const
Definition: ARMSubtarget.h:604
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:537
Provides the logic to select generic machine instructions.
bool isThumb2() const
Definition: ARMSubtarget.h:707
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:638
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:597
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:619
bool isTargetIOS() const
Definition: ARMSubtarget.h:641
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:213
TargetOptions Options
Definition: TargetMachine.h:98
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:454
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:173
bool isCortexA7() const
Definition: ARMSubtarget.h:548
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:498
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:611
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:431
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:780
bool hasV5TOps() const
Definition: ARMSubtarget.h:529
bool HasFP16FML
HasFP16FML - True if subtarget supports half-precision FP fml operations.
Definition: ARMSubtarget.h:231
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:605
bool isTargetMachO() const
Definition: ARMSubtarget.h:651
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:188
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:435
bool isKrait() const
Definition: ARMSubtarget.h:556
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:235
bool isSwift() const
Definition: ARMSubtarget.h:552
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool supportsTailCall() const
Definition: ARMSubtarget.h:736
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:127
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:265
bool isCortexA8() const
Definition: ARMSubtarget.h:549
This file describes how to lower LLVM calls to machine code calls.
bool hasVFP4() const
Definition: ARMSubtarget.h:563
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:622
bool isRWPI() const
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:542
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:119
bool isTargetWindows() const
Definition: ARMSubtarget.h:647
bool HasFullDataBarrier
HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction. ...
Definition: ARMSubtarget.h:249
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:426
bool isCortexA15() const
Definition: ARMSubtarget.h:551
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:256
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:636
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:585
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition: ARMSubtarget.h:756
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:327
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:245
bool isAAPCS_ABI() const
bool hasDataBarrier() const
Definition: ARMSubtarget.h:580
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:247
bool hasFP16FML() const
Definition: ARMSubtarget.h:631
bool hasThumb2() const
Definition: ARMSubtarget.h:708
bool isLikeA9() const
Definition: ARMSubtarget.h:554
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:384
bool HasSHA2
HasSHA2 - if true, processor supports SHA1 and SHA256.
Definition: ARMSubtarget.h:308
bool isAAPCS16_ABI() const
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:415
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:610
bool hasFullFP16() const
Definition: ARMSubtarget.h:630
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:428
bool hasV8_3aOps() const
Definition: ARMSubtarget.h:539