LLVM  10.0.0svn
ARMTargetMachine.cpp
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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Transforms/Scalar.h"
50 #include <cassert>
51 #include <memory>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
58  cl::desc("Inhibit optimization of S->D register accesses on A15"),
59  cl::init(false));
60 
61 static cl::opt<bool>
62 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
63  cl::desc("Run SimplifyCFG after expanding atomic operations"
64  " to make use of cmpxchg flow-based information"),
65  cl::init(true));
66 
67 static cl::opt<bool>
68 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
69  cl::desc("Enable ARM load/store optimization pass"),
70  cl::init(true));
71 
72 // FIXME: Unify control over GlobalMerge.
74 EnableGlobalMerge("arm-global-merge", cl::Hidden,
75  cl::desc("Enable the global merge pass"));
76 
77 namespace llvm {
79 }
80 
81 extern "C" void LLVMInitializeARMTarget() {
82  // Register the target.
87 
89  initializeGlobalISel(Registry);
98  initializeMVEVPTBlockPass(Registry);
100 }
101 
102 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
103  if (TT.isOSBinFormatMachO())
104  return std::make_unique<TargetLoweringObjectFileMachO>();
105  if (TT.isOSWindows())
106  return std::make_unique<TargetLoweringObjectFileCOFF>();
107  return std::make_unique<ARMElfTargetObjectFile>();
108 }
109 
112  const TargetOptions &Options) {
113  StringRef ABIName = Options.MCOptions.getABIName();
114 
115  if (ABIName.empty())
116  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
117 
118  if (ABIName == "aapcs16")
120  else if (ABIName.startswith("aapcs"))
122  else if (ABIName.startswith("apcs"))
124 
125  llvm_unreachable("Unhandled/unknown ABI Name!");
127 }
128 
129 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
130  const TargetOptions &Options,
131  bool isLittle) {
132  auto ABI = computeTargetABI(TT, CPU, Options);
133  std::string Ret;
134 
135  if (isLittle)
136  // Little endian.
137  Ret += "e";
138  else
139  // Big endian.
140  Ret += "E";
141 
143 
144  // Pointers are 32 bits and aligned to 32 bits.
145  Ret += "-p:32:32";
146 
147  // Function pointers are aligned to 8 bits (because the LSB stores the
148  // ARM/Thumb state).
149  Ret += "-Fi8";
150 
151  // ABIs other than APCS have 64 bit integers with natural alignment.
153  Ret += "-i64:64";
154 
155  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
156  // bits, others to 64 bits. We always try to align to 64 bits.
158  Ret += "-f64:32:64";
159 
160  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
161  // to 64. We always ty to give them natural alignment.
163  Ret += "-v64:32:64-v128:32:128";
165  Ret += "-v128:64:128";
166 
167  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
168  // particular hardware support on 32-bit ARM).
169  Ret += "-a:0:32";
170 
171  // Integer registers are 32 bits.
172  Ret += "-n32";
173 
174  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
175  // aligned everywhere else.
177  Ret += "-S128";
179  Ret += "-S64";
180  else
181  Ret += "-S32";
182 
183  return Ret;
184 }
185 
188  if (!RM.hasValue())
189  // Default relocation model on Darwin is PIC.
191 
192  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
193  assert(TT.isOSBinFormatELF() &&
194  "ROPI/RWPI currently only supported for ELF");
195 
196  // DynamicNoPIC is only used on darwin.
197  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
198  return Reloc::Static;
199 
200  return *RM;
201 }
202 
203 /// Create an ARM architecture model.
204 ///
206  StringRef CPU, StringRef FS,
207  const TargetOptions &Options,
210  CodeGenOpt::Level OL, bool isLittle)
211  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
212  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
213  getEffectiveCodeModel(CM, CodeModel::Small), OL),
214  TargetABI(computeTargetABI(TT, CPU, Options)),
215  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
216 
217  // Default to triple-appropriate float ABI
218  if (Options.FloatABIType == FloatABI::Default) {
219  if (isTargetHardFloat())
220  this->Options.FloatABIType = FloatABI::Hard;
221  else
222  this->Options.FloatABIType = FloatABI::Soft;
223  }
224 
225  // Default to triple-appropriate EABI
226  if (Options.EABIVersion == EABI::Default ||
227  Options.EABIVersion == EABI::Unknown) {
228  // musl is compatible with glibc with regard to EABI version
234  this->Options.EABIVersion = EABI::GNU;
235  else
236  this->Options.EABIVersion = EABI::EABI5;
237  }
238 
239  if (TT.isOSBinFormatMachO()) {
240  this->Options.TrapUnreachable = true;
241  this->Options.NoTrapAfterNoreturn = true;
242  }
243 
244  initAsmInfo();
245 }
246 
248 
249 const ARMSubtarget *
251  Attribute CPUAttr = F.getFnAttribute("target-cpu");
252  Attribute FSAttr = F.getFnAttribute("target-features");
253 
254  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
255  ? CPUAttr.getValueAsString().str()
256  : TargetCPU;
257  std::string FS = !FSAttr.hasAttribute(Attribute::None)
258  ? FSAttr.getValueAsString().str()
259  : TargetFS;
260 
261  // FIXME: This is related to the code below to reset the target options,
262  // we need to know whether or not the soft float flag is set on the
263  // function before we can generate a subtarget. We also need to use
264  // it as a key for the subtarget since that can be the only difference
265  // between two functions.
266  bool SoftFloat =
267  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
268  // If the soft float attribute is set on the function turn on the soft float
269  // subtarget feature.
270  if (SoftFloat)
271  FS += FS.empty() ? "+soft-float" : ",+soft-float";
272 
273  // Use the optminsize to identify the subtarget, but don't use it in the
274  // feature string.
275  std::string Key = CPU + FS;
276  if (F.hasMinSize())
277  Key += "+minsize";
278 
279  auto &I = SubtargetMap[Key];
280  if (!I) {
281  // This needs to be done before we create a new subtarget since any
282  // creation will depend on the TM and the code generation flags on the
283  // function that reside in TargetOptions.
285  I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
286  F.hasMinSize());
287 
288  if (!I->isThumb() && !I->hasARMOps())
289  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
290  "instructions, but the target does not support ARM mode execution.");
291  }
292 
293  return I.get();
294 }
295 
298  return TargetTransformInfo(ARMTTIImpl(this, F));
299 }
300 
302  StringRef CPU, StringRef FS,
303  const TargetOptions &Options,
306  CodeGenOpt::Level OL, bool JIT)
307  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
308 
310  StringRef CPU, StringRef FS,
311  const TargetOptions &Options,
314  CodeGenOpt::Level OL, bool JIT)
315  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
316 
317 namespace {
318 
319 /// ARM Code Generator Pass Configuration Options.
320 class ARMPassConfig : public TargetPassConfig {
321 public:
322  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
323  : TargetPassConfig(TM, PM) {
324  if (TM.getOptLevel() != CodeGenOpt::None) {
327  if (STI.hasFeature(ARM::FeatureUseMISched))
328  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
329  }
330  }
331 
332  ARMBaseTargetMachine &getARMTargetMachine() const {
333  return getTM<ARMBaseTargetMachine>();
334  }
335 
337  createMachineScheduler(MachineSchedContext *C) const override {
339  // add DAG Mutations here.
340  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
341  if (ST.hasFusion())
343  return DAG;
344  }
345 
347  createPostMachineScheduler(MachineSchedContext *C) const override {
349  // add DAG Mutations here.
350  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
351  if (ST.hasFusion())
353  return DAG;
354  }
355 
356  void addIRPasses() override;
357  void addCodeGenPrepare() override;
358  bool addPreISel() override;
359  bool addInstSelector() override;
360  bool addIRTranslator() override;
361  bool addLegalizeMachineIR() override;
362  bool addRegBankSelect() override;
363  bool addGlobalInstructionSelect() override;
364  void addPreRegAlloc() override;
365  void addPreSched2() override;
366  void addPreEmitPass() override;
367 
368  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
369 };
370 
371 class ARMExecutionDomainFix : public ExecutionDomainFix {
372 public:
373  static char ID;
374  ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
375  StringRef getPassName() const override {
376  return "ARM Execution Domain Fix";
377  }
378 };
380 
381 } // end anonymous namespace
382 
383 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
384  "ARM Execution Domain Fix", false, false)
386 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
387  "ARM Execution Domain Fix", false, false)
388 
390  return new ARMPassConfig(*this, PM);
391 }
392 
393 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
394  return getStandardCSEConfigForOpt(TM->getOptLevel());
395 }
396 
397 void ARMPassConfig::addIRPasses() {
398  if (TM->Options.ThreadModel == ThreadModel::Single)
399  addPass(createLowerAtomicPass());
400  else
401  addPass(createAtomicExpandPass());
402 
403  // Cmpxchg instructions are often used with a subsequent comparison to
404  // determine whether it succeeded. We can exploit existing control-flow in
405  // ldrex/strex loops to simplify this, but it needs tidying up.
406  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
408  1, false, false, true, true, [this](const Function &F) {
409  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
410  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
411  }));
412 
414 
415  // Run the parallel DSP pass.
417  addPass(createARMParallelDSPPass());
418 
419  // Match interleaved memory accesses to ldN/stN intrinsics.
420  if (TM->getOptLevel() != CodeGenOpt::None)
421  addPass(createInterleavedAccessPass());
422 }
423 
424 void ARMPassConfig::addCodeGenPrepare() {
425  if (getOptLevel() != CodeGenOpt::None)
426  addPass(createARMCodeGenPreparePass());
428 }
429 
430 bool ARMPassConfig::addPreISel() {
431  if ((TM->getOptLevel() != CodeGenOpt::None &&
433  EnableGlobalMerge == cl::BOU_TRUE) {
434  // FIXME: This is using the thumb1 only constant value for
435  // maximal global offset for merging globals. We may want
436  // to look into using the old value for non-thumb1 code of
437  // 4095 based on the TargetMachine, but this starts to become
438  // tricky when doing code gen per function.
439  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
440  (EnableGlobalMerge == cl::BOU_UNSET);
441  // Merging of extern globals is enabled by default on non-Mach-O as we
442  // expect it to be generally either beneficial or harmless. On Mach-O it
443  // is disabled as we emit the .subsections_via_symbols directive which
444  // means that merging extern globals is not safe.
445  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
446  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
447  MergeExternalByDefault));
448  }
449 
450  if (TM->getOptLevel() != CodeGenOpt::None)
451  addPass(createHardwareLoopsPass());
452 
453  return false;
454 }
455 
456 bool ARMPassConfig::addInstSelector() {
457  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
458  return false;
459 }
460 
461 bool ARMPassConfig::addIRTranslator() {
462  addPass(new IRTranslator());
463  return false;
464 }
465 
466 bool ARMPassConfig::addLegalizeMachineIR() {
467  addPass(new Legalizer());
468  return false;
469 }
470 
471 bool ARMPassConfig::addRegBankSelect() {
472  addPass(new RegBankSelect());
473  return false;
474 }
475 
476 bool ARMPassConfig::addGlobalInstructionSelect() {
477  addPass(new InstructionSelect());
478  return false;
479 }
480 
481 void ARMPassConfig::addPreRegAlloc() {
482  if (getOptLevel() != CodeGenOpt::None) {
483  addPass(createMLxExpansionPass());
484 
486  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
487 
489  addPass(createA15SDOptimizerPass());
490  }
491 }
492 
493 void ARMPassConfig::addPreSched2() {
494  if (getOptLevel() != CodeGenOpt::None) {
497 
498  addPass(new ARMExecutionDomainFix());
499  addPass(createBreakFalseDeps());
500  }
501 
502  // Expand some pseudo instructions into multiple instructions to allow
503  // proper scheduling.
504  addPass(createARMExpandPseudoPass());
505 
506  if (getOptLevel() != CodeGenOpt::None) {
507  // in v8, IfConversion depends on Thumb instruction widths
508  addPass(createThumb2SizeReductionPass([this](const Function &F) {
509  return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
510  }));
511 
512  addPass(createIfConverter([](const MachineFunction &MF) {
513  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
514  }));
515  }
516  addPass(createMVEVPTBlockPass());
517  addPass(createThumb2ITBlockPass());
518 }
519 
520 void ARMPassConfig::addPreEmitPass() {
522 
523  // Constant island pass work on unbundled instructions.
524  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
525  return MF.getSubtarget<ARMSubtarget>().isThumb2();
526  }));
527 
528  // Don't optimize barriers at -O0.
529  if (getOptLevel() != CodeGenOpt::None)
531 
532  addPass(createARMConstantIslandPass());
534 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
StringRef getTargetFeatureString() const
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
FunctionPass * createA15SDOptimizerPass()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
FunctionPass * createMLxExpansionPass()
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
MCTargetOptions MCOptions
Machine level options.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:581
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
void initializeARMExecutionDomainFixPass(PassRegistry &)
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
F(f)
block Block Frequency true
Target & getTheThumbLETarget()
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, bool SinkCommon=false, std::function< bool(const Function &)> Ftor=nullptr)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target & getTheARMBETarget()
Target-Independent Code Generator Pass Configuration Options.
void initializeARMCodeGenPreparePass(PassRegistry &)
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
Key
PAL metadata keys.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void LLVMInitializeARMTarget()
Target & getTheThumbBETarget()
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
std::unique_ptr< const MCSubtargetInfo > STI
Definition: TargetMachine.h:96
StringRef getTargetCPU() const
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
speculative execution
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
void initializeARMExpandPseudoPass(PassRegistry &)
void initializeARMLoadStoreOptPass(PassRegistry &)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:238
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Pass * createARMParallelDSPPass()
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeARMParallelDSPPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
void initializeThumb2SizeReducePass(PassRegistry &)
arm execution domain fix
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
arm execution domain ARM Execution Domain Fix
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
void initializeARMLowOverheadLoopsPass(PassRegistry &)
Pass * createLowerAtomicPass()
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
std::string TargetCPU
Definition: TargetMachine.h:85
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:619
const ARMSubtarget * getSubtargetImpl() const =delete
std::string TargetFS
Definition: TargetMachine.h:86
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createARMCodeGenPreparePass()
This file describes how to lower LLVM calls to machine code calls.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:686
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
This pass exposes codegen information to IR-level passes.
Target & getTheARMLETarget()
FunctionPass * createAtomicExpandPass()
FunctionPass * createARMLowOverheadLoopsPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void initializeMVEVPTBlockPass(PassRegistry &)
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...