LLVM  7.0.0svn
ARMTargetMachine.cpp
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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMTargetMachine.h"
14 #include "ARM.h"
15 #include "ARMMacroFusion.h"
16 #include "ARMSubtarget.h"
17 #include "ARMTargetObjectFile.h"
18 #include "ARMTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Transforms/Scalar.h"
50 #include <cassert>
51 #include <memory>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
58  cl::desc("Inhibit optimization of S->D register accesses on A15"),
59  cl::init(false));
60 
61 static cl::opt<bool>
62 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
63  cl::desc("Run SimplifyCFG after expanding atomic operations"
64  " to make use of cmpxchg flow-based information"),
65  cl::init(true));
66 
67 static cl::opt<bool>
68 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
69  cl::desc("Enable ARM load/store optimization pass"),
70  cl::init(true));
71 
72 // FIXME: Unify control over GlobalMerge.
74 EnableGlobalMerge("arm-global-merge", cl::Hidden,
75  cl::desc("Enable the global merge pass"));
76 
77 namespace llvm {
79 }
80 
81 extern "C" void LLVMInitializeARMTarget() {
82  // Register the target.
87 
89  initializeGlobalISel(Registry);
96 }
97 
98 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
99  if (TT.isOSBinFormatMachO())
100  return llvm::make_unique<TargetLoweringObjectFileMachO>();
101  if (TT.isOSWindows())
102  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
103  return llvm::make_unique<ARMElfTargetObjectFile>();
104 }
105 
108  const TargetOptions &Options) {
109  StringRef ABIName = Options.MCOptions.getABIName();
110 
111  if (ABIName.empty())
112  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
113 
114  if (ABIName == "aapcs16")
116  else if (ABIName.startswith("aapcs"))
118  else if (ABIName.startswith("apcs"))
120 
121  llvm_unreachable("Unhandled/unknown ABI Name!");
123 }
124 
125 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
126  const TargetOptions &Options,
127  bool isLittle) {
128  auto ABI = computeTargetABI(TT, CPU, Options);
129  std::string Ret;
130 
131  if (isLittle)
132  // Little endian.
133  Ret += "e";
134  else
135  // Big endian.
136  Ret += "E";
137 
139 
140  // Pointers are 32 bits and aligned to 32 bits.
141  Ret += "-p:32:32";
142 
143  // ABIs other than APCS have 64 bit integers with natural alignment.
145  Ret += "-i64:64";
146 
147  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
148  // bits, others to 64 bits. We always try to align to 64 bits.
150  Ret += "-f64:32:64";
151 
152  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
153  // to 64. We always ty to give them natural alignment.
155  Ret += "-v64:32:64-v128:32:128";
157  Ret += "-v128:64:128";
158 
159  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
160  // particular hardware support on 32-bit ARM).
161  Ret += "-a:0:32";
162 
163  // Integer registers are 32 bits.
164  Ret += "-n32";
165 
166  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
167  // aligned everywhere else.
169  Ret += "-S128";
170  else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
171  Ret += "-S64";
172  else
173  Ret += "-S32";
174 
175  return Ret;
176 }
177 
180  if (!RM.hasValue())
181  // Default relocation model on Darwin is PIC.
183 
184  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
185  assert(TT.isOSBinFormatELF() &&
186  "ROPI/RWPI currently only supported for ELF");
187 
188  // DynamicNoPIC is only used on darwin.
189  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
190  return Reloc::Static;
191 
192  return *RM;
193 }
194 
196  if (CM)
197  return *CM;
198  return CodeModel::Small;
199 }
200 
201 /// Create an ARM architecture model.
202 ///
204  StringRef CPU, StringRef FS,
205  const TargetOptions &Options,
208  CodeGenOpt::Level OL, bool isLittle)
209  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
210  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
211  getEffectiveCodeModel(CM), OL),
212  TargetABI(computeTargetABI(TT, CPU, Options)),
213  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
214 
215  // Default to triple-appropriate float ABI
216  if (Options.FloatABIType == FloatABI::Default) {
222  this->Options.FloatABIType = FloatABI::Hard;
223  else
224  this->Options.FloatABIType = FloatABI::Soft;
225  }
226 
227  // Default to triple-appropriate EABI
228  if (Options.EABIVersion == EABI::Default ||
229  Options.EABIVersion == EABI::Unknown) {
230  // musl is compatible with glibc with regard to EABI version
236  this->Options.EABIVersion = EABI::GNU;
237  else
238  this->Options.EABIVersion = EABI::EABI5;
239  }
240 
241  initAsmInfo();
242 }
243 
245 
246 const ARMSubtarget *
248  Attribute CPUAttr = F.getFnAttribute("target-cpu");
249  Attribute FSAttr = F.getFnAttribute("target-features");
250 
251  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
252  ? CPUAttr.getValueAsString().str()
253  : TargetCPU;
254  std::string FS = !FSAttr.hasAttribute(Attribute::None)
255  ? FSAttr.getValueAsString().str()
256  : TargetFS;
257 
258  // FIXME: This is related to the code below to reset the target options,
259  // we need to know whether or not the soft float flag is set on the
260  // function before we can generate a subtarget. We also need to use
261  // it as a key for the subtarget since that can be the only difference
262  // between two functions.
263  bool SoftFloat =
264  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
265  // If the soft float attribute is set on the function turn on the soft float
266  // subtarget feature.
267  if (SoftFloat)
268  FS += FS.empty() ? "+soft-float" : ",+soft-float";
269 
270  auto &I = SubtargetMap[CPU + FS];
271  if (!I) {
272  // This needs to be done before we create a new subtarget since any
273  // creation will depend on the TM and the code generation flags on the
274  // function that reside in TargetOptions.
276  I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
277 
278  if (!I->isThumb() && !I->hasARMOps())
279  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
280  "instructions, but the target does not support ARM mode execution.");
281  }
282 
283  return I.get();
284 }
285 
288  return TargetTransformInfo(ARMTTIImpl(this, F));
289 }
290 
292  StringRef CPU, StringRef FS,
293  const TargetOptions &Options,
296  CodeGenOpt::Level OL, bool JIT)
297  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
298 
300  StringRef CPU, StringRef FS,
301  const TargetOptions &Options,
304  CodeGenOpt::Level OL, bool JIT)
305  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
306 
307 namespace {
308 
309 /// ARM Code Generator Pass Configuration Options.
310 class ARMPassConfig : public TargetPassConfig {
311 public:
312  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
313  : TargetPassConfig(TM, PM) {
314  if (TM.getOptLevel() != CodeGenOpt::None) {
317  if (STI.hasFeature(ARM::FeatureUseMISched))
318  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
319  }
320  }
321 
322  ARMBaseTargetMachine &getARMTargetMachine() const {
323  return getTM<ARMBaseTargetMachine>();
324  }
325 
327  createMachineScheduler(MachineSchedContext *C) const override {
329  // add DAG Mutations here.
330  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
331  if (ST.hasFusion())
333  return DAG;
334  }
335 
337  createPostMachineScheduler(MachineSchedContext *C) const override {
339  // add DAG Mutations here.
340  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
341  if (ST.hasFusion())
343  return DAG;
344  }
345 
346  void addIRPasses() override;
347  bool addPreISel() override;
348  bool addInstSelector() override;
349  bool addIRTranslator() override;
350  bool addLegalizeMachineIR() override;
351  bool addRegBankSelect() override;
352  bool addGlobalInstructionSelect() override;
353  void addPreRegAlloc() override;
354  void addPreSched2() override;
355  void addPreEmitPass() override;
356 };
357 
358 class ARMExecutionDomainFix : public ExecutionDomainFix {
359 public:
360  static char ID;
361  ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
362  StringRef getPassName() const override {
363  return "ARM Execution Domain Fix";
364  }
365 };
367 
368 } // end anonymous namespace
369 
370 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
371  "ARM Execution Domain Fix", false, false)
373 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
374  "ARM Execution Domain Fix", false, false)
375 
377  return new ARMPassConfig(*this, PM);
378 }
379 
380 void ARMPassConfig::addIRPasses() {
381  if (TM->Options.ThreadModel == ThreadModel::Single)
382  addPass(createLowerAtomicPass());
383  else
384  addPass(createAtomicExpandPass());
385 
386  // Cmpxchg instructions are often used with a subsequent comparison to
387  // determine whether it succeeded. We can exploit existing control-flow in
388  // ldrex/strex loops to simplify this, but it needs tidying up.
389  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
391  1, false, false, true, true, [this](const Function &F) {
392  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
393  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
394  }));
395 
397 
398  // Match interleaved memory accesses to ldN/stN intrinsics.
399  if (TM->getOptLevel() != CodeGenOpt::None)
400  addPass(createInterleavedAccessPass());
401 }
402 
403 bool ARMPassConfig::addPreISel() {
404  if ((TM->getOptLevel() != CodeGenOpt::None &&
406  EnableGlobalMerge == cl::BOU_TRUE) {
407  // FIXME: This is using the thumb1 only constant value for
408  // maximal global offset for merging globals. We may want
409  // to look into using the old value for non-thumb1 code of
410  // 4095 based on the TargetMachine, but this starts to become
411  // tricky when doing code gen per function.
412  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
413  (EnableGlobalMerge == cl::BOU_UNSET);
414  // Merging of extern globals is enabled by default on non-Mach-O as we
415  // expect it to be generally either beneficial or harmless. On Mach-O it
416  // is disabled as we emit the .subsections_via_symbols directive which
417  // means that merging extern globals is not safe.
418  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
419  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
420  MergeExternalByDefault));
421  }
422 
423  return false;
424 }
425 
426 bool ARMPassConfig::addInstSelector() {
427  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
428  return false;
429 }
430 
431 bool ARMPassConfig::addIRTranslator() {
432  addPass(new IRTranslator());
433  return false;
434 }
435 
436 bool ARMPassConfig::addLegalizeMachineIR() {
437  addPass(new Legalizer());
438  return false;
439 }
440 
441 bool ARMPassConfig::addRegBankSelect() {
442  addPass(new RegBankSelect());
443  return false;
444 }
445 
446 bool ARMPassConfig::addGlobalInstructionSelect() {
447  addPass(new InstructionSelect());
448  return false;
449 }
450 
451 void ARMPassConfig::addPreRegAlloc() {
452  if (getOptLevel() != CodeGenOpt::None) {
453  addPass(createMLxExpansionPass());
454 
456  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
457 
459  addPass(createA15SDOptimizerPass());
460  }
461 }
462 
463 void ARMPassConfig::addPreSched2() {
464  if (getOptLevel() != CodeGenOpt::None) {
467 
468  addPass(new ARMExecutionDomainFix());
469  addPass(createBreakFalseDeps());
470  }
471 
472  // Expand some pseudo instructions into multiple instructions to allow
473  // proper scheduling.
474  addPass(createARMExpandPseudoPass());
475 
476  if (getOptLevel() != CodeGenOpt::None) {
477  // in v8, IfConversion depends on Thumb instruction widths
478  addPass(createThumb2SizeReductionPass([this](const Function &F) {
479  return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
480  }));
481 
482  addPass(createIfConverter([](const MachineFunction &MF) {
483  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
484  }));
485  }
486  addPass(createThumb2ITBlockPass());
487 }
488 
489 void ARMPassConfig::addPreEmitPass() {
491 
492  // Constant island pass work on unbundled instructions.
493  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
494  return MF.getSubtarget<ARMSubtarget>().isThumb2();
495  }));
496 
497  // Don't optimize barriers at -O0.
498  if (getOptLevel() != CodeGenOpt::None)
500 
501  addPass(createARMConstantIslandPass());
502 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
StringRef getTargetFeatureString() const
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
FunctionPass * createA15SDOptimizerPass()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
FunctionPass * createMLxExpansionPass()
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
MCTargetOptions MCOptions
Machine level options.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:45
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
void initializeARMExecutionDomainFixPass(PassRegistry &)
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
F(f)
setjmp/longjmp based exceptions
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
Target & getTheThumbLETarget()
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:157
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, bool SinkCommon=false, std::function< bool(const Function &)> Ftor=nullptr)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
Target & getTheARMBETarget()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
const MCSubtargetInfo * STI
Definition: TargetMachine.h:91
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void LLVMInitializeARMTarget()
Target & getTheThumbBETarget()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
StringRef getTargetCPU() const
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
speculative execution
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
void initializeARMExpandPseudoPass(PassRegistry &)
void initializeARMLoadStoreOptPass(PassRegistry &)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
void initializeThumb2SizeReducePass(PassRegistry &)
arm execution domain fix
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
arm execution domain ARM Execution Domain Fix
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
Pass * createLowerAtomicPass()
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
std::string TargetCPU
Definition: TargetMachine.h:79
A ScheduleDAG for scheduling lists of MachineInstr.
Basic Alias true
bool hasValue() const
Definition: Optional.h:183
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:224
TargetOptions Options
Definition: TargetMachine.h:98
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasFeature(unsigned Feature) const
const ARMSubtarget * getSubtargetImpl() const =delete
std::string TargetFS
Definition: TargetMachine.h:80
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM calls to machine code calls.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:312
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:602
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
This pass exposes codegen information to IR-level passes.
Target & getTheARMLETarget()
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:19
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...