LLVM  6.0.0svn
ARMTargetMachine.cpp
Go to the documentation of this file.
1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMTargetMachine.h"
14 #include "ARM.h"
15 #include "ARMMacroFusion.h"
16 #include "ARMSubtarget.h"
17 #include "ARMTargetObjectFile.h"
18 #include "ARMTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Transforms/Scalar.h"
50 #include <cassert>
51 #include <memory>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
58  cl::desc("Inhibit optimization of S->D register accesses on A15"),
59  cl::init(false));
60 
61 static cl::opt<bool>
62 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
63  cl::desc("Run SimplifyCFG after expanding atomic operations"
64  " to make use of cmpxchg flow-based information"),
65  cl::init(true));
66 
67 static cl::opt<bool>
68 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
69  cl::desc("Enable ARM load/store optimization pass"),
70  cl::init(true));
71 
72 // FIXME: Unify control over GlobalMerge.
74 EnableGlobalMerge("arm-global-merge", cl::Hidden,
75  cl::desc("Enable the global merge pass"));
76 
77 namespace llvm {
79 }
80 
81 extern "C" void LLVMInitializeARMTarget() {
82  // Register the target.
87 
89  initializeGlobalISel(Registry);
95 }
96 
97 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
98  if (TT.isOSBinFormatMachO())
99  return llvm::make_unique<TargetLoweringObjectFileMachO>();
100  if (TT.isOSWindows())
101  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
102  return llvm::make_unique<ARMElfTargetObjectFile>();
103 }
104 
107  const TargetOptions &Options) {
109 
110  if (ABIName.empty())
111  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
112 
113  if (ABIName == "aapcs16")
115  else if (ABIName.startswith("aapcs"))
117  else if (ABIName.startswith("apcs"))
119 
120  llvm_unreachable("Unhandled/unknown ABI Name!");
122 }
123 
124 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
125  const TargetOptions &Options,
126  bool isLittle) {
127  auto ABI = computeTargetABI(TT, CPU, Options);
128  std::string Ret;
129 
130  if (isLittle)
131  // Little endian.
132  Ret += "e";
133  else
134  // Big endian.
135  Ret += "E";
136 
138 
139  // Pointers are 32 bits and aligned to 32 bits.
140  Ret += "-p:32:32";
141 
142  // ABIs other than APCS have 64 bit integers with natural alignment.
144  Ret += "-i64:64";
145 
146  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
147  // bits, others to 64 bits. We always try to align to 64 bits.
149  Ret += "-f64:32:64";
150 
151  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
152  // to 64. We always ty to give them natural alignment.
154  Ret += "-v64:32:64-v128:32:128";
156  Ret += "-v128:64:128";
157 
158  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
159  // particular hardware support on 32-bit ARM).
160  Ret += "-a:0:32";
161 
162  // Integer registers are 32 bits.
163  Ret += "-n32";
164 
165  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
166  // aligned everywhere else.
168  Ret += "-S128";
169  else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
170  Ret += "-S64";
171  else
172  Ret += "-S32";
173 
174  return Ret;
175 }
176 
179  if (!RM.hasValue())
180  // Default relocation model on Darwin is PIC.
182 
183  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
184  assert(TT.isOSBinFormatELF() &&
185  "ROPI/RWPI currently only supported for ELF");
186 
187  // DynamicNoPIC is only used on darwin.
188  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
189  return Reloc::Static;
190 
191  return *RM;
192 }
193 
195  if (CM)
196  return *CM;
197  return CodeModel::Small;
198 }
199 
200 /// Create an ARM architecture model.
201 ///
203  StringRef CPU, StringRef FS,
204  const TargetOptions &Options,
207  CodeGenOpt::Level OL, bool isLittle)
208  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
209  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
210  getEffectiveCodeModel(CM), OL),
211  TargetABI(computeTargetABI(TT, CPU, Options)),
212  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
213 
214  // Default to triple-appropriate float ABI
215  if (Options.FloatABIType == FloatABI::Default) {
221  this->Options.FloatABIType = FloatABI::Hard;
222  else
223  this->Options.FloatABIType = FloatABI::Soft;
224  }
225 
226  // Default to triple-appropriate EABI
227  if (Options.EABIVersion == EABI::Default ||
228  Options.EABIVersion == EABI::Unknown) {
229  // musl is compatible with glibc with regard to EABI version
235  this->Options.EABIVersion = EABI::GNU;
236  else
237  this->Options.EABIVersion = EABI::EABI5;
238  }
239 
240  initAsmInfo();
241 }
242 
244 
245 const ARMSubtarget *
247  Attribute CPUAttr = F.getFnAttribute("target-cpu");
248  Attribute FSAttr = F.getFnAttribute("target-features");
249 
250  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
251  ? CPUAttr.getValueAsString().str()
252  : TargetCPU;
253  std::string FS = !FSAttr.hasAttribute(Attribute::None)
254  ? FSAttr.getValueAsString().str()
255  : TargetFS;
256 
257  // FIXME: This is related to the code below to reset the target options,
258  // we need to know whether or not the soft float flag is set on the
259  // function before we can generate a subtarget. We also need to use
260  // it as a key for the subtarget since that can be the only difference
261  // between two functions.
262  bool SoftFloat =
263  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
264  // If the soft float attribute is set on the function turn on the soft float
265  // subtarget feature.
266  if (SoftFloat)
267  FS += FS.empty() ? "+soft-float" : ",+soft-float";
268 
269  auto &I = SubtargetMap[CPU + FS];
270  if (!I) {
271  // This needs to be done before we create a new subtarget since any
272  // creation will depend on the TM and the code generation flags on the
273  // function that reside in TargetOptions.
275  I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
276 
277  if (!I->isThumb() && !I->hasARMOps())
278  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
279  "instructions, but the target does not support ARM mode execution.");
280  }
281 
282  return I.get();
283 }
284 
286  return TargetIRAnalysis([this](const Function &F) {
287  return TargetTransformInfo(ARMTTIImpl(this, F));
288  });
289 }
290 
292  StringRef CPU, StringRef FS,
293  const TargetOptions &Options,
296  CodeGenOpt::Level OL, bool JIT)
297  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
298 
300  StringRef CPU, StringRef FS,
301  const TargetOptions &Options,
304  CodeGenOpt::Level OL, bool JIT)
305  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
306 
307 namespace {
308 
309 /// ARM Code Generator Pass Configuration Options.
310 class ARMPassConfig : public TargetPassConfig {
311 public:
312  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
313  : TargetPassConfig(TM, PM) {
314  if (TM.getOptLevel() != CodeGenOpt::None) {
317  if (STI.hasFeature(ARM::FeatureUseMISched))
318  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
319  }
320  }
321 
322  ARMBaseTargetMachine &getARMTargetMachine() const {
323  return getTM<ARMBaseTargetMachine>();
324  }
325 
327  createMachineScheduler(MachineSchedContext *C) const override {
329  // add DAG Mutations here.
330  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
331  if (ST.hasFusion())
333  return DAG;
334  }
335 
337  createPostMachineScheduler(MachineSchedContext *C) const override {
339  // add DAG Mutations here.
340  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
341  if (ST.hasFusion())
343  return DAG;
344  }
345 
346  void addIRPasses() override;
347  bool addPreISel() override;
348  bool addInstSelector() override;
349  bool addIRTranslator() override;
350  bool addLegalizeMachineIR() override;
351  bool addRegBankSelect() override;
352  bool addGlobalInstructionSelect() override;
353  void addPreRegAlloc() override;
354  void addPreSched2() override;
355  void addPreEmitPass() override;
356 };
357 
358 class ARMExecutionDepsFix : public ExecutionDepsFix {
359 public:
360  static char ID;
361  ARMExecutionDepsFix() : ExecutionDepsFix(ID, ARM::DPRRegClass) {}
362  StringRef getPassName() const override {
363  return "ARM Execution Dependency Fix";
364  }
365 };
367 
368 } // end anonymous namespace
369 
370 INITIALIZE_PASS(ARMExecutionDepsFix, "arm-execution-deps-fix",
371  "ARM Execution Dependency Fix", false, false)
372 
374  return new ARMPassConfig(*this, PM);
375 }
376 
377 void ARMPassConfig::addIRPasses() {
378  if (TM->Options.ThreadModel == ThreadModel::Single)
379  addPass(createLowerAtomicPass());
380  else
381  addPass(createAtomicExpandPass());
382 
383  // Cmpxchg instructions are often used with a subsequent comparison to
384  // determine whether it succeeded. We can exploit existing control-flow in
385  // ldrex/strex loops to simplify this, but it needs tidying up.
386  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
388  1, false, false, true, [this](const Function &F) {
389  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
390  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
391  }));
392 
394 
395  // Match interleaved memory accesses to ldN/stN intrinsics.
396  if (TM->getOptLevel() != CodeGenOpt::None)
397  addPass(createInterleavedAccessPass());
398 }
399 
400 bool ARMPassConfig::addPreISel() {
401  if ((TM->getOptLevel() != CodeGenOpt::None &&
403  EnableGlobalMerge == cl::BOU_TRUE) {
404  // FIXME: This is using the thumb1 only constant value for
405  // maximal global offset for merging globals. We may want
406  // to look into using the old value for non-thumb1 code of
407  // 4095 based on the TargetMachine, but this starts to become
408  // tricky when doing code gen per function.
409  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
410  (EnableGlobalMerge == cl::BOU_UNSET);
411  // Merging of extern globals is enabled by default on non-Mach-O as we
412  // expect it to be generally either beneficial or harmless. On Mach-O it
413  // is disabled as we emit the .subsections_via_symbols directive which
414  // means that merging extern globals is not safe.
415  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
416  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
417  MergeExternalByDefault));
418  }
419 
420  return false;
421 }
422 
423 bool ARMPassConfig::addInstSelector() {
424  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
425  return false;
426 }
427 
428 bool ARMPassConfig::addIRTranslator() {
429  addPass(new IRTranslator());
430  return false;
431 }
432 
433 bool ARMPassConfig::addLegalizeMachineIR() {
434  addPass(new Legalizer());
435  return false;
436 }
437 
438 bool ARMPassConfig::addRegBankSelect() {
439  addPass(new RegBankSelect());
440  return false;
441 }
442 
443 bool ARMPassConfig::addGlobalInstructionSelect() {
444  addPass(new InstructionSelect());
445  return false;
446 }
447 
448 void ARMPassConfig::addPreRegAlloc() {
449  if (getOptLevel() != CodeGenOpt::None) {
450  addPass(createMLxExpansionPass());
451 
453  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
454 
456  addPass(createA15SDOptimizerPass());
457  }
458 }
459 
460 void ARMPassConfig::addPreSched2() {
461  if (getOptLevel() != CodeGenOpt::None) {
464 
465  addPass(new ARMExecutionDepsFix());
466  }
467 
468  // Expand some pseudo instructions into multiple instructions to allow
469  // proper scheduling.
470  addPass(createARMExpandPseudoPass());
471 
472  if (getOptLevel() != CodeGenOpt::None) {
473  // in v8, IfConversion depends on Thumb instruction widths
474  addPass(createThumb2SizeReductionPass([this](const Function &F) {
475  return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
476  }));
477 
478  addPass(createIfConverter([](const MachineFunction &MF) {
479  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
480  }));
481  }
482  addPass(createThumb2ITBlockPass());
483 }
484 
485 void ARMPassConfig::addPreEmitPass() {
487 
488  // Constant island pass work on unbundled instructions.
489  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
490  return MF.getSubtarget<ARMSubtarget>().isThumb2();
491  }));
492 
493  // Don't optimize barriers at -O0.
494  if (getOptLevel() != CodeGenOpt::None)
496 
497  addPass(createARMConstantIslandPass());
498 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
StringRef getTargetFeatureString() const
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
INITIALIZE_PASS(ARMExecutionDepsFix, "arm-execution-deps-fix", "ARM Execution Dependency Fix", false, false) TargetPassConfig *ARMBaseTargetMachine
FunctionPass * createA15SDOptimizerPass()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
FunctionPass * createMLxExpansionPass()
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
TargetIRAnalysis getTargetIRAnalysis() override
Get the TargetIRAnalysis for this target.
MCTargetOptions MCOptions
Machine level options.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, std::function< bool(const Function &)> Ftor=nullptr)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:76
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:45
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
Analysis pass providing the TargetTransformInfo.
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
F(f)
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
Target & getTheThumbLETarget()
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:154
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
Target & getTheARMBETarget()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
const MCSubtargetInfo * STI
Definition: TargetMachine.h:89
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void LLVMInitializeARMTarget()
Target & getTheThumbBETarget()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
StringRef getTargetCPU() const
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
void initializeARMExpandPseudoPass(PassRegistry &)
void initializeARMLoadStoreOptPass(PassRegistry &)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
void initializeARMExecutionDepsFixPass(PassRegistry &)
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
cl::opt< std::string > ABIName("target-abi", cl::Hidden, cl::desc("The name of the ABI to be targeted from the backend."), cl::init(""))
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
Pass * createLowerAtomicPass()
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
std::string TargetCPU
Definition: TargetMachine.h:77
A ScheduleDAG for scheduling lists of MachineInstr.
Basic Alias true
bool hasValue() const
Definition: Optional.h:137
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:220
TargetOptions Options
Definition: TargetMachine.h:96
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasFeature(unsigned Feature) const
const ARMSubtarget * getSubtargetImpl() const =delete
std::string TargetFS
Definition: TargetMachine.h:78
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM calls to machine code calls.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:270
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:597
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
This pass exposes codegen information to IR-level passes.
Target & getTheARMLETarget()
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:19
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...