LLVM  9.0.0svn
ARMTargetMachine.cpp
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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Triple.h"
35 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CodeGen.h"
48 #include "llvm/Transforms/Scalar.h"
49 #include <cassert>
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool>
56 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
57  cl::desc("Inhibit optimization of S->D register accesses on A15"),
58  cl::init(false));
59 
60 static cl::opt<bool>
61 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
62  cl::desc("Run SimplifyCFG after expanding atomic operations"
63  " to make use of cmpxchg flow-based information"),
64  cl::init(true));
65 
66 static cl::opt<bool>
67 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
68  cl::desc("Enable ARM load/store optimization pass"),
69  cl::init(true));
70 
71 // FIXME: Unify control over GlobalMerge.
73 EnableGlobalMerge("arm-global-merge", cl::Hidden,
74  cl::desc("Enable the global merge pass"));
75 
76 namespace llvm {
78 }
79 
80 extern "C" void LLVMInitializeARMTarget() {
81  // Register the target.
86 
88  initializeGlobalISel(Registry);
97 }
98 
99 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100  if (TT.isOSBinFormatMachO())
101  return llvm::make_unique<TargetLoweringObjectFileMachO>();
102  if (TT.isOSWindows())
103  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
104  return llvm::make_unique<ARMElfTargetObjectFile>();
105 }
106 
109  const TargetOptions &Options) {
110  StringRef ABIName = Options.MCOptions.getABIName();
111 
112  if (ABIName.empty())
113  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
114 
115  if (ABIName == "aapcs16")
117  else if (ABIName.startswith("aapcs"))
119  else if (ABIName.startswith("apcs"))
121 
122  llvm_unreachable("Unhandled/unknown ABI Name!");
124 }
125 
126 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
127  const TargetOptions &Options,
128  bool isLittle) {
129  auto ABI = computeTargetABI(TT, CPU, Options);
130  std::string Ret;
131 
132  if (isLittle)
133  // Little endian.
134  Ret += "e";
135  else
136  // Big endian.
137  Ret += "E";
138 
140 
141  // Pointers are 32 bits and aligned to 32 bits.
142  Ret += "-p:32:32";
143 
144  // Function pointers are aligned to 8 bits (because the LSB stores the
145  // ARM/Thumb state).
146  Ret += "-Fi8";
147 
148  // ABIs other than APCS have 64 bit integers with natural alignment.
150  Ret += "-i64:64";
151 
152  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
153  // bits, others to 64 bits. We always try to align to 64 bits.
155  Ret += "-f64:32:64";
156 
157  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
158  // to 64. We always ty to give them natural alignment.
160  Ret += "-v64:32:64-v128:32:128";
162  Ret += "-v128:64:128";
163 
164  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
165  // particular hardware support on 32-bit ARM).
166  Ret += "-a:0:32";
167 
168  // Integer registers are 32 bits.
169  Ret += "-n32";
170 
171  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
172  // aligned everywhere else.
174  Ret += "-S128";
176  Ret += "-S64";
177  else
178  Ret += "-S32";
179 
180  return Ret;
181 }
182 
185  if (!RM.hasValue())
186  // Default relocation model on Darwin is PIC.
188 
189  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
190  assert(TT.isOSBinFormatELF() &&
191  "ROPI/RWPI currently only supported for ELF");
192 
193  // DynamicNoPIC is only used on darwin.
194  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
195  return Reloc::Static;
196 
197  return *RM;
198 }
199 
200 /// Create an ARM architecture model.
201 ///
203  StringRef CPU, StringRef FS,
204  const TargetOptions &Options,
207  CodeGenOpt::Level OL, bool isLittle)
208  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
209  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
210  getEffectiveCodeModel(CM, CodeModel::Small), OL),
211  TargetABI(computeTargetABI(TT, CPU, Options)),
212  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
213 
214  // Default to triple-appropriate float ABI
215  if (Options.FloatABIType == FloatABI::Default) {
216  if (isTargetHardFloat())
217  this->Options.FloatABIType = FloatABI::Hard;
218  else
219  this->Options.FloatABIType = FloatABI::Soft;
220  }
221 
222  // Default to triple-appropriate EABI
223  if (Options.EABIVersion == EABI::Default ||
224  Options.EABIVersion == EABI::Unknown) {
225  // musl is compatible with glibc with regard to EABI version
231  this->Options.EABIVersion = EABI::GNU;
232  else
233  this->Options.EABIVersion = EABI::EABI5;
234  }
235 
236  if (TT.isOSBinFormatMachO()) {
237  this->Options.TrapUnreachable = true;
238  this->Options.NoTrapAfterNoreturn = true;
239  }
240 
241  initAsmInfo();
242 }
243 
245 
246 const ARMSubtarget *
248  Attribute CPUAttr = F.getFnAttribute("target-cpu");
249  Attribute FSAttr = F.getFnAttribute("target-features");
250 
251  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
252  ? CPUAttr.getValueAsString().str()
253  : TargetCPU;
254  std::string FS = !FSAttr.hasAttribute(Attribute::None)
255  ? FSAttr.getValueAsString().str()
256  : TargetFS;
257 
258  // FIXME: This is related to the code below to reset the target options,
259  // we need to know whether or not the soft float flag is set on the
260  // function before we can generate a subtarget. We also need to use
261  // it as a key for the subtarget since that can be the only difference
262  // between two functions.
263  bool SoftFloat =
264  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
265  // If the soft float attribute is set on the function turn on the soft float
266  // subtarget feature.
267  if (SoftFloat)
268  FS += FS.empty() ? "+soft-float" : ",+soft-float";
269 
270  // Use the optminsize to identify the subtarget, but don't use it in the
271  // feature string.
272  std::string Key = CPU + FS;
273  if (F.hasMinSize())
274  Key += "+minsize";
275 
276  auto &I = SubtargetMap[Key];
277  if (!I) {
278  // This needs to be done before we create a new subtarget since any
279  // creation will depend on the TM and the code generation flags on the
280  // function that reside in TargetOptions.
282  I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
283  F.hasMinSize());
284 
285  if (!I->isThumb() && !I->hasARMOps())
286  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
287  "instructions, but the target does not support ARM mode execution.");
288  }
289 
290  return I.get();
291 }
292 
295  return TargetTransformInfo(ARMTTIImpl(this, F));
296 }
297 
299  StringRef CPU, StringRef FS,
300  const TargetOptions &Options,
303  CodeGenOpt::Level OL, bool JIT)
304  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
305 
307  StringRef CPU, StringRef FS,
308  const TargetOptions &Options,
311  CodeGenOpt::Level OL, bool JIT)
312  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
313 
314 namespace {
315 
316 /// ARM Code Generator Pass Configuration Options.
317 class ARMPassConfig : public TargetPassConfig {
318 public:
319  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
320  : TargetPassConfig(TM, PM) {
321  if (TM.getOptLevel() != CodeGenOpt::None) {
324  if (STI.hasFeature(ARM::FeatureUseMISched))
325  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
326  }
327  }
328 
329  ARMBaseTargetMachine &getARMTargetMachine() const {
330  return getTM<ARMBaseTargetMachine>();
331  }
332 
334  createMachineScheduler(MachineSchedContext *C) const override {
336  // add DAG Mutations here.
337  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
338  if (ST.hasFusion())
340  return DAG;
341  }
342 
344  createPostMachineScheduler(MachineSchedContext *C) const override {
346  // add DAG Mutations here.
347  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
348  if (ST.hasFusion())
350  return DAG;
351  }
352 
353  void addIRPasses() override;
354  void addCodeGenPrepare() override;
355  bool addPreISel() override;
356  bool addInstSelector() override;
357  bool addIRTranslator() override;
358  bool addLegalizeMachineIR() override;
359  bool addRegBankSelect() override;
360  bool addGlobalInstructionSelect() override;
361  void addPreRegAlloc() override;
362  void addPreSched2() override;
363  void addPreEmitPass() override;
364 
365  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
366 };
367 
368 class ARMExecutionDomainFix : public ExecutionDomainFix {
369 public:
370  static char ID;
371  ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
372  StringRef getPassName() const override {
373  return "ARM Execution Domain Fix";
374  }
375 };
377 
378 } // end anonymous namespace
379 
380 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
381  "ARM Execution Domain Fix", false, false)
383 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
384  "ARM Execution Domain Fix", false, false)
385 
387  return new ARMPassConfig(*this, PM);
388 }
389 
390 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
391  return getStandardCSEConfigForOpt(TM->getOptLevel());
392 }
393 
394 void ARMPassConfig::addIRPasses() {
395  if (TM->Options.ThreadModel == ThreadModel::Single)
396  addPass(createLowerAtomicPass());
397  else
398  addPass(createAtomicExpandPass());
399 
400  // Cmpxchg instructions are often used with a subsequent comparison to
401  // determine whether it succeeded. We can exploit existing control-flow in
402  // ldrex/strex loops to simplify this, but it needs tidying up.
403  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
405  1, false, false, true, true, [this](const Function &F) {
406  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
407  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
408  }));
409 
411 
412  // Run the parallel DSP pass.
414  addPass(createARMParallelDSPPass());
415 
416  // Match interleaved memory accesses to ldN/stN intrinsics.
417  if (TM->getOptLevel() != CodeGenOpt::None)
418  addPass(createInterleavedAccessPass());
419 }
420 
421 void ARMPassConfig::addCodeGenPrepare() {
422  if (getOptLevel() != CodeGenOpt::None)
423  addPass(createARMCodeGenPreparePass());
425 }
426 
427 bool ARMPassConfig::addPreISel() {
428  if ((TM->getOptLevel() != CodeGenOpt::None &&
430  EnableGlobalMerge == cl::BOU_TRUE) {
431  // FIXME: This is using the thumb1 only constant value for
432  // maximal global offset for merging globals. We may want
433  // to look into using the old value for non-thumb1 code of
434  // 4095 based on the TargetMachine, but this starts to become
435  // tricky when doing code gen per function.
436  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
437  (EnableGlobalMerge == cl::BOU_UNSET);
438  // Merging of extern globals is enabled by default on non-Mach-O as we
439  // expect it to be generally either beneficial or harmless. On Mach-O it
440  // is disabled as we emit the .subsections_via_symbols directive which
441  // means that merging extern globals is not safe.
442  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
443  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
444  MergeExternalByDefault));
445  }
446 
447  return false;
448 }
449 
450 bool ARMPassConfig::addInstSelector() {
451  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
452  return false;
453 }
454 
455 bool ARMPassConfig::addIRTranslator() {
456  addPass(new IRTranslator());
457  return false;
458 }
459 
460 bool ARMPassConfig::addLegalizeMachineIR() {
461  addPass(new Legalizer());
462  return false;
463 }
464 
465 bool ARMPassConfig::addRegBankSelect() {
466  addPass(new RegBankSelect());
467  return false;
468 }
469 
470 bool ARMPassConfig::addGlobalInstructionSelect() {
471  addPass(new InstructionSelect());
472  return false;
473 }
474 
475 void ARMPassConfig::addPreRegAlloc() {
476  if (getOptLevel() != CodeGenOpt::None) {
477  addPass(createMLxExpansionPass());
478 
480  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
481 
483  addPass(createA15SDOptimizerPass());
484  }
485 }
486 
487 void ARMPassConfig::addPreSched2() {
488  if (getOptLevel() != CodeGenOpt::None) {
491 
492  addPass(new ARMExecutionDomainFix());
493  addPass(createBreakFalseDeps());
494  }
495 
496  // Expand some pseudo instructions into multiple instructions to allow
497  // proper scheduling.
498  addPass(createARMExpandPseudoPass());
499 
500  if (getOptLevel() != CodeGenOpt::None) {
501  // in v8, IfConversion depends on Thumb instruction widths
502  addPass(createThumb2SizeReductionPass([this](const Function &F) {
503  return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
504  }));
505 
506  addPass(createIfConverter([](const MachineFunction &MF) {
507  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
508  }));
509  }
510  addPass(createThumb2ITBlockPass());
511 }
512 
513 void ARMPassConfig::addPreEmitPass() {
515 
516  // Constant island pass work on unbundled instructions.
517  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
518  return MF.getSubtarget<ARMSubtarget>().isThumb2();
519  }));
520 
521  // Don't optimize barriers at -O0.
522  if (getOptLevel() != CodeGenOpt::None)
524 
525  addPass(createARMConstantIslandPass());
526 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:476
StringRef getTargetFeatureString() const
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
FunctionPass * createA15SDOptimizerPass()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
FunctionPass * createMLxExpansionPass()
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
MCTargetOptions MCOptions
Machine level options.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:614
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:572
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
void initializeARMExecutionDomainFixPass(PassRegistry &)
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
F(f)
block Block Frequency true
Target & getTheThumbLETarget()
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, bool SinkCommon=false, std::function< bool(const Function &)> Ftor=nullptr)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target & getTheARMBETarget()
Target-Independent Code Generator Pass Configuration Options.
void initializeARMCodeGenPreparePass(PassRegistry &)
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
Key
PAL metadata keys.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void LLVMInitializeARMTarget()
Target & getTheThumbBETarget()
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
std::unique_ptr< const MCSubtargetInfo > STI
Definition: TargetMachine.h:96
StringRef getTargetCPU() const
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
speculative execution
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:529
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:65
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
void initializeARMExpandPseudoPass(PassRegistry &)
void initializeARMLoadStoreOptPass(PassRegistry &)
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Pass * createARMParallelDSPPass()
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeARMParallelDSPPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const Triple & getTargetTriple() const
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:624
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
void initializeThumb2SizeReducePass(PassRegistry &)
arm execution domain fix
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
arm execution domain ARM Execution Domain Fix
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:309
Pass * createLowerAtomicPass()
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
std::string TargetCPU
Definition: TargetMachine.h:85
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:597
const ARMSubtarget * getSubtargetImpl() const =delete
std::string TargetFS
Definition: TargetMachine.h:86
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createARMCodeGenPreparePass()
This file describes how to lower LLVM calls to machine code calls.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:648
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
This pass exposes codegen information to IR-level passes.
Target & getTheARMLETarget()
FunctionPass * createAtomicExpandPass()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...