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AVRISelLowering.h
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1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_AVR_ISEL_LOWERING_H
16 #define LLVM_AVR_ISEL_LOWERING_H
17 
20 
21 namespace llvm {
22 
23 namespace AVRISD {
24 
25 /// AVR Specific DAG Nodes
26 enum NodeType {
27  /// Start the numbering where the builtin ops leave off.
29  /// Return from subroutine.
31  /// Return from ISR.
33  /// Represents an abstract call instruction,
34  /// which includes a bunch of information.
36  /// A wrapper node for TargetConstantPool,
37  /// TargetExternalSymbol, and TargetGlobalAddress.
39  LSL, ///< Logical shift left.
40  LSR, ///< Logical shift right.
41  ASR, ///< Arithmetic shift right.
42  ROR, ///< Bit rotate right.
43  ROL, ///< Bit rotate left.
44  LSLLOOP, ///< A loop of single logical shift left instructions.
45  LSRLOOP, ///< A loop of single logical shift right instructions.
46  ROLLOOP, ///< A loop of single left bit rotate instructions.
47  RORLOOP, ///< A loop of single right bit rotate instructions.
48  ASRLOOP, ///< A loop of single arithmetic shift right instructions.
49  /// AVR conditional branches. Operand 0 is the chain operand, operand 1
50  /// is the block to branch if condition is true, operand 2 is the
51  /// condition code, and operand 3 is the flag operand produced by a CMP
52  /// or TEST instruction.
54  /// Compare instruction.
55  CMP,
56  /// Compare with carry instruction.
58  /// Test for zero or minus instruction.
59  TST,
60  /// Operand 0 and operand 1 are selection variable, operand 2
61  /// is condition code and operand 3 is flag operand.
63 };
64 
65 } // end of namespace AVRISD
66 
67 class AVRTargetMachine;
68 
69 /// Performs target lowering for the AVR.
71 public:
73 
74 public:
75  MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
76  return MVT::i8;
77  }
78 
80  return MVT::i8;
81  }
82 
83  const char *getTargetNodeName(unsigned Opcode) const override;
84 
85  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
86 
87  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
88  SelectionDAG &DAG) const override;
89 
90  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
91  unsigned AS,
92  Instruction *I = nullptr) const override;
93 
94  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
96  SelectionDAG &DAG) const override;
97 
98  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
99  SDValue &Offset, ISD::MemIndexedMode &AM,
100  SelectionDAG &DAG) const override;
101 
102  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
103 
104  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
105  EVT VT) const override;
106 
108  EmitInstrWithCustomInserter(MachineInstr &MI,
109  MachineBasicBlock *MBB) const override;
110 
111  ConstraintType getConstraintType(StringRef Constraint) const override;
112 
114  getSingleConstraintMatchWeight(AsmOperandInfo &info,
115  const char *constraint) const override;
116 
117  std::pair<unsigned, const TargetRegisterClass *>
118  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
119  StringRef Constraint, MVT VT) const override;
120 
121  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
122 
123  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
124  std::vector<SDValue> &Ops,
125  SelectionDAG &DAG) const override;
126 
127  unsigned getRegisterByName(const char* RegName, EVT VT,
128  SelectionDAG &DAG) const override;
129 
130 private:
131  SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
132  SelectionDAG &DAG, SDLoc dl) const;
133  SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
134  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
135  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
136  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
137  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
138  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
139  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
140  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
141  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
142 
143  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
144 
145  bool CanLowerReturn(CallingConv::ID CallConv,
146  MachineFunction &MF, bool isVarArg,
148  LLVMContext &Context) const override;
149 
150  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
152  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
153  SelectionDAG &DAG) const override;
154  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
155  bool isVarArg,
157  const SDLoc &dl, SelectionDAG &DAG,
158  SmallVectorImpl<SDValue> &InVals) const override;
160  SmallVectorImpl<SDValue> &InVals) const override;
161  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
162  CallingConv::ID CallConv, bool isVarArg,
164  const SDLoc &dl, SelectionDAG &DAG,
165  SmallVectorImpl<SDValue> &InVals) const;
166 
167 private:
168  MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
169  MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
170 };
171 
172 } // end namespace llvm
173 
174 #endif // LLVM_AVR_ISEL_LOWERING_H
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:877
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
EVT is not used in-tree, but is used by out-of-tree target.
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
Test for zero or minus instruction.
unsigned const TargetRegisterInfo * TRI
Compare with carry instruction.
Represents an abstract call instruction, which includes a bunch of information.
A loop of single right bit rotate instructions.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
A generic AVR implementation.
Return from subroutine.
This contains information for each constraint that we are lowering.
NodeType
AVR Specific DAG Nodes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
AVR conditional branches.
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
Compare instruction.
A loop of single logical shift right instructions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
Performs target lowering for the AVR.
A loop of single left bit rotate instructions.
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Return from ISR.
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
A loop of single logical shift left instructions.
Bit rotate left.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:64
Start the numbering where the builtin ops leave off.
A loop of single arithmetic shift right instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Logical shift right.
Arithmetic shift right.
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:914