LLVM  6.0.0svn
AllocationOrder.cpp
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1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements an allocation order for virtual registers.
11 //
12 // The preferred allocation order for a virtual register depends on allocation
13 // hints and target hooks. The AllocationOrder class encapsulates all of that.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "AllocationOrder.h"
22 #include "llvm/Support/Debug.h"
24 
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "regalloc"
28 
29 // Compare VirtRegMap::getRegAllocPref().
31  const VirtRegMap &VRM,
32  const RegisterClassInfo &RegClassInfo,
33  const LiveRegMatrix *Matrix)
34  : Pos(0), HardHints(false) {
35  const MachineFunction &MF = VRM.getMachineFunction();
36  const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
37  Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
38  if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
39  HardHints = true;
40  rewind();
41 
42  DEBUG({
43  if (!Hints.empty()) {
44  dbgs() << "hints:";
45  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
46  dbgs() << ' ' << PrintReg(Hints[I], TRI);
47  dbgs() << '\n';
48  }
49  });
50 #ifndef NDEBUG
51  for (unsigned I = 0, E = Hints.size(); I != E; ++I)
52  assert(is_contained(Order, Hints[I]) &&
53  "Target hint is outside allocation order.");
54 #endif
55 }
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void rewind()
Start over from the beginning.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
const TargetRegisterInfo & getTargetRegInfo() const
Definition: VirtRegMap.h:89
Live Register Matrix
AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)
Create a new AllocationOrder for VirtReg.
MachineFunction & getMachineFunction() const
Definition: VirtRegMap.h:83
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:118
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:867