LLVM  6.0.0svn
AntiDepBreaker.h
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1 //===- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AntiDepBreaker class, which implements
11 // anti-dependence breaking heuristics for post-register-allocation scheduling.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
16 #define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
17 
23 #include "llvm/Support/Compiler.h"
24 #include <cassert>
25 #include <utility>
26 #include <vector>
27 
28 namespace llvm {
29 
30 /// This class works in conjunction with the post-RA scheduler to rename
31 /// registers to break register anti-dependencies (WAR hazards).
33 public:
34  using DbgValueVector =
35  std::vector<std::pair<MachineInstr *, MachineInstr *>>;
36 
37  virtual ~AntiDepBreaker();
38 
39  /// Initialize anti-dep breaking for a new basic block.
40  virtual void StartBlock(MachineBasicBlock *BB) = 0;
41 
42  /// Identifiy anti-dependencies within a basic-block region and break them by
43  /// renaming registers. Return the number of anti-dependencies broken.
44  virtual unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
47  unsigned InsertPosIndex,
48  DbgValueVector &DbgValues) = 0;
49 
50  /// Update liveness information to account for the current
51  /// instruction, which will not be scheduled.
52  virtual void Observe(MachineInstr &MI, unsigned Count,
53  unsigned InsertPosIndex) = 0;
54 
55  /// Finish anti-dep breaking for a basic block.
56  virtual void FinishBlock() = 0;
57 
58  /// Update DBG_VALUE if dependency breaker is updating
59  /// other machine instruction to use NewReg.
60  void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
61  assert(MI.isDebugValue() && "MI is not DBG_VALUE!");
62  if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
63  MI.getOperand(0).setReg(NewReg);
64  }
65 
66  /// Update all DBG_VALUE instructions that may be affected by the dependency
67  /// breaker's update of ParentMI to use NewReg.
68  void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
69  unsigned OldReg, unsigned NewReg) {
70  // The following code is dependent on the order in which the DbgValues are
71  // constructed in ScheduleDAGInstrs::buildSchedGraph.
72  MachineInstr *PrevDbgMI = nullptr;
73  for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
74  MachineInstr *PrevMI = DV.second;
75  if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
76  MachineInstr *DbgMI = DV.first;
77  UpdateDbgValue(*DbgMI, OldReg, NewReg);
78  PrevDbgMI = DbgMI;
79  } else if (PrevDbgMI) {
80  break; // If no match and already found a DBG_VALUE, we're done.
81  }
82  }
83  }
84 };
85 
86 } // end namespace llvm
87 
88 #endif // LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
static const unsigned End
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
Definition: Compiler.h:105
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isDebugValue() const
Definition: MachineInstr.h:816
void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg)
Update DBG_VALUE if dependency breaker is updating other machine instruction to use NewReg...
Representation of each machine instruction.
Definition: MachineInstr.h:59
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg)
Update all DBG_VALUE instructions that may be affected by the dependency breaker&#39;s update of ParentMI...
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295