LLVM  11.0.0git
AntiDepBreaker.h
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1 //===- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AntiDepBreaker class, which implements
10 // anti-dependence breaking heuristics for post-register-allocation scheduling.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
15 #define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
16 
22 #include "llvm/Support/Compiler.h"
23 #include <cassert>
24 #include <utility>
25 #include <vector>
26 
27 namespace llvm {
28 
29 class RegisterClassInfo;
30 
31 /// This class works in conjunction with the post-RA scheduler to rename
32 /// registers to break register anti-dependencies (WAR hazards).
34 public:
35  using DbgValueVector =
36  std::vector<std::pair<MachineInstr *, MachineInstr *>>;
37 
38  virtual ~AntiDepBreaker();
39 
40  /// Initialize anti-dep breaking for a new basic block.
41  virtual void StartBlock(MachineBasicBlock *BB) = 0;
42 
43  /// Identifiy anti-dependencies within a basic-block region and break them by
44  /// renaming registers. Return the number of anti-dependencies broken.
45  virtual unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
48  unsigned InsertPosIndex,
49  DbgValueVector &DbgValues) = 0;
50 
51  /// Update liveness information to account for the current
52  /// instruction, which will not be scheduled.
53  virtual void Observe(MachineInstr &MI, unsigned Count,
54  unsigned InsertPosIndex) = 0;
55 
56  /// Finish anti-dep breaking for a basic block.
57  virtual void FinishBlock() = 0;
58 
59  /// Update DBG_VALUE if dependency breaker is updating
60  /// other machine instruction to use NewReg.
61  void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
62  assert(MI.isDebugValue() && "MI is not DBG_VALUE!");
63  if (MI.getDebugOperand(0).isReg() &&
64  MI.getDebugOperand(0).getReg() == OldReg)
65  MI.getDebugOperand(0).setReg(NewReg);
66  }
67 
68  /// Update all DBG_VALUE instructions that may be affected by the dependency
69  /// breaker's update of ParentMI to use NewReg.
70  void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
71  unsigned OldReg, unsigned NewReg) {
72  // The following code is dependent on the order in which the DbgValues are
73  // constructed in ScheduleDAGInstrs::buildSchedGraph.
74  MachineInstr *PrevDbgMI = nullptr;
75  for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
76  MachineInstr *PrevMI = DV.second;
77  if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
78  MachineInstr *DbgMI = DV.first;
79  UpdateDbgValue(*DbgMI, OldReg, NewReg);
80  PrevDbgMI = DbgMI;
81  } else if (PrevDbgMI) {
82  break; // If no match and already found a DBG_VALUE, we're done.
83  }
84  }
85  }
86 };
87 
89  MachineFunction &MFi, const RegisterClassInfo &RCI,
90  TargetSubtargetInfo::RegClassVector &CriticalPathRCs);
91 
93  const RegisterClassInfo &RCI);
94 
95 } // end namespace llvm
96 
97 #endif // LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:475
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
AntiDepBreaker * createAggressiveAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
virtual void StartBlock(MachineBasicBlock *BB)=0
Initialize anti-dep breaking for a new basic block.
void setReg(Register Reg)
Change the register this operand corresponds to.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
virtual unsigned BreakAntiDependencies(const std::vector< SUnit > &SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex, DbgValueVector &DbgValues)=0
Identifiy anti-dependencies within a basic-block region and break them by renaming registers...
virtual void FinishBlock()=0
Finish anti-dep breaking for a basic block.
AntiDepBreaker * createCriticalAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isDebugValue() const
void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg)
Update DBG_VALUE if dependency breaker is updating other machine instruction to use NewReg...
virtual void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex)=0
Update liveness information to account for the current instruction, which will not be scheduled...
Representation of each machine instruction.
Definition: MachineInstr.h:62
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg)
Update all DBG_VALUE instructions that may be affected by the dependency breaker&#39;s update of ParentMI...
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.