LLVM  6.0.0svn
BitTracker.cpp
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1 //===- BitTracker.cpp -----------------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 // SSA-based bit propagation.
11 //
12 // The purpose of this code is, for a given virtual register, to provide
13 // information about the value of each bit in the register. The values
14 // of bits are represented by the class BitValue, and take one of four
15 // cases: 0, 1, "ref" and "bottom". The 0 and 1 are rather clear, the
16 // "ref" value means that the bit is a copy of another bit (which itself
17 // cannot be a copy of yet another bit---such chains are not allowed).
18 // A "ref" value is associated with a BitRef structure, which indicates
19 // which virtual register, and which bit in that register is the origin
20 // of the value. For example, given an instruction
21 // vreg2 = ASL vreg1, 1
22 // assuming that nothing is known about bits of vreg1, bit 1 of vreg2
23 // will be a "ref" to (vreg1, 0). If there is a subsequent instruction
24 // vreg3 = ASL vreg2, 2
25 // then bit 3 of vreg3 will be a "ref" to (vreg1, 0) as well.
26 // The "bottom" case means that the bit's value cannot be determined,
27 // and that this virtual register actually defines it. The "bottom" case
28 // is discussed in detail in BitTracker.h. In fact, "bottom" is a "ref
29 // to self", so for the vreg1 above, the bit 0 of it will be a "ref" to
30 // (vreg1, 0), bit 1 will be a "ref" to (vreg1, 1), etc.
31 //
32 // The tracker implements the Wegman-Zadeck algorithm, originally developed
33 // for SSA-based constant propagation. Each register is represented as
34 // a sequence of bits, with the convention that bit 0 is the least signi-
35 // ficant bit. Each bit is propagated individually. The class RegisterCell
36 // implements the register's representation, and is also the subject of
37 // the lattice operations in the tracker.
38 //
39 // The intended usage of the bit tracker is to create a target-specific
40 // machine instruction evaluator, pass the evaluator to the BitTracker
41 // object, and run the tracker. The tracker will then collect the bit
42 // value information for a given machine function. After that, it can be
43 // queried for the cells for each virtual register.
44 // Sample code:
45 // const TargetSpecificEvaluator TSE(TRI, MRI);
46 // BitTracker BT(TSE, MF);
47 // BT.run();
48 // ...
49 // unsigned Reg = interestingRegister();
50 // RegisterCell RC = BT.get(Reg);
51 // if (RC[3].is(1))
52 // Reg0bit3 = 1;
53 //
54 // The code below is intended to be fully target-independent.
55 
56 #include "BitTracker.h"
57 #include "llvm/ADT/APInt.h"
58 #include "llvm/ADT/BitVector.h"
65 #include "llvm/IR/Constants.h"
66 #include "llvm/Support/Debug.h"
68 #include <cassert>
69 #include <cstdint>
70 #include <iterator>
71 
72 using namespace llvm;
73 
74 using BT = BitTracker;
75 
76 namespace {
77 
78  // Local trickery to pretty print a register (without the whole "%vreg"
79  // business).
80  struct printv {
81  printv(unsigned r) : R(r) {}
82 
83  unsigned R;
84  };
85 
86  raw_ostream &operator<< (raw_ostream &OS, const printv &PV) {
87  if (PV.R)
88  OS << 'v' << TargetRegisterInfo::virtReg2Index(PV.R);
89  else
90  OS << 's';
91  return OS;
92  }
93 
94 } // end anonymous namespace
95 
96 namespace llvm {
97 
99  switch (BV.Type) {
100  case BT::BitValue::Top:
101  OS << 'T';
102  break;
103  case BT::BitValue::Zero:
104  OS << '0';
105  break;
106  case BT::BitValue::One:
107  OS << '1';
108  break;
109  case BT::BitValue::Ref:
110  OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']';
111  break;
112  }
113  return OS;
114  }
115 
117  unsigned n = RC.Bits.size();
118  OS << "{ w:" << n;
119  // Instead of printing each bit value individually, try to group them
120  // into logical segments, such as sequences of 0 or 1 bits or references
121  // to consecutive bits (e.g. "bits 3-5 are same as bits 7-9 of reg xyz").
122  // "Start" will be the index of the beginning of the most recent segment.
123  unsigned Start = 0;
124  bool SeqRef = false; // A sequence of refs to consecutive bits.
125  bool ConstRef = false; // A sequence of refs to the same bit.
126 
127  for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) {
128  const BT::BitValue &V = RC[i];
129  const BT::BitValue &SV = RC[Start];
130  bool IsRef = (V.Type == BT::BitValue::Ref);
131  // If the current value is the same as Start, skip to the next one.
132  if (!IsRef && V == SV)
133  continue;
134  if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) {
135  if (Start+1 == i) {
136  SeqRef = (V.RefI.Pos == SV.RefI.Pos+1);
137  ConstRef = (V.RefI.Pos == SV.RefI.Pos);
138  }
139  if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start))
140  continue;
141  if (ConstRef && V.RefI.Pos == SV.RefI.Pos)
142  continue;
143  }
144 
145  // The current value is different. Print the previous one and reset
146  // the Start.
147  OS << " [" << Start;
148  unsigned Count = i - Start;
149  if (Count == 1) {
150  OS << "]:" << SV;
151  } else {
152  OS << '-' << i-1 << "]:";
153  if (SV.Type == BT::BitValue::Ref && SeqRef)
154  OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-'
155  << SV.RefI.Pos+(Count-1) << ']';
156  else
157  OS << SV;
158  }
159  Start = i;
160  SeqRef = ConstRef = false;
161  }
162 
163  OS << " [" << Start;
164  unsigned Count = n - Start;
165  if (n-Start == 1) {
166  OS << "]:" << RC[Start];
167  } else {
168  OS << '-' << n-1 << "]:";
169  const BT::BitValue &SV = RC[Start];
170  if (SV.Type == BT::BitValue::Ref && SeqRef)
171  OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-'
172  << SV.RefI.Pos+(Count-1) << ']';
173  else
174  OS << SV;
175  }
176  OS << " }";
177 
178  return OS;
179  }
180 
181 } // end namespace llvm
182 
184  for (const std::pair<unsigned, RegisterCell> P : Map)
185  dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
186 }
187 
189  : Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) {}
190 
192  delete &Map;
193 }
194 
195 // If we were allowed to update a cell for a part of a register, the meet
196 // operation would need to be parametrized by the register number and the
197 // exact part of the register, so that the computer BitRefs correspond to
198 // the actual bits of the "self" register.
199 // While this cannot happen in the current implementation, I'm not sure
200 // if this should be ruled out in the future.
201 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) {
202  // An example when "meet" can be invoked with SelfR == 0 is a phi node
203  // with a physical register as an operand.
204  assert(SelfR == 0 || TargetRegisterInfo::isVirtualRegister(SelfR));
205  bool Changed = false;
206  for (uint16_t i = 0, n = Bits.size(); i < n; ++i) {
207  const BitValue &RCV = RC[i];
208  Changed |= Bits[i].meet(RCV, BitRef(SelfR, i));
209  }
210  return Changed;
211 }
212 
213 // Insert the entire cell RC into the current cell at position given by M.
215  const BitMask &M) {
216  uint16_t B = M.first(), E = M.last(), W = width();
217  // Sanity: M must be a valid mask for *this.
218  assert(B < W && E < W);
219  // Sanity: the masked part of *this must have the same number of bits
220  // as the source.
221  assert(B > E || E-B+1 == RC.width()); // B <= E => E-B+1 = |RC|.
222  assert(B <= E || E+(W-B)+1 == RC.width()); // E < B => E+(W-B)+1 = |RC|.
223  if (B <= E) {
224  for (uint16_t i = 0; i <= E-B; ++i)
225  Bits[i+B] = RC[i];
226  } else {
227  for (uint16_t i = 0; i < W-B; ++i)
228  Bits[i+B] = RC[i];
229  for (uint16_t i = 0; i <= E; ++i)
230  Bits[i] = RC[i+(W-B)];
231  }
232  return *this;
233 }
234 
236  uint16_t B = M.first(), E = M.last(), W = width();
237  assert(B < W && E < W);
238  if (B <= E) {
239  RegisterCell RC(E-B+1);
240  for (uint16_t i = B; i <= E; ++i)
241  RC.Bits[i-B] = Bits[i];
242  return RC;
243  }
244 
245  RegisterCell RC(E+(W-B)+1);
246  for (uint16_t i = 0; i < W-B; ++i)
247  RC.Bits[i] = Bits[i+B];
248  for (uint16_t i = 0; i <= E; ++i)
249  RC.Bits[i+(W-B)] = Bits[i];
250  return RC;
251 }
252 
254  // Rotate left (i.e. towards increasing bit indices).
255  // Swap the two parts: [0..W-Sh-1] [W-Sh..W-1]
256  uint16_t W = width();
257  Sh = Sh % W;
258  if (Sh == 0)
259  return *this;
260 
261  RegisterCell Tmp(W-Sh);
262  // Tmp = [0..W-Sh-1].
263  for (uint16_t i = 0; i < W-Sh; ++i)
264  Tmp[i] = Bits[i];
265  // Shift [W-Sh..W-1] to [0..Sh-1].
266  for (uint16_t i = 0; i < Sh; ++i)
267  Bits[i] = Bits[W-Sh+i];
268  // Copy Tmp to [Sh..W-1].
269  for (uint16_t i = 0; i < W-Sh; ++i)
270  Bits[i+Sh] = Tmp.Bits[i];
271  return *this;
272 }
273 
275  const BitValue &V) {
276  assert(B <= E);
277  while (B < E)
278  Bits[B++] = V;
279  return *this;
280 }
281 
283  // Append the cell given as the argument to the "this" cell.
284  // Bit 0 of RC becomes bit W of the result, where W is this->width().
285  uint16_t W = width(), WRC = RC.width();
286  Bits.resize(W+WRC);
287  for (uint16_t i = 0; i < WRC; ++i)
288  Bits[i+W] = RC.Bits[i];
289  return *this;
290 }
291 
292 uint16_t BT::RegisterCell::ct(bool B) const {
293  uint16_t W = width();
294  uint16_t C = 0;
295  BitValue V = B;
296  while (C < W && Bits[C] == V)
297  C++;
298  return C;
299 }
300 
301 uint16_t BT::RegisterCell::cl(bool B) const {
302  uint16_t W = width();
303  uint16_t C = 0;
304  BitValue V = B;
305  while (C < W && Bits[W-(C+1)] == V)
306  C++;
307  return C;
308 }
309 
311  uint16_t W = Bits.size();
312  if (RC.Bits.size() != W)
313  return false;
314  for (uint16_t i = 0; i < W; ++i)
315  if (Bits[i] != RC[i])
316  return false;
317  return true;
318 }
319 
321  for (unsigned i = 0, n = width(); i < n; ++i) {
322  const BitValue &V = Bits[i];
323  if (V.Type == BitValue::Ref && V.RefI.Reg == 0)
324  Bits[i].RefI = BitRef(R, i);
325  }
326  return *this;
327 }
328 
330  // The general problem is with finding a register class that corresponds
331  // to a given reference reg:sub. There can be several such classes, and
332  // since we only care about the register size, it does not matter which
333  // such class we would find.
334  // The easiest way to accomplish what we want is to
335  // 1. find a physical register PhysR from the same class as RR.Reg,
336  // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
337  // 3. find a register class that contains PhysS.
339  const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
340  return TRI.getRegSizeInBits(VC);
341  }
343  unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
344  return getPhysRegBitWidth(PhysR);
345 }
346 
348  const CellMapType &M) const {
349  uint16_t BW = getRegBitWidth(RR);
350 
351  // Physical registers are assumed to be present in the map with an unknown
352  // value. Don't actually insert anything in the map, just return the cell.
354  return RegisterCell::self(0, BW);
355 
357  // For virtual registers that belong to a class that is not tracked,
358  // generate an "unknown" value as well.
359  const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
360  if (!track(C))
361  return RegisterCell::self(0, BW);
362 
363  CellMapType::const_iterator F = M.find(RR.Reg);
364  if (F != M.end()) {
365  if (!RR.Sub)
366  return F->second;
367  BitMask M = mask(RR.Reg, RR.Sub);
368  return F->second.extract(M);
369  }
370  // If not found, create a "top" entry, but do not insert it in the map.
371  return RegisterCell::top(BW);
372 }
373 
375  CellMapType &M) const {
376  // While updating the cell map can be done in a meaningful way for
377  // a part of a register, it makes little sense to implement it as the
378  // SSA representation would never contain such "partial definitions".
380  return;
381  assert(RR.Sub == 0 && "Unexpected sub-register in definition");
382  // Eliminate all ref-to-reg-0 bit values: replace them with "self".
383  M[RR.Reg] = RC.regify(RR.Reg);
384 }
385 
386 // Check if the cell represents a compile-time integer value.
388  uint16_t W = A.width();
389  for (uint16_t i = 0; i < W; ++i)
390  if (!A[i].is(0) && !A[i].is(1))
391  return false;
392  return true;
393 }
394 
395 // Convert a cell to the integer value. The result must fit in uint64_t.
396 uint64_t BT::MachineEvaluator::toInt(const RegisterCell &A) const {
397  assert(isInt(A));
398  uint64_t Val = 0;
399  uint16_t W = A.width();
400  for (uint16_t i = 0; i < W; ++i) {
401  Val <<= 1;
402  Val |= A[i].is(1);
403  }
404  return Val;
405 }
406 
407 // Evaluator helper functions. These implement some common operation on
408 // register cells that can be used to implement target-specific instructions
409 // in a target-specific evaluator.
410 
411 BT::RegisterCell BT::MachineEvaluator::eIMM(int64_t V, uint16_t W) const {
412  RegisterCell Res(W);
413  // For bits beyond the 63rd, this will generate the sign bit of V.
414  for (uint16_t i = 0; i < W; ++i) {
415  Res[i] = BitValue(V & 1);
416  V >>= 1;
417  }
418  return Res;
419 }
420 
422  const APInt &A = CI->getValue();
423  uint16_t BW = A.getBitWidth();
424  assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow");
425  RegisterCell Res(BW);
426  for (uint16_t i = 0; i < BW; ++i)
427  Res[i] = A[i];
428  return Res;
429 }
430 
432  const RegisterCell &A2) const {
433  uint16_t W = A1.width();
434  assert(W == A2.width());
435  RegisterCell Res(W);
436  bool Carry = false;
437  uint16_t I;
438  for (I = 0; I < W; ++I) {
439  const BitValue &V1 = A1[I];
440  const BitValue &V2 = A2[I];
441  if (!V1.num() || !V2.num())
442  break;
443  unsigned S = bool(V1) + bool(V2) + Carry;
444  Res[I] = BitValue(S & 1);
445  Carry = (S > 1);
446  }
447  for (; I < W; ++I) {
448  const BitValue &V1 = A1[I];
449  const BitValue &V2 = A2[I];
450  // If the next bit is same as Carry, the result will be 0 plus the
451  // other bit. The Carry bit will remain unchanged.
452  if (V1.is(Carry))
453  Res[I] = BitValue::ref(V2);
454  else if (V2.is(Carry))
455  Res[I] = BitValue::ref(V1);
456  else
457  break;
458  }
459  for (; I < W; ++I)
460  Res[I] = BitValue::self();
461  return Res;
462 }
463 
465  const RegisterCell &A2) const {
466  uint16_t W = A1.width();
467  assert(W == A2.width());
468  RegisterCell Res(W);
469  bool Borrow = false;
470  uint16_t I;
471  for (I = 0; I < W; ++I) {
472  const BitValue &V1 = A1[I];
473  const BitValue &V2 = A2[I];
474  if (!V1.num() || !V2.num())
475  break;
476  unsigned S = bool(V1) - bool(V2) - Borrow;
477  Res[I] = BitValue(S & 1);
478  Borrow = (S > 1);
479  }
480  for (; I < W; ++I) {
481  const BitValue &V1 = A1[I];
482  const BitValue &V2 = A2[I];
483  if (V1.is(Borrow)) {
484  Res[I] = BitValue::ref(V2);
485  break;
486  }
487  if (V2.is(Borrow))
488  Res[I] = BitValue::ref(V1);
489  else
490  break;
491  }
492  for (; I < W; ++I)
493  Res[I] = BitValue::self();
494  return Res;
495 }
496 
498  const RegisterCell &A2) const {
499  uint16_t W = A1.width() + A2.width();
500  uint16_t Z = A1.ct(false) + A2.ct(false);
501  RegisterCell Res(W);
502  Res.fill(0, Z, BitValue::Zero);
503  Res.fill(Z, W, BitValue::self());
504  return Res;
505 }
506 
508  const RegisterCell &A2) const {
509  uint16_t W = A1.width() + A2.width();
510  uint16_t Z = A1.ct(false) + A2.ct(false);
511  RegisterCell Res(W);
512  Res.fill(0, Z, BitValue::Zero);
513  Res.fill(Z, W, BitValue::self());
514  return Res;
515 }
516 
518  uint16_t Sh) const {
519  assert(Sh <= A1.width());
521  Res.rol(Sh);
522  Res.fill(0, Sh, BitValue::Zero);
523  return Res;
524 }
525 
527  uint16_t Sh) const {
528  uint16_t W = A1.width();
529  assert(Sh <= W);
531  Res.rol(W-Sh);
532  Res.fill(W-Sh, W, BitValue::Zero);
533  return Res;
534 }
535 
537  uint16_t Sh) const {
538  uint16_t W = A1.width();
539  assert(Sh <= W);
541  BitValue Sign = Res[W-1];
542  Res.rol(W-Sh);
543  Res.fill(W-Sh, W, Sign);
544  return Res;
545 }
546 
548  const RegisterCell &A2) const {
549  uint16_t W = A1.width();
550  assert(W == A2.width());
551  RegisterCell Res(W);
552  for (uint16_t i = 0; i < W; ++i) {
553  const BitValue &V1 = A1[i];
554  const BitValue &V2 = A2[i];
555  if (V1.is(1))
556  Res[i] = BitValue::ref(V2);
557  else if (V2.is(1))
558  Res[i] = BitValue::ref(V1);
559  else if (V1.is(0) || V2.is(0))
560  Res[i] = BitValue::Zero;
561  else if (V1 == V2)
562  Res[i] = V1;
563  else
564  Res[i] = BitValue::self();
565  }
566  return Res;
567 }
568 
570  const RegisterCell &A2) const {
571  uint16_t W = A1.width();
572  assert(W == A2.width());
573  RegisterCell Res(W);
574  for (uint16_t i = 0; i < W; ++i) {
575  const BitValue &V1 = A1[i];
576  const BitValue &V2 = A2[i];
577  if (V1.is(1) || V2.is(1))
578  Res[i] = BitValue::One;
579  else if (V1.is(0))
580  Res[i] = BitValue::ref(V2);
581  else if (V2.is(0))
582  Res[i] = BitValue::ref(V1);
583  else if (V1 == V2)
584  Res[i] = V1;
585  else
586  Res[i] = BitValue::self();
587  }
588  return Res;
589 }
590 
592  const RegisterCell &A2) const {
593  uint16_t W = A1.width();
594  assert(W == A2.width());
595  RegisterCell Res(W);
596  for (uint16_t i = 0; i < W; ++i) {
597  const BitValue &V1 = A1[i];
598  const BitValue &V2 = A2[i];
599  if (V1.is(0))
600  Res[i] = BitValue::ref(V2);
601  else if (V2.is(0))
602  Res[i] = BitValue::ref(V1);
603  else if (V1 == V2)
604  Res[i] = BitValue::Zero;
605  else
606  Res[i] = BitValue::self();
607  }
608  return Res;
609 }
610 
612  uint16_t W = A1.width();
613  RegisterCell Res(W);
614  for (uint16_t i = 0; i < W; ++i) {
615  const BitValue &V = A1[i];
616  if (V.is(0))
617  Res[i] = BitValue::One;
618  else if (V.is(1))
619  Res[i] = BitValue::Zero;
620  else
621  Res[i] = BitValue::self();
622  }
623  return Res;
624 }
625 
627  uint16_t BitN) const {
628  assert(BitN < A1.width());
630  Res[BitN] = BitValue::One;
631  return Res;
632 }
633 
635  uint16_t BitN) const {
636  assert(BitN < A1.width());
638  Res[BitN] = BitValue::Zero;
639  return Res;
640 }
641 
643  uint16_t W) const {
644  uint16_t C = A1.cl(B), AW = A1.width();
645  // If the last leading non-B bit is not a constant, then we don't know
646  // the real count.
647  if ((C < AW && A1[AW-1-C].num()) || C == AW)
648  return eIMM(C, W);
649  return RegisterCell::self(0, W);
650 }
651 
653  uint16_t W) const {
654  uint16_t C = A1.ct(B), AW = A1.width();
655  // If the last trailing non-B bit is not a constant, then we don't know
656  // the real count.
657  if ((C < AW && A1[C].num()) || C == AW)
658  return eIMM(C, W);
659  return RegisterCell::self(0, W);
660 }
661 
663  uint16_t FromN) const {
664  uint16_t W = A1.width();
665  assert(FromN <= W);
667  BitValue Sign = Res[FromN-1];
668  // Sign-extend "inreg".
669  Res.fill(FromN, W, Sign);
670  return Res;
671 }
672 
674  uint16_t FromN) const {
675  uint16_t W = A1.width();
676  assert(FromN <= W);
678  Res.fill(FromN, W, BitValue::Zero);
679  return Res;
680 }
681 
683  uint16_t B, uint16_t E) const {
684  uint16_t W = A1.width();
685  assert(B < W && E <= W);
686  if (B == E)
687  return RegisterCell(0);
688  uint16_t Last = (E > 0) ? E-1 : W-1;
690  // Return shorter cell.
691  return Res;
692 }
693 
695  const RegisterCell &A2, uint16_t AtN) const {
696  uint16_t W1 = A1.width(), W2 = A2.width();
697  (void)W1;
698  assert(AtN < W1 && AtN+W2 <= W1);
699  // Copy bits from A1, insert A2 at position AtN.
701  if (W2 > 0)
702  Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1));
703  return Res;
704 }
705 
706 BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
707  assert(Sub == 0 && "Generic BitTracker::mask called for Sub != 0");
708  uint16_t W = getRegBitWidth(Reg);
709  assert(W > 0 && "Cannot generate mask for empty register");
710  return BitMask(0, W-1);
711 }
712 
716  return TRI.getRegSizeInBits(PC);
717 }
718 
720  const CellMapType &Inputs,
721  CellMapType &Outputs) const {
722  unsigned Opc = MI.getOpcode();
723  switch (Opc) {
724  case TargetOpcode::REG_SEQUENCE: {
725  RegisterRef RD = MI.getOperand(0);
726  assert(RD.Sub == 0);
727  RegisterRef RS = MI.getOperand(1);
728  unsigned SS = MI.getOperand(2).getImm();
729  RegisterRef RT = MI.getOperand(3);
730  unsigned ST = MI.getOperand(4).getImm();
731  assert(SS != ST);
732 
733  uint16_t W = getRegBitWidth(RD);
734  RegisterCell Res(W);
735  Res.insert(RegisterCell::ref(getCell(RS, Inputs)), mask(RD.Reg, SS));
736  Res.insert(RegisterCell::ref(getCell(RT, Inputs)), mask(RD.Reg, ST));
737  putCell(RD, Res, Outputs);
738  break;
739  }
740 
741  case TargetOpcode::COPY: {
742  // COPY can transfer a smaller register into a wider one.
743  // If that is the case, fill the remaining high bits with 0.
744  RegisterRef RD = MI.getOperand(0);
745  RegisterRef RS = MI.getOperand(1);
746  assert(RD.Sub == 0);
747  uint16_t WD = getRegBitWidth(RD);
748  uint16_t WS = getRegBitWidth(RS);
749  assert(WD >= WS);
750  RegisterCell Src = getCell(RS, Inputs);
751  RegisterCell Res(WD);
752  Res.insert(Src, BitMask(0, WS-1));
753  Res.fill(WS, WD, BitValue::Zero);
754  putCell(RD, Res, Outputs);
755  break;
756  }
757 
758  default:
759  return false;
760  }
761 
762  return true;
763 }
764 
765 // Main W-Z implementation.
766 
767 void BT::visitPHI(const MachineInstr &PI) {
768  int ThisN = PI.getParent()->getNumber();
769  if (Trace)
770  dbgs() << "Visit FI(BB#" << ThisN << "): " << PI;
771 
772  const MachineOperand &MD = PI.getOperand(0);
773  assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
774  RegisterRef DefRR(MD);
775  uint16_t DefBW = ME.getRegBitWidth(DefRR);
776 
777  RegisterCell DefC = ME.getCell(DefRR, Map);
778  if (DefC == RegisterCell::self(DefRR.Reg, DefBW)) // XXX slow
779  return;
780 
781  bool Changed = false;
782 
783  for (unsigned i = 1, n = PI.getNumOperands(); i < n; i += 2) {
784  const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB();
785  int PredN = PB->getNumber();
786  if (Trace)
787  dbgs() << " edge BB#" << PredN << "->BB#" << ThisN;
788  if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
789  if (Trace)
790  dbgs() << " not executable\n";
791  continue;
792  }
793 
794  RegisterRef RU = PI.getOperand(i);
795  RegisterCell ResC = ME.getCell(RU, Map);
796  if (Trace)
797  dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
798  << " cell: " << ResC << "\n";
799  Changed |= DefC.meet(ResC, DefRR.Reg);
800  }
801 
802  if (Changed) {
803  if (Trace)
804  dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
805  << " cell: " << DefC << "\n";
806  ME.putCell(DefRR, DefC, Map);
807  visitUsesOf(DefRR.Reg);
808  }
809 }
810 
811 void BT::visitNonBranch(const MachineInstr &MI) {
812  if (Trace) {
813  int ThisN = MI.getParent()->getNumber();
814  dbgs() << "Visit MI(BB#" << ThisN << "): " << MI;
815  }
816  if (MI.isDebugValue())
817  return;
818  assert(!MI.isBranch() && "Unexpected branch instruction");
819 
820  CellMapType ResMap;
821  bool Eval = ME.evaluate(MI, Map, ResMap);
822 
823  if (Trace && Eval) {
824  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
825  const MachineOperand &MO = MI.getOperand(i);
826  if (!MO.isReg() || !MO.isUse())
827  continue;
828  RegisterRef RU(MO);
829  dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
830  << " cell: " << ME.getCell(RU, Map) << "\n";
831  }
832  dbgs() << "Outputs:\n";
833  for (const std::pair<unsigned, RegisterCell> &P : ResMap) {
834  RegisterRef RD(P.first);
835  dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: "
836  << ME.getCell(RD, ResMap) << "\n";
837  }
838  }
839 
840  // Iterate over all definitions of the instruction, and update the
841  // cells accordingly.
842  for (const MachineOperand &MO : MI.operands()) {
843  // Visit register defs only.
844  if (!MO.isReg() || !MO.isDef())
845  continue;
846  RegisterRef RD(MO);
847  assert(RD.Sub == 0 && "Unexpected sub-register in definition");
849  continue;
850 
851  bool Changed = false;
852  if (!Eval || ResMap.count(RD.Reg) == 0) {
853  // Set to "ref" (aka "bottom").
854  uint16_t DefBW = ME.getRegBitWidth(RD);
855  RegisterCell RefC = RegisterCell::self(RD.Reg, DefBW);
856  if (RefC != ME.getCell(RD, Map)) {
857  ME.putCell(RD, RefC, Map);
858  Changed = true;
859  }
860  } else {
861  RegisterCell DefC = ME.getCell(RD, Map);
862  RegisterCell ResC = ME.getCell(RD, ResMap);
863  // This is a non-phi instruction, so the values of the inputs come
864  // from the same registers each time this instruction is evaluated.
865  // During the propagation, the values of the inputs can become lowered
866  // in the sense of the lattice operation, which may cause different
867  // results to be calculated in subsequent evaluations. This should
868  // not cause the bottoming of the result in the map, since the new
869  // result is already reflecting the lowered inputs.
870  for (uint16_t i = 0, w = DefC.width(); i < w; ++i) {
871  BitValue &V = DefC[i];
872  // Bits that are already "bottom" should not be updated.
873  if (V.Type == BitValue::Ref && V.RefI.Reg == RD.Reg)
874  continue;
875  // Same for those that are identical in DefC and ResC.
876  if (V == ResC[i])
877  continue;
878  V = ResC[i];
879  Changed = true;
880  }
881  if (Changed)
882  ME.putCell(RD, DefC, Map);
883  }
884  if (Changed)
885  visitUsesOf(RD.Reg);
886  }
887 }
888 
889 void BT::visitBranchesFrom(const MachineInstr &BI) {
890  const MachineBasicBlock &B = *BI.getParent();
892  BranchTargetList Targets, BTs;
893  bool FallsThrough = true, DefaultToAll = false;
894  int ThisN = B.getNumber();
895 
896  do {
897  BTs.clear();
898  const MachineInstr &MI = *It;
899  if (Trace)
900  dbgs() << "Visit BR(BB#" << ThisN << "): " << MI;
901  assert(MI.isBranch() && "Expecting branch instruction");
902  InstrExec.insert(&MI);
903  bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);
904  if (!Eval) {
905  // If the evaluation failed, we will add all targets. Keep going in
906  // the loop to mark all executable branches as such.
907  DefaultToAll = true;
908  FallsThrough = true;
909  if (Trace)
910  dbgs() << " failed to evaluate: will add all CFG successors\n";
911  } else if (!DefaultToAll) {
912  // If evaluated successfully add the targets to the cumulative list.
913  if (Trace) {
914  dbgs() << " adding targets:";
915  for (unsigned i = 0, n = BTs.size(); i < n; ++i)
916  dbgs() << " BB#" << BTs[i]->getNumber();
917  if (FallsThrough)
918  dbgs() << "\n falls through\n";
919  else
920  dbgs() << "\n does not fall through\n";
921  }
922  Targets.insert(BTs.begin(), BTs.end());
923  }
924  ++It;
925  } while (FallsThrough && It != End);
926 
927  if (!DefaultToAll) {
928  // Need to add all CFG successors that lead to EH landing pads.
929  // There won't be explicit branches to these blocks, but they must
930  // be processed.
931  for (const MachineBasicBlock *SB : B.successors()) {
932  if (SB->isEHPad())
933  Targets.insert(SB);
934  }
935  if (FallsThrough) {
937  MachineFunction::const_iterator Next = std::next(BIt);
938  if (Next != MF.end())
939  Targets.insert(&*Next);
940  }
941  } else {
942  for (const MachineBasicBlock *SB : B.successors())
943  Targets.insert(SB);
944  }
945 
946  for (const MachineBasicBlock *TB : Targets)
947  FlowQ.push(CFGEdge(ThisN, TB->getNumber()));
948 }
949 
950 void BT::visitUsesOf(unsigned Reg) {
951  if (Trace)
952  dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
953 
954  for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) {
955  if (!InstrExec.count(&UseI))
956  continue;
957  if (UseI.isPHI())
958  visitPHI(UseI);
959  else if (!UseI.isBranch())
960  visitNonBranch(UseI);
961  else
962  visitBranchesFrom(UseI);
963  }
964 }
965 
967  return ME.getCell(RR, Map);
968 }
969 
970 void BT::put(RegisterRef RR, const RegisterCell &RC) {
971  ME.putCell(RR, RC, Map);
972 }
973 
974 // Replace all references to bits from OldRR with the corresponding bits
975 // in NewRR.
976 void BT::subst(RegisterRef OldRR, RegisterRef NewRR) {
977  assert(Map.count(OldRR.Reg) > 0 && "OldRR not present in map");
978  BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub);
979  BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub);
980  uint16_t OMB = OM.first(), OME = OM.last();
981  uint16_t NMB = NM.first(), NME = NM.last();
982  (void)NME;
983  assert((OME-OMB == NME-NMB) &&
984  "Substituting registers of different lengths");
985  for (std::pair<const unsigned, RegisterCell> &P : Map) {
986  RegisterCell &RC = P.second;
987  for (uint16_t i = 0, w = RC.width(); i < w; ++i) {
988  BitValue &V = RC[i];
989  if (V.Type != BitValue::Ref || V.RefI.Reg != OldRR.Reg)
990  continue;
991  if (V.RefI.Pos < OMB || V.RefI.Pos > OME)
992  continue;
993  V.RefI.Reg = NewRR.Reg;
994  V.RefI.Pos += NMB-OMB;
995  }
996  }
997 }
998 
999 // Check if the block has been "executed" during propagation. (If not, the
1000 // block is dead, but it may still appear to be reachable.)
1001 bool BT::reached(const MachineBasicBlock *B) const {
1002  int BN = B->getNumber();
1003  assert(BN >= 0);
1004  return ReachedBB.count(BN);
1005 }
1006 
1007 // Visit an individual instruction. This could be a newly added instruction,
1008 // or one that has been modified by an optimization.
1009 void BT::visit(const MachineInstr &MI) {
1010  assert(!MI.isBranch() && "Only non-branches are allowed");
1011  InstrExec.insert(&MI);
1012  visitNonBranch(MI);
1013  // The call to visitNonBranch could propagate the changes until a branch
1014  // is actually visited. This could result in adding CFG edges to the flow
1015  // queue. Since the queue won't be processed, clear it.
1016  while (!FlowQ.empty())
1017  FlowQ.pop();
1018 }
1019 
1020 void BT::reset() {
1021  EdgeExec.clear();
1022  InstrExec.clear();
1023  Map.clear();
1024  ReachedBB.clear();
1025  ReachedBB.reserve(MF.size());
1026 }
1027 
1028 void BT::run() {
1029  reset();
1030  assert(FlowQ.empty());
1031 
1032  using MachineFlowGraphTraits = GraphTraits<const MachineFunction*>;
1033 
1034  const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
1035 
1036  unsigned MaxBN = 0;
1037  for (const MachineBasicBlock &B : MF) {
1038  assert(B.getNumber() >= 0 && "Disconnected block");
1039  unsigned BN = B.getNumber();
1040  if (BN > MaxBN)
1041  MaxBN = BN;
1042  }
1043 
1044  // Keep track of visited blocks.
1045  BitVector BlockScanned(MaxBN+1);
1046 
1047  int EntryN = Entry->getNumber();
1048  // Generate a fake edge to get something to start with.
1049  FlowQ.push(CFGEdge(-1, EntryN));
1050 
1051  while (!FlowQ.empty()) {
1052  CFGEdge Edge = FlowQ.front();
1053  FlowQ.pop();
1054 
1055  if (EdgeExec.count(Edge))
1056  continue;
1057  EdgeExec.insert(Edge);
1058  ReachedBB.insert(Edge.second);
1059 
1060  const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second);
1062  // Visit PHI nodes first.
1063  while (It != End && It->isPHI()) {
1064  const MachineInstr &PI = *It++;
1065  InstrExec.insert(&PI);
1066  visitPHI(PI);
1067  }
1068 
1069  // If this block has already been visited through a flow graph edge,
1070  // then the instructions have already been processed. Any updates to
1071  // the cells would now only happen through visitUsesOf...
1072  if (BlockScanned[Edge.second])
1073  continue;
1074  BlockScanned[Edge.second] = true;
1075 
1076  // Visit non-branch instructions.
1077  while (It != End && !It->isBranch()) {
1078  const MachineInstr &MI = *It++;
1079  InstrExec.insert(&MI);
1080  visitNonBranch(MI);
1081  }
1082  // If block end has been reached, add the fall-through edge to the queue.
1083  if (It == End) {
1085  MachineFunction::const_iterator Next = std::next(BIt);
1086  if (Next != MF.end() && B.isSuccessor(&*Next)) {
1087  int ThisN = B.getNumber();
1088  int NextN = Next->getNumber();
1089  FlowQ.push(CFGEdge(ThisN, NextN));
1090  }
1091  } else {
1092  // Handle the remaining sequence of branches. This function will update
1093  // the work queue.
1094  visitBranchesFrom(*It);
1095  }
1096  } // while (!FlowQ->empty())
1097 
1098  if (Trace)
1099  print_cells(dbgs() << "Cells after propagation:\n");
1100 }
virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const
Definition: BitTracker.cpp:719
uint64_t CallInst * C
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:517
const TargetRegisterInfo & TRI
Definition: BitTracker.h:449
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
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static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Compute iterated dominance frontiers using a linear time algorithm.
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size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:78
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
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RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
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static RegisterCell top(uint16_t Width)
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static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
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void visit(const MachineInstr &MI)
unsigned getSubReg() const
static RegisterCell self(unsigned Reg, uint16_t Width)
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RegisterCell & rol(uint16_t Sh)
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F(f)
bool isInt(const RegisterCell &A) const
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iterator_range< mop_iterator > operands()
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iterator end()
Get an iterator to the end of the SetVector.
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RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
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unsigned getBitWidth() const
Return the number of bits in the APInt.
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iterator_range< succ_iterator > successors()
void print_cells(raw_ostream &OS) const
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unsigned getNumOperands() const
Access to explicit operands of the instruction.
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RegisterCell extract(const BitMask &M) const
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Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
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RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
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zlib-gnu style compression
This file implements a class to represent arbitrary precision integral constant values and operations...
uint16_t cl(bool B) const
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bool insert(const value_type &X)
Insert a new element into the SetVector.
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iterator begin()
Get an iterator to the beginning of the SetVector.
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const APInt & getValue() const
Return the constant as an APInt value reference.
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RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
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bool reached(const MachineBasicBlock *B) const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
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RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
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#define P(N)
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
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static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
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bool operator==(const RegisterCell &RC) const
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RegisterCell eNOT(const RegisterCell &A1) const
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static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
virtual const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const
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unsigned getSubReg(unsigned Reg, unsigned Idx) const
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static const unsigned End
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self_iterator getIterator()
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virtual bool track(const TargetRegisterClass *RC) const
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virtual BitMask mask(unsigned Reg, unsigned Sub) const
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std::map< unsigned, RegisterCell > CellMapType
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RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
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uint16_t getRegBitWidth(const RegisterRef &RR) const
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Iterator for intrusive lists based on ilist_node.
uint16_t first() const
Definition: BitTracker.h:250
This is the shared class of boolean and integer constants.
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uint16_t last() const
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static BitValue self(const BitRef &Self=BitRef())
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uint64_t toInt(const RegisterCell &A) const
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bool isDebugValue() const
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MachineOperand class - Representation of each machine instruction operand.
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bool is(unsigned T) const
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MachineRegisterInfo & MRI
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int64_t getImm() const
uint16_t ct(bool B) const
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void clear()
Completely clear the SetVector.
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Class for arbitrary precision integers.
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RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
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Representation of each machine instruction.
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RegisterCell & cat(const RegisterCell &RC)
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bool isSuccessor(const MachineBasicBlock *MBB) const
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A vector that has set insertion semantics.
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RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
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Return the size in bits of a register from class RC.
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const MachineOperand & getOperand(unsigned i) const
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