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BitTracker.h
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1 //===- BitTracker.h ---------------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
11 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
12 
13 #include "llvm/ADT/DenseSet.h"
14 #include "llvm/ADT/SetVector.h"
15 #include "llvm/ADT/SmallVector.h"
17 #include <cassert>
18 #include <cstdint>
19 #include <map>
20 #include <queue>
21 #include <set>
22 #include <utility>
23 
24 namespace llvm {
25 
26 class ConstantInt;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
30 class MachineInstr;
31 class raw_ostream;
32 class TargetRegisterClass;
33 class TargetRegisterInfo;
34 
35 struct BitTracker {
36  struct BitRef;
37  struct RegisterRef;
38  struct BitValue;
39  struct BitMask;
40  struct RegisterCell;
41  struct MachineEvaluator;
42 
44  using CellMapType = std::map<unsigned, RegisterCell>;
45 
47  ~BitTracker();
48 
49  void run();
50  void trace(bool On = false) { Trace = On; }
51  bool has(unsigned Reg) const;
52  const RegisterCell &lookup(unsigned Reg) const;
53  RegisterCell get(RegisterRef RR) const;
54  void put(RegisterRef RR, const RegisterCell &RC);
55  void subst(RegisterRef OldRR, RegisterRef NewRR);
56  bool reached(const MachineBasicBlock *B) const;
57  void visit(const MachineInstr &MI);
58 
59  void print_cells(raw_ostream &OS) const;
60 
61 private:
62  void visitPHI(const MachineInstr &PI);
63  void visitNonBranch(const MachineInstr &MI);
64  void visitBranchesFrom(const MachineInstr &BI);
65  void visitUsesOf(unsigned Reg);
66  void reset();
67 
68  using CFGEdge = std::pair<int, int>;
69  using EdgeSetType = std::set<CFGEdge>;
70  using InstrSetType = std::set<const MachineInstr *>;
71  using EdgeQueueType = std::queue<CFGEdge>;
72 
73  EdgeSetType EdgeExec; // Executable flow graph edges.
74  InstrSetType InstrExec; // Executable instructions.
75  EdgeQueueType FlowQ; // Work queue of CFG edges.
76  DenseSet<unsigned> ReachedBB; // Cache of reached blocks.
77  bool Trace; // Enable tracing for debugging.
78 
79  const MachineEvaluator &ME;
80  MachineFunction &MF;
82  CellMapType &Map;
83 };
84 
85 // Abstraction of a reference to bit at position Pos from a register Reg.
87  BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
88 
89  bool operator== (const BitRef &BR) const {
90  // If Reg is 0, disregard Pos.
91  return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
92  }
93 
94  unsigned Reg;
95  uint16_t Pos;
96 };
97 
98 // Abstraction of a register reference in MachineOperand. It contains the
99 // register number and the subregister index.
101  RegisterRef(unsigned R = 0, unsigned S = 0)
102  : Reg(R), Sub(S) {}
104  : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
105 
106  unsigned Reg, Sub;
107 };
108 
109 // Value that a single bit can take. This is outside of the context of
110 // any register, it is more of an abstraction of the two-element set of
111 // possible bit values. One extension here is the "Ref" type, which
112 // indicates that this bit takes the same value as the bit described by
113 // RefInfo.
115  enum ValueType {
116  Top, // Bit not yet defined.
117  Zero, // Bit = 0.
118  One, // Bit = 1.
119  Ref // Bit value same as the one described in RefI.
120  // Conceptually, there is no explicit "bottom" value: the lattice's
121  // bottom will be expressed as a "ref to itself", which, in the context
122  // of registers, could be read as "this value of this bit is defined by
123  // this bit".
124  // The ordering is:
125  // x <= Top,
126  // Self <= x, where "Self" is "ref to itself".
127  // This makes the value lattice different for each virtual register
128  // (even for each bit in the same virtual register), since the "bottom"
129  // for one register will be a simple "ref" for another register.
130  // Since we do not store the "Self" bit and register number, the meet
131  // operation will need to take it as a parameter.
132  //
133  // In practice there is a special case for values that are not associa-
134  // ted with any specific virtual register. An example would be a value
135  // corresponding to a bit of a physical register, or an intermediate
136  // value obtained in some computation (such as instruction evaluation).
137  // Such cases are identical to the usual Ref type, but the register
138  // number is 0. In such case the Pos field of the reference is ignored.
139  //
140  // What is worthy of notice is that in value V (that is a "ref"), as long
141  // as the RefI.Reg is not 0, it may actually be the same register as the
142  // one in which V will be contained. If the RefI.Pos refers to the posi-
143  // tion of V, then V is assumed to be "bottom" (as a "ref to itself"),
144  // otherwise V is taken to be identical to the referenced bit of the
145  // same register.
146  // If RefI.Reg is 0, however, such a reference to the same register is
147  // not possible. Any value V that is a "ref", and whose RefI.Reg is 0
148  // is treated as "bottom".
149  };
152 
153  BitValue(ValueType T = Top) : Type(T) {}
154  BitValue(bool B) : Type(B ? One : Zero) {}
155  BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {}
156 
157  bool operator== (const BitValue &V) const {
158  if (Type != V.Type)
159  return false;
160  if (Type == Ref && !(RefI == V.RefI))
161  return false;
162  return true;
163  }
164  bool operator!= (const BitValue &V) const {
165  return !operator==(V);
166  }
167 
168  bool is(unsigned T) const {
169  assert(T == 0 || T == 1);
170  return T == 0 ? Type == Zero
171  : (T == 1 ? Type == One : false);
172  }
173 
174  // The "meet" operation is the "." operation in a semilattice (L, ., T, B):
175  // (1) x.x = x
176  // (2) x.y = y.x
177  // (3) x.(y.z) = (x.y).z
178  // (4) x.T = x (i.e. T = "top")
179  // (5) x.B = B (i.e. B = "bottom")
180  //
181  // This "meet" function will update the value of the "*this" object with
182  // the newly calculated one, and return "true" if the value of *this has
183  // changed, and "false" otherwise.
184  // To prove that it satisfies the conditions (1)-(5), it is sufficient
185  // to show that a relation
186  // x <= y <=> x.y = x
187  // defines a partial order (i.e. that "meet" is same as "infimum").
188  bool meet(const BitValue &V, const BitRef &Self) {
189  // First, check the cases where there is nothing to be done.
190  if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This)
191  return false;
192  if (V.Type == Top) // This.meet(Top) = This
193  return false;
194  if (*this == V) // This.meet(This) = This
195  return false;
196 
197  // At this point, we know that the value of "this" will change.
198  // If it is Top, it will become the same as V, otherwise it will
199  // become "bottom" (i.e. Self).
200  if (Type == Top) {
201  Type = V.Type;
202  RefI = V.RefI; // This may be irrelevant, but copy anyway.
203  return true;
204  }
205  // Become "bottom".
206  Type = Ref;
207  RefI = Self;
208  return true;
209  }
210 
211  // Create a reference to the bit value V.
212  static BitValue ref(const BitValue &V);
213  // Create a "self".
214  static BitValue self(const BitRef &Self = BitRef());
215 
216  bool num() const {
217  return Type == Zero || Type == One;
218  }
219 
220  operator bool() const {
221  assert(Type == Zero || Type == One);
222  return Type == One;
223  }
224 
225  friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV);
226 };
227 
228 // This operation must be idempotent, i.e. ref(ref(V)) == ref(V).
231  if (V.Type != Ref)
232  return BitValue(V.Type);
233  if (V.RefI.Reg != 0)
234  return BitValue(V.RefI.Reg, V.RefI.Pos);
235  return self();
236 }
237 
240  return BitValue(Self.Reg, Self.Pos);
241 }
242 
243 // A sequence of bits starting from index B up to and including index E.
244 // If E < B, the mask represents two sections: [0..E] and [B..W) where
245 // W is the width of the register.
247  BitMask() = default;
248  BitMask(uint16_t b, uint16_t e) : B(b), E(e) {}
249 
250  uint16_t first() const { return B; }
251  uint16_t last() const { return E; }
252 
253 private:
254  uint16_t B = 0;
255  uint16_t E = 0;
256 };
257 
258 // Representation of a register: a list of BitValues.
260  RegisterCell(uint16_t Width = DefaultBitN) : Bits(Width) {}
261 
262  uint16_t width() const {
263  return Bits.size();
264  }
265 
266  const BitValue &operator[](uint16_t BitN) const {
267  assert(BitN < Bits.size());
268  return Bits[BitN];
269  }
270  BitValue &operator[](uint16_t BitN) {
271  assert(BitN < Bits.size());
272  return Bits[BitN];
273  }
274 
275  bool meet(const RegisterCell &RC, unsigned SelfR);
276  RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
277  RegisterCell extract(const BitMask &M) const; // Returns a new cell.
278  RegisterCell &rol(uint16_t Sh); // Rotate left.
279  RegisterCell &fill(uint16_t B, uint16_t E, const BitValue &V);
280  RegisterCell &cat(const RegisterCell &RC); // Concatenate.
281  uint16_t cl(bool B) const;
282  uint16_t ct(bool B) const;
283 
284  bool operator== (const RegisterCell &RC) const;
285  bool operator!= (const RegisterCell &RC) const {
286  return !operator==(RC);
287  }
288 
289  // Replace the ref-to-reg-0 bit values with the given register.
290  RegisterCell &regify(unsigned R);
291 
292  // Generate a "ref" cell for the corresponding register. In the resulting
293  // cell each bit will be described as being the same as the corresponding
294  // bit in register Reg (i.e. the cell is "defined" by register Reg).
295  static RegisterCell self(unsigned Reg, uint16_t Width);
296  // Generate a "top" cell of given size.
297  static RegisterCell top(uint16_t Width);
298  // Generate a cell that is a "ref" to another cell.
299  static RegisterCell ref(const RegisterCell &C);
300 
301 private:
302  // The DefaultBitN is here only to avoid frequent reallocation of the
303  // memory in the vector.
304  static const unsigned DefaultBitN = 32;
307 
308  friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
309 };
310 
311 inline bool BitTracker::has(unsigned Reg) const {
312  return Map.find(Reg) != Map.end();
313 }
314 
315 inline const BitTracker::RegisterCell&
316 BitTracker::lookup(unsigned Reg) const {
317  CellMapType::const_iterator F = Map.find(Reg);
318  assert(F != Map.end());
319  return F->second;
320 }
321 
323 BitTracker::RegisterCell::self(unsigned Reg, uint16_t Width) {
324  RegisterCell RC(Width);
325  for (uint16_t i = 0; i < Width; ++i)
326  RC.Bits[i] = BitValue::self(BitRef(Reg, i));
327  return RC;
328 }
329 
332  RegisterCell RC(Width);
333  for (uint16_t i = 0; i < Width; ++i)
334  RC.Bits[i] = BitValue(BitValue::Top);
335  return RC;
336 }
337 
340  uint16_t W = C.width();
341  RegisterCell RC(W);
342  for (unsigned i = 0; i < W; ++i)
343  RC[i] = BitValue::ref(C[i]);
344  return RC;
345 }
346 
347 // A class to evaluate target's instructions and update the cell maps.
348 // This is used internally by the bit tracker. A target that wants to
349 // utilize this should implement the evaluation functions (noted below)
350 // in a subclass of this class.
353  : TRI(T), MRI(M) {}
354  virtual ~MachineEvaluator() = default;
355 
356  uint16_t getRegBitWidth(const RegisterRef &RR) const;
357 
358  RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
359  void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
360 
361  // A result of any operation should use refs to the source cells, not
362  // the cells directly. This function is a convenience wrapper to quickly
363  // generate a ref for a cell corresponding to a register reference.
364  RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const {
365  RegisterCell RC = getCell(RR, M);
366  return RegisterCell::ref(RC);
367  }
368 
369  // Helper functions.
370  // Check if a cell is an immediate value (i.e. all bits are either 0 or 1).
371  bool isInt(const RegisterCell &A) const;
372  // Convert cell to an immediate value.
373  uint64_t toInt(const RegisterCell &A) const;
374 
375  // Generate cell from an immediate value.
376  RegisterCell eIMM(int64_t V, uint16_t W) const;
377  RegisterCell eIMM(const ConstantInt *CI) const;
378 
379  // Arithmetic.
380  RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const;
381  RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const;
382  RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const;
383  RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const;
384 
385  // Shifts.
386  RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const;
387  RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const;
388  RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const;
389 
390  // Logical.
391  RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const;
392  RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const;
393  RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const;
394  RegisterCell eNOT(const RegisterCell &A1) const;
395 
396  // Set bit, clear bit.
397  RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const;
398  RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const;
399 
400  // Count leading/trailing bits (zeros/ones).
401  RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const;
402  RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const;
403 
404  // Sign/zero extension.
405  RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const;
406  RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const;
407 
408  // Extract/insert
409  // XTR R,b,e: extract bits from A1 starting at bit b, ending at e-1.
410  // INS R,S,b: take R and replace bits starting from b with S.
411  RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const;
412  RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2,
413  uint16_t AtN) const;
414 
415  // User-provided functions for individual targets:
416 
417  // Return a sub-register mask that indicates which bits in Reg belong
418  // to the subregister Sub. These bits are assumed to be contiguous in
419  // the super-register, and have the same ordering in the sub-register
420  // as in the super-register. It is valid to call this function with
421  // Sub == 0, in this case, the function should return a mask that spans
422  // the entire register Reg (which is what the default implementation
423  // does).
424  virtual BitMask mask(unsigned Reg, unsigned Sub) const;
425  // Indicate whether a given register class should be tracked.
426  virtual bool track(const TargetRegisterClass *RC) const { return true; }
427  // Evaluate a non-branching machine instruction, given the cell map with
428  // the input values. Place the results in the Outputs map. Return "true"
429  // if evaluation succeeded, "false" otherwise.
430  virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
431  CellMapType &Outputs) const;
432  // Evaluate a branch, given the cell map with the input values. Fill out
433  // a list of all possible branch targets and indicate (through a flag)
434  // whether the branch could fall-through. Return "true" if this information
435  // has been successfully computed, "false" otherwise.
436  virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
437  BranchTargetList &Targets, bool &FallsThru) const = 0;
438  // Given a register class RC, return a register class that should be assumed
439  // when a register from class RC is used with a subregister of index Idx.
440  virtual const TargetRegisterClass&
441  composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const {
442  if (Idx == 0)
443  return RC;
444  llvm_unreachable("Unimplemented composeWithSubRegIndex");
445  }
446  // Return the size in bits of the physical register Reg.
447  virtual uint16_t getPhysRegBitWidth(unsigned Reg) const;
448 
451 };
452 
453 } // end namespace llvm
454 
455 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
uint64_t CallInst * C
RegisterRef(unsigned R=0, unsigned S=0)
Definition: BitTracker.h:101
MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
Definition: BitTracker.h:352
const TargetRegisterInfo & TRI
Definition: BitTracker.h:449
BitValue(ValueType T=Top)
Definition: BitTracker.h:153
void trace(bool On=false)
Definition: BitTracker.h:50
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
BitValue(unsigned Reg, uint16_t Pos)
Definition: BitTracker.h:155
static RegisterCell top(uint16_t Width)
Definition: BitTracker.h:331
void visit(const MachineInstr &MI)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:323
F(f)
void print_cells(raw_ostream &OS) const
Definition: BitTracker.cpp:183
Reg
All possible values of the reg field in the ModR/M byte.
BitValue & operator[](uint16_t BitN)
Definition: BitTracker.h:270
BitRef(unsigned R=0, uint16_t P=0)
Definition: BitTracker.h:87
BitMask(uint16_t b, uint16_t e)
Definition: BitTracker.h:248
bool reached(const MachineBasicBlock *B) const
#define P(N)
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:596
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition: MathExtras.h:291
const RegisterCell & lookup(unsigned Reg) const
Definition: BitTracker.h:316
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const
Definition: BitTracker.h:441
static uint32_t rol(uint32_t Number, int Bits)
Definition: SHA1.cpp:30
RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.h:364
void subst(RegisterRef OldRR, RegisterRef NewRR)
Definition: BitTracker.cpp:976
virtual bool track(const TargetRegisterClass *RC) const
Definition: BitTracker.h:426
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::map< unsigned, RegisterCell > CellMapType
Definition: BitTracker.h:44
const BitValue & operator[](uint16_t BitN) const
Definition: BitTracker.h:266
uint16_t first() const
Definition: BitTracker.h:250
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
uint16_t last() const
Definition: BitTracker.h:251
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:239
MachineOperand class - Representation of each machine instruction operand.
bool is(unsigned T) const
Definition: BitTracker.h:168
MachineRegisterInfo & MRI
Definition: BitTracker.h:450
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
loop extract
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1948
Representation of each machine instruction.
Definition: MachineInstr.h:59
BitTracker(const MachineEvaluator &E, MachineFunction &F)
Definition: BitTracker.cpp:188
bool has(unsigned Reg) const
Definition: BitTracker.h:311
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2018
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterRef(const MachineOperand &MO)
Definition: BitTracker.h:103
RegisterCell(uint16_t Width=DefaultBitN)
Definition: BitTracker.h:260
A vector that has set insertion semantics.
Definition: SetVector.h:41
void put(RegisterRef RR, const RegisterCell &RC)
Definition: BitTracker.cpp:970
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1946
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:339
bool meet(const BitValue &V, const BitRef &Self)
Definition: BitTracker.h:188
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:230