LLVM  7.0.0svn
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/Twine.h"
24 #include "llvm/IR/Constants.h"
25 
26 #define DEBUG_TYPE "globalisel-utils"
27 
28 using namespace llvm;
29 
31  const TargetInstrInfo &TII,
32  const RegisterBankInfo &RBI,
33  MachineInstr &InsertPt, unsigned Reg,
34  const TargetRegisterClass &RegClass) {
35  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
36  unsigned NewReg = MRI.createVirtualRegister(&RegClass);
37  BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
38  TII.get(TargetOpcode::COPY), NewReg)
39  .addReg(Reg);
40  return NewReg;
41  }
42 
43  return Reg;
44 }
45 
47  const MachineFunction &MF, const TargetRegisterInfo &TRI,
49  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
50  const MachineOperand &RegMO, unsigned OpIdx) {
51  unsigned Reg = RegMO.getReg();
52  // Assume physical registers are properly constrained.
54  "PhysReg not implemented");
55 
56  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
57  // Some of the target independent instructions, like COPY, may not impose any
58  // register class constraints on some of their operands: If it's a use, we can
59  // skip constraining as the instruction defining the register would constrain
60  // it.
61 
62  // We can't constrain unallocatable register classes, because we can't create
63  // virtual registers for these classes, so we need to let targets handled this
64  // case.
65  if (RegClass && !RegClass->isAllocatable())
66  RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
67 
68  if (!RegClass) {
69  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
70  "Register class constraint is required unless either the "
71  "instruction is target independent or the operand is a use");
72  // FIXME: Just bailing out like this here could be not enough, unless we
73  // expect the users of this function to do the right thing for PHIs and
74  // COPY:
75  // v1 = COPY v0
76  // v2 = COPY v1
77  // v1 here may end up not being constrained at all. Please notice that to
78  // reproduce the issue we likely need a destination pattern of a selection
79  // rule producing such extra copies, not just an input GMIR with them as
80  // every existing target using selectImpl handles copies before calling it
81  // and they never reach this function.
82  return Reg;
83  }
84  return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
85 }
86 
88  const TargetInstrInfo &TII,
89  const TargetRegisterInfo &TRI,
90  const RegisterBankInfo &RBI) {
92  "A selected instruction is expected");
93  MachineBasicBlock &MBB = *I.getParent();
94  MachineFunction &MF = *MBB.getParent();
96 
97  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
98  MachineOperand &MO = I.getOperand(OpI);
99 
100  // There's nothing to be done on non-register operands.
101  if (!MO.isReg())
102  continue;
103 
104  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
105  assert(MO.isReg() && "Unsupported non-reg operand");
106 
107  unsigned Reg = MO.getReg();
108  // Physical registers don't need to be constrained.
109  if (TRI.isPhysicalRegister(Reg))
110  continue;
111 
112  // Register operands with a value of 0 (e.g. predicate operands) don't need
113  // to be constrained.
114  if (Reg == 0)
115  continue;
116 
117  // If the operand is a vreg, we should constrain its regclass, and only
118  // insert COPYs if that's impossible.
119  // constrainOperandRegClass does that for us.
120  MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
121  MO, OpI));
122 
123  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
124  // done.
125  if (MO.isUse()) {
126  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
127  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
128  I.tieOperands(DefIdx, OpI);
129  }
130  }
131  return true;
132 }
133 
135  const MachineRegisterInfo &MRI) {
136  // If we can move an instruction, we can remove it. Otherwise, it has
137  // a side-effect of some sort.
138  bool SawStore = false;
139  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
140  return false;
141 
142  // Instructions without side-effects are dead iff they only define dead vregs.
143  for (auto &MO : MI.operands()) {
144  if (!MO.isReg() || !MO.isDef())
145  continue;
146 
147  unsigned Reg = MO.getReg();
149  !MRI.use_nodbg_empty(Reg))
150  return false;
151  }
152  return true;
153 }
154 
159 
160  // Print the function name explicitly if we don't have a debug location (which
161  // makes the diagnostic less useful) or if we're going to emit a raw error.
162  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
163  R << (" (in function: " + MF.getName() + ")").str();
164 
165  if (TPC.isGlobalISelAbortEnabled())
167  else
168  MORE.emit(R);
169 }
170 
173  const char *PassName, StringRef Msg,
174  const MachineInstr &MI) {
175  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
176  MI.getDebugLoc(), MI.getParent());
177  R << Msg;
178  // Printing MI is expensive; only do it if expensive remarks are enabled.
179  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
180  R << ": " << ore::MNV("Inst", MI);
181  reportGISelFailure(MF, TPC, MORE, R);
182 }
183 
185  const MachineRegisterInfo &MRI) {
186  MachineInstr *MI = MRI.getVRegDef(VReg);
187  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
188  return None;
189 
190  if (MI->getOperand(1).isImm())
191  return MI->getOperand(1).getImm();
192 
193  if (MI->getOperand(1).isCImm() &&
194  MI->getOperand(1).getCImm()->getBitWidth() <= 64)
195  return MI->getOperand(1).getCImm()->getSExtValue();
196 
197  return None;
198 }
199 
201  const MachineRegisterInfo &MRI) {
202  MachineInstr *MI = MRI.getVRegDef(VReg);
203  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
204  return nullptr;
205  return MI->getOperand(1).getFPImm();
206 }
207 
208 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
209  const MachineRegisterInfo &MRI) {
210  auto *DefMI = MRI.getVRegDef(Reg);
211  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
212  if (!DstTy.isValid())
213  return nullptr;
214  while (DefMI->getOpcode() == TargetOpcode::COPY) {
215  unsigned SrcReg = DefMI->getOperand(1).getReg();
216  auto SrcTy = MRI.getType(SrcReg);
217  if (!SrcTy.isValid() || SrcTy != DstTy)
218  break;
219  DefMI = MRI.getVRegDef(SrcReg);
220  }
221  return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
222 }
223 
224 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
225  if (Size == 32)
226  return APFloat(float(Val));
227  if (Size == 64)
228  return APFloat(Val);
229  if (Size != 16)
230  llvm_unreachable("Unsupported FPConstant size");
231  bool Ignored;
232  APFloat APF(Val);
234  return APF;
235 }
const NoneType None
Definition: None.h:24
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const MachineFunctionProperties & getProperties() const
Get the function properties.
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:200
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:161
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void getLocation(StringRef *Filename, unsigned *Line, unsigned *Column) const
Return location information for this diagnostic in three parts: the source file name, line number and column.
unsigned const TargetRegisterInfo * TRI
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:361
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:143
void emit(DiagnosticInfoOptimizationBase &OptDiag)
Emit an optimization remark.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
Target-Independent Code Generator Pass Configuration Options.
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:224
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:308
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4444
bool allowExtraAnalysis(StringRef PassName) const
Whether we allow for extra compile-time budget to perform more analysis to be more informative...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
MachineInstr * getOpcodeDef(unsigned Opcode, unsigned Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:208
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:37
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:185
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:117
The optimization diagnostic interface.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
#define MORE()
Definition: regcomp.c:251
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:87
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:184
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:134
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Diagnostic information for missed-optimization remarks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:201
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
const ConstantInt * getCImm() const
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:155
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.