LLVM  6.0.0svn
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Twine.h"
23 #include "llvm/IR/Constants.h"
24 
25 #define DEBUG_TYPE "globalisel-utils"
26 
27 using namespace llvm;
28 
30  const TargetInstrInfo &TII,
31  const RegisterBankInfo &RBI,
32  MachineInstr &InsertPt, unsigned Reg,
33  const TargetRegisterClass &RegClass) {
34  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
35  unsigned NewReg = MRI.createVirtualRegister(&RegClass);
36  BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
37  TII.get(TargetOpcode::COPY), NewReg)
38  .addReg(Reg);
39  return NewReg;
40  }
41 
42  return Reg;
43 }
44 
45 
47  const MachineFunction &MF, const TargetRegisterInfo &TRI,
49  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
50  unsigned Reg, unsigned OpIdx) {
51  // Assume physical registers are properly constrained.
53  "PhysReg not implemented");
54 
55  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
56  return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
57 }
58 
60  const MachineRegisterInfo &MRI) {
61  // If we can move an instruction, we can remove it. Otherwise, it has
62  // a side-effect of some sort.
63  bool SawStore = false;
64  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
65  return false;
66 
67  // Instructions without side-effects are dead iff they only define dead vregs.
68  for (auto &MO : MI.operands()) {
69  if (!MO.isReg() || !MO.isDef())
70  continue;
71 
72  unsigned Reg = MO.getReg();
74  !MRI.use_nodbg_empty(Reg))
75  return false;
76  }
77  return true;
78 }
79 
84 
85  // Print the function name explicitly if we don't have a debug location (which
86  // makes the diagnostic less useful) or if we're going to emit a raw error.
87  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
88  R << (" (in function: " + MF.getName() + ")").str();
89 
90  if (TPC.isGlobalISelAbortEnabled())
92  else
93  MORE.emit(R);
94 }
95 
98  const char *PassName, StringRef Msg,
99  const MachineInstr &MI) {
100  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
101  MI.getDebugLoc(), MI.getParent());
102  R << Msg;
103  // Printing MI is expensive; only do it if expensive remarks are enabled.
104  if (MORE.allowExtraAnalysis(PassName))
105  R << ": " << ore::MNV("Inst", MI);
106  reportGISelFailure(MF, TPC, MORE, R);
107 }
108 
110  const MachineRegisterInfo &MRI) {
111  MachineInstr *MI = MRI.getVRegDef(VReg);
112  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
113  return None;
114 
115  if (MI->getOperand(1).isImm())
116  return MI->getOperand(1).getImm();
117 
118  if (MI->getOperand(1).isCImm() &&
119  MI->getOperand(1).getCImm()->getBitWidth() <= 64)
120  return MI->getOperand(1).getCImm()->getSExtValue();
121 
122  return None;
123 }
124 
126  const MachineRegisterInfo &MRI) {
127  MachineInstr *MI = MRI.getVRegDef(VReg);
128  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
129  return nullptr;
130  return MI->getOperand(1).getFPImm();
131 }
132 
133 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
134  const MachineRegisterInfo &MRI) {
135  auto *DefMI = MRI.getVRegDef(Reg);
136  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
137  if (!DstTy.isValid())
138  return nullptr;
139  while (DefMI->getOpcode() == TargetOpcode::COPY) {
140  unsigned SrcReg = DefMI->getOperand(1).getReg();
141  auto SrcTy = MRI.getType(SrcReg);
142  if (!SrcTy.isValid() || SrcTy != DstTy)
143  break;
144  DefMI = MRI.getVRegDef(SrcReg);
145  }
146  return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
147 }
const NoneType None
Definition: None.h:24
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MachineFunctionProperties & getProperties() const
Get the function properties.
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:125
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void getLocation(StringRef *Filename, unsigned *Line, unsigned *Column) const
Return location information for this diagnostic in three parts: the source file name, line number and column.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:332
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:143
void emit(DiagnosticInfoOptimizationBase &OptDiag)
Emit an optimization remark.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
Target-Independent Code Generator Pass Configuration Options.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool allowExtraAnalysis(StringRef PassName) const
Whether we allow for extra compile-time budget to perform more analysis to be more informative...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
MachineInstr * getOpcodeDef(unsigned Opcode, unsigned Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:133
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:29
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
The optimization diagnostic interface.
MachineInstrBuilder MachineInstrBuilder & DefMI
#define MORE()
Definition: regcomp.c:256
int64_t getImm() const
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:109
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:59
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Diagnostic information for missed-optimization remarks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
const ConstantInt * getCImm() const
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:80
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.