LLVM  7.0.0svn
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Twine.h"
23 #include "llvm/IR/Constants.h"
24 
25 #define DEBUG_TYPE "globalisel-utils"
26 
27 using namespace llvm;
28 
30  const TargetInstrInfo &TII,
31  const RegisterBankInfo &RBI,
32  MachineInstr &InsertPt, unsigned Reg,
33  const TargetRegisterClass &RegClass) {
34  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) {
35  unsigned NewReg = MRI.createVirtualRegister(&RegClass);
36  BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
37  TII.get(TargetOpcode::COPY), NewReg)
38  .addReg(Reg);
39  return NewReg;
40  }
41 
42  return Reg;
43 }
44 
45 
47  const MachineFunction &MF, const TargetRegisterInfo &TRI,
49  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
50  unsigned Reg, unsigned OpIdx) {
51  // Assume physical registers are properly constrained.
53  "PhysReg not implemented");
54 
55  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
56  // Some of the target independent instructions, like COPY, may not impose any
57  // register class constraints on some of their operands:
58  if (!RegClass) {
60  "Only target independent instructions are allowed to have operands "
61  "with no register class constraints");
62  // FIXME: Just bailing out like this here could be not enough, unless we
63  // expect the users of this function to do the right thing for PHIs and
64  // COPY:
65  // v1 = COPY v0
66  // v2 = COPY v1
67  // v1 here may end up not being constrained at all. Please notice that to
68  // reproduce the issue we likely need a destination pattern of a selection
69  // rule producing such extra copies, not just an input GMIR with them as
70  // every existing target using selectImpl handles copies before calling it
71  // and they never reach this function.
72  return Reg;
73  }
74  return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
75 }
76 
78  const TargetInstrInfo &TII,
79  const TargetRegisterInfo &TRI,
80  const RegisterBankInfo &RBI) {
82  "A selected instruction is expected");
83  MachineBasicBlock &MBB = *I.getParent();
84  MachineFunction &MF = *MBB.getParent();
86 
87  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
88  MachineOperand &MO = I.getOperand(OpI);
89 
90  // There's nothing to be done on non-register operands.
91  if (!MO.isReg())
92  continue;
93 
94  DEBUG(dbgs() << "Converting operand: " << MO << '\n');
95  assert(MO.isReg() && "Unsupported non-reg operand");
96 
97  unsigned Reg = MO.getReg();
98  // Physical registers don't need to be constrained.
99  if (TRI.isPhysicalRegister(Reg))
100  continue;
101 
102  // Register operands with a value of 0 (e.g. predicate operands) don't need
103  // to be constrained.
104  if (Reg == 0)
105  continue;
106 
107  // If the operand is a vreg, we should constrain its regclass, and only
108  // insert COPYs if that's impossible.
109  // constrainOperandRegClass does that for us.
110  MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
111  Reg, OpI));
112 
113  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
114  // done.
115  if (MO.isUse()) {
116  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
117  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
118  I.tieOperands(DefIdx, OpI);
119  }
120  }
121  return true;
122 }
123 
125  const MachineRegisterInfo &MRI) {
126  // If we can move an instruction, we can remove it. Otherwise, it has
127  // a side-effect of some sort.
128  bool SawStore = false;
129  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
130  return false;
131 
132  // Instructions without side-effects are dead iff they only define dead vregs.
133  for (auto &MO : MI.operands()) {
134  if (!MO.isReg() || !MO.isDef())
135  continue;
136 
137  unsigned Reg = MO.getReg();
139  !MRI.use_nodbg_empty(Reg))
140  return false;
141  }
142  return true;
143 }
144 
149 
150  // Print the function name explicitly if we don't have a debug location (which
151  // makes the diagnostic less useful) or if we're going to emit a raw error.
152  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
153  R << (" (in function: " + MF.getName() + ")").str();
154 
155  if (TPC.isGlobalISelAbortEnabled())
157  else
158  MORE.emit(R);
159 }
160 
163  const char *PassName, StringRef Msg,
164  const MachineInstr &MI) {
165  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
166  MI.getDebugLoc(), MI.getParent());
167  R << Msg;
168  // Printing MI is expensive; only do it if expensive remarks are enabled.
169  if (MORE.allowExtraAnalysis(PassName))
170  R << ": " << ore::MNV("Inst", MI);
171  reportGISelFailure(MF, TPC, MORE, R);
172 }
173 
175  const MachineRegisterInfo &MRI) {
176  MachineInstr *MI = MRI.getVRegDef(VReg);
177  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
178  return None;
179 
180  if (MI->getOperand(1).isImm())
181  return MI->getOperand(1).getImm();
182 
183  if (MI->getOperand(1).isCImm() &&
184  MI->getOperand(1).getCImm()->getBitWidth() <= 64)
185  return MI->getOperand(1).getCImm()->getSExtValue();
186 
187  return None;
188 }
189 
191  const MachineRegisterInfo &MRI) {
192  MachineInstr *MI = MRI.getVRegDef(VReg);
193  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
194  return nullptr;
195  return MI->getOperand(1).getFPImm();
196 }
197 
198 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, unsigned Reg,
199  const MachineRegisterInfo &MRI) {
200  auto *DefMI = MRI.getVRegDef(Reg);
201  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
202  if (!DstTy.isValid())
203  return nullptr;
204  while (DefMI->getOpcode() == TargetOpcode::COPY) {
205  unsigned SrcReg = DefMI->getOperand(1).getReg();
206  auto SrcTy = MRI.getType(SrcReg);
207  if (!SrcTy.isValid() || SrcTy != DstTy)
208  break;
209  DefMI = MRI.getVRegDef(SrcReg);
210  }
211  return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
212 }
const NoneType None
Definition: None.h:24
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MachineFunctionProperties & getProperties() const
Get the function properties.
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:190
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void getLocation(StringRef *Filename, unsigned *Line, unsigned *Column) const
Return location information for this diagnostic in three parts: the source file name, line number and column.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:335
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:143
void emit(DiagnosticInfoOptimizationBase &OptDiag)
Emit an optimization remark.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
Target-Independent Code Generator Pass Configuration Options.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:290
bool allowExtraAnalysis(StringRef PassName) const
Whether we allow for extra compile-time budget to perform more analysis to be more informative...
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
MachineInstr * getOpcodeDef(unsigned Opcode, unsigned Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:198
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:37
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:29
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
The optimization diagnostic interface.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
#define MORE()
Definition: regcomp.c:256
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:77
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:174
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:124
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Diagnostic information for missed-optimization remarks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:157
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
const ConstantInt * getCImm() const
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:145
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.