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CombinerHelper.h
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1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===--------------------------------------------------------------------===//
8 //
9 /// This contains common combine transformations that may be used in a combine
10 /// pass,or by the target elsewhere.
11 /// Targets can pick individual opcode transformations from the helper or use
12 /// tryCombine which invokes all transformations. All of the transformations
13 /// return true if the MachineInstruction changed and false otherwise.
14 //
15 //===--------------------------------------------------------------------===//
16 
17 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINER_HELPER_H
18 #define LLVM_CODEGEN_GLOBALISEL_COMBINER_HELPER_H
19 
21 #include "llvm/CodeGen/Register.h"
22 
23 namespace llvm {
24 
25 class GISelChangeObserver;
26 class MachineIRBuilder;
27 class MachineRegisterInfo;
28 class MachineInstr;
29 class MachineOperand;
30 class GISelKnownBits;
31 class MachineDominatorTree;
32 
34  LLT Ty; // The result type of the extend.
35  unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
37 };
38 
40 protected:
46 
47 public:
49  GISelKnownBits *KB = nullptr,
50  MachineDominatorTree *MDT = nullptr);
51 
52  /// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
53  void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
54 
55  /// Replace a single register operand with a new register and inform the
56  /// observer of the changes.
57  void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp,
58  Register ToReg) const;
59 
60  /// If \p MI is COPY, try to combine it.
61  /// Returns true if MI changed.
62  bool tryCombineCopy(MachineInstr &MI);
63  bool matchCombineCopy(MachineInstr &MI);
64  void applyCombineCopy(MachineInstr &MI);
65 
66  /// Returns true if \p DefMI precedes \p UseMI or they are the same
67  /// instruction. Both must be in the same basic block.
68  bool isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI);
69 
70  /// Returns true if \p DefMI dominates \p UseMI. By definition an
71  /// instruction dominates itself.
72  ///
73  /// If we haven't been provided with a MachineDominatorTree during
74  /// construction, this function returns a conservative result that tracks just
75  /// a single basic block.
76  bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
77 
78  /// If \p MI is extend that consumes the result of a load, try to combine it.
79  /// Returns true if MI changed.
80  bool tryCombineExtendingLoads(MachineInstr &MI);
81  bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
82  void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
83 
84  /// Combine \p MI into a pre-indexed or post-indexed load/store operation if
85  /// legal and the surrounding code makes it useful.
86  bool tryCombineIndexedLoadStore(MachineInstr &MI);
87 
88  bool matchElideBrByInvertingCond(MachineInstr &MI);
89  void applyElideBrByInvertingCond(MachineInstr &MI);
90  bool tryElideBrByInvertingCond(MachineInstr &MI);
91 
92  /// If \p MI is G_CONCAT_VECTORS, try to combine it.
93  /// Returns true if MI changed.
94  /// Right now, we support:
95  /// - concat_vector(undef, undef) => undef
96  /// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
97  /// build_vector(A, B, C, D)
98  ///
99  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
100  bool tryCombineConcatVectors(MachineInstr &MI);
101  /// Check if the G_CONCAT_VECTORS \p MI is undef or if it
102  /// can be flattened into a build_vector.
103  /// In the first case \p IsUndef will be true.
104  /// In the second case \p Ops will contain the operands needed
105  /// to produce the flattened build_vector.
106  ///
107  /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
108  bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
110  /// Replace \p MI with a flattened build_vector with \p Ops or an
111  /// implicit_def if IsUndef is true.
112  void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
113  const ArrayRef<Register> Ops);
114 
115  /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
116  /// Returns true if MI changed.
117  ///
118  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
119  bool tryCombineShuffleVector(MachineInstr &MI);
120  /// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
121  /// concat_vectors.
122  /// \p Ops will contain the operands needed to produce the flattened
123  /// concat_vectors.
124  ///
125  /// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
126  bool matchCombineShuffleVector(MachineInstr &MI,
128  /// Replace \p MI with a concat_vectors with \p Ops.
129  void applyCombineShuffleVector(MachineInstr &MI,
130  const ArrayRef<Register> Ops);
131 
132  /// Optimize memcpy intrinsics et al, e.g. constant len calls.
133  /// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
134  ///
135  /// For example (pre-indexed):
136  ///
137  /// $addr = G_GEP $base, $offset
138  /// [...]
139  /// $val = G_LOAD $addr
140  /// [...]
141  /// $whatever = COPY $addr
142  ///
143  /// -->
144  ///
145  /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
146  /// [...]
147  /// $whatever = COPY $addr
148  ///
149  /// or (post-indexed):
150  ///
151  /// G_STORE $val, $base
152  /// [...]
153  /// $addr = G_GEP $base, $offset
154  /// [...]
155  /// $whatever = COPY $addr
156  ///
157  /// -->
158  ///
159  /// $addr = G_INDEXED_STORE $val, $base, $offset
160  /// [...]
161  /// $whatever = COPY $addr
162  bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
163 
164  /// Try to transform \p MI by using all of the above
165  /// combine functions. Returns true if changed.
166  bool tryCombine(MachineInstr &MI);
167 
168 private:
169  // Memcpy family optimization helpers.
170  bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
171  unsigned KnownLen, unsigned DstAlign, unsigned SrcAlign,
172  bool IsVolatile);
173  bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
174  unsigned KnownLen, unsigned DstAlign, unsigned SrcAlign,
175  bool IsVolatile);
176  bool optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
177  unsigned KnownLen, unsigned DstAlign, bool IsVolatile);
178 
179  /// Given a non-indexed load or store instruction \p MI, find an offset that
180  /// can be usefully and legally folded into it as a post-indexing operation.
181  ///
182  /// \returns true if a candidate is found.
183  bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
184  Register &Offset);
185 
186  /// Given a non-indexed load or store instruction \p MI, find an offset that
187  /// can be usefully and legally folded into it as a pre-indexing operation.
188  ///
189  /// \returns true if a candidate is found.
190  bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
191  Register &Offset);
192 };
193 } // namespace llvm
194 
195 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
constexpr char IsVolatile[]
Key for Kernel::Arg::Metadata::mIsVolatile.
GISelKnownBits * KB
GISelChangeObserver & Observer
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
MachineIRBuilder & Builder
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Abstract class that contains various methods for clients to notify about changes. ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineInstrBuilder & UseMI
Helper class to build MachineInstr.
MachineDominatorTree * MDT
MachineRegisterInfo & MRI
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineInstr * MI
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19