#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IntervalMap.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Metadata.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <functional>
#include <iterator>
#include <string>
#include <tuple>
#include <utility>

Macros
#define	DEBUG_TYPE "dagcombine"

Functions
	STATISTIC (NodesCombined, "Number of dag nodes combined")

	STATISTIC (PreIndexedNodes, "Number of pre-indexed nodes created")

	STATISTIC (PostIndexedNodes, "Number of post-indexed nodes created")

	STATISTIC (OpsNarrowed, "Number of load/op/store narrowed")

	STATISTIC (LdStFP2Int, "Number of fp load/store pairs transformed to int")

	STATISTIC (SlicedLoads, "Number of load sliced")

	STATISTIC (NumFPLogicOpsConv, "Number of logic ops converted to fp ops")

static void	zeroExtendToMatch (APInt &LHS, APInt &RHS, unsigned Offset=0)

static SDNode *	isConstantFPBuildVectorOrConstantFP (SDValue N)

static bool	isConstantOrConstantVector (SDValue N, bool NoOpaques=false)

static bool	isAnyConstantBuildVector (SDValue V, bool NoOpaques=false)

static SDValue	getInputChainForNode (SDNode *N)
	Given a node, return its input chain if it has one, otherwise return a null sd operand. More...

static ConstantSDNode *	getAsNonOpaqueConstant (SDValue N)
	If `N` is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr. More...

static SDValue	foldAddSubBoolOfMaskedVal (SDNode *N, SelectionDAG &DAG)

static SDValue	foldAddSubOfSignBit (SDNode *N, SelectionDAG &DAG)
	Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant. More...

static SDValue	getAsCarry (const TargetLowering &TLI, SDValue V)

static SDValue	foldAddSubMasked1 (bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL)
	Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1. More...

static SDValue	flipBoolean (SDValue V, const SDLoc &DL, SelectionDAG &DAG, const TargetLowering &TLI)

static SDValue	extractBooleanFlip (SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force)
	Flips a boolean if it is cheaper to compute. More...

static SDValue	combineADDCARRYDiamond (DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N)
	If we are facing some sort of diamond carry propapagtion pattern try to break it up to generate something like: (addcarry X, 0, (addcarry A, B, Z):Carry) More...

static SDValue	tryFoldToZero (const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations)

static bool	isDivRemLibcallAvailable (SDNode *Node, bool isSigned, const TargetLowering &TLI)
	Return true if divmod libcall is available. More...

static SDValue	simplifyDivRem (SDNode *N, SelectionDAG &DAG)

static SDValue	combineShiftAnd1ToBitTest (SDNode *And, SelectionDAG &DAG)
	Try to replace shift/logic that tests if a bit is clear with mask + setcc. More...

static bool	isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode *> Parts)
	Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap. More...

static bool	isBSwapHWordPair (SDValue N, MutableArrayRef< SDNode *> Parts)

static SDValue	visitORCommutative (SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N)
	OR combines for which the commuted variant will be tried as well. More...

static SDValue	stripConstantMask (SelectionDAG &DAG, SDValue Op, SDValue &Mask)

static bool	matchRotateHalf (SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask)
	Match "(X shl/srl V1) & V2" where V2 may not be present. More...

static SDValue	extractShiftForRotate (SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL)
	Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv. More...

static bool	matchRotateSub (SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG)

static const Optional< ByteProvider >	calculateByteProvider (SDValue Op, unsigned Index, unsigned Depth, bool Root=false)
	Recursively traverses the expression calculating the origin of the requested byte of the given value. More...

static unsigned	LittleEndianByteAt (unsigned BW, unsigned i)

static unsigned	BigEndianByteAt (unsigned BW, unsigned i)

static Optional< bool >	isBigEndian (const SmallVector< int64_t, 4 > &ByteOffsets, int64_t FirstOffset)

static SDValue	stripTruncAndExt (SDValue Value)

static SDValue	combineShiftOfShiftedLogic (SDNode *Shift, SelectionDAG &DAG)
	If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op. More...

static bool	isLegalToCombineMinNumMaxNum (SelectionDAG &DAG, SDValue LHS, SDValue RHS, const TargetLowering &TLI)

static SDValue	combineMinNumMaxNum (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG)
	Generate Min/Max node. More...

static SDValue	foldSelectOfConstantsUsingSra (SDNode *N, SelectionDAG &DAG)
	If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask. More...

static SDValue	ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG)

static SDValue	tryToFoldExtendOfConstant (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes)
	Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants. More...

static bool	ExtendUsesToFormExtLoad (EVT VT, SDNode N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode > &ExtendNodes, const TargetLowering &TLI)

static SDValue	tryToFoldExtOfExtload (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType)

static SDValue	tryToFoldExtOfLoad (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc)

static SDValue	tryToFoldExtOfMaskedLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc)

static SDValue	foldExtendedSignBitTest (SDNode *N, SelectionDAG &DAG, bool LegalOperations)

static bool	isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known)

static SDNode *	getBuildPairElt (SDNode *N, unsigned i)

static unsigned	getPPCf128HiElementSelector (const SelectionDAG &DAG)

static SDValue	foldBitcastedFPLogic (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)

static bool	isContractable (SDNode *N)

static bool	CanCombineFCOPYSIGN_EXTEND_ROUND (SDNode *N)
	copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) More...

static SDValue	foldFPToIntToFP (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)

static SDValue	FoldIntToFPToInt (SDNode *N, SelectionDAG &DAG)

static SDValue	visitFMinMax (SelectionDAG &DAG, SDNode N, APFloat(Op)(const APFloat &, const APFloat &))

static bool	canFoldInAddressingMode (SDNode N, SDNode Use, SelectionDAG &DAG, const TargetLowering &TLI)
	Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode. More...

static int	numVectorEltsOrZero (EVT T)

static bool	areUsedBitsDense (const APInt &UsedBits)
	Check that all bits set in `UsedBits` form a dense region, i.e., `UsedBits` looks like 0..0 1..1 0..0. More...

static bool	areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second)
	Check whether or not `First` and `Second` are next to each other in memory. More...

static void	adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost)
	Adjust the `GlobalLSCost` according to the target paring capabilities and the layout of the slices. More...

static bool	isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize)
	Check the profitability of all involved LoadedSlice. More...

static std::pair< unsigned, unsigned >	CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain)
	Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out. More...

static SDValue	ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode St, DAGCombiner DC)
	Check to see if IVal is something that provides a value as specified by MaskInfo. More...

static SDValue	scalarizeExtractedBinop (SDNode *ExtElt, SelectionDAG &DAG, bool LegalOperations)
	Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector. More...

static SDValue	reduceBuildVecToShuffleWithZero (SDNode *BV, SelectionDAG &DAG)

static SDValue	combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG)

static SDValue	combineConcatVectorOfExtracts (SDNode *N, SelectionDAG &DAG)

static SDValue	getSubVectorSrc (SDValue V, SDValue Index, EVT SubVT)

static SDValue	narrowInsertExtractVectorBinOp (SDNode *Extract, SelectionDAG &DAG)

static SDValue	narrowExtractedVectorBinOp (SDNode *Extract, SelectionDAG &DAG)
	If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction. More...

static SDValue	narrowExtractedVectorLoad (SDNode *Extract, SelectionDAG &DAG)
	If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) –> (load narrow vector) More...

static SDValue	foldShuffleOfConcatUndefs (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
	Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation. More...

static SDValue	partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG)

static SDValue	combineShuffleOfScalars (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI)

static SDValue	combineShuffleToVectorExtend (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)

static SDValue	combineTruncationShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG)

static SDValue	combineShuffleOfSplatVal (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)

static int	getShuffleMaskIndexOfOneElementFromOp0IntoOp1 (ArrayRef< int > Mask)
	If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand. More...

static SDValue	replaceShuffleOfInsert (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
	If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle. More...

static SDValue	simplifyShuffleOfShuffle (ShuffleVectorSDNode *Shuf)
	If we have a unary shuffle of a shuffle, see if it can be folded away completely. More...

static SDValue	scalarizeBinOpOfSplats (SDNode *N, SelectionDAG &DAG)
	If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat. More...

Variables
static cl::opt< bool >	CombinerGlobalAA ("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis"))

static cl::opt< bool >	UseTBAA ("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA"))

static cl::opt< std::string >	CombinerAAOnlyFunc ("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function"))

static cl::opt< bool >	StressLoadSlicing ("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false))
	Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards. More...

static cl::opt< bool >	MaySplitLoadIndex ("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads"))

static cl::opt< bool >	EnableStoreMerging ("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store"))

static cl::opt< unsigned >	TokenFactorInlineLimit ("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors"))

static cl::opt< unsigned >	StoreMergeDependenceLimit ("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check"))

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "dagcombine"

Definition at line 77 of file DAGCombiner.cpp.

Function Documentation

◆ adjustCostForPairing()

static void adjustCostForPairing	(	SmallVectorImpl< LoadedSlice > &	LoadedSlices,
		LoadedSlice::Cost &	GlobalLSCost
	)

static

Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices.

Precondition: GlobalLSCost should account for at least as many loads as there is in the slices in LoadedSlices.

Definition at line 14467 of file DAGCombiner.cpp.

References areSlicesNextToEachOther(), assert(), llvm::SmallVectorBase::size(), and llvm::sort().

Referenced by isSlicingProfitable().

◆ areSlicesNextToEachOther()

static bool areSlicesNextToEachOther	(	const LoadedSlice &	First,
		const LoadedSlice &	Second
	)

static

Check whether or not First and Second are next to each other in memory.

This means that there is no hole between the bits loaded by First and the bits loaded by Second.

Definition at line 14452 of file DAGCombiner.cpp.

References areUsedBitsDense(), and assert().

Referenced by adjustCostForPairing().

◆ areUsedBitsDense()

static bool areUsedBitsDense ( const APInt & UsedBits )

static

Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0.

Definition at line 14435 of file DAGCombiner.cpp.

References llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnesValue(), llvm::APInt::lshr(), and llvm::APInt::trunc().

Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().

◆ BigEndianByteAt()

static unsigned BigEndianByteAt	(	unsigned	BW,
		unsigned	i
	)

static

Definition at line 6414 of file DAGCombiner.cpp.

Referenced by isBigEndian(), and stripTruncAndExt().

◆ calculateByteProvider()

static const Optional<ByteProvider> calculateByteProvider	(	SDValue	Op,
		unsigned	Index,
		unsigned	Depth,
		bool	Root = `false`
	)

static

Recursively traverses the expression calculating the origin of the requested byte of the given value.

Returns None if the provider can't be calculated.

For all the values except the root of the expression verifies that the value has exactly one use and if it's not true return None. This way if the origin of the byte is returned it's guaranteed that the values which contribute to the byte are not used outside of this expression.

Because the parts of the expression are not allowed to have more than one use this function iterates over trees, not DAGs. So it never visits the same node more than once.

Definition at line 6324 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BSWAP, llvm::dyn_cast(), getMemory(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, llvm::None, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

Referenced by stripTruncAndExt().

◆ CanCombineFCOPYSIGN_EXTEND_ROUND()

static bool CanCombineFCOPYSIGN_EXTEND_ROUND ( SDNode * N )

inlinestatic

copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y)

Definition at line 12619 of file DAGCombiner.cpp.

References llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FCBRT, llvm::ISD::FCOPYSIGN, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FPOW, llvm::ISD::FSQRT, llvm::SDNode::getFlags(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getLibInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLibraryInfo::has(), llvm::SDNodeFlags::hasApproximateFuncs(), llvm::SDNodeFlags::hasNoInfs(), llvm::SDNodeFlags::hasNoNaNs(), llvm::SDNodeFlags::hasNoSignedZeros(), llvm::Function::hasOptSize(), isConstantFPBuildVectorOrConstantFP(), llvm::isConstOrConstSplatFP(), llvm::APFloat::isExactlyValue(), llvm::APFloat::isNegative(), llvm::TargetLoweringBase::isOperationExpand(), llvm::TargetLoweringBase::isOperationLegal(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().

◆ canFoldInAddressingMode()

static bool canFoldInAddressingMode	(	SDNode *	N,
		SDNode *	Use,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.

Definition at line 13420 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::AfterLegalizeDAG, assert(), llvm::SmallVectorImpl< T >::clear(), llvm::dbgs(), llvm::SDNode::dump(), llvm::dyn_cast(), llvm::numbers::e, llvm::LSBaseSDNode::getAddressingMode(), llvm::SelectionDAG::getConstant(), llvm::ConstantSDNode::getConstantIntValue(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLowering::getPostIndexedAddressParts(), llvm::TargetLowering::getPreIndexedAddressParts(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getTypeForEVT(), llvm::SDUse::getUser(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), llvm::TargetLoweringBase::isLegalAddressingMode(), isLoad(), llvm::isNullConstant(), llvm::SDNode::isPredecessorOf(), llvm::ARM_MB::LD, LLVM_DEBUG, N, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorBase::size(), llvm::ARM_MB::ST, llvm::ISD::SUB, std::swap(), llvm::ISD::TargetConstant, llvm::ISD::UNINDEXED, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::Value::uses(), and llvm::SDNode::uses().

◆ CheckForMaskedLoad()

static std::pair<unsigned, unsigned> CheckForMaskedLoad	(	SDValue	V,
		SDValue	Ptr,
		SDValue	Chain
	)

static

Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.

If so, return the byte size being masked out and the shift amount.

Definition at line 14673 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::countLeadingZeros(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), llvm::LoadSDNode::getBasePtr(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::isNormalLoad(), llvm::SDNode::isOperandOf(), and llvm::ISD::TokenFactor.

Referenced by ShrinkLoadReplaceStoreWithStore().

◆ combineADDCARRYDiamond()

static SDValue combineADDCARRYDiamond	(	DAGCombiner &	Combiner,
		SelectionDAG &	DAG,
		SDValue	X,
		SDValue	Carry0,
		SDValue	Carry1,
		SDNode *	N
	)

static

If we are facing some sort of diamond carry propapagtion pattern try to break it up to generate something like: (addcarry X, 0, (addcarry A, B, Z):Carry)

The end result is usually an increase in operation required, but because the carry is now linearized, other tranforms can kick in and optimize the DAG.

Patterns typically look something like (uaddo A, B) / \ Carry Sum | \ | (addcarry *, 0, Z) | / \ Carry | / (addcarry X, *, *)

But numerous variation exist. Our goal is to identify A, B, X and Z and produce a combine with a single path for carry propagation.

First look for a suitable Z. It will present itself in the form of (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true

 (uaddo A, B)
      |
     Sum
      |

(addcarry *, 0, Z)

(addcarry A, 0, Z) | Sum | (uaddo *, B)

Definition at line 2738 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDCARRY, B, extractBooleanFlip(), flipBoolean(), getAsCarry(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::SDNode::hasAnyUseOfValue(), llvm::isBitwiseNot(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::ISD::SUBCARRY, llvm::ISD::UADDO, X, Y, and llvm::Z.

◆ combineConcatVectorOfExtracts()

static SDValue combineConcatVectorOfExtracts	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 17743 of file DAGCombiner.cpp.

References llvm::AfterLegalizeVectorOps, llvm::all_of(), llvm::ISD::allOperandsUndef(), llvm::SmallVectorImpl< T >::append(), assert(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::buildLegalVectorShuffle(), combineConcatVectorOfScalars(), llvm::ISD::CONCAT_VECTORS, llvm::dyn_cast(), llvm::numbers::e, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::tgtok::In, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::SDNode::ops(), llvm::peekThroughBitcasts(), llvm::peekThroughOneUseBitcasts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorImpl< T >::resize(), llvm::NVPTX::PTXLdStInstCode::Scalar, llvm::ISD::SCALAR_TO_VECTOR, llvm::SmallVectorBase::size(), llvm::ISD::TRUNCATE, and llvm::ISD::UNDEF.

◆ combineConcatVectorOfScalars()

static SDValue combineConcatVectorOfScalars	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 17678 of file DAGCombiner.cpp.

References llvm::SmallVectorTemplateCommon< T >::back(), llvm::ISD::BITCAST, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorVT(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::SDNode::ops(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::UNDEF.

Referenced by combineConcatVectorOfExtracts().

◆ combineMinNumMaxNum()

static SDValue combineMinNumMaxNum	(	const SDLoc &	DL,
		EVT	VT,
		SDValue	LHS,
		SDValue	RHS,
		SDValue	True,
		SDValue	False,
		ISD::CondCode	CC,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG
	)

static

◆ combineShiftAnd1ToBitTest()

static SDValue combineShiftAnd1ToBitTest	(	SDNode *	And,
		SelectionDAG &	DAG
	)

static

Try to replace shift/logic that tests if a bit is clear with mask + setcc.

For a target with a bit test, this is expected to become test + set and save at least 1 instruction.

Definition at line 4984 of file DAGCombiner.cpp.

◆ combineShiftOfShiftedLogic()

static SDValue combineShiftOfShiftedLogic	(	SDNode *	Shift,
		SelectionDAG &	DAG
	)

static

If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.

This is a throughput improvement.

Definition at line 7061 of file DAGCombiner.cpp.

◆ combineShuffleOfScalars()

static SDValue combineShuffleOfScalars	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 18462 of file DAGCombiner.cpp.

References llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasOneUse(), llvm::SmallSet< T, N, C >::insert(), isAnyConstantBuildVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), llvm::TargetLoweringBase::isZExtFree(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by simplifyShuffleOfShuffle().

◆ combineShuffleOfSplatVal()

static SDValue combineShuffleOfSplatVal	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG
	)

static

Definition at line 18661 of file DAGCombiner.cpp.

References assert(), llvm::dyn_cast(), llvm::numbers::e, llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDValue::isUndef(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ArrayRef< T >::size().

Referenced by simplifyShuffleOfShuffle().

◆ combineShuffleToVectorExtend()

static SDValue combineShuffleToVectorExtend	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations
	)

static

◆ combineTruncationShuffle()

static SDValue combineTruncationShuffle	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG
	)

static

◆ ConvertSelectToConcatVector()

static SDValue ConvertSelectToConcatVector	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 8512 of file DAGCombiner.cpp.

◆ ExtendUsesToFormExtLoad()

static bool ExtendUsesToFormExtLoad	(	EVT	VT,
		SDNode *	N,
		SDValue	N0,
		unsigned	ExtOpc,
		SmallVectorImpl< SDNode *> &	ExtendNodes,
		const TargetLowering &	TLI
	)

static

Definition at line 8973 of file DAGCombiner.cpp.

References llvm::MCID::Add, llvm::ISD::ADD, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), B, llvm::ISD::CONCAT_VECTORS, llvm::ISD::Constant, llvm::ISD::CopyToReg, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SDValue::getResNo(), llvm::SDUse::getResNo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::EVT::getStoreSize(), llvm::SDUse::getUser(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDValue::hasOneUse(), hasOneUse(), llvm::LSBaseSDNode::isIndexed(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::TargetLoweringBase::isLoadExtLegalOrCustom(), llvm::ISD::isNON_EXTLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isPow2VectorType(), llvm::ISD::isSignedIntSetCC(), llvm::MemSDNode::isSimple(), llvm::TargetLoweringBase::isTruncateFree(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isVectorLoadExtDesirable(), llvm::TargetLoweringBase::isZExtFree(), llvm::ISD::LOAD, llvm::MinAlign(), llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::ISD::SRL, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.

Referenced by foldExtendedSignBitTest(), isTruncateOf(), and tryToFoldExtOfLoad().

◆ extractBooleanFlip()

static SDValue extractBooleanFlip	(	SDValue	V,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	Force
	)

static

Flips a boolean if it is cheaper to compute.

If the Force parameters is set, then the flip also occurs if computing the inverse is the same cost. This function returns an empty SDValue in case it cannot flip the boolean without increasing the cost of the computation. If you want to flip a boolean no matter what, use flipBoolean.

Definition at line 2552 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::CARRY_FALSE, llvm::SelectionDAG::computeOverflowKind(), llvm::dyn_cast(), flipBoolean(), llvm::ConstantSDNode::getAPIntValue(), getAsCarry(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::SDNode::hasAnyUseOfValue(), llvm::ConstantSDNode::isAllOnesValue(), llvm::isBitwiseNot(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::isConstOrConstSplat(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::ConstantSDNode::isOne(), llvm::isOneOrOneSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::SelectionDAG::OFK_Never, llvm::ISD::SADDO, llvm::ISD::UADDO, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::USUBO, llvm::ISD::XOR, Y, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by combineADDCARRYDiamond().

◆ extractShiftForRotate()

static SDValue extractShiftForRotate	(	SelectionDAG &	DAG,
		SDValue	OppShift,
		SDValue	ExtractFrom,
		SDValue &	Mask,
		const SDLoc &	DL
	)

static

Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.

This is meant to handle cases where InstCombine merged some outside op with one of the shifts from the rotate pattern.

Returns: An empty SDValue if the needed shift couldn't be extracted. Otherwise, returns an expansion of ExtractFrom based on the following patterns:

(or (add v v) (shrl v bitwidth-1)): expands (add v v) -> (shl v 1)

(or (mul v c0) (shrl (mul v c1) c2)): expands (mul v c0) -> (shl (mul v c1) c3)

(or (udiv v c0) (shl (udiv v c1) c2)): expands (udiv v c0) -> (shrl (udiv v c1) c3)

(or (shl v c0) (shrl (shl v c1) c2)): expands (shl v c0) -> (shl (shl v c1) c3)

(or (shrl v c0) (shl (shrl v c1) c2)): expands (shrl v c0) -> (shrl (shrl v c1) c3)

Such that in all cases, c3+c2==bitwidth(op v c1).

Definition at line 5889 of file DAGCombiner.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::DELETED_NODE, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::isConstOrConstSplat(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::ISD::SRL, stripConstantMask(), llvm::ISD::UDIV, llvm::APInt::udivrem(), llvm::APInt::ugt(), zeroExtendToMatch(), and llvm::APInt::zextOrTrunc().

Referenced by matchRotateSub().

◆ flipBoolean()

static SDValue flipBoolean	(	SDValue	V,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 2527 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getAllOnesConstant(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::XOR, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by combineADDCARRYDiamond(), and extractBooleanFlip().

◆ foldAddSubBoolOfMaskedVal()

static SDValue foldAddSubBoolOfMaskedVal	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

◆ foldAddSubMasked1()

static SDValue foldAddSubMasked1	(	bool	IsAdd,
		SDValue	N0,
		SDValue	N1,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

static

Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.

If so, invert the opcode and bypass the mask operation.

Definition at line 2403 of file DAGCombiner.cpp.

References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::AND, llvm::ISD::CARRY_FALSE, llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::computeOverflowKind(), llvm::dyn_cast(), llvm::SelectionDAG::getAllOnesConstant(), getAsCarry(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::VTSDNode::getVT(), llvm::SelectionDAG::getVTList(), llvm::SDNode::getVTList(), llvm::MVT::Glue, llvm::SDNode::hasAnyUseOfValue(), llvm::SDValue::hasOneUse(), llvm::MVT::i1, isConstantOrConstantVector(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::isOneOrOneSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::OFK_Never, llvm::TargetLoweringBase::preferIncOfAddToSubOfNot(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUB, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by tryFoldToZero().

◆ foldAddSubOfSignBit()

static SDValue foldAddSubOfSignBit	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.

Definition at line 2035 of file DAGCombiner.cpp.

Referenced by tryFoldToZero().

◆ foldBitcastedFPLogic()

static SDValue foldBitcastedFPLogic	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 10866 of file DAGCombiner.cpp.

References llvm::AfterLegalizeDAG, llvm::ISD::AND, llvm::SmallVectorImpl< T >::append(), assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::ISD::BITCAST, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::buildLegalVectorShuffle(), C, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::numbers::e, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FNEG, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::ConstantSDNode::getAPIntValue(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), getPPCf128HiElementSelector(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSignMask(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::hasBigEndianPartOrdering(), llvm::TargetLoweringBase::hasBitPreservingFPLogic(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MipsISD::Hi, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), isConstant(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isFAbsFree(), llvm::EVT::isFloatingPoint(), llvm::TargetLoweringBase::isFNegFree(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::DefaultDOTGraphTraits::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::SPII::Load, llvm::ISD::LOAD, llvm::APInt::lshrInPlace(), N, llvm::SDNode::op_values(), llvm::ISD::OR, llvm::MVT::ppcf128, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reverse(), llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::ISD::SRL, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::VECTOR_SHUFFLE, X, llvm::ISD::XOR, llvm::APInt::zext(), and llvm::APInt::zextOrTrunc().

◆ foldExtendedSignBitTest()

static SDValue foldExtendedSignBitTest	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

Definition at line 9377 of file DAGCombiner.cpp.

Referenced by isTruncateOf().

◆ foldFPToIntToFP()

static SDValue foldFPToIntToFP	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 12757 of file DAGCombiner.cpp.

References llvm::ISD::ConstantFP, llvm::StringRef::equals(), F(), llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, llvm::SelectionDAG::getConstantFP(), llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTarget(), llvm::Attribute::getValueAsString(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i1, llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::TargetOptions::NoSignedZerosFPMath, llvm::TargetMachine::Options, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::SelectionDAG::SignBitIsZero(), llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

◆ FoldIntToFPToInt()

static SDValue FoldIntToFPToInt	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 12900 of file DAGCombiner.cpp.

◆ foldSelectOfConstantsUsingSra()

static SDValue foldSelectOfConstantsUsingSra	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.

Definition at line 8180 of file DAGCombiner.cpp.

◆ foldShuffleOfConcatUndefs()

static SDValue foldShuffleOfConcatUndefs	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG
	)

static

Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.

Narrow vector ops may have better performance than wide ops, and this can unlock further narrowing of other vector ops. Targets can invert this transform later if it is not profitable.

Definition at line 18338 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getContext(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isShuffleMaskLegal(), and llvm::SDValue::isUndef().

Referenced by simplifyShuffleOfShuffle().

◆ getAsCarry()

static SDValue getAsCarry	(	const TargetLowering &	TLI,
		SDValue	V
	)

static

◆ getAsNonOpaqueConstant()

static ConstantSDNode* getAsNonOpaqueConstant ( SDValue N )

static

If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.

Definition at line 1911 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), llvm::dyn_cast(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesOrAllOnesSplat(), llvm::TargetLoweringBase::isBinOp(), isConstantFPBuildVectorOrConstantFP(), isConstantOrConstantVector(), llvm::isNullOrNullSplat(), llvm::ConstantSDNode::isOpaque(), llvm::SDValue::isUndef(), N, llvm::ISD::OR, llvm::ISD::SELECT, and llvm::SDNode::setFlags().

Referenced by combineShiftAnd1ToBitTest(), combineShiftOfShiftedLogic(), isBSwapHWordPair(), simplifyDivRem(), simplifyShuffleOfShuffle(), stripTruncAndExt(), tryFoldToZero(), and visitORCommutative().

◆ getBuildPairElt()

static SDNode* getBuildPairElt	(	SDNode *	N,
		unsigned	i
	)

static

◆ getInputChainForNode()

static SDValue getInputChainForNode ( SDNode * N )

static

Given a node, return its input chain if it has one, otherwise return a null sd operand.

Definition at line 1692 of file DAGCombiner.cpp.

References assert(), llvm::ISD::CopyFromReg, llvm::ISD::CopyToReg, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorTemplateCommon< T >::data(), llvm::numbers::e, llvm::SmallVectorImpl< T >::emplace_back(), llvm::ISD::EntryToken, llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTokenFactor(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::is_contained(), llvm::ISD::LIFETIME_END, llvm::ISD::LIFETIME_START, LLVM_FALLTHROUGH, llvm::CodeGenOpt::None, llvm::SDNode::op_values(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::SmallVectorImpl< T >::resize(), second, llvm::SmallVectorBase::size(), llvm::ISD::TokenFactor, TokenFactorInlineLimit, llvm::SDNode::use_begin(), and llvm::SDNode::use_empty().

◆ getPPCf128HiElementSelector()

static unsigned getPPCf128HiElementSelector ( const SelectionDAG & DAG )

static

Definition at line 10860 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getDataLayout(), and llvm::DataLayout::isBigEndian().

Referenced by foldBitcastedFPLogic().

◆ getShuffleMaskIndexOfOneElementFromOp0IntoOp1()

static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1 ( ArrayRef< int > Mask )

static

If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.

Otherwise, return -1.

Definition at line 18715 of file DAGCombiner.cpp.

References llvm::ArrayRef< T >::size().

Referenced by replaceShuffleOfInsert().

◆ getSubVectorSrc()

static SDValue getSubVectorSrc	(	SDValue	V,
		SDValue	Index,
		EVT	SubVT
	)

static

Definition at line 17992 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), and llvm::ISD::INSERT_SUBVECTOR.

Referenced by narrowInsertExtractVectorBinOp().

◆ isAnyConstantBuildVector()

static bool isAnyConstantBuildVector	(	SDValue	V,
		bool	NoOpaques = `false`
	)

static

Definition at line 873 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), llvm::SDValue::hasOneUse(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), and isConstantOrConstantVector().

Referenced by combineShuffleOfScalars(), and scalarizeExtractedBinop().

◆ isBigEndian()

static Optional<bool> isBigEndian	(	const SmallVector< int64_t, 4 > &	ByteOffsets,
		int64_t	FirstOffset
	)

static

Definition at line 6421 of file DAGCombiner.cpp.

References assert(), BigEndianByteAt(), LittleEndianByteAt(), llvm::None, and llvm::SmallVectorBase::size().

Referenced by collectInsertionElements(), createGPRPairNode(), PerformSTORECombine(), ReplaceCMP_SWAP_64Results(), and stripTruncAndExt().

◆ isBSwapHWordElement()

static bool isBSwapHWordElement	(	SDValue	N,
		MutableArrayRef< SDNode *>	Parts
	)

static

Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.

((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)

Definition at line 5443 of file DAGCombiner.cpp.

References llvm::ISD::AND, C, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by isBSwapHWordPair().

◆ isBSwapHWordPair()

static bool isBSwapHWordPair	(	SDValue	N,
		MutableArrayRef< SDNode *>	Parts
	)

static

◆ isConstantFPBuildVectorOrConstantFP()

static SDNode* isConstantFPBuildVectorOrConstantFP ( SDValue N )

static

Definition at line 843 of file DAGCombiner.cpp.

References llvm::SDValue::getNode(), and llvm::ISD::isBuildVectorOfConstantFPSDNodes().

Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND(), FoldIntToFPToInt(), getAsNonOpaqueConstant(), llvm::SelectionDAG::isConstantValueOfAnyType(), isContractable(), and visitFMinMax().

◆ isConstantOrConstantVector()

static bool isConstantOrConstantVector	(	SDValue	N,
		bool	NoOpaques = `false`
	)

static

Definition at line 854 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), llvm::SDValue::getScalarValueSizeInBits(), llvm::ConstantSDNode::isOpaque(), llvm::SDValue::isUndef(), and llvm::SDNode::op_values().

Referenced by combineShiftOfShiftedLogic(), foldAddSubMasked1(), foldAddSubOfSignBit(), getAsNonOpaqueConstant(), isAnyConstantBuildVector(), simplifyDivRem(), and tryFoldToZero().

◆ isContractable()

static bool isContractable ( SDNode * N )

static

Definition at line 11287 of file DAGCombiner.cpp.

References llvm::MCID::Add, llvm::AfterLegalizeDAG, Aggressive, llvm::TargetOptions::AllowFPOpFusion, assert(), B, C, llvm::TargetLoweringBase::enableAggressiveFMAFusion(), F(), llvm::ISD::FABS, llvm::ISD::FADD, llvm::FPOpFusion::Fast, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FSUB, llvm::SelectionDAGTargetInfo::generateFMAsInMachineCombiner(), llvm::SelectionDAG::getConstantFP(), llvm::SDNode::getFlags(), llvm::TargetLowering::getNegatedExpression(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetSubtargetInfo::getSelectionDAGInfo(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTarget(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNodeFlags::hasAllowContract(), llvm::SDNodeFlags::hasAllowReassociation(), llvm::SDNodeFlags::hasNoNaNs(), llvm::SDNodeFlags::hasNoSignedZeros(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), isConstantFPBuildVectorOrConstantFP(), llvm::isConstOrConstSplatFP(), llvm::ConstantFPSDNode::isExactlyValue(), llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd(), llvm::TargetLoweringBase::isFPExtFoldable(), llvm::TargetLowering::isNegatibleForFree(), llvm::ConstantFPSDNode::isNegative(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::ConstantFPSDNode::isZero(), N, llvm::TargetOptions::NoNaNsFPMath, llvm::TargetOptions::NoSignedZerosFPMath, llvm::TargetMachine::Options, llvm::MCID::Select, llvm::ISD::SELECT, std::swap(), llvm::TargetOptions::UnsafeFPMath, llvm::SDNode::use_size(), X, Y, and llvm::Z.

◆ isDivRemLibcallAvailable()

static bool isDivRemLibcallAvailable	(	SDNode *	Node,
		bool	isSigned,
		const TargetLowering &	TLI
	)

static

Return true if divmod libcall is available.

Definition at line 3488 of file DAGCombiner.cpp.

◆ isLegalToCombineMinNumMaxNum()

static bool isLegalToCombineMinNumMaxNum	(	SelectionDAG &	DAG,
		SDValue	LHS,
		SDValue	RHS,
		const TargetLowering &	TLI
	)

static

Definition at line 8119 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getTarget(), llvm::SDValue::getValueType(), llvm::EVT::isFloatingPoint(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::TargetLoweringBase::isProfitableToCombineMinNumMaxNum(), llvm::TargetOptions::NoSignedZerosFPMath, and llvm::TargetMachine::Options.

◆ isSlicingProfitable()

static bool isSlicingProfitable	(	SmallVectorImpl< LoadedSlice > &	LoadedSlices,
		const APInt &	UsedBits,
		bool	ForCodeSize
	)

static

Check the profitability of all involved LoadedSlice.

Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (

See also: LoadedSlice::Cost) is smaller than the original load (3).

Note: The order of the elements in LoadedSlices may be modified, but not the elements themselves.

FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).

Definition at line 14533 of file DAGCombiner.cpp.

References adjustCostForPairing(), llvm::AfterLegalizeDAG, areUsedBitsDense(), assert(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::EVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::isPowerOf2_32(), llvm::MemSDNode::isSimple(), llvm::ISD::LOAD, llvm::AArch64CC::LS, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorBase::size(), llvm::ISD::SRL, StressLoadSlicing, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

◆ isTruncateOf()

static bool isTruncateOf	(	SelectionDAG &	DAG,
		SDValue	N,
		SDValue &	Op,
		KnownBits &	Known
	)

static

Definition at line 9645 of file DAGCombiner.cpp.

◆ LittleEndianByteAt()

static unsigned LittleEndianByteAt	(	unsigned	BW,
		unsigned	i
	)

static

Definition at line 6410 of file DAGCombiner.cpp.

Referenced by isBigEndian(), and stripTruncAndExt().

◆ matchRotateHalf()

static bool matchRotateHalf	(	SelectionDAG &	DAG,
		SDValue	Op,
		SDValue &	Shift,
		SDValue &	Mask
	)

static

Match "(X shl/srl V1) & V2" where V2 may not be present.

Definition at line 5855 of file DAGCombiner.cpp.

References llvm::SDValue::getOpcode(), llvm::ISD::SHL, llvm::ISD::SRL, and stripConstantMask().

Referenced by matchRotateSub().

◆ matchRotateSub()

static bool matchRotateSub	(	SDValue	Pos,
		SDValue	Neg,
		unsigned	EltSize,
		SelectionDAG &	DAG
	)

static

Definition at line 6004 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::tgtok::Bits, llvm::SelectionDAG::computeKnownBits(), llvm::countTrailingOnes(), extractShiftForRotate(), llvm::SelectionDAG::getAllOnesConstant(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getLoBits(), getMemory(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::isPowerOf2_64(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SPII::Load, llvm::Log2_64(), llvm::ISD::matchBinaryPredicate(), matchRotateHalf(), llvm::operator==(), llvm::ISD::OR, Other, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::KnownBits::Zero, and llvm::ISD::ZERO_EXTEND.

◆ narrowExtractedVectorBinOp()

static SDValue narrowExtractedVectorBinOp	(	SDNode *	Extract,
		SelectionDAG &	DAG
	)

static

If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.

Definition at line 18043 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), llvm::ISD::CONCAT_VECTORS, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::TargetLoweringBase::isBinOp(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::EVT::isVector(), narrowInsertExtractVectorBinOp(), llvm::ISD::OR, llvm::peekThroughBitcasts(), and llvm::ISD::XOR.

Referenced by narrowExtractedVectorLoad().

◆ narrowExtractedVectorLoad()

static SDValue narrowExtractedVectorLoad	(	SDNode *	Extract,
		SelectionDAG &	DAG
	)

static

If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) –> (load narrow vector)

Definition at line 18162 of file DAGCombiner.cpp.

◆ narrowInsertExtractVectorBinOp()

static SDValue narrowInsertExtractVectorBinOp	(	SDNode *	Extract,
		SelectionDAG &	DAG
	)

static

Definition at line 18007 of file DAGCombiner.cpp.

References llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getSubVectorSrc(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::isBinOp(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().

Referenced by narrowExtractedVectorBinOp().

◆ numVectorEltsOrZero()

static int numVectorEltsOrZero ( EVT T )

inlinestatic

Definition at line 13846 of file DAGCombiner.cpp.

◆ partitionShuffleOfConcats()

static SDValue partitionShuffleOfConcats	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

◆ reduceBuildVecToShuffleWithZero()

static SDValue reduceBuildVecToShuffleWithZero	(	SDNode *	BV,
		SelectionDAG &	DAG
	)

static

Definition at line 17255 of file DAGCombiner.cpp.

◆ replaceShuffleOfInsert()

static SDValue replaceShuffleOfInsert	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG
	)

static

If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle.

Definition at line 18739 of file DAGCombiner.cpp.

References assert(), llvm::ArrayRef< T >::begin(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::dyn_cast(), llvm::ArrayRef< T >::end(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), getShuffleMaskIndexOfOneElementFromOp0IntoOp1(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ArrayRef< T >::size(), and std::swap().

Referenced by simplifyShuffleOfShuffle().

◆ scalarizeBinOpOfSplats()

static SDValue scalarizeBinOpOfSplats	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat.

Definition at line 19507 of file DAGCombiner.cpp.

◆ scalarizeExtractedBinop()

static SDValue scalarizeExtractedBinop	(	SDNode *	ExtElt,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.

Definition at line 16734 of file DAGCombiner.cpp.

◆ ShrinkLoadReplaceStoreWithStore()

static SDValue ShrinkLoadReplaceStoreWithStore	(	const std::pair< unsigned, unsigned > &	MaskInfo,
		SDValue	IVal,
		StoreSDNode *	St,
		DAGCombiner *	DC
	)

static

Check to see if IVal is something that provides a value as specified by MaskInfo.

If so, replace the specified store with a narrower store of truncated IVal.

Definition at line 14743 of file DAGCombiner.cpp.

◆ simplifyDivRem()

static SDValue simplifyDivRem	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 3577 of file DAGCombiner.cpp.

◆ simplifyShuffleOfShuffle()

static SDValue simplifyShuffleOfShuffle ( ShuffleVectorSDNode * Shuf )

static

If we have a unary shuffle of a shuffle, see if it can be folded away completely.

This has the potential to lose undef knowledge because the first shuffle may not have an undef mask element where the second one does. So only call this after doing simplifications based on demanded elements.

Definition at line 18793 of file DAGCombiner.cpp.

◆ STATISTIC() [1/7]

STATISTIC	(	NodesCombined	,
		"Number of dag nodes combined"
	)

◆ STATISTIC() [2/7]

STATISTIC	(	PreIndexedNodes	,
		"Number of pre-indexed nodes created"
	)

◆ STATISTIC() [3/7]

STATISTIC	(	PostIndexedNodes	,
		"Number of post-indexed nodes created"
	)

◆ STATISTIC() [4/7]

STATISTIC	(	OpsNarrowed	,
		"Number of load/op/store narrowed"
	)

◆ STATISTIC() [5/7]

STATISTIC	(	LdStFP2Int	,
		"Number of fp load/store pairs transformed to int"
	)

◆ STATISTIC() [6/7]

STATISTIC	(	SlicedLoads	,
		"Number of load sliced"
	)

◆ STATISTIC() [7/7]

STATISTIC	(	NumFPLogicOpsConv	,
		"Number of logic ops converted to fp ops"
	)

◆ stripConstantMask()

static SDValue stripConstantMask	(	SelectionDAG &	DAG,
		SDValue	Op,
		SDValue &	Mask
	)

static

Definition at line 5845 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt().

Referenced by extractShiftForRotate(), and matchRotateHalf().

◆ stripTruncAndExt()

static SDValue stripTruncAndExt ( SDValue Value )

static

Definition at line 6442 of file DAGCombiner.cpp.

◆ tryFoldToZero()

static SDValue tryFoldToZero	(	const SDLoc &	DL,
		const TargetLowering &	TLI,
		EVT	VT,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

Definition at line 2844 of file DAGCombiner.cpp.

Referenced by simplifyDivRem(), and stripTruncAndExt().

◆ tryToFoldExtendOfConstant()

static SDValue tryToFoldExtendOfConstant	(	SDNode *	N,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		bool	LegalTypes
	)

static

Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.

This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). Vector extends are not folded if operations are legal; this is to avoid introducing illegal build_vector dag nodes.

Definition at line 8886 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, assert(), C, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isZExtFree(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SELECT, llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::APInt::zext().

Referenced by foldExtendedSignBitTest(), and isTruncateOf().

◆ tryToFoldExtOfExtload()

static SDValue tryToFoldExtOfExtload	(	SelectionDAG &	DAG,
		DAGCombiner &	Combiner,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType
	)

static

◆ tryToFoldExtOfLoad()

static SDValue tryToFoldExtOfLoad	(	SelectionDAG &	DAG,
		DAGCombiner &	Combiner,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType,
		ISD::NodeType	ExtOpc
	)

static

◆ tryToFoldExtOfMaskedLoad()

static SDValue tryToFoldExtOfMaskedLoad	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		EVT	VT,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType,
		ISD::NodeType	ExtOpc
	)

static

◆ visitFMinMax()

static SDValue visitFMinMax	(	SelectionDAG &	DAG,
		SDNode *	N,
		APFloat(*)(const APFloat &, const APFloat &)	Op
	)

static

Definition at line 13184 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ISD::Constant, llvm::object::Equal, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FNEG, llvm::CondCodeSDNode::get(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::HandleSDNode::getValue(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), isConstantFPBuildVectorOrConstantFP(), llvm::isConstOrConstSplatFP(), llvm::TargetLoweringBase::isFAbsFree(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::APInt::isPowerOf2(), llvm::EVT::isVector(), llvm::APInt::logBase2(), llvm::maximum(), llvm::maxnum(), llvm::minimum(), llvm::minnum(), llvm::MVT::Other, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.

◆ visitORCommutative()

static SDValue visitORCommutative	(	SelectionDAG &	DAG,
		SDValue	N0,
		SDValue	N1,
		SDNode *	N
	)

static

OR combines for which the commuted variant will be tried as well.

Definition at line 5656 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::TargetLowering::buildLegalVectorShuffle(), llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getAllOnesConstant(), llvm::ConstantSDNode::getAPIntValue(), getAsNonOpaqueConstant(), llvm::SDNode::getFlags(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::hasOneUse(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::APInt::intersects(), llvm::isAllOnesConstant(), llvm::isBitwiseNot(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::isNullConstant(), llvm::ConstantSDNode::isOpaque(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::matchBinaryPredicate(), llvm::ISD::OR, and llvm::AArch64_AM::ROR.

◆ zeroExtendToMatch()

static void zeroExtendToMatch	(	APInt &	LHS,
		APInt &	RHS,
		unsigned	Offset = `0`
	)

static

Definition at line 796 of file DAGCombiner.cpp.

References llvm::tgtok::Bits, llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::isConstFalseVal(), llvm::TargetLowering::isConstTrueVal(), llvm::max(), llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLoweringBase::UndefinedBooleanContent, and llvm::APInt::zextOrSelf().

Referenced by combineShiftOfShiftedLogic(), and extractShiftForRotate().

Variable Documentation

◆ CombinerAAOnlyFunc

cl::opt<std::string> CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function"))

static

◆ CombinerGlobalAA

cl::opt<bool> CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis"))

static

◆ EnableStoreMerging

cl::opt<bool> EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store"))

static

Referenced by ShrinkLoadReplaceStoreWithStore().

◆ MaySplitLoadIndex

cl::opt<bool> MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads"))

static

Referenced by numVectorEltsOrZero().

◆ StoreMergeDependenceLimit

cl::opt<unsigned> StoreMergeDependenceLimit("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check"))

static

Referenced by ShrinkLoadReplaceStoreWithStore().

◆ StressLoadSlicing

cl::opt<bool> StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false))

static

Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards.

Referenced by isSlicingProfitable().

◆ TokenFactorInlineLimit

cl::opt<unsigned> TokenFactorInlineLimit("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors"))

static

Referenced by getInputChainForNode().

◆ UseTBAA

cl::opt<bool> UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA"))

static

Macros

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ adjustCostForPairing()

◆ areSlicesNextToEachOther()

◆ areUsedBitsDense()

◆ BigEndianByteAt()

◆ calculateByteProvider()

◆ CanCombineFCOPYSIGN_EXTEND_ROUND()

◆ canFoldInAddressingMode()

◆ CheckForMaskedLoad()

◆ combineADDCARRYDiamond()

◆ combineConcatVectorOfExtracts()

◆ combineConcatVectorOfScalars()

◆ combineMinNumMaxNum()

◆ combineShiftAnd1ToBitTest()

◆ combineShiftOfShiftedLogic()

◆ combineShuffleOfScalars()

◆ combineShuffleOfSplatVal()

◆ combineShuffleToVectorExtend()

◆ combineTruncationShuffle()

◆ ConvertSelectToConcatVector()

◆ ExtendUsesToFormExtLoad()

◆ extractBooleanFlip()

◆ extractShiftForRotate()

◆ flipBoolean()

◆ foldAddSubBoolOfMaskedVal()

◆ foldAddSubMasked1()

◆ foldAddSubOfSignBit()

◆ foldBitcastedFPLogic()

◆ foldExtendedSignBitTest()

◆ foldFPToIntToFP()

◆ FoldIntToFPToInt()

◆ foldSelectOfConstantsUsingSra()

◆ foldShuffleOfConcatUndefs()

◆ getAsCarry()

◆ getAsNonOpaqueConstant()

◆ getBuildPairElt()

◆ getInputChainForNode()

◆ getPPCf128HiElementSelector()

◆ getShuffleMaskIndexOfOneElementFromOp0IntoOp1()

◆ getSubVectorSrc()

◆ isAnyConstantBuildVector()

◆ isBigEndian()

◆ isBSwapHWordElement()

◆ isBSwapHWordPair()

◆ isConstantFPBuildVectorOrConstantFP()

◆ isConstantOrConstantVector()

◆ isContractable()

◆ isDivRemLibcallAvailable()

◆ isLegalToCombineMinNumMaxNum()

◆ isSlicingProfitable()

◆ isTruncateOf()

◆ LittleEndianByteAt()

◆ matchRotateHalf()

◆ matchRotateSub()

◆ narrowExtractedVectorBinOp()

◆ narrowExtractedVectorLoad()

◆ narrowInsertExtractVectorBinOp()

◆ numVectorEltsOrZero()

◆ partitionShuffleOfConcats()

◆ reduceBuildVecToShuffleWithZero()

◆ replaceShuffleOfInsert()

◆ scalarizeBinOpOfSplats()

◆ scalarizeExtractedBinop()

◆ ShrinkLoadReplaceStoreWithStore()

◆ simplifyDivRem()

◆ simplifyShuffleOfShuffle()

◆ STATISTIC() [1/7]

◆ STATISTIC() [2/7]

◆ STATISTIC() [3/7]

◆ STATISTIC() [4/7]

◆ STATISTIC() [5/7]

◆ STATISTIC() [6/7]

◆ STATISTIC() [7/7]

◆ stripConstantMask()

◆ stripTruncAndExt()