LLVM
9.0.0svn
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#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IntervalMap.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Metadata.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <functional>
#include <iterator>
#include <string>
#include <tuple>
#include <utility>
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "dagcombine" |
Functions | |
STATISTIC (NodesCombined, "Number of dag nodes combined") | |
STATISTIC (PreIndexedNodes, "Number of pre-indexed nodes created") | |
STATISTIC (PostIndexedNodes, "Number of post-indexed nodes created") | |
STATISTIC (OpsNarrowed, "Number of load/op/store narrowed") | |
STATISTIC (LdStFP2Int, "Number of fp load/store pairs transformed to int") | |
STATISTIC (SlicedLoads, "Number of load sliced") | |
STATISTIC (NumFPLogicOpsConv, "Number of logic ops converted to fp ops") | |
static char | isNegatibleForFree (SDValue Op, bool LegalOperations, const TargetLowering &TLI, const TargetOptions *Options, unsigned Depth=0) |
Return 1 if we can compute the negated form of the specified expression for the same cost as the expression itself, or 2 if we can compute the negated form more cheaply than the expression itself. More... | |
static SDValue | GetNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOperations, unsigned Depth=0) |
If isNegatibleForFree returns true, return the newly negated expression. More... | |
static void | zeroExtendToMatch (APInt &LHS, APInt &RHS, unsigned Offset=0) |
static SDNode * | isConstantFPBuildVectorOrConstantFP (SDValue N) |
static bool | isConstantOrConstantVector (SDValue N, bool NoOpaques=false) |
static bool | isAnyConstantBuildVector (SDValue V, bool NoOpaques=false) |
static SDValue | getInputChainForNode (SDNode *N) |
Given a node, return its input chain if it has one, otherwise return a null sd operand. More... | |
static ConstantSDNode * | getAsNonOpaqueConstant (SDValue N) |
If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr. More... | |
static SDValue | foldAddSubBoolOfMaskedVal (SDNode *N, SelectionDAG &DAG) |
static SDValue | foldAddSubOfSignBit (SDNode *N, SelectionDAG &DAG) |
Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant. More... | |
static SDValue | getAsCarry (const TargetLowering &TLI, SDValue V) |
static SDValue | foldAddSubMasked1 (bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL) |
Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1. More... | |
static SDValue | flipBoolean (SDValue V, const SDLoc &DL, EVT VT, SelectionDAG &DAG, const TargetLowering &TLI) |
static bool | isBooleanFlip (SDValue V, EVT VT, const TargetLowering &TLI) |
static SDValue | tryFoldToZero (const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations) |
static bool | isDivRemLibcallAvailable (SDNode *Node, bool isSigned, const TargetLowering &TLI) |
Return true if divmod libcall is available. More... | |
static SDValue | simplifyDivRem (SDNode *N, SelectionDAG &DAG) |
static bool | isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode *> Parts) |
Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap. More... | |
static SDValue | stripConstantMask (SelectionDAG &DAG, SDValue Op, SDValue &Mask) |
static bool | matchRotateHalf (SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask) |
Match "(X shl/srl V1) & V2" where V2 may not be present. More... | |
static SDValue | extractShiftForRotate (SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL) |
Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv. More... | |
static bool | matchRotateSub (SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG) |
static const Optional< ByteProvider > | calculateByteProvider (SDValue Op, unsigned Index, unsigned Depth, bool Root=false) |
Recursively traverses the expression calculating the origin of the requested byte of the given value. More... | |
static bool | isLegalToCombineMinNumMaxNum (SelectionDAG &DAG, SDValue LHS, SDValue RHS, const TargetLowering &TLI) |
static SDValue | combineMinNumMaxNum (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) |
Generate Min/Max node. More... | |
static std::pair< SDValue, SDValue > | SplitVSETCC (const SDNode *N, SelectionDAG &DAG) |
static SDValue | ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG) |
static SDValue | tryToFoldExtendOfConstant (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes) |
Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants. More... | |
static bool | ExtendUsesToFormExtLoad (EVT VT, SDNode *N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode *> &ExtendNodes, const TargetLowering &TLI) |
static SDValue | tryToFoldExtOfExtload (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType) |
static SDValue | tryToFoldExtOfLoad (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) |
static SDValue | foldExtendedSignBitTest (SDNode *N, SelectionDAG &DAG, bool LegalOperations) |
static bool | isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known) |
static SDNode * | getBuildPairElt (SDNode *N, unsigned i) |
static unsigned | getPPCf128HiElementSelector (const SelectionDAG &DAG) |
static SDValue | foldBitcastedFPLogic (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) |
static bool | isContractable (SDNode *N) |
static bool | CanCombineFCOPYSIGN_EXTEND_ROUND (SDNode *N) |
copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) More... | |
static SDValue | foldFPToIntToFP (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) |
static SDValue | FoldIntToFPToInt (SDNode *N, SelectionDAG &DAG) |
static SDValue | visitFMinMax (SelectionDAG &DAG, SDNode *N, APFloat(*Op)(const APFloat &, const APFloat &)) |
static bool | canFoldInAddressingMode (SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI) |
Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode. More... | |
static int | numVectorEltsOrZero (EVT T) |
static bool | areUsedBitsDense (const APInt &UsedBits) |
Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0. More... | |
static bool | areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second) |
Check whether or not First and Second are next to each other in memory. More... | |
static void | adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost) |
Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices. More... | |
static bool | isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize) |
Check the profitability of all involved LoadedSlice. More... | |
static std::pair< unsigned, unsigned > | CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain) |
Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out. More... | |
static SDNode * | ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode *St, DAGCombiner *DC) |
Check to see if IVal is something that provides a value as specified by MaskInfo. More... | |
static SDValue | scalarizeExtractedBinop (SDNode *ExtElt, SelectionDAG &DAG, bool LegalOperations) |
Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector. More... | |
static SDValue | reduceBuildVecToShuffleWithZero (SDNode *BV, SelectionDAG &DAG) |
static SDValue | combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG) |
static SDValue | combineConcatVectorOfExtracts (SDNode *N, SelectionDAG &DAG) |
static SDValue | narrowExtractedVectorBinOp (SDNode *Extract, SelectionDAG &DAG) |
If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction. More... | |
static SDValue | narrowExtractedVectorLoad (SDNode *Extract, SelectionDAG &DAG) |
If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) –> (load narrow vector) More... | |
static SDValue | partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG) |
static SDValue | combineShuffleOfScalars (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI) |
static SDValue | combineShuffleToVectorExtend (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations) |
static SDValue | combineTruncationShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG) |
static SDValue | combineShuffleOfSplat (ArrayRef< int > UserMask, ShuffleVectorSDNode *Splat, SelectionDAG &DAG) |
static int | getShuffleMaskIndexOfOneElementFromOp0IntoOp1 (ArrayRef< int > Mask) |
If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand. More... | |
static SDValue | replaceShuffleOfInsert (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) |
If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle. More... | |
Variables | |
static cl::opt< bool > | CombinerGlobalAA ("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis")) |
static cl::opt< bool > | UseTBAA ("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA")) |
static cl::opt< std::string > | CombinerAAOnlyFunc ("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function")) |
static cl::opt< bool > | StressLoadSlicing ("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false)) |
Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards. More... | |
static cl::opt< bool > | MaySplitLoadIndex ("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads")) |
#define DEBUG_TYPE "dagcombine" |
Definition at line 78 of file DAGCombiner.cpp.
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Adjust the GlobalLSCost
according to the target paring capabilities and the layout of the slices.
GlobalLSCost
should account for at least as many loads as there is in the slices in LoadedSlices
. Definition at line 13724 of file DAGCombiner.cpp.
References areSlicesNextToEachOther(), assert(), llvm::SmallVectorBase::size(), and llvm::sort().
Referenced by isSlicingProfitable().
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Check whether or not First
and Second
are next to each other in memory.
This means that there is no hole between the bits loaded by First
and the bits loaded by Second
.
Definition at line 13709 of file DAGCombiner.cpp.
References areUsedBitsDense(), and assert().
Referenced by adjustCostForPairing().
Check that all bits set in UsedBits
form a dense region, i.e., UsedBits
looks like 0..0 1..1 0..0.
Definition at line 13692 of file DAGCombiner.cpp.
References llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnesValue(), llvm::APInt::lshr(), and llvm::APInt::trunc().
Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().
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Recursively traverses the expression calculating the origin of the requested byte of the given value.
Returns None if the provider can't be calculated.
For all the values except the root of the expression verifies that the value has exactly one use and if it's not true return None. This way if the origin of the byte is returned it's guaranteed that the values which contribute to the byte are not used outside of this expression.
Because the parts of the expression are not allowed to have more than one use this function iterates over trees, not DAGs. So it never visits the same node more than once.
Definition at line 5860 of file DAGCombiner.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ARMBuildAttrs::Allowed, llvm::TargetLoweringBase::allowsMemoryAccess(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITREVERSE, llvm::ISD::BRCOND, llvm::ISD::BSWAP, C, llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::ISD::CopyFromReg, llvm::APInt::countTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::dyn_cast(), llvm::SmallPtrSetImplBase::empty(), llvm::BaseIndexOffset::equalBaseIndex(), llvm::CallingConv::Fast, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::ISD::FSHL, llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getAllOnesConstant(), llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), getAsNonOpaqueConstant(), llvm::LoadSDNode::getBasePtr(), llvm::TargetLoweringBase::getBooleanContents(), llvm::APInt::getBoolValue(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getFlags(), llvm::APInt::getHighBitsSet(), llvm::EVT::getIntegerVT(), llvm::ConstantSDNode::getLimitedValue(), llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), getMemory(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::LoadSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), llvm::TargetLoweringBase::hasAndNot(), llvm::SDNodeFlags::hasExact(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), INT64_MAX, llvm::isAllOnesConstant(), llvm::isAllOnesOrAllOnesSplat(), llvm::DataLayout::isBigEndian(), llvm::isBitwiseNot(), llvm::ISD::isBuildVectorAllZeros(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::BuildVectorSDNode::isConstant(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isConstantOrConstantVector(), llvm::isConstOrConstSplat(), llvm::TargetLowering::isConstTrueVal(), llvm::TargetLowering::isDesirableToCommuteWithShift(), llvm::LSBaseSDNode::isIndexed(), llvm::EVT::isInteger(), llvm::SelectionDAG::isKnownNeverZero(), llvm::APInt::isNegative(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::isOneConstant(), llvm::ConstantSDNode::isOpaque(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::APInt::isPowerOf2(), llvm::isPowerOf2_32(), llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isTruncateFree(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm_unreachable, llvm::ISD::LOAD, llvm::Log2_32(), llvm::APInt::lshr(), llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::BaseIndexOffset::match(), llvm::ISD::matchBinaryPredicate(), llvm::ISD::MUL, llvm::None, llvm::KnownBits::One, llvm::ISD::OR, Other, P, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::APInt::shl(), llvm::TargetLowering::shouldFoldShiftPairToMask(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::SelectionDAG::SignBitIsZero(), llvm::SelectionDAG::simplifyShift(), llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, tryFoldToZero(), llvm::APInt::uge(), llvm::SDNode::use_begin(), X, llvm::ISD::XOR, Y, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, zeroExtendToMatch(), llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::ISD::ZEXTLOAD.
copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y)
Definition at line 11881 of file DAGCombiner.cpp.
References llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FCBRT, llvm::ISD::FCOPYSIGN, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FPOW, llvm::ISD::FSQRT, llvm::SDNode::getFlags(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getLibInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLibraryInfo::has(), llvm::SDNodeFlags::hasApproximateFuncs(), llvm::SDNodeFlags::hasNoInfs(), llvm::SDNodeFlags::hasNoNaNs(), llvm::SDNodeFlags::hasNoSignedZeros(), isConstantFPBuildVectorOrConstantFP(), llvm::isConstOrConstSplatFP(), llvm::APFloat::isExactlyValue(), llvm::APFloat::isNegative(), llvm::TargetLoweringBase::isOperationExpand(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), and llvm::Function::optForSize().
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Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.
Definition at line 12683 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::AfterLegalizeDAG, assert(), llvm::SmallVectorImpl< T >::clear(), llvm::dbgs(), llvm::SDNode::dump(), llvm::dyn_cast(), llvm::LSBaseSDNode::getAddressingMode(), llvm::SelectionDAG::getConstant(), llvm::ConstantSDNode::getConstantIntValue(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLowering::getPostIndexedAddressParts(), llvm::TargetLowering::getPreIndexedAddressParts(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getTypeForEVT(), llvm::SDUse::getUser(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), llvm::TargetLoweringBase::isLegalAddressingMode(), isLoad(), llvm::isNullConstant(), llvm::SDNode::isPredecessorOf(), llvm::ARM_MB::LD, LLVM_DEBUG, N, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorBase::size(), llvm::ARM_MB::ST, llvm::ISD::SUB, std::swap(), llvm::ISD::TargetConstant, llvm::ISD::UNINDEXED, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::Value::uses(), and llvm::SDNode::uses().
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Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.
If so, return the byte size being masked out and the shift amount.
Definition at line 13930 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::countLeadingZeros(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), llvm::LoadSDNode::getBasePtr(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::isNormalLoad(), llvm::ARM_MB::LD, llvm::SDNode::op_values(), and llvm::ISD::TokenFactor.
Referenced by ShrinkLoadReplaceStoreWithStore().
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Definition at line 16824 of file DAGCombiner.cpp.
References llvm::AfterLegalizeVectorOps, llvm::all_of(), llvm::ISD::allOperandsUndef(), llvm::SmallVectorImpl< T >::append(), assert(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_VECTOR, combineConcatVectorOfScalars(), llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::tgtok::In, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::SDNode::ops(), llvm::peekThroughBitcasts(), llvm::peekThroughOneUseBitcasts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::NVPTX::PTXLdStInstCode::Scalar, llvm::ISD::SCALAR_TO_VECTOR, llvm::SmallVectorBase::size(), llvm::ISD::TRUNCATE, and llvm::ISD::UNDEF.
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Definition at line 16759 of file DAGCombiner.cpp.
References llvm::SmallVectorTemplateCommon< T >::back(), llvm::ISD::BITCAST, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorVT(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::SDNode::ops(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::UNDEF.
Referenced by combineConcatVectorOfExtracts().
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Generate Min/Max node.
Definition at line 7335 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::EVT::bitsEq(), C, llvm::TargetLoweringBase::convertSelectOfConstantsToMath(), llvm::dyn_cast(), llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i1, llvm::isAllOnesConstant(), llvm::isBitwiseNot(), llvm::EVT::isInteger(), isLegalToCombineMinNumMaxNum(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::TargetLoweringBase::shouldNormalizeToSelectSequence(), llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::simplifySelect(), llvm::ISD::UADDO, llvm::SDValue::use_empty(), llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by ConvertSelectToConcatVector().
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Definition at line 17409 of file DAGCombiner.cpp.
References assert(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasOneUse(), llvm::SmallSet< T, N, C >::insert(), isAnyConstantBuildVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), llvm::TargetLoweringBase::isZExtFree(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::SCALAR_TO_VECTOR.
Referenced by replaceShuffleOfInsert().
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Definition at line 17608 of file DAGCombiner.cpp.
References assert(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ArrayRef< T >::size().
Referenced by replaceShuffleOfInsert().
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Definition at line 17490 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::BitmaskEnumDetail::Mask().
Referenced by replaceShuffleOfInsert().
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Definition at line 17547 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::BitmaskEnumDetail::Mask(), llvm::peekThroughBitcasts(), llvm::ISD::SIGN_EXTEND_VECTOR_INREG, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by replaceShuffleOfInsert().
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Definition at line 7670 of file DAGCombiner.cpp.
References llvm::ISD::ABS, llvm::MCID::Add, llvm::ISD::ADD, llvm::AfterLegalizeTypes, assert(), llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::EVT::changeVectorElementTypeToInteger(), combineMinNumMaxNum(), llvm::ISD::CONCAT_VECTORS, llvm::TargetLoweringBase::convertSelectOfConstantsToMath(), llvm::Data, llvm::dyn_cast(), llvm::MemSDNode::getAAInfo(), llvm::MaskedLoadSDNode::getBasePtr(), llvm::MaskedStoreSDNode::getBasePtr(), llvm::MaskedGatherScatterSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MaskedGatherScatterSDNode::getIndex(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::MaskedLoadSDNode::getMask(), llvm::MaskedStoreSDNode::getMask(), llvm::MaskedGatherScatterSDNode::getMask(), llvm::SelectionDAG::getMaskedGather(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMaskedScatter(), llvm::SelectionDAG::getMaskedStore(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlignment(), llvm::MaskedLoadSDNode::getPassThru(), llvm::MaskedGatherSDNode::getPassThru(), llvm::MemSDNode::getPointerInfo(), llvm::MemSDNode::getRanges(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::MaskedGatherScatterSDNode::getScale(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::EVT::getStoreSize(), llvm::TargetLoweringBase::getTypeAction(), llvm::SDValue::getValue(), llvm::MaskedStoreSDNode::getValue(), llvm::MaskedScatterSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MipsISD::Hi, llvm::TargetLowering::IncrementMemoryAddress(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MaskedStoreSDNode::isCompressingStore(), llvm::MaskedLoadSDNode::isExpandingLoad(), isLegalToCombineMinNumMaxNum(), llvm::TargetLoweringBase::isLoadExtLegalOrCustom(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::ConstantSDNode::isNullValue(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ISD::isSignedIntSetCC(), llvm::MaskedStoreSDNode::isTruncatingStore(), llvm::SDValue::isUndef(), llvm::SDNode::isUndef(), llvm::MipsISD::Lo, llvm::ISD::LOAD, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, N, llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::simplifySelect(), llvm::SelectionDAG::SplitVector(), SplitVSETCC(), llvm::ISD::SRA, llvm::ISD::SUB, llvm::ISD::TokenFactor, llvm::TargetLoweringBase::TypeSplitVector, llvm::SDNode::use_begin(), llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.
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Definition at line 8330 of file DAGCombiner.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), B, llvm::ISD::CONCAT_VECTORS, llvm::ISD::Constant, llvm::ISD::CopyToReg, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SDValue::getResNo(), llvm::SDUse::getResNo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::EVT::getStoreSize(), llvm::SDUse::getUser(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDValue::hasOneUse(), hasOneUse(), llvm::LSBaseSDNode::isIndexed(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::TargetLoweringBase::isLoadExtLegalOrCustom(), llvm::ISD::isNON_EXTLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isPow2VectorType(), llvm::ISD::isSignedIntSetCC(), llvm::TargetLoweringBase::isTruncateFree(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isVectorLoadExtDesirable(), llvm::MemSDNode::isVolatile(), llvm::TargetLoweringBase::isZExtFree(), llvm::ISD::LOAD, llvm::MinAlign(), llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::ISD::SRL, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.
Referenced by foldExtendedSignBitTest(), isTruncateOf(), and tryToFoldExtOfLoad().
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Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.
This is meant to handle cases where InstCombine merged some outside op with one of the shifts from the rotate pattern.
SDValue
if the needed shift couldn't be extracted. Otherwise, returns an expansion of ExtractFrom
based on the following patterns:(or (mul v c0) (shrl (mul v c1) c2)): expands (mul v c0) -> (shl (mul v c1) c3)
(or (udiv v c0) (shl (udiv v c1) c2)): expands (udiv v c0) -> (shrl (udiv v c1) c3)
(or (shl v c0) (shrl (shl v c1) c2)): expands (shl v c0) -> (shl (shl v c1) c3)
(or (shrl v c0) (shl (shrl v c1) c2)): expands (shrl v c0) -> (shrl (shrl v c1) c3)
Such that in all cases, c3+c2==bitwidth(op v c1).
Definition at line 5439 of file DAGCombiner.cpp.
References assert(), llvm::ISD::DELETED_NODE, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::isConstOrConstSplat(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::ISD::SRL, stripConstantMask(), llvm::ISD::UDIV, llvm::APInt::udivrem(), llvm::APInt::ugt(), zeroExtendToMatch(), and llvm::APInt::zextOrTrunc().
Referenced by matchRotateSub().
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Definition at line 2381 of file DAGCombiner.cpp.
References llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::XOR, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by isBooleanFlip().
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Definition at line 1945 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, assert(), C, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::i1, llvm::isNullConstant(), llvm::isOneConstant(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SUB, llvm::Z, and llvm::ISD::ZERO_EXTEND.
Referenced by foldAddSubOfSignBit(), and tryFoldToZero().
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Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.
If so, invert the opcode and bypass the mask operation.
Definition at line 2286 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::AND, llvm::ISD::CARRY_FALSE, llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAG::computeOverflowKind(), llvm::dyn_cast(), getAsCarry(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::VTSDNode::getVT(), llvm::SelectionDAG::getVTList(), llvm::SDNode::getVTList(), llvm::MVT::Glue, llvm::SDNode::hasAnyUseOfValue(), llvm::MVT::i1, llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::isOneOrOneSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SelectionDAG::OFK_Never, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUB, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by tryFoldToZero().
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Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.
Definition at line 1986 of file DAGCombiner.cpp.
References llvm::ISD::ADD, assert(), C, llvm::SelectionDAG::computeOverflowKind(), foldAddSubBoolOfMaskedVal(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getAllOnesConstant(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::isBitwiseNot(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isConstantOrConstantVector(), llvm::isConstOrConstSplat(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::isOneOrOneSplat(), llvm::TargetLoweringBase::isOperationLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::ISD::matchBinaryPredicate(), llvm::SelectionDAG::OFK_Never, llvm::ISD::OR, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::UADDSAT, llvm::ISD::UMAX, llvm::ISD::USUBSAT, X, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by tryFoldToZero().
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Definition at line 10147 of file DAGCombiner.cpp.
References llvm::AfterLegalizeDAG, llvm::TargetLoweringBase::allowsMemoryAccess(), llvm::ISD::AND, llvm::SmallVectorImpl< T >::append(), assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::ISD::BITCAST, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C, llvm::ShuffleVectorSDNode::commuteMask(), llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::FABS, llvm::CallingConv::Fast, llvm::ISD::FCOPYSIGN, llvm::ISD::FNEG, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlignment(), llvm::ConstantSDNode::getAPIntValue(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::ShuffleVectorSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), getPPCf128HiElementSelector(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSignMask(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::hasBigEndianPartOrdering(), llvm::TargetLoweringBase::hasBitPreservingFPLogic(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MipsISD::Hi, llvm::MVT::i64, llvm::DataLayout::isBigEndian(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), isConstant(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isFAbsFree(), llvm::EVT::isFloatingPoint(), llvm::TargetLoweringBase::isFNegFree(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), isVolatile(), llvm::SPII::Load, llvm::ISD::LOAD, llvm::APInt::lshrInPlace(), N, llvm::SDNode::op_values(), llvm::ISD::OR, llvm::MVT::ppcf128, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::reverse(), llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::ISD::SRL, std::swap(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::VECTOR_SHUFFLE, X, llvm::ISD::XOR, llvm::APInt::zext(), and llvm::APInt::zextOrTrunc().
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Definition at line 8703 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::ISD::Constant, llvm::TargetLoweringBase::convertSelectOfConstantsToMath(), ExtendUsesToFormExtLoad(), llvm::SelectionDAG::getAllOnesConstant(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBoolConstant(), llvm::TargetLoweringBase::getBooleanContents(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i1, llvm::isAllOnesConstant(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::TargetLoweringBase::isOperationLegal(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::ISD::OR, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::APInt::sext(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::SelectionDAG::SignBitIsZero(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), X, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::ISD::ZEXTLOAD.
Referenced by isTruncateOf().
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Definition at line 12019 of file DAGCombiner.cpp.
References llvm::ISD::ConstantFP, llvm::StringRef::equals(), F(), llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, llvm::SelectionDAG::getConstantFP(), llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTarget(), llvm::Attribute::getValueAsString(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i1, llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::TargetOptions::NoSignedZerosFPMath, llvm::TargetMachine::Options, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::SelectionDAG::SignBitIsZero(), llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.
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Definition at line 12154 of file DAGCombiner.cpp.
References llvm::AfterLegalizeDAG, llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::APFloat::changeSign(), llvm::ISD::ConstantFP, llvm::dyn_cast(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::ISD::EXTLOAD, llvm::MVT::f16, llvm::MVT::f80, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FFLOOR, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRINT, llvm::ISD::FTRUNC, llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::ConstantFPSDNode::getConstantFPValue(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), GetNegatedExpression(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getOperationAction(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::APInt::getSignMask(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::tgtok::In, isConstantFPBuildVectorOrConstantFP(), llvm::TargetLoweringBase::isFNegFree(), llvm::TargetLoweringBase::isFPImmLegal(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isLoadExtLegal(), isNegatibleForFree(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::EVT::isVector(), llvm::TargetLoweringBase::Legal, llvm::TargetMachine::Options, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::TargetOptions::UnsafeFPMath, llvm::SDNode::use_begin(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
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Definition at line 2245 of file DAGCombiner.cpp.
References llvm::ISD::ADDCARRY, llvm::ISD::AND, llvm::TargetLoweringBase::getBooleanContents(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValueType(), llvm::isOneConstant(), llvm::ISD::SUBCARRY, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::USUBO, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by foldAddSubMasked1(), and isBooleanFlip().
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If N
is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.
Definition at line 1865 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesOrAllOnesSplat(), llvm::ISD::isBinaryOp(), isConstantFPBuildVectorOrConstantFP(), isConstantOrConstantVector(), llvm::isNullOrNullSplat(), llvm::ConstantSDNode::isOpaque(), llvm::SDValue::isUndef(), N, llvm::ISD::OR, and llvm::ISD::SELECT.
Referenced by calculateByteProvider(), isBSwapHWordElement(), replaceShuffleOfInsert(), simplifyDivRem(), and tryFoldToZero().
Definition at line 10100 of file DAGCombiner.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), assert(), llvm::ISD::BUILD_PAIR, llvm::dyn_cast(), llvm::DataLayout::getABITypeAlignment(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getStoreSize(), llvm::EVT::getTypeForEVT(), llvm::DataLayout::isBigEndian(), llvm::ISD::isNON_EXTLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, and std::swap().
Given a node, return its input chain if it has one, otherwise return a null sd operand.
Definition at line 1668 of file DAGCombiner.cpp.
References assert(), llvm::ISD::CopyFromReg, llvm::ISD::CopyToReg, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorTemplateCommon< T >::data(), llvm::ISD::EntryToken, llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::is_contained(), LLVM_FALLTHROUGH, llvm::CodeGenOpt::None, llvm::SDNode::op_values(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesWith(), second, llvm::SmallVectorBase::size(), llvm::ISD::TokenFactor, and llvm::SDNode::use_empty().
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If isNegatibleForFree returns true, return the newly negated expression.
Definition at line 768 of file DAGCombiner.cpp.
References assert(), llvm::APFloat::changeSign(), llvm::ISD::ConstantFP, llvm::Depth, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNodeFlags::hasNoSignedZeros(), isNegatibleForFree(), llvm_unreachable, llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
Referenced by FoldIntToFPToInt(), and isContractable().
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Definition at line 10141 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getDataLayout(), and llvm::DataLayout::isBigEndian().
Referenced by foldBitcastedFPLogic().
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If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.
Otherwise, return -1.
Definition at line 17656 of file DAGCombiner.cpp.
References llvm::ArrayRef< T >::size().
Referenced by replaceShuffleOfInsert().
Definition at line 919 of file DAGCombiner.cpp.
References llvm::AfterLegalizeTypes, llvm::AfterLegalizeVectorOps, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BUILD_VECTOR, llvm::ISD::Constant, llvm::dbgs(), llvm::ISD::DELETED_NODE, llvm::SelectionDAG::DeleteNode(), llvm::SDNode::dump(), llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::empty(), llvm::ISD::EXTLOAD, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::SDNodeFlags::hasVectorReduction(), llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::insert(), llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::EVT::isByteSized(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isConstantOrConstantVector(), llvm::TargetLowering::IsDesirableToPromoteOp(), llvm::EVT::isInteger(), llvm::ISD::isNON_EXTLoad(), llvm::TargetLoweringBase::isOperationLegal(), llvm::SDNode::isPredecessorOf(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::ARM_MB::LD, LLVM_DEBUG, llvm::SPII::Load, N, llvm::TargetLowering::TargetLoweringOpt::New, llvm::TargetLowering::TargetLoweringOpt::Old, llvm::SDNode::op_values(), llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::pop_back_val(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::ISD::SRA, llvm::ISD::SRL, std::swap(), llvm::ISD::TRUNCATE, llvm::SDNode::use_empty(), and llvm::ISD::ZERO_EXTEND.
Referenced by combineShuffleOfScalars(), and scalarizeExtractedBinop().
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Definition at line 2397 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::CARRY_FALSE, llvm::SelectionDAG::computeOverflowKind(), llvm::dyn_cast(), flipBoolean(), llvm::ConstantSDNode::getAPIntValue(), getAsCarry(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::SDNode::hasAnyUseOfValue(), llvm::ConstantSDNode::isAllOnesValue(), llvm::isBitwiseNot(), llvm::isNullConstant(), llvm::ConstantSDNode::isOne(), llvm::isOneOrOneSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm_unreachable, llvm::SelectionDAG::OFK_Never, llvm::ISD::SUBCARRY, llvm::ISD::UADDO, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::USUBO, llvm::ISD::XOR, Y, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
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Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.
((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)
Definition at line 5020 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::BSWAP, C, llvm::ShuffleVectorSDNode::commuteMask(), llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getAllOnesConstant(), llvm::ConstantSDNode::getAPIntValue(), getAsNonOpaqueConstant(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::APInt::intersects(), llvm::isAllOnesConstant(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::isNullConstant(), llvm::ConstantSDNode::isOpaque(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::matchBinaryPredicate(), llvm::ISD::OR, llvm::AArch64_AM::ROR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRL, std::swap(), and X.
Definition at line 889 of file DAGCombiner.cpp.
References llvm::SDValue::getNode(), and llvm::ISD::isBuildVectorOfConstantFPSDNodes().
Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND(), FoldIntToFPToInt(), getAsNonOpaqueConstant(), llvm::SelectionDAG::isConstantValueOfAnyType(), isContractable(), and visitFMinMax().
Definition at line 900 of file DAGCombiner.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), llvm::SDValue::getScalarValueSizeInBits(), llvm::ConstantSDNode::isOpaque(), llvm::SDValue::isUndef(), and llvm::SDNode::op_values().
Referenced by calculateByteProvider(), foldAddSubOfSignBit(), getAsNonOpaqueConstant(), isAnyConstantBuildVector(), isTruncateOf(), simplifyDivRem(), and tryFoldToZero().
Definition at line 10574 of file DAGCombiner.cpp.
References llvm::MCID::Add, llvm::AfterLegalizeDAG, Aggressive, llvm::TargetOptions::AllowFPOpFusion, assert(), B, C, llvm::TargetLowering::combineRepeatedFPDivisors(), llvm::ISD::ConstantFP, llvm::dyn_cast(), llvm::TargetLoweringBase::enableAggressiveFMAFusion(), F(), llvm::ISD::FABS, llvm::ISD::FADD, llvm::FPOpFusion::Fast, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FREM, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::SelectionDAGTargetInfo::generateFMAsInMachineCombiner(), llvm::SelectionDAG::getConstantFP(), llvm::SDNode::getFlags(), GetNegatedExpression(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetSubtargetInfo::getSelectionDAGInfo(), llvm::APFloat::getSemantics(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTarget(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNodeFlags::hasAllowContract(), llvm::SDNodeFlags::hasAllowReassociation(), llvm::SDNodeFlags::hasAllowReciprocal(), llvm::SDNodeFlags::hasApproximateFuncs(), llvm::SDNodeFlags::hasNoNaNs(), llvm::SDNodeFlags::hasNoSignedZeros(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::SetVector< T, Vector, Set >::insert(), isConstantFPBuildVectorOrConstantFP(), llvm::isConstOrConstSplatFP(), llvm::ConstantFPSDNode::isExactlyValue(), llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd(), llvm::TargetLoweringBase::isFPExtFoldable(), llvm::TargetLoweringBase::isFPImmLegal(), llvm::TargetLoweringBase::isFsqrtCheap(), isNegatibleForFree(), llvm::ConstantFPSDNode::isNegative(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::ConstantFPSDNode::isZero(), LLVM_FALLTHROUGH, N, llvm::TargetOptions::NoSignedZerosFPMath, llvm::APFloatBase::opInexact, llvm::APFloatBase::opOK, llvm::TargetMachine::Options, llvm::APFloatBase::rmNearestTiesToEven, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::SetVector< T, Vector, Set >::size(), std::swap(), llvm::TargetOptions::UnsafeFPMath, llvm::SDNode::use_size(), Users, llvm::SDNode::uses(), X, Y, and llvm::Z.
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Return true if divmod libcall is available.
Definition at line 3127 of file DAGCombiner.cpp.
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Definition at line 7323 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getTarget(), llvm::SDValue::getValueType(), llvm::EVT::isFloatingPoint(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::TargetLoweringBase::isProfitableToCombineMinNumMaxNum(), llvm::TargetOptions::NoSignedZerosFPMath, and llvm::TargetMachine::Options.
Referenced by combineMinNumMaxNum(), and ConvertSelectToConcatVector().
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Return 1 if we can compute the negated form of the specified expression for the same cost as the expression itself, or 2 if we can compute the negated form more cheaply than the expression itself.
Definition at line 696 of file DAGCombiner.cpp.
References llvm::ISD::ConstantFP, llvm::Depth, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::SDNode::getFlags(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNodeFlags::hasNoSignedZeros(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isFPExtFree(), llvm::TargetLoweringBase::isFPImmLegal(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::neg(), and llvm::TargetOptions::UnsafeFPMath.
Referenced by FoldIntToFPToInt(), GetNegatedExpression(), and isContractable().
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Check the profitability of all involved LoadedSlice.
Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (
Note: The order of the elements in LoadedSlices
may be modified, but not the elements themselves.
FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).
Definition at line 13790 of file DAGCombiner.cpp.
References adjustCostForPairing(), llvm::AfterLegalizeDAG, areUsedBitsDense(), assert(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::EVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::isPowerOf2_32(), llvm::MemSDNode::isVolatile(), llvm::ISD::LOAD, llvm::AArch64CC::LS, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorBase::size(), llvm::ISD::SRL, StressLoadSlicing, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
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Definition at line 8947 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::AfterLegalizeVectorOps, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLE(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, C, llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::Constant, llvm::KnownBits::countMinLeadingZeros(), llvm::APInt::countTrailingOnes(), llvm::APInt::countTrailingZeros(), llvm::dyn_cast(), ExtendUsesToFormExtLoad(), llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, foldExtendedSignBitTest(), llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::ConstantSDNode::getAPIntValue(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::APInt::getBitsSet(), llvm::KnownBits::getBitWidth(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::GetDemandedBits(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::EVT::getStoreSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i1, llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isConstantOrConstantVector(), llvm::ISD::isEXTLoad(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::APInt::isMask(), llvm::TargetLoweringBase::isNarrowingProfitable(), llvm::ISD::isNON_EXTLoad(), llvm::isNullOrNullSplat(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isScalarInteger(), llvm::APInt::isShiftedMask(), llvm::APInt::isSubsetOf(), llvm::TargetLoweringBase::isTruncateFree(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::isUIntN(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), isVolatile(), llvm::MemSDNode::isVolatile(), llvm::TargetLoweringBase::isZExtFree(), llvm::ISD::isZEXTLoad(), llvm::SPII::Load, llvm::ISD::LOAD, llvm::Log2_32(), llvm::APInt::lshr(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::MinAlign(), llvm::ISD::MUL, N, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SETNE, llvm::SDNodeFlags::setNoUnsignedWrap(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, Size, llvm::SmallVectorBase::size(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SelectionDAG::transferDbgValues(), llvm::ISD::TRUNCATE, tryToFoldExtendOfConstant(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), llvm::SDNode::use_begin(), X, llvm::ISD::XOR, Y, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.
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Match "(X shl/srl V1) & V2" where V2 may not be present.
Definition at line 5408 of file DAGCombiner.cpp.
References llvm::SDValue::getOpcode(), llvm::ISD::SHL, llvm::ISD::SRL, and stripConstantMask().
Referenced by matchRotateSub().
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Definition at line 5541 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::tgtok::Bits, llvm::SelectionDAG::computeKnownBits(), llvm::countTrailingOnes(), extractShiftForRotate(), llvm::SelectionDAG::getAllOnesConstant(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getLoBits(), getMemory(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::isPowerOf2_64(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SPII::Load, llvm::Log2_64(), llvm::ISD::matchBinaryPredicate(), matchRotateHalf(), llvm::operator==(), llvm::ISD::OR, Other, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::KnownBits::Zero, and llvm::ISD::ZERO_EXTEND.
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If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.
Definition at line 17066 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::CONCAT_VECTORS, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::ISD::isBinaryOp(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::EVT::isVector(), llvm::ISD::OR, llvm::peekThroughBitcasts(), X, llvm::ISD::XOR, and Y.
Referenced by narrowExtractedVectorLoad().
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If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) –> (load narrow vector)
Definition at line 17182 of file DAGCombiner.cpp.
References llvm::AfterLegalizeDAG, assert(), llvm::EVT::bitsEq(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::DataLayout::isBigEndian(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::isNullConstant(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::ISD::LOAD, llvm::makeArrayRef(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), narrowExtractedVectorBinOp(), llvm::SDNode::op_begin(), llvm::peekThroughBitcasts(), llvm::TargetLoweringBase::shouldReduceLoadWidth(), and llvm::ISD::TRUNCATE.
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Definition at line 13107 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::dbgs(), llvm::SDNode::dump(), llvm::dyn_cast(), llvm::BaseIndexOffset::equalBaseIndex(), llvm::ISD::EXTLOAD, llvm::ISD::FTRUNC, llvm::MemSDNode::getAAInfo(), llvm::DataLayout::getABITypeAlignment(), llvm::LSBaseSDNode::getAddressingMode(), getAlignment(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::MemSDNode::getChain(), llvm::TargetRegisterInfo::getCommonSubClass(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::LoadSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getRegClassFor(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MemSDNode::getSrcValueOffset(), llvm::EVT::getStoreSizeInBits(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getTypeForEVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDNode::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::hasOneUse(), llvm::SelectionDAG::InferPtrAlignment(), llvm::DataLayout::isBigEndian(), llvm::EVT::isExtended(), llvm::EVT::isFloatingPoint(), llvm::LSBaseSDNode::isIndexed(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isLegalAddImmediate(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isTruncateFree(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::ARM_MB::LD, LLVM_DEBUG, llvm::ISD::LOAD, llvm::AArch64CC::LS, llvm::BitmaskEnumDetail::Mask(), llvm::BaseIndexOffset::match(), MaySplitLoadIndex, llvm::MinAlign(), N, llvm::ISD::NON_EXTLOAD, llvm::CodeGenOpt::None, llvm::operator!=(), llvm::operator+=(), llvm::operator<(), llvm::operator<=(), llvm::operator==(), llvm::operator>(), llvm::operator>=(), llvm::MVT::Other, llvm::ISD::POST_DEC, llvm::ISD::PRE_DEC, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::APInt::setAllBits(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ARM_MB::ST, llvm::ISD::SUB, llvm::ISD::TargetConstant, llvm::ISD::TokenFactor, TRI, llvm::ISD::TRUNCATE, llvm::RegState::Undef, llvm::MVT::Untyped, llvm::SDNode::use_begin(), llvm::SDNode::use_empty(), llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.
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Definition at line 17331 of file DAGCombiner.cpp.
References llvm::all_of(), llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::SDValue::isUndef(), llvm::makeArrayRef(), and N.
Referenced by replaceShuffleOfInsert().
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Definition at line 16347 of file DAGCombiner.cpp.
References llvm::ISD::allOperandsUndef(), assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BUILD_VECTOR, C, Concat, llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorTemplateCommon< T >::end(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::find(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::tgtok::In, llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::isNullFPConstant(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::Left, llvm::BitmaskEnumDetail::Mask(), llvm::max(), llvm::peekThroughBitcasts(), llvm::SmallVectorTemplateBase< T >::pop_back(), llvm::PowerOf2Ceil(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::Right, llvm::SmallVectorBase::size(), llvm::APInt::uge(), llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::ZERO_EXTEND.
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If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle.
Definition at line 17680 of file DAGCombiner.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::AfterLegalizeDAG, llvm::AfterLegalizeVectorOps, llvm::AAResults::alias(), llvm::all_of(), Allocator, llvm::ISD::AND, Arg, assert(), B, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ArrayRef< T >::begin(), llvm::ISD::BITCAST, llvm::tgtok::Bits, llvm::EVT::bitsGE(), llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), C, llvm::SmallVectorImpl< T >::clear(), CombinerAAOnlyFunc, CombinerGlobalAA, combineShuffleOfScalars(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), combineTruncationShuffle(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::CopyFromReg, llvm::APInt::countLeadingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::Depth, llvm::dyn_cast(), llvm::SmallVectorBase::empty(), Enabled, llvm::ArrayRef< T >::end(), llvm::ISD::EntryToken, llvm::BaseIndexOffset::equalBaseIndex(), llvm::StringRef::equals(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, F(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FMUL, llvm::SelectionDAG::FoldConstantVectorArithmetic(), llvm::ISD::FP16_TO_FP, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ArrayType::get(), llvm::ConstantArray::get(), llvm::MemSDNode::getAAInfo(), llvm::MachinePointerInfo::getAddrSpace(), getAlignment(), llvm::MemSDNode::getAlignment(), llvm::ConstantSDNode::getAPIntValue(), getAsNonOpaqueConstant(), llvm::BaseIndexOffset::getBase(), llvm::MemSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::StoreSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getCommutedVectorShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SDValue::getConstantOperandVal(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::TargetLoweringBase::getDivRefinementSteps(), llvm::SelectionDAG::getEntryNode(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::SDNode::getFlags(), llvm::Function::getFnAttribute(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::TargetLoweringBase::getGatherAllAliasesMaxDepth(), llvm::BaseIndexOffset::getIndex(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::MachineFunction::getName(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getNumOperands(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getOperationAction(), llvm::MemSDNode::getOriginalAlignment(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::DataLayout::getPrefTypeAlignment(), llvm::TargetLowering::getRecipEstimate(), llvm::TargetLoweringBase::getRecipEstimateDivEnabled(), llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), getShuffleMaskIndexOfOneElementFromOp0IntoOp1(), llvm::EVT::getSizeInBits(), llvm::APFloat::getSmallestNormalized(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::TargetLowering::getSqrtEstimate(), llvm::TargetLoweringBase::getSqrtRefinementSteps(), llvm::MemSDNode::getSrcValueOffset(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTokenFactor(), llvm::SelectionDAG::getTruncStore(), llvm::Value::getType(), llvm::DataLayout::getTypeAllocSize(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::MachineMemOperand::getValue(), llvm::StoreSDNode::getValue(), llvm::Attribute::getValueAsString(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::TargetLoweringBase::hasAndNot(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::SDNode::hasPredecessorHelper(), I, llvm::MVT::i1, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SmallVectorImpl< T >::insert(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::isAllOnesConstant(), llvm::APInt::isAllOnesValue(), llvm::DataLayout::isBigEndian(), llvm::isConstOrConstSplat(), llvm::isConstOrConstSplatFP(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::EVT::isFloatingPoint(), llvm::TargetLoweringBase::isFPImmLegal(), llvm::LSBaseSDNode::isIndexed(), llvm::EVT::isInteger(), llvm::MemSDNode::isInvariant(), llvm::isNullConstant(), llvm::ConstantSDNode::isNullValue(), llvm::isOneConstant(), llvm::SDNode::isOnlyUserOf(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::SDNode::isPredecessorOf(), llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::ShuffleVectorSDNode::isSplat(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::SDNode::isUndef(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isVectorClearMaskLegal(), isVolatile(), llvm::MemSDNode::isVolatile(), llvm::ConstantFPSDNode::isZero(), llvm::TargetLoweringBase::Legal, llvm::SPII::Load, llvm::ISD::LOAD, llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), llvm::BaseIndexOffset::match(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, N, llvm::NoAlias, llvm::ISD::NON_EXTLOAD, llvm::CodeGenOpt::None, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::operator!=(), llvm::operator==(), llvm::Function::optForMinSize(), llvm::MVT::Other, partitionShuffleOfConcats(), llvm::peekThroughBitcasts(), llvm::peekThroughOneUseBitcasts(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetLoweringBase::reduceSelectOfFPConstantLoads(), llvm::ISD::SCALAR_TO_VECTOR, second, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOLT, llvm::ISD::SETULT, llvm::ISD::SHL, llvm::TargetLowering::SimplifySetCC(), llvm::SmallVectorBase::size(), llvm::ArrayRef< T >::size(), Split(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARM_MB::ST, llvm::ISD::STORE, llvm::ISD::SUB, std::swap(), llvm::ISD::TokenFactor, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::SelectionDAG::UpdateNodeOperands(), llvm::TargetSubtargetInfo::useAA(), UseTBAA, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::MemSDNode::writeMem(), X, llvm::ISD::XOR, Y, llvm::Z, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
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Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.
Definition at line 15822 of file DAGCombiner.cpp.
References llvm::AfterLegalizeTypes, llvm::AfterLegalizeVectorOps, llvm::TargetLoweringBase::aggressivelyPreferBuildVectorSources(), llvm::all_of(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::APInt::getNullValue(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::tgtok::In, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, isAnyConstantBuildVector(), llvm::ISD::isBinaryOp(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isOperationExpand(), llvm::TargetLoweringBase::isOperationLegal(), llvm::isPowerOf2_32(), llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isTruncateFree(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SCALAR_TO_VECTOR, llvm::APInt::setBit(), llvm::TargetLoweringBase::shouldScalarizeBinop(), llvm::SmallVectorBase::size(), llvm::ISD::TRUNCATE, llvm::SDNode::uses(), llvm::NVPTX::VecLoad, llvm::ISD::VECTOR_SHUFFLE, X, and llvm::ISD::ZERO_EXTEND.
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Check to see if IVal is something that provides a value as specified by MaskInfo.
If so, replace the specified store with a narrower store of truncated IVal.
Definition at line 14006 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::TargetLoweringBase::allowsMemoryAccess(), llvm::ISD::AND, llvm::SmallVectorImpl< T >::append(), assert(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::EVT::bitsEq(), llvm::ISD::BUILD_VECTOR, C, llvm::TargetLoweringBase::canMergeStoresTo(), CheckForMaskedLoad(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::Constant, Context, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::ISD::DELETED_NODE, llvm::dyn_cast(), E, llvm::SmallVectorBase::empty(), llvm::BaseIndexOffset::equalBaseIndex(), llvm::SmallVectorImpl< T >::erase(), llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::CallingConv::Fast, llvm::ISD::FP_ROUND, From, llvm::MemSDNode::getAAInfo(), llvm::DataLayout::getABITypeAlignment(), llvm::MemSDNode::getAddressSpace(), llvm::MachinePointerInfo::getAddrSpace(), llvm::MemSDNode::getAlignment(), llvm::APInt::getAllOnesValue(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::ConstantSDNode::getAPIntValue(), llvm::BaseIndexOffset::getBase(), llvm::MemSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::StoreSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::APInt::getBitsSet(), llvm::SelectionDAG::getBuildVector(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::GetDemandedBits(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::MachineFunction::getFunction(), llvm::EVT::getIntegerVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::MemSDNode::getSrcValueOffset(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::EVT::getStoreSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::TargetLoweringBase::getTypeAction(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::APInt::getZExtValue(), llvm::Function::hasFnAttribute(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::TargetLoweringBase::hasPairedLoad(), llvm::SDNode::hasPredecessorHelper(), llvm::MipsISD::Hi, I, llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::InferPtrAlignment(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::isAllOnesValue(), llvm::DataLayout::isBigEndian(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::TargetLowering::isDesirableToTransformToIntegerOp(), llvm::LSBaseSDNode::isIndexed(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::TargetLoweringBase::isMultiStoresCheaperThanBitsMerge(), llvm::TargetLoweringBase::isNarrowingProfitable(), llvm::MemSDNode::isNonTemporal(), llvm::ISD::isNormalLoad(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isStoreBitCastBeneficial(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTruncStoreLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm_unreachable, llvm::MipsISD::Lo, llvm::SPII::Load, llvm::ISD::LOAD, llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::BaseIndexOffset::match(), llvm::max(), llvm::TargetLoweringBase::mergeStoresAfterLegalization(), llvm::MinAlign(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MONone, llvm::ISD::MUL, N, llvm::NextPowerOf2(), llvm::ISD::NON_EXTLOAD, llvm::CodeGenOpt::None, llvm::SDNode::ops(), llvm::ISD::OR, llvm::MVT::Other, Other, llvm::peekThroughBitcasts(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::MVT::ppcf128, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::TargetLoweringBase::shouldReduceLoadWidth(), llvm::TargetLoweringBase::shouldSplatInsEltVarIndex(), llvm::MVT::SimpleTy, llvm::SmallVectorBase::size(), llvm::SmallPtrSetImplBase::size(), llvm::sort(), splitMergedValStore(), llvm::ISD::SRL, llvm::ARM_MB::ST, llvm::ISD::STORE, llvm::TargetLoweringBase::storeOfVectorConstantIsCheap(), std::swap(), llvm::ISD::TargetConstantFP, llvm::ISD::TokenFactor, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::TypePromoteInteger, llvm::SDNode::use_begin(), llvm::SDNode::use_empty(), llvm::SDNode::use_end(), llvm::SDNode::uses(), llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZEXTLOAD, and llvm::APInt::zextOrTrunc().
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Definition at line 3216 of file DAGCombiner.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::AfterLegalizeDAG, llvm::AfterLegalizeTypes, llvm::TargetLoweringBase::allowsMemoryAccess(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertZext, B, llvm::ISD::BITCAST, llvm::tgtok::Bits, llvm::EVT::bitsGE(), llvm::ISD::BSWAP, C, llvm::TargetLoweringBase::convertSetCCLogicToBitwiseLogic(), llvm::APInt::countTrailingOnes(), llvm::ISD::CTTZ, llvm::dbgs(), llvm::MipsISD::DivRem, llvm::SDNode::dump(), llvm::dyn_cast(), llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::LSBaseSDNode::getAddressingMode(), llvm::MemSDNode::getAddressSpace(), llvm::SelectionDAG::getAllOnesConstant(), llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), getAsNonOpaqueConstant(), llvm::Function::getAttributes(), llvm::MemSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::SDNode::getFlags(), llvm::MachineFunction::getFunction(), llvm::APInt::getHighBitsSet(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::APInt::getMinSignedBits(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNodeIfExists(), llvm::APInt::getNullValue(), llvm::SDValue::getNumOperands(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::LoadSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCAndOperation(), llvm::ISD::getSetCCOrOperation(), llvm::ISD::getSetCCSwappedOperands(), llvm::APInt::getSExtValue(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDNode::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), llvm::MVT::Glue, llvm::SDNode::hasAnyUseOfValue(), llvm::SDNodeFlags::hasExact(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::HasValue(), llvm::MipsISD::Hi, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::isAllOnesConstant(), llvm::isAllOnesOrAllOnesSplat(), llvm::APInt::isAllOnesValue(), llvm::ConstantSDNode::isAllOnesValue(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isConstantOrConstantVector(), llvm::isConstOrConstSplat(), llvm::EVT::isExtended(), llvm::ISD::isEXTLoad(), llvm::TargetLoweringBase::isIntDivCheap(), llvm::EVT::isInteger(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::TargetLoweringBase::isLegalAddImmediate(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::APInt::isMask(), llvm::APInt::isMinSignedValue(), llvm::TargetLoweringBase::isNarrowingProfitable(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::ConstantSDNode::isNullValue(), llvm::ConstantSDNode::isOne(), llvm::isOneConstant(), llvm::ConstantSDNode::isOpaque(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isRound(), llvm::ISD::isSEXTLoad(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTruncateFree(), llvm::TargetLoweringBase::isTruncStoreLegal(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::SelectionDAG::isUndef(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::TargetLoweringBase::isZExtFree(), LLVM_DEBUG, llvm_unreachable, llvm::MipsISD::Lo, llvm::SPII::Load, llvm::ISD::LOAD, llvm::APInt::lshr(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::matchBinaryPredicate(), llvm::ISD::matchUnaryPredicate(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::NON_EXTLOAD, llvm::SDNode::ops(), llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::preferShiftsToClearExtremeBits(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SETCC, llvm::ISD::SETCC_INVALID, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SHL, llvm::APInt::shl(), llvm::TargetLoweringBase::shouldReduceLoadWidth(), llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SignBitIsZero(), Size, llvm::SmallVectorBase::size(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::SUB, std::swap(), T1, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, tryFoldToZero(), llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::APInt::ugt(), llvm::APInt::ult(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::MVT::Untyped, llvm::SelectionDAG::UpdateNodeOperands(), llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, X, llvm::ISD::XOR, Y, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZEXTLOAD, and llvm::APInt::zextOrTrunc().
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Definition at line 7652 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDNode::getValueType(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, and llvm::SelectionDAG::SplitVectorOperand().
Referenced by ConvertSelectToConcatVector().
STATISTIC | ( | NodesCombined | , |
"Number of dag nodes combined" | |||
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STATISTIC | ( | PreIndexedNodes | , |
"Number of pre-indexed nodes created" | |||
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STATISTIC | ( | PostIndexedNodes | , |
"Number of post-indexed nodes created" | |||
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STATISTIC | ( | OpsNarrowed | , |
"Number of load/op/store narrowed" | |||
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STATISTIC | ( | LdStFP2Int | , |
"Number of fp load/store pairs transformed to int" | |||
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STATISTIC | ( | SlicedLoads | , |
"Number of load sliced" | |||
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Definition at line 5398 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt().
Referenced by extractShiftForRotate(), and matchRotateHalf().
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Definition at line 2602 of file DAGCombiner.cpp.
References llvm::ISD::ABS, llvm::APInt::abs(), llvm::ISD::ADD, llvm::AfterLegalizeVectorOps, llvm::ISD::AND, assert(), llvm::ISD::BUILD_VECTOR, C, llvm::ISD::CARRY_FALSE, llvm::TargetLoweringBase::decomposeMulByConstant(), llvm::ISD::DELETED_NODE, foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::ConstantSDNode::getAPIntValue(), getAsNonOpaqueConstant(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getGlobalAddress(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::APInt::getSignMask(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::VTSDNode::getVT(), llvm::SDNode::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::GlobalAddress, llvm::MVT::Glue, llvm::SDNode::hasAnyUseOfValue(), llvm::SDNodeFlags::hasNoSignedWrap(), llvm::SDNodeFlags::hasNoUnsignedWrap(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i1, llvm::isAllOnesConstant(), llvm::isAllOnesOrAllOnesSplat(), llvm::APInt::isAllOnesValue(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isConstantOrConstantVector(), llvm::ISD::isConstantSplatVector(), llvm::isConstOrConstSplat(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::APInt::isNegative(), llvm::isNullConstant(), llvm::isNullOrNullSplat(), llvm::APInt::isNullValue(), llvm::TargetLowering::isOffsetFoldingLegal(), llvm::APInt::isOneValue(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::USUBO, llvm::ISD::XOR, Y, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent.
Referenced by calculateByteProvider(), and simplifyDivRem().
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Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.
This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). Vector extends are not folded if operations are legal; this is to avoid introducing illegal build_vector dag nodes.
Definition at line 8269 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, assert(), C, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::APInt::sext(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::APInt::zext().
Referenced by foldExtendedSignBitTest(), and isTruncateOf().
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Definition at line 8633 of file DAGCombiner.cpp.
References llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getValue(), llvm::SDValue::hasOneUse(), llvm::ISD::isEXTLoad(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::ISD::isSEXTLoad(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::ISD::isZEXTLoad(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, and llvm::SDNode::use_empty().
Referenced by foldExtendedSignBitTest(), and isTruncateOf().
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Definition at line 8663 of file DAGCombiner.cpp.
References ExtendUsesToFormExtLoad(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isVectorLoadExtDesirable(), isVolatile(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ISD::TRUNCATE.
Referenced by foldExtendedSignBitTest(), and isTruncateOf().
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Definition at line 12447 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ISD::Constant, llvm::object::Equal, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FNEG, llvm::CondCodeSDNode::get(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::HandleSDNode::getValue(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), isConstantFPBuildVectorOrConstantFP(), llvm::isConstOrConstSplatFP(), llvm::TargetLoweringBase::isFAbsFree(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::APInt::isPowerOf2(), llvm::EVT::isVector(), llvm::APInt::logBase2(), llvm::maximum(), llvm::maxnum(), llvm::minimum(), llvm::minnum(), llvm::MVT::Other, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.
Definition at line 842 of file DAGCombiner.cpp.
References llvm::tgtok::Bits, llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::isConstFalseVal(), llvm::TargetLowering::isConstTrueVal(), llvm::max(), llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLoweringBase::UndefinedBooleanContent, and llvm::APInt::zextOrSelf().
Referenced by calculateByteProvider(), and extractShiftForRotate().
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Referenced by replaceShuffleOfInsert().
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Referenced by replaceShuffleOfInsert().
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Referenced by numVectorEltsOrZero().
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Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards.
Referenced by isSlicingProfitable().