LLVM  8.0.0svn
DbgEntityHistoryCalculator.cpp
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1 //===- llvm/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/ADT/BitVector.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/IR/DebugLoc.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
26 #include <cassert>
27 #include <map>
28 #include <utility>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "dwarfdebug"
33 
34 // If @MI is a DBG_VALUE with debug value described by a
35 // defined register, returns the number of this register.
36 // In the other case, returns 0.
37 static unsigned isDescribedByReg(const MachineInstr &MI) {
38  assert(MI.isDebugValue());
39  assert(MI.getNumOperands() == 4);
40  // If location of variable is described using a register (directly or
41  // indirectly), this register is always a first operand.
42  return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
43 }
44 
46  const MachineInstr &MI) {
47  // Instruction range should start with a DBG_VALUE instruction for the
48  // variable.
49  assert(MI.isDebugValue() && "not a DBG_VALUE");
50  auto &Ranges = VarInstrRanges[Var];
51  if (!Ranges.empty() && Ranges.back().second == nullptr &&
52  Ranges.back().first->isIdenticalTo(MI)) {
53  LLVM_DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
54  << "\t" << Ranges.back().first << "\t" << MI << "\n");
55  return;
56  }
57  Ranges.push_back(std::make_pair(&MI, nullptr));
58 }
59 
61  const MachineInstr &MI) {
62  auto &Ranges = VarInstrRanges[Var];
63  // Verify that the current instruction range is not yet closed.
64  assert(!Ranges.empty() && Ranges.back().second == nullptr);
65  // For now, instruction ranges are not allowed to cross basic block
66  // boundaries.
67  assert(Ranges.back().first->getParent() == MI.getParent());
68  Ranges.back().second = &MI;
69 }
70 
72  const auto &I = VarInstrRanges.find(Var);
73  if (I == VarInstrRanges.end())
74  return 0;
75  const auto &Ranges = I->second;
76  if (Ranges.empty() || Ranges.back().second != nullptr)
77  return 0;
78  return isDescribedByReg(*Ranges.back().first);
79 }
80 
82  assert(MI.isDebugLabel() && "not a DBG_LABEL");
83  LabelInstr[Label] = &MI;
84 }
85 
86 namespace {
87 
88 // Maps physreg numbers to the variables they describe.
90 using RegDescribedVarsMap = std::map<unsigned, SmallVector<InlinedEntity, 1>>;
91 
92 } // end anonymous namespace
93 
94 // Claim that @Var is not described by @RegNo anymore.
95 static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo,
96  InlinedEntity Var) {
97  const auto &I = RegVars.find(RegNo);
98  assert(RegNo != 0U && I != RegVars.end());
99  auto &VarSet = I->second;
100  const auto &VarPos = llvm::find(VarSet, Var);
101  assert(VarPos != VarSet.end());
102  VarSet.erase(VarPos);
103  // Don't keep empty sets in a map to keep it as small as possible.
104  if (VarSet.empty())
105  RegVars.erase(I);
106 }
107 
108 // Claim that @Var is now described by @RegNo.
109 static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo,
110  InlinedEntity Var) {
111  assert(RegNo != 0U);
112  auto &VarSet = RegVars[RegNo];
113  assert(!is_contained(VarSet, Var));
114  VarSet.push_back(Var);
115 }
116 
117 // Terminate the location range for variables described by register at
118 // @I by inserting @ClobberingInstr to their history.
119 static void clobberRegisterUses(RegDescribedVarsMap &RegVars,
120  RegDescribedVarsMap::iterator I,
121  DbgValueHistoryMap &HistMap,
122  const MachineInstr &ClobberingInstr) {
123  // Iterate over all variables described by this register and add this
124  // instruction to their history, clobbering it.
125  for (const auto &Var : I->second)
126  HistMap.endInstrRange(Var, ClobberingInstr);
127  RegVars.erase(I);
128 }
129 
130 // Terminate the location range for variables described by register
131 // @RegNo by inserting @ClobberingInstr to their history.
132 static void clobberRegisterUses(RegDescribedVarsMap &RegVars, unsigned RegNo,
133  DbgValueHistoryMap &HistMap,
134  const MachineInstr &ClobberingInstr) {
135  const auto &I = RegVars.find(RegNo);
136  if (I == RegVars.end())
137  return;
138  clobberRegisterUses(RegVars, I, HistMap, ClobberingInstr);
139 }
140 
141 // Returns the first instruction in @MBB which corresponds to
142 // the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
144  auto LastMI = MBB.getLastNonDebugInstr();
145  if (LastMI == MBB.end() || !LastMI->isReturn())
146  return nullptr;
147  // Assume that epilogue starts with instruction having the same debug location
148  // as the return instruction.
149  DebugLoc LastLoc = LastMI->getDebugLoc();
150  auto Res = LastMI;
151  for (MachineBasicBlock::const_reverse_iterator I = LastMI.getReverse(),
152  E = MBB.rend();
153  I != E; ++I) {
154  if (I->getDebugLoc() != LastLoc)
155  return &*Res;
156  Res = &*I;
157  }
158  // If all instructions have the same debug location, assume whole MBB is
159  // an epilogue.
160  return &*MBB.begin();
161 }
162 
163 // Collect registers that are modified in the function body (their
164 // contents is changed outside of the prologue and epilogue).
165 static void collectChangingRegs(const MachineFunction *MF,
166  const TargetRegisterInfo *TRI,
167  BitVector &Regs) {
168  for (const auto &MBB : *MF) {
169  auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
170 
171  for (const auto &MI : MBB) {
172  // Avoid looking at prologue or epilogue instructions.
173  if (&MI == FirstEpilogueInst)
174  break;
175  if (MI.getFlag(MachineInstr::FrameSetup))
176  continue;
177 
178  // Look for register defs and register masks. Register masks are
179  // typically on calls and they clobber everything not in the mask.
180  for (const MachineOperand &MO : MI.operands()) {
181  // Skip virtual registers since they are handled by the parent.
182  if (MO.isReg() && MO.isDef() && MO.getReg() &&
183  !TRI->isVirtualRegister(MO.getReg())) {
184  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
185  ++AI)
186  Regs.set(*AI);
187  } else if (MO.isRegMask()) {
188  Regs.setBitsNotInMask(MO.getRegMask());
189  }
190  }
191  }
192  }
193 }
194 
196  const TargetRegisterInfo *TRI,
197  DbgValueHistoryMap &DbgValues,
198  DbgLabelInstrMap &DbgLabels) {
199  BitVector ChangingRegs(TRI->getNumRegs());
200  collectChangingRegs(MF, TRI, ChangingRegs);
201 
202  const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
203  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
204  RegDescribedVarsMap RegVars;
205  for (const auto &MBB : *MF) {
206  for (const auto &MI : MBB) {
207  if (!MI.isDebugInstr()) {
208  // Not a DBG_VALUE instruction. It may clobber registers which describe
209  // some variables.
210  for (const MachineOperand &MO : MI.operands()) {
211  if (MO.isReg() && MO.isDef() && MO.getReg()) {
212  // Ignore call instructions that claim to clobber SP. The AArch64
213  // backend does this for aggregate function arguments.
214  if (MI.isCall() && MO.getReg() == SP)
215  continue;
216  // If this is a virtual register, only clobber it since it doesn't
217  // have aliases.
218  if (TRI->isVirtualRegister(MO.getReg()))
219  clobberRegisterUses(RegVars, MO.getReg(), DbgValues, MI);
220  // If this is a register def operand, it may end a debug value
221  // range.
222  else {
223  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
224  ++AI)
225  if (ChangingRegs.test(*AI))
226  clobberRegisterUses(RegVars, *AI, DbgValues, MI);
227  }
228  } else if (MO.isRegMask()) {
229  // If this is a register mask operand, clobber all debug values in
230  // non-CSRs.
231  for (unsigned I : ChangingRegs.set_bits()) {
232  // Don't consider SP to be clobbered by register masks.
233  if (unsigned(I) != SP && TRI->isPhysicalRegister(I) &&
234  MO.clobbersPhysReg(I)) {
235  clobberRegisterUses(RegVars, I, DbgValues, MI);
236  }
237  }
238  }
239  }
240  continue;
241  }
242 
243  if (MI.isDebugValue()) {
244  assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
245  // Use the base variable (without any DW_OP_piece expressions)
246  // as index into History. The full variables including the
247  // piece expressions are attached to the MI.
248  const DILocalVariable *RawVar = MI.getDebugVariable();
249  assert(RawVar->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
250  "Expected inlined-at fields to agree");
251  InlinedEntity Var(RawVar, MI.getDebugLoc()->getInlinedAt());
252 
253  if (unsigned PrevReg = DbgValues.getRegisterForVar(Var))
254  dropRegDescribedVar(RegVars, PrevReg, Var);
255 
256  DbgValues.startInstrRange(Var, MI);
257 
258  if (unsigned NewReg = isDescribedByReg(MI))
259  addRegDescribedVar(RegVars, NewReg, Var);
260  } else if (MI.isDebugLabel()) {
261  assert(MI.getNumOperands() == 1 && "Invalid DBG_LABEL instruction!");
262  const DILabel *RawLabel = MI.getDebugLabel();
263  assert(RawLabel->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
264  "Expected inlined-at fields to agree");
265  // When collecting debug information for labels, there is no MCSymbol
266  // generated for it. So, we keep MachineInstr in DbgLabels in order
267  // to query MCSymbol afterward.
268  InlinedEntity L(RawLabel, MI.getDebugLoc()->getInlinedAt());
269  DbgLabels.addInstr(L, MI);
270  }
271  }
272 
273  // Make sure locations for register-described variables are valid only
274  // until the end of the basic block (unless it's the last basic block, in
275  // which case let their liveness run off to the end of the function).
276  if (!MBB.empty() && &MBB != &MF->back()) {
277  for (auto I = RegVars.begin(), E = RegVars.end(); I != E;) {
278  auto CurElem = I++; // CurElem can be erased below.
279  if (TRI->isVirtualRegister(CurElem->first) ||
280  ChangingRegs.test(CurElem->first))
281  clobberRegisterUses(RegVars, CurElem, DbgValues, MBB.back());
282  }
283  }
284  }
285 }
286 
287 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
289  dbgs() << "DbgValueHistoryMap:\n";
290  for (const auto &VarRangePair : *this) {
291  const InlinedEntity &Var = VarRangePair.first;
292  const InstrRanges &Ranges = VarRangePair.second;
293 
294  const DILocalVariable *LocalVar = cast<DILocalVariable>(Var.first);
295  const DILocation *Location = Var.second;
296 
297  dbgs() << " - " << LocalVar->getName() << " at ";
298 
299  if (Location)
300  dbgs() << Location->getFilename() << ":" << Location->getLine() << ":"
301  << Location->getColumn();
302  else
303  dbgs() << "<unknown location>";
304 
305  dbgs() << " --\n";
306 
307  for (const InstrRange &Range : Ranges) {
308  dbgs() << " Begin: " << *Range.first;
309  if (Range.second)
310  dbgs() << " End : " << *Range.second;
311  dbgs() << "\n";
312  }
313  }
314 }
315 #endif
For each inlined instance of a source-level label, keep the corresponding DBG_LABEL instruction...
BitVector & set()
Definition: BitVector.h:398
bool isDebugLabel() const
Definition: MachineInstr.h:998
static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedEntity Var)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
static const MachineInstr * getFirstEpilogueInst(const MachineBasicBlock &MBB)
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
virtual const TargetLowering * getTargetLowering() const
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every &#39;0&#39; bit in Mask.
Definition: BitVector.h:788
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
unsigned getRegisterForVar(InlinedEntity Var) const
void calculateDbgEntityHistory(const MachineFunction *MF, const TargetRegisterInfo *TRI, DbgValueHistoryMap &DbgValues, DbgLabelInstrMap &DbgLabels)
std::pair< const DINode *, const DILocation * > InlinedEntity
StringRef getName() const
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedEntity Var)
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
Debug location.
iterator find(const KeyT &Key)
Definition: MapVector.h:148
reverse_iterator rend()
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCRegAliasIterator enumerates all registers aliasing Reg.
static void clobberRegisterUses(RegDescribedVarsMap &RegVars, RegDescribedVarsMap::iterator I, DbgValueHistoryMap &HistMap, const MachineInstr &ClobberingInstr)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1201
static unsigned isDescribedByReg(const MachineInstr &MI)
std::pair< const DINode *, const DILocation * > InlinedEntity
void addInstr(InlinedEntity Label, const MachineInstr &MI)
bool isDebugValue() const
Definition: MachineInstr.h:997
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void startInstrRange(InlinedEntity Var, const MachineInstr &MI)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
#define I(x, y, z)
Definition: MD5.cpp:58
void endInstrRange(InlinedEntity Var, const MachineInstr &MI)
std::pair< const MachineInstr *, const MachineInstr * > InstrRange
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator end()
Definition: MapVector.h:72
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
static void collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, BitVector &Regs)
IRTranslator LLVM IR MI
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
LLVM_DUMP_METHOD void dump() const
This file describes how to lower LLVM code to machine code.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1239