LLVM  6.0.0svn
DbgValueHistoryCalculator.cpp
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1 //===- llvm/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/ADT/BitVector.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/IR/DebugLoc.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
26 #include <cassert>
27 #include <map>
28 #include <utility>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "dwarfdebug"
33 
34 // \brief If @MI is a DBG_VALUE with debug value described by a
35 // defined register, returns the number of this register.
36 // In the other case, returns 0.
37 static unsigned isDescribedByReg(const MachineInstr &MI) {
38  assert(MI.isDebugValue());
39  assert(MI.getNumOperands() == 4);
40  // If location of variable is described using a register (directly or
41  // indirectly), this register is always a first operand.
42  return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
43 }
44 
46  const MachineInstr &MI) {
47  // Instruction range should start with a DBG_VALUE instruction for the
48  // variable.
49  assert(MI.isDebugValue() && "not a DBG_VALUE");
50  auto &Ranges = VarInstrRanges[Var];
51  if (!Ranges.empty() && Ranges.back().second == nullptr &&
52  Ranges.back().first->isIdenticalTo(MI)) {
53  DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
54  << "\t" << Ranges.back().first << "\t" << MI << "\n");
55  return;
56  }
57  Ranges.push_back(std::make_pair(&MI, nullptr));
58 }
59 
61  const MachineInstr &MI) {
62  auto &Ranges = VarInstrRanges[Var];
63  // Verify that the current instruction range is not yet closed.
64  assert(!Ranges.empty() && Ranges.back().second == nullptr);
65  // For now, instruction ranges are not allowed to cross basic block
66  // boundaries.
67  assert(Ranges.back().first->getParent() == MI.getParent());
68  Ranges.back().second = &MI;
69 }
70 
72  const auto &I = VarInstrRanges.find(Var);
73  if (I == VarInstrRanges.end())
74  return 0;
75  const auto &Ranges = I->second;
76  if (Ranges.empty() || Ranges.back().second != nullptr)
77  return 0;
78  return isDescribedByReg(*Ranges.back().first);
79 }
80 
81 namespace {
82 
83 // Maps physreg numbers to the variables they describe.
85 using RegDescribedVarsMap = std::map<unsigned, SmallVector<InlinedVariable, 1>>;
86 
87 } // end anonymous namespace
88 
89 // \brief Claim that @Var is not described by @RegNo anymore.
90 static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo,
91  InlinedVariable Var) {
92  const auto &I = RegVars.find(RegNo);
93  assert(RegNo != 0U && I != RegVars.end());
94  auto &VarSet = I->second;
95  const auto &VarPos = llvm::find(VarSet, Var);
96  assert(VarPos != VarSet.end());
97  VarSet.erase(VarPos);
98  // Don't keep empty sets in a map to keep it as small as possible.
99  if (VarSet.empty())
100  RegVars.erase(I);
101 }
102 
103 // \brief Claim that @Var is now described by @RegNo.
104 static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo,
105  InlinedVariable Var) {
106  assert(RegNo != 0U);
107  auto &VarSet = RegVars[RegNo];
108  assert(!is_contained(VarSet, Var));
109  VarSet.push_back(Var);
110 }
111 
112 // \brief Terminate the location range for variables described by register at
113 // @I by inserting @ClobberingInstr to their history.
114 static void clobberRegisterUses(RegDescribedVarsMap &RegVars,
115  RegDescribedVarsMap::iterator I,
116  DbgValueHistoryMap &HistMap,
117  const MachineInstr &ClobberingInstr) {
118  // Iterate over all variables described by this register and add this
119  // instruction to their history, clobbering it.
120  for (const auto &Var : I->second)
121  HistMap.endInstrRange(Var, ClobberingInstr);
122  RegVars.erase(I);
123 }
124 
125 // \brief Terminate the location range for variables described by register
126 // @RegNo by inserting @ClobberingInstr to their history.
127 static void clobberRegisterUses(RegDescribedVarsMap &RegVars, unsigned RegNo,
128  DbgValueHistoryMap &HistMap,
129  const MachineInstr &ClobberingInstr) {
130  const auto &I = RegVars.find(RegNo);
131  if (I == RegVars.end())
132  return;
133  clobberRegisterUses(RegVars, I, HistMap, ClobberingInstr);
134 }
135 
136 // \brief Returns the first instruction in @MBB which corresponds to
137 // the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
139  auto LastMI = MBB.getLastNonDebugInstr();
140  if (LastMI == MBB.end() || !LastMI->isReturn())
141  return nullptr;
142  // Assume that epilogue starts with instruction having the same debug location
143  // as the return instruction.
144  DebugLoc LastLoc = LastMI->getDebugLoc();
145  auto Res = LastMI;
146  for (MachineBasicBlock::const_reverse_iterator I = LastMI.getReverse(),
147  E = MBB.rend();
148  I != E; ++I) {
149  if (I->getDebugLoc() != LastLoc)
150  return &*Res;
151  Res = &*I;
152  }
153  // If all instructions have the same debug location, assume whole MBB is
154  // an epilogue.
155  return &*MBB.begin();
156 }
157 
158 // \brief Collect registers that are modified in the function body (their
159 // contents is changed outside of the prologue and epilogue).
160 static void collectChangingRegs(const MachineFunction *MF,
161  const TargetRegisterInfo *TRI,
162  BitVector &Regs) {
163  for (const auto &MBB : *MF) {
164  auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
165 
166  for (const auto &MI : MBB) {
167  // Avoid looking at prologue or epilogue instructions.
168  if (&MI == FirstEpilogueInst)
169  break;
170  if (MI.getFlag(MachineInstr::FrameSetup))
171  continue;
172 
173  // Look for register defs and register masks. Register masks are
174  // typically on calls and they clobber everything not in the mask.
175  for (const MachineOperand &MO : MI.operands()) {
176  // Skip virtual registers since they are handled by the parent.
177  if (MO.isReg() && MO.isDef() && MO.getReg() &&
178  !TRI->isVirtualRegister(MO.getReg())) {
179  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
180  ++AI)
181  Regs.set(*AI);
182  } else if (MO.isRegMask()) {
183  Regs.setBitsNotInMask(MO.getRegMask());
184  }
185  }
186  }
187  }
188 }
189 
191  const TargetRegisterInfo *TRI,
192  DbgValueHistoryMap &Result) {
193  BitVector ChangingRegs(TRI->getNumRegs());
194  collectChangingRegs(MF, TRI, ChangingRegs);
195 
196  const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
197  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
198  RegDescribedVarsMap RegVars;
199  for (const auto &MBB : *MF) {
200  for (const auto &MI : MBB) {
201  if (!MI.isDebugValue()) {
202  // Not a DBG_VALUE instruction. It may clobber registers which describe
203  // some variables.
204  for (const MachineOperand &MO : MI.operands()) {
205  if (MO.isReg() && MO.isDef() && MO.getReg()) {
206  // Ignore call instructions that claim to clobber SP. The AArch64
207  // backend does this for aggregate function arguments.
208  if (MI.isCall() && MO.getReg() == SP)
209  continue;
210  // If this is a virtual register, only clobber it since it doesn't
211  // have aliases.
212  if (TRI->isVirtualRegister(MO.getReg()))
213  clobberRegisterUses(RegVars, MO.getReg(), Result, MI);
214  // If this is a register def operand, it may end a debug value
215  // range.
216  else {
217  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
218  ++AI)
219  if (ChangingRegs.test(*AI))
220  clobberRegisterUses(RegVars, *AI, Result, MI);
221  }
222  } else if (MO.isRegMask()) {
223  // If this is a register mask operand, clobber all debug values in
224  // non-CSRs.
225  for (unsigned I : ChangingRegs.set_bits()) {
226  // Don't consider SP to be clobbered by register masks.
227  if (unsigned(I) != SP && TRI->isPhysicalRegister(I) &&
228  MO.clobbersPhysReg(I)) {
229  clobberRegisterUses(RegVars, I, Result, MI);
230  }
231  }
232  }
233  }
234  continue;
235  }
236 
237  assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
238  // Use the base variable (without any DW_OP_piece expressions)
239  // as index into History. The full variables including the
240  // piece expressions are attached to the MI.
241  const DILocalVariable *RawVar = MI.getDebugVariable();
242  assert(RawVar->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
243  "Expected inlined-at fields to agree");
244  InlinedVariable Var(RawVar, MI.getDebugLoc()->getInlinedAt());
245 
246  if (unsigned PrevReg = Result.getRegisterForVar(Var))
247  dropRegDescribedVar(RegVars, PrevReg, Var);
248 
249  Result.startInstrRange(Var, MI);
250 
251  if (unsigned NewReg = isDescribedByReg(MI))
252  addRegDescribedVar(RegVars, NewReg, Var);
253  }
254 
255  // Make sure locations for register-described variables are valid only
256  // until the end of the basic block (unless it's the last basic block, in
257  // which case let their liveness run off to the end of the function).
258  if (!MBB.empty() && &MBB != &MF->back()) {
259  for (auto I = RegVars.begin(), E = RegVars.end(); I != E;) {
260  auto CurElem = I++; // CurElem can be erased below.
261  if (TRI->isVirtualRegister(CurElem->first) ||
262  ChangingRegs.test(CurElem->first))
263  clobberRegisterUses(RegVars, CurElem, Result, MBB.back());
264  }
265  }
266  }
267 }
BitVector & set()
Definition: BitVector.h:398
void calculateDbgValueHistory(const MachineFunction *MF, const TargetRegisterInfo *TRI, DbgValueHistoryMap &Result)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
std::pair< const DILocalVariable *, const DILocation * > InlinedVariable
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
virtual const TargetLowering * getTargetLowering() const
static void collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, BitVector &Regs)
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every &#39;0&#39; bit in Mask.
Definition: BitVector.h:771
A debug info location.
Definition: DebugLoc.h:34
static void clobberRegisterUses(RegDescribedVarsMap &RegVars, RegDescribedVarsMap::iterator I, DbgValueHistoryMap &HistMap, const MachineInstr &ClobberingInstr)
static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
const RegList & Regs
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
iterator find(const KeyT &Key)
Definition: MapVector.h:144
reverse_iterator rend()
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void startInstrRange(InlinedVariable Var, const MachineInstr &MI)
MCRegAliasIterator enumerates all registers aliasing Reg.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned isDescribedByReg(const MachineInstr &MI)
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:788
bool isDebugValue() const
Definition: MachineInstr.h:816
MachineOperand class - Representation of each machine instruction operand.
static const MachineInstr * getFirstEpilogueInst(const MachineBasicBlock &MBB)
static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
#define I(x, y, z)
Definition: MD5.cpp:58
void endInstrRange(InlinedVariable Var, const MachineInstr &MI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator end()
Definition: MapVector.h:68
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
This file describes how to lower LLVM code to machine code.
unsigned getRegisterForVar(InlinedVariable Var) const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:821