LLVM  9.0.0svn
DwarfExpression.cpp
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1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "llvm/ADT/APInt.h"
20 #include <algorithm>
21 #include <cassert>
22 #include <cstdint>
23 
24 using namespace llvm;
25 
27  if (Value < 32)
28  emitOp(dwarf::DW_OP_lit0 + Value);
29  else if (Value == std::numeric_limits<uint64_t>::max()) {
30  // Only do this for 64-bit values as the DWARF expression stack uses
31  // target-address-size values.
32  emitOp(dwarf::DW_OP_lit0);
33  emitOp(dwarf::DW_OP_not);
34  } else {
35  emitOp(dwarf::DW_OP_constu);
36  emitUnsigned(Value);
37  }
38 }
39 
40 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
41  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
43  "location description already locked down");
45  if (DwarfReg < 32) {
46  emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
47  } else {
48  emitOp(dwarf::DW_OP_regx, Comment);
49  emitUnsigned(DwarfReg);
50  }
51 }
52 
53 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
54  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
55  assert(LocationKind != Register && "location description already locked down");
56  if (DwarfReg < 32) {
57  emitOp(dwarf::DW_OP_breg0 + DwarfReg);
58  } else {
59  emitOp(dwarf::DW_OP_bregx);
60  emitUnsigned(DwarfReg);
61  }
62  emitSigned(Offset);
63 }
64 
66  emitOp(dwarf::DW_OP_fbreg);
67  emitSigned(Offset);
68 }
69 
70 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
71  if (!SizeInBits)
72  return;
73 
74  const unsigned SizeOfByte = 8;
75  if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
76  emitOp(dwarf::DW_OP_bit_piece);
77  emitUnsigned(SizeInBits);
78  emitUnsigned(OffsetInBits);
79  } else {
80  emitOp(dwarf::DW_OP_piece);
81  unsigned ByteSize = SizeInBits / SizeOfByte;
82  emitUnsigned(ByteSize);
83  }
84  this->OffsetInBits += SizeInBits;
85 }
86 
87 void DwarfExpression::addShr(unsigned ShiftBy) {
88  emitConstu(ShiftBy);
89  emitOp(dwarf::DW_OP_shr);
90 }
91 
92 void DwarfExpression::addAnd(unsigned Mask) {
93  emitConstu(Mask);
94  emitOp(dwarf::DW_OP_and);
95 }
96 
98  unsigned MachineReg, unsigned MaxSize) {
99  if (!TRI.isPhysicalRegister(MachineReg)) {
100  if (isFrameRegister(TRI, MachineReg)) {
101  DwarfRegs.push_back({-1, 0, nullptr});
102  return true;
103  }
104  return false;
105  }
106 
107  int Reg = TRI.getDwarfRegNum(MachineReg, false);
108 
109  // If this is a valid register number, emit it.
110  if (Reg >= 0) {
111  DwarfRegs.push_back({Reg, 0, nullptr});
112  return true;
113  }
114 
115  // Walk up the super-register chain until we find a valid number.
116  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
117  for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
118  Reg = TRI.getDwarfRegNum(*SR, false);
119  if (Reg >= 0) {
120  unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
121  unsigned Size = TRI.getSubRegIdxSize(Idx);
122  unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
123  DwarfRegs.push_back({Reg, 0, "super-register"});
124  // Use a DW_OP_bit_piece to describe the sub-register.
125  setSubRegisterPiece(Size, RegOffset);
126  return true;
127  }
128  }
129 
130  // Otherwise, attempt to find a covering set of sub-register numbers.
131  // For example, Q0 on ARM is a composition of D0+D1.
132  unsigned CurPos = 0;
133  // The size of the register in bits.
134  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
135  unsigned RegSize = TRI.getRegSizeInBits(*RC);
136  // Keep track of the bits in the register we already emitted, so we
137  // can avoid emitting redundant aliasing subregs. Because this is
138  // just doing a greedy scan of all subregisters, it is possible that
139  // this doesn't find a combination of subregisters that fully cover
140  // the register (even though one may exist).
141  SmallBitVector Coverage(RegSize, false);
142  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
143  unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
144  unsigned Size = TRI.getSubRegIdxSize(Idx);
145  unsigned Offset = TRI.getSubRegIdxOffset(Idx);
146  Reg = TRI.getDwarfRegNum(*SR, false);
147  if (Reg < 0)
148  continue;
149 
150  // Intersection between the bits we already emitted and the bits
151  // covered by this subregister.
152  SmallBitVector CurSubReg(RegSize, false);
153  CurSubReg.set(Offset, Offset + Size);
154 
155  // If this sub-register has a DWARF number and we haven't covered
156  // its range, emit a DWARF piece for it.
157  if (CurSubReg.test(Coverage)) {
158  // Emit a piece for any gap in the coverage.
159  if (Offset > CurPos)
160  DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
161  DwarfRegs.push_back(
162  {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
163  if (Offset >= MaxSize)
164  break;
165 
166  // Mark it as emitted.
167  Coverage.set(Offset, Offset + Size);
168  CurPos = Offset + Size;
169  }
170  }
171  // Failed to find any DWARF encoding.
172  if (CurPos == 0)
173  return false;
174  // Found a partial or complete DWARF encoding.
175  if (CurPos < RegSize)
176  DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
177  return true;
178 }
179 
181  if (DwarfVersion >= 4)
182  emitOp(dwarf::DW_OP_stack_value);
183 }
184 
188  emitOp(dwarf::DW_OP_consts);
189  emitSigned(Value);
190 }
191 
195  emitConstu(Value);
196 }
197 
201 
202  unsigned Size = Value.getBitWidth();
203  const uint64_t *Data = Value.getRawData();
204 
205  // Chop it up into 64-bit pieces, because that's the maximum that
206  // addUnsignedConstant takes.
207  unsigned Offset = 0;
208  while (Offset < Size) {
209  addUnsignedConstant(*Data++);
210  if (Offset == 0 && Size <= 64)
211  break;
212  addStackValue();
213  addOpPiece(std::min(Size - Offset, 64u), Offset);
214  Offset += 64;
215  }
216 }
217 
219  DIExpressionCursor &ExprCursor,
220  unsigned MachineReg,
221  unsigned FragmentOffsetInBits) {
222  auto Fragment = ExprCursor.getFragmentInfo();
223  if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
225  return false;
226  }
227 
228  bool HasComplexExpression = false;
229  auto Op = ExprCursor.peek();
230  if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
231  HasComplexExpression = true;
232 
233  // If the register can only be described by a complex expression (i.e.,
234  // multiple subregisters) it doesn't safely compose with another complex
235  // expression. For example, it is not possible to apply a DW_OP_deref
236  // operation to multiple DW_OP_pieces.
237  if (HasComplexExpression && DwarfRegs.size() > 1) {
238  DwarfRegs.clear();
240  return false;
241  }
242 
243  // Handle simple register locations.
244  if (LocationKind != Memory && !HasComplexExpression) {
245  for (auto &Reg : DwarfRegs) {
246  if (Reg.DwarfRegNo >= 0)
247  addReg(Reg.DwarfRegNo, Reg.Comment);
248  addOpPiece(Reg.Size);
249  }
250  DwarfRegs.clear();
251  return true;
252  }
253 
254  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
255  if (DwarfVersion < 4)
256  if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
257  return Op.getOp() == dwarf::DW_OP_stack_value;
258  })) {
259  DwarfRegs.clear();
261  return false;
262  }
263 
264  assert(DwarfRegs.size() == 1);
265  auto Reg = DwarfRegs[0];
266  bool FBReg = isFrameRegister(TRI, MachineReg);
267  int SignedOffset = 0;
268  assert(Reg.Size == 0 && "subregister has same size as superregister");
269 
270  // Pattern-match combinations for which more efficient representations exist.
271  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
272  if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
273  SignedOffset = Op->getArg(0);
274  ExprCursor.take();
275  }
276 
277  // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
278  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
279  // If Reg is a subregister we need to mask it out before subtracting.
280  if (Op && Op->getOp() == dwarf::DW_OP_constu) {
281  auto N = ExprCursor.peekNext();
282  if (N && (N->getOp() == dwarf::DW_OP_plus ||
283  (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
284  int Offset = Op->getArg(0);
285  SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
286  ExprCursor.consume(2);
287  }
288  }
289 
290  if (FBReg)
291  addFBReg(SignedOffset);
292  else
293  addBReg(Reg.DwarfRegNo, SignedOffset);
294  DwarfRegs.clear();
295  return true;
296 }
297 
298 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
299 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
300  while (ExprCursor) {
301  auto Op = ExprCursor.take();
302  switch (Op->getOp()) {
303  case dwarf::DW_OP_deref:
305  break;
306  default:
307  return false;
308  }
309  }
310  return true;
311 }
312 
314  unsigned FragmentOffsetInBits) {
315  // If we need to mask out a subregister, do it now, unless the next
316  // operation would emit an OpPiece anyway.
317  auto N = ExprCursor.peek();
318  if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
319  maskSubRegister();
320 
321  while (ExprCursor) {
322  auto Op = ExprCursor.take();
323  switch (Op->getOp()) {
325  unsigned SizeInBits = Op->getArg(1);
326  unsigned FragmentOffset = Op->getArg(0);
327  // The fragment offset must have already been adjusted by emitting an
328  // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
329  // location.
330  assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
331 
332  // If addMachineReg already emitted DW_OP_piece operations to represent
333  // a super-register by splicing together sub-registers, subtract the size
334  // of the pieces that was already emitted.
335  SizeInBits -= OffsetInBits - FragmentOffset;
336 
337  // If addMachineReg requested a DW_OP_bit_piece to stencil out a
338  // sub-register that is smaller than the current fragment's size, use it.
340  SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
341 
342  // Emit a DW_OP_stack_value for implicit location descriptions.
343  if (LocationKind == Implicit)
344  addStackValue();
345 
346  // Emit the DW_OP_piece.
347  addOpPiece(SizeInBits, SubRegisterOffsetInBits);
348  setSubRegisterPiece(0, 0);
349  // Reset the location description kind.
351  return;
352  }
353  case dwarf::DW_OP_plus_uconst:
355  emitOp(dwarf::DW_OP_plus_uconst);
356  emitUnsigned(Op->getArg(0));
357  break;
358  case dwarf::DW_OP_plus:
359  case dwarf::DW_OP_minus:
360  case dwarf::DW_OP_mul:
361  case dwarf::DW_OP_div:
362  case dwarf::DW_OP_mod:
363  case dwarf::DW_OP_or:
364  case dwarf::DW_OP_and:
365  case dwarf::DW_OP_xor:
366  case dwarf::DW_OP_shl:
367  case dwarf::DW_OP_shr:
368  case dwarf::DW_OP_shra:
369  case dwarf::DW_OP_lit0:
370  case dwarf::DW_OP_not:
371  case dwarf::DW_OP_dup:
372  emitOp(Op->getOp());
373  break;
374  case dwarf::DW_OP_deref:
376  if (LocationKind != Memory && ::isMemoryLocation(ExprCursor))
377  // Turning this into a memory location description makes the deref
378  // implicit.
380  else
381  emitOp(dwarf::DW_OP_deref);
382  break;
383  case dwarf::DW_OP_constu:
385  emitConstu(Op->getArg(0));
386  break;
387  case dwarf::DW_OP_stack_value:
389  break;
390  case dwarf::DW_OP_swap:
392  emitOp(dwarf::DW_OP_swap);
393  break;
394  case dwarf::DW_OP_xderef:
396  emitOp(dwarf::DW_OP_xderef);
397  break;
398  default:
399  llvm_unreachable("unhandled opcode found in expression");
400  }
401  }
402 
403  if (LocationKind == Implicit)
404  // Turn this into an implicit location description.
405  addStackValue();
406 }
407 
408 /// add masking operations to stencil out a subregister.
410  assert(SubRegisterSizeInBits && "no subregister was registered");
411  if (SubRegisterOffsetInBits > 0)
413  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
414  addAnd(Mask);
415 }
416 
418  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
419  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
420  if (SubRegisterSizeInBits == 0)
421  return;
422  // Don't emit a DW_OP_piece for a subregister at offset 0.
423  if (SubRegisterOffsetInBits == 0)
424  return;
426 }
427 
429  if (!Expr || !Expr->isFragment())
430  return;
431 
432  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
433  assert(FragmentOffset >= OffsetInBits &&
434  "overlapping or duplicate fragments");
435  if (FragmentOffset > OffsetInBits)
436  addOpPiece(FragmentOffset - OffsetInBits);
437  OffsetInBits = FragmentOffset;
438 }
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
void addShr(unsigned ShiftBy)
Emit a shift-right dwarf operation.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void addUnsignedConstant(uint64_t Value)
Emit an unsigned constant.
void emitConstu(uint64_t Value)
Emit a normalized unsigned constant.
This class provides various memory handling functions that manipulate MemoryBlock instances...
Definition: Memory.h:45
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned Reg
unsigned const TargetRegisterInfo * TRI
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
bool test(unsigned Idx) const
MCSuperRegIterator enumerates all super-registers of Reg.
void addBReg(int DwarfReg, int Offset)
Emit a DW_OP_breg operation.
void addFBReg(int Offset)
Emit DW_OP_fbreg <Offset>.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Only used in LLVM metadata.
Definition: Dwarf.h:132
Holds a DIExpression and keeps track of how many operands have been consumed so far.
This file implements a class to represent arbitrary precision integral constant values and operations...
void addReg(int DwarfReg, const char *Comment=nullptr)
Emit a DW_OP_reg operation.
void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits)
Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed to represent a subregister...
Optional< DIExpression::ExprOperand > peek() const
Return the current operation.
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
void maskSubRegister()
Add masking operations to stencil out a subregister.
uint64_t getArg(unsigned I) const
Get an argument to the operand.
Optional< DIExpression::ExprOperand > peekNext() const
Return the next operation.
virtual void emitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
Optional< DIExpression::ExprOperand > take()
Consume one operation.
uint64_t getOp() const
Get the operand code.
virtual void emitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
A lightweight wrapper around an expression operand.
uint64_t OffsetInBits
Current Fragment Offset in Bits.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
virtual void emitSigned(int64_t Value)=0
Emit a raw signed value.
bool isMemoryLocation() const
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SmallBitVector & set()
void addExpression(DIExpressionCursor &&Expr, unsigned FragmentOffsetInBits=0)
Emit all remaining operations in the DIExpressionCursor.
bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg, unsigned MaxSize=~1U)
Emit a partial DWARF register operation.
void addStackValue()
Emit a DW_OP_stack_value, if supported.
enum llvm::DwarfExpression::@340 LocationKind
The kind of location description being produced.
DWARF expression.
This file contains constants used for implementing Dwarf debug support.
Class for arbitrary precision integers.
Definition: APInt.h:69
void addAnd(unsigned Mask)
Emit a bitwise and dwarf operation.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Optional< DIExpression::FragmentInfo > getFragmentInfo() const
Retrieve the fragment information, if any.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
unsigned SubRegisterSizeInBits
Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
void consume(unsigned N)
Consume N operations.
void finalize()
This needs to be called last to commit any pending changes.
#define N
uint32_t Size
Definition: Profile.cpp:46
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void addFragmentOffset(const DIExpression *Expr)
If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to the fragment described by Ex...
Holds information about all subregisters comprising a register location.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void addSignedConstant(int64_t Value)
Emit a signed constant.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
SmallVector< Register, 2 > DwarfRegs
The register location, if any.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isFragment() const
Return whether this is a piece of an aggregate variable.
bool addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &Expr, unsigned MachineReg, unsigned FragmentOffsetInBits=0)
Emit a machine register location.
virtual bool isFrameRegister(const TargetRegisterInfo &TRI, unsigned MachineReg)=0
Return whether the given machine register is the frame register in the current function.