LLVM  9.0.0svn
DwarfExpression.cpp
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1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
21 #include <algorithm>
22 #include <cassert>
23 #include <cstdint>
24 
25 using namespace llvm;
26 
28  if (Value < 32)
29  emitOp(dwarf::DW_OP_lit0 + Value);
30  else if (Value == std::numeric_limits<uint64_t>::max()) {
31  // Only do this for 64-bit values as the DWARF expression stack uses
32  // target-address-size values.
33  emitOp(dwarf::DW_OP_lit0);
34  emitOp(dwarf::DW_OP_not);
35  } else {
36  emitOp(dwarf::DW_OP_constu);
37  emitUnsigned(Value);
38  }
39 }
40 
41 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
42  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
44  "location description already locked down");
46  if (DwarfReg < 32) {
47  emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
48  } else {
49  emitOp(dwarf::DW_OP_regx, Comment);
50  emitUnsigned(DwarfReg);
51  }
52 }
53 
54 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
55  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
56  assert(LocationKind != Register && "location description already locked down");
57  if (DwarfReg < 32) {
58  emitOp(dwarf::DW_OP_breg0 + DwarfReg);
59  } else {
60  emitOp(dwarf::DW_OP_bregx);
61  emitUnsigned(DwarfReg);
62  }
63  emitSigned(Offset);
64 }
65 
67  emitOp(dwarf::DW_OP_fbreg);
68  emitSigned(Offset);
69 }
70 
71 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
72  if (!SizeInBits)
73  return;
74 
75  const unsigned SizeOfByte = 8;
76  if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
77  emitOp(dwarf::DW_OP_bit_piece);
78  emitUnsigned(SizeInBits);
79  emitUnsigned(OffsetInBits);
80  } else {
81  emitOp(dwarf::DW_OP_piece);
82  unsigned ByteSize = SizeInBits / SizeOfByte;
83  emitUnsigned(ByteSize);
84  }
85  this->OffsetInBits += SizeInBits;
86 }
87 
88 void DwarfExpression::addShr(unsigned ShiftBy) {
89  emitConstu(ShiftBy);
90  emitOp(dwarf::DW_OP_shr);
91 }
92 
93 void DwarfExpression::addAnd(unsigned Mask) {
94  emitConstu(Mask);
95  emitOp(dwarf::DW_OP_and);
96 }
97 
99  unsigned MachineReg, unsigned MaxSize) {
100  if (!TRI.isPhysicalRegister(MachineReg)) {
101  if (isFrameRegister(TRI, MachineReg)) {
102  DwarfRegs.push_back({-1, 0, nullptr});
103  return true;
104  }
105  return false;
106  }
107 
108  int Reg = TRI.getDwarfRegNum(MachineReg, false);
109 
110  // If this is a valid register number, emit it.
111  if (Reg >= 0) {
112  DwarfRegs.push_back({Reg, 0, nullptr});
113  return true;
114  }
115 
116  // Walk up the super-register chain until we find a valid number.
117  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
118  for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
119  Reg = TRI.getDwarfRegNum(*SR, false);
120  if (Reg >= 0) {
121  unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
122  unsigned Size = TRI.getSubRegIdxSize(Idx);
123  unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
124  DwarfRegs.push_back({Reg, 0, "super-register"});
125  // Use a DW_OP_bit_piece to describe the sub-register.
126  setSubRegisterPiece(Size, RegOffset);
127  return true;
128  }
129  }
130 
131  // Otherwise, attempt to find a covering set of sub-register numbers.
132  // For example, Q0 on ARM is a composition of D0+D1.
133  unsigned CurPos = 0;
134  // The size of the register in bits.
135  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
136  unsigned RegSize = TRI.getRegSizeInBits(*RC);
137  // Keep track of the bits in the register we already emitted, so we
138  // can avoid emitting redundant aliasing subregs. Because this is
139  // just doing a greedy scan of all subregisters, it is possible that
140  // this doesn't find a combination of subregisters that fully cover
141  // the register (even though one may exist).
142  SmallBitVector Coverage(RegSize, false);
143  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
144  unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
145  unsigned Size = TRI.getSubRegIdxSize(Idx);
146  unsigned Offset = TRI.getSubRegIdxOffset(Idx);
147  Reg = TRI.getDwarfRegNum(*SR, false);
148  if (Reg < 0)
149  continue;
150 
151  // Intersection between the bits we already emitted and the bits
152  // covered by this subregister.
153  SmallBitVector CurSubReg(RegSize, false);
154  CurSubReg.set(Offset, Offset + Size);
155 
156  // If this sub-register has a DWARF number and we haven't covered
157  // its range, emit a DWARF piece for it.
158  if (CurSubReg.test(Coverage)) {
159  // Emit a piece for any gap in the coverage.
160  if (Offset > CurPos)
161  DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
162  DwarfRegs.push_back(
163  {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
164  if (Offset >= MaxSize)
165  break;
166 
167  // Mark it as emitted.
168  Coverage.set(Offset, Offset + Size);
169  CurPos = Offset + Size;
170  }
171  }
172  // Failed to find any DWARF encoding.
173  if (CurPos == 0)
174  return false;
175  // Found a partial or complete DWARF encoding.
176  if (CurPos < RegSize)
177  DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
178  return true;
179 }
180 
182  if (DwarfVersion >= 4)
183  emitOp(dwarf::DW_OP_stack_value);
184 }
185 
189  emitOp(dwarf::DW_OP_consts);
190  emitSigned(Value);
191 }
192 
196  emitConstu(Value);
197 }
198 
202 
203  unsigned Size = Value.getBitWidth();
204  const uint64_t *Data = Value.getRawData();
205 
206  // Chop it up into 64-bit pieces, because that's the maximum that
207  // addUnsignedConstant takes.
208  unsigned Offset = 0;
209  while (Offset < Size) {
210  addUnsignedConstant(*Data++);
211  if (Offset == 0 && Size <= 64)
212  break;
213  addStackValue();
214  addOpPiece(std::min(Size - Offset, 64u), Offset);
215  Offset += 64;
216  }
217 }
218 
220  DIExpressionCursor &ExprCursor,
221  unsigned MachineReg,
222  unsigned FragmentOffsetInBits) {
223  auto Fragment = ExprCursor.getFragmentInfo();
224  if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
226  return false;
227  }
228 
229  bool HasComplexExpression = false;
230  auto Op = ExprCursor.peek();
231  if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
232  HasComplexExpression = true;
233 
234  // If the register can only be described by a complex expression (i.e.,
235  // multiple subregisters) it doesn't safely compose with another complex
236  // expression. For example, it is not possible to apply a DW_OP_deref
237  // operation to multiple DW_OP_pieces.
238  if (HasComplexExpression && DwarfRegs.size() > 1) {
239  DwarfRegs.clear();
241  return false;
242  }
243 
244  // Handle simple register locations.
245  if (LocationKind != Memory && !HasComplexExpression) {
246  for (auto &Reg : DwarfRegs) {
247  if (Reg.DwarfRegNo >= 0)
248  addReg(Reg.DwarfRegNo, Reg.Comment);
249  addOpPiece(Reg.Size);
250  }
251  DwarfRegs.clear();
252  return true;
253  }
254 
255  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
256  if (DwarfVersion < 4)
257  if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
258  return Op.getOp() == dwarf::DW_OP_stack_value;
259  })) {
260  DwarfRegs.clear();
262  return false;
263  }
264 
265  assert(DwarfRegs.size() == 1);
266  auto Reg = DwarfRegs[0];
267  bool FBReg = isFrameRegister(TRI, MachineReg);
268  int SignedOffset = 0;
269  assert(Reg.Size == 0 && "subregister has same size as superregister");
270 
271  // Pattern-match combinations for which more efficient representations exist.
272  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
273  if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
274  SignedOffset = Op->getArg(0);
275  ExprCursor.take();
276  }
277 
278  // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
279  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
280  // If Reg is a subregister we need to mask it out before subtracting.
281  if (Op && Op->getOp() == dwarf::DW_OP_constu) {
282  auto N = ExprCursor.peekNext();
283  if (N && (N->getOp() == dwarf::DW_OP_plus ||
284  (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
285  int Offset = Op->getArg(0);
286  SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
287  ExprCursor.consume(2);
288  }
289  }
290 
291  if (FBReg)
292  addFBReg(SignedOffset);
293  else
294  addBReg(Reg.DwarfRegNo, SignedOffset);
295  DwarfRegs.clear();
296  return true;
297 }
298 
299 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
300 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
301  while (ExprCursor) {
302  auto Op = ExprCursor.take();
303  switch (Op->getOp()) {
304  case dwarf::DW_OP_deref:
306  break;
307  default:
308  return false;
309  }
310  }
311  return true;
312 }
313 
315  unsigned FragmentOffsetInBits) {
316  // If we need to mask out a subregister, do it now, unless the next
317  // operation would emit an OpPiece anyway.
318  auto N = ExprCursor.peek();
319  if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
320  maskSubRegister();
321 
323 
324  while (ExprCursor) {
325  auto Op = ExprCursor.take();
326  switch (Op->getOp()) {
328  unsigned SizeInBits = Op->getArg(1);
329  unsigned FragmentOffset = Op->getArg(0);
330  // The fragment offset must have already been adjusted by emitting an
331  // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
332  // location.
333  assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
334 
335  // If addMachineReg already emitted DW_OP_piece operations to represent
336  // a super-register by splicing together sub-registers, subtract the size
337  // of the pieces that was already emitted.
338  SizeInBits -= OffsetInBits - FragmentOffset;
339 
340  // If addMachineReg requested a DW_OP_bit_piece to stencil out a
341  // sub-register that is smaller than the current fragment's size, use it.
343  SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
344 
345  // Emit a DW_OP_stack_value for implicit location descriptions.
346  if (LocationKind == Implicit)
347  addStackValue();
348 
349  // Emit the DW_OP_piece.
350  addOpPiece(SizeInBits, SubRegisterOffsetInBits);
351  setSubRegisterPiece(0, 0);
352  // Reset the location description kind.
354  return;
355  }
356  case dwarf::DW_OP_plus_uconst:
358  emitOp(dwarf::DW_OP_plus_uconst);
359  emitUnsigned(Op->getArg(0));
360  break;
361  case dwarf::DW_OP_plus:
362  case dwarf::DW_OP_minus:
363  case dwarf::DW_OP_mul:
364  case dwarf::DW_OP_div:
365  case dwarf::DW_OP_mod:
366  case dwarf::DW_OP_or:
367  case dwarf::DW_OP_and:
368  case dwarf::DW_OP_xor:
369  case dwarf::DW_OP_shl:
370  case dwarf::DW_OP_shr:
371  case dwarf::DW_OP_shra:
372  case dwarf::DW_OP_lit0:
373  case dwarf::DW_OP_not:
374  case dwarf::DW_OP_dup:
375  emitOp(Op->getOp());
376  break;
377  case dwarf::DW_OP_deref:
379  if (LocationKind != Memory && ::isMemoryLocation(ExprCursor))
380  // Turning this into a memory location description makes the deref
381  // implicit.
383  else
384  emitOp(dwarf::DW_OP_deref);
385  break;
386  case dwarf::DW_OP_constu:
388  emitConstu(Op->getArg(0));
389  break;
391  unsigned BitSize = Op->getArg(0);
392  dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
393  if (DwarfVersion >= 5) {
394  emitOp(dwarf::DW_OP_convert);
395  // Reuse the base_type if we already have one in this CU otherwise we
396  // create a new one.
397  unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
398  for (; I != E; ++I)
399  if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
400  CU.ExprRefedBaseTypes[I].Encoding == Encoding)
401  break;
402 
403  if (I == E)
404  CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
405 
406  // If targeting a location-list; simply emit the index into the raw
407  // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
408  // fitted with means to extract it later.
409  // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
410  // (containing the index and a resolve mechanism during emit) into the
411  // DIE value list.
412  emitBaseTypeRef(I);
413  } else {
414  if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
415  if (Encoding == dwarf::DW_ATE_signed)
416  emitLegacySExt(PrevConvertOp->getArg(0));
417  else if (Encoding == dwarf::DW_ATE_unsigned)
418  emitLegacyZExt(PrevConvertOp->getArg(0));
419  PrevConvertOp = None;
420  } else {
421  PrevConvertOp = Op;
422  }
423  }
424  break;
425  }
426  case dwarf::DW_OP_stack_value:
428  break;
429  case dwarf::DW_OP_swap:
431  emitOp(dwarf::DW_OP_swap);
432  break;
433  case dwarf::DW_OP_xderef:
435  emitOp(dwarf::DW_OP_xderef);
436  break;
437  default:
438  llvm_unreachable("unhandled opcode found in expression");
439  }
440  }
441 
442  if (LocationKind == Implicit)
443  // Turn this into an implicit location description.
444  addStackValue();
445 }
446 
447 /// add masking operations to stencil out a subregister.
449  assert(SubRegisterSizeInBits && "no subregister was registered");
450  if (SubRegisterOffsetInBits > 0)
452  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
453  addAnd(Mask);
454 }
455 
457  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
458  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
459  if (SubRegisterSizeInBits == 0)
460  return;
461  // Don't emit a DW_OP_piece for a subregister at offset 0.
462  if (SubRegisterOffsetInBits == 0)
463  return;
465 }
466 
468  if (!Expr || !Expr->isFragment())
469  return;
470 
471  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
472  assert(FragmentOffset >= OffsetInBits &&
473  "overlapping or duplicate fragments");
474  if (FragmentOffset > OffsetInBits)
475  addOpPiece(FragmentOffset - OffsetInBits);
476  OffsetInBits = FragmentOffset;
477 }
478 
479 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
480  // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
481  emitOp(dwarf::DW_OP_dup);
482  emitOp(dwarf::DW_OP_constu);
483  emitUnsigned(FromBits - 1);
484  emitOp(dwarf::DW_OP_shr);
485  emitOp(dwarf::DW_OP_lit0);
486  emitOp(dwarf::DW_OP_not);
487  emitOp(dwarf::DW_OP_mul);
488  emitOp(dwarf::DW_OP_constu);
489  emitUnsigned(FromBits);
490  emitOp(dwarf::DW_OP_shl);
491  emitOp(dwarf::DW_OP_or);
492 }
493 
494 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
495  // (X & (1 << FromBits - 1))
496  emitOp(dwarf::DW_OP_constu);
497  emitUnsigned((1ULL << FromBits) - 1);
498  emitOp(dwarf::DW_OP_and);
499 }
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
void addShr(unsigned ShiftBy)
Emit a shift-right dwarf operation.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void addUnsignedConstant(uint64_t Value)
Emit an unsigned constant.
void emitConstu(uint64_t Value)
Emit a normalized unsigned constant.
This class provides various memory handling functions that manipulate MemoryBlock instances...
Definition: Memory.h:46
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned Reg
Only used in LLVM metadata.
Definition: Dwarf.h:133
unsigned const TargetRegisterInfo * TRI
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
bool test(unsigned Idx) const
MCSuperRegIterator enumerates all super-registers of Reg.
void addBReg(int DwarfReg, int Offset)
Emit a DW_OP_breg operation.
void addFBReg(int Offset)
Emit DW_OP_fbreg <Offset>.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Only used in LLVM metadata.
Definition: Dwarf.h:132
Holds a DIExpression and keeps track of how many operands have been consumed so far.
This file implements a class to represent arbitrary precision integral constant values and operations...
void addReg(int DwarfReg, const char *Comment=nullptr)
Emit a DW_OP_reg operation.
void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits)
Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed to represent a subregister...
Optional< DIExpression::ExprOperand > peek() const
Return the current operation.
enum llvm::DwarfExpression::@348 LocationKind
The kind of location description being produced.
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
void emitLegacyZExt(unsigned FromBits)
void maskSubRegister()
Add masking operations to stencil out a subregister.
uint64_t getArg(unsigned I) const
Get an argument to the operand.
Optional< DIExpression::ExprOperand > peekNext() const
Return the next operation.
virtual void emitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
Optional< DIExpression::ExprOperand > take()
Consume one operation.
uint64_t getOp() const
Get the operand code.
virtual void emitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
A lightweight wrapper around an expression operand.
uint64_t OffsetInBits
Current Fragment Offset in Bits.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
virtual void emitSigned(int64_t Value)=0
Emit a raw signed value.
bool isMemoryLocation() const
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SmallBitVector & set()
void addExpression(DIExpressionCursor &&Expr, unsigned FragmentOffsetInBits=0)
Emit all remaining operations in the DIExpressionCursor.
bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg, unsigned MaxSize=~1U)
Emit a partial DWARF register operation.
void addStackValue()
Emit a DW_OP_stack_value, if supported.
DWARF expression.
This file contains constants used for implementing Dwarf debug support.
Class for arbitrary precision integers.
Definition: APInt.h:69
void addAnd(unsigned Mask)
Emit a bitwise and dwarf operation.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Optional< DIExpression::FragmentInfo > getFragmentInfo() const
Retrieve the fragment information, if any.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
unsigned SubRegisterSizeInBits
Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
void consume(unsigned N)
Consume N operations.
virtual void emitBaseTypeRef(uint64_t Idx)=0
void finalize()
This needs to be called last to commit any pending changes.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
uint32_t Size
Definition: Profile.cpp:46
void emitLegacySExt(unsigned FromBits)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void addFragmentOffset(const DIExpression *Expr)
If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to the fragment described by Ex...
Holds information about all subregisters comprising a register location.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void addSignedConstant(int64_t Value)
Emit a signed constant.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
SmallVector< Register, 2 > DwarfRegs
The register location, if any.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isFragment() const
Return whether this is a piece of an aggregate variable.
bool addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &Expr, unsigned MachineReg, unsigned FragmentOffsetInBits=0)
Emit a machine register location.
virtual bool isFrameRegister(const TargetRegisterInfo &TRI, unsigned MachineReg)=0
Return whether the given machine register is the frame register in the current function.