LLVM  7.0.0svn
ExpandPostRAPseudos.cpp
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1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11 // instructions after register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
19 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Support/Debug.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "postrapseudos"
29 
30 namespace {
31 struct ExpandPostRA : public MachineFunctionPass {
32 private:
33  const TargetRegisterInfo *TRI;
34  const TargetInstrInfo *TII;
35 
36 public:
37  static char ID; // Pass identification, replacement for typeid
38  ExpandPostRA() : MachineFunctionPass(ID) {}
39 
40  void getAnalysisUsage(AnalysisUsage &AU) const override {
41  AU.setPreservesCFG();
45  }
46 
47  /// runOnMachineFunction - pass entry point
48  bool runOnMachineFunction(MachineFunction&) override;
49 
50 private:
51  bool LowerSubregToReg(MachineInstr *MI);
52  bool LowerCopy(MachineInstr *MI);
53 
54  void TransferImplicitOperands(MachineInstr *MI);
55 };
56 } // end anonymous namespace
57 
58 char ExpandPostRA::ID = 0;
60 
62  "Post-RA pseudo instruction expansion pass", false, false)
63 
64 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
65 /// replacement instructions immediately precede it. Copy any implicit
66 /// operands from MI to the replacement instruction.
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
69  --CopyMI;
70 
71  for (const MachineOperand &MO : MI->implicit_operands())
72  if (MO.isReg())
73  CopyMI->addOperand(MO);
74 }
75 
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
77  MachineBasicBlock *MBB = MI->getParent();
78  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
79  MI->getOperand(1).isImm() &&
80  (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
81  MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
82 
83  unsigned DstReg = MI->getOperand(0).getReg();
84  unsigned InsReg = MI->getOperand(2).getReg();
85  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
86  unsigned SubIdx = MI->getOperand(3).getImm();
87 
88  assert(SubIdx != 0 && "Invalid index for insert_subreg");
89  unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
90 
92  "Insert destination must be in a physical register");
94  "Inserted value must be in a physical register");
95 
96  LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
97 
98  if (MI->allDefsAreDead()) {
99  MI->setDesc(TII->get(TargetOpcode::KILL));
100  LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
101  return true;
102  }
103 
104  if (DstSubReg == InsReg) {
105  // No need to insert an identity copy instruction.
106  // Watch out for case like this:
107  // %rax = SUBREG_TO_REG 0, killed %eax, 3
108  // We must leave %rax live.
109  if (DstReg != InsReg) {
110  MI->setDesc(TII->get(TargetOpcode::KILL));
111  MI->RemoveOperand(3); // SubIdx
112  MI->RemoveOperand(1); // Imm
113  LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
114  return true;
115  }
116  LLVM_DEBUG(dbgs() << "subreg: eliminated!");
117  } else {
118  TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
119  MI->getOperand(2).isKill());
120 
121  // Implicitly define DstReg for subsequent uses.
123  --CopyMI;
124  CopyMI->addRegisterDefined(DstReg);
125  LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
126  }
127 
128  LLVM_DEBUG(dbgs() << '\n');
129  MBB->erase(MI);
130  return true;
131 }
132 
133 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
134 
135  if (MI->allDefsAreDead()) {
136  LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
137  MI->setDesc(TII->get(TargetOpcode::KILL));
138  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
139  return true;
140  }
141 
142  MachineOperand &DstMO = MI->getOperand(0);
143  MachineOperand &SrcMO = MI->getOperand(1);
144 
145  bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
146  if (IdentityCopy || SrcMO.isUndef()) {
147  LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ")
148  << *MI);
149  // No need to insert an identity copy instruction, but replace with a KILL
150  // if liveness is changed.
151  if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
152  // We must make sure the super-register gets killed. Replace the
153  // instruction with KILL.
154  MI->setDesc(TII->get(TargetOpcode::KILL));
155  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
156  return true;
157  }
158  // Vanilla identity copy.
159  MI->eraseFromParent();
160  return true;
161  }
162 
163  LLVM_DEBUG(dbgs() << "real copy: " << *MI);
164  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
165  DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
166 
167  if (MI->getNumOperands() > 2)
168  TransferImplicitOperands(MI);
169  LLVM_DEBUG({
171  dbgs() << "replaced by: " << *(--dMI);
172  });
173  MI->eraseFromParent();
174  return true;
175 }
176 
177 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
178 /// copies.
179 ///
180 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
181  LLVM_DEBUG(dbgs() << "Machine Function\n"
182  << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
183  << "********** Function: " << MF.getName() << '\n');
185  TII = MF.getSubtarget().getInstrInfo();
186 
187  bool MadeChange = false;
188 
189  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
190  mbbi != mbbe; ++mbbi) {
191  for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
192  mi != me;) {
193  MachineInstr &MI = *mi;
194  // Advance iterator here because MI may be erased.
195  ++mi;
196 
197  // Only expand pseudos.
198  if (!MI.isPseudo())
199  continue;
200 
201  // Give targets a chance to expand even standard pseudos.
202  if (TII->expandPostRAPseudo(MI)) {
203  MadeChange = true;
204  continue;
205  }
206 
207  // Expand standard pseudos.
208  switch (MI.getOpcode()) {
209  case TargetOpcode::SUBREG_TO_REG:
210  MadeChange |= LowerSubregToReg(&MI);
211  break;
212  case TargetOpcode::COPY:
213  MadeChange |= LowerCopy(&MI);
214  break;
215  case TargetOpcode::DBG_VALUE:
216  continue;
217  case TargetOpcode::INSERT_SUBREG:
218  case TargetOpcode::EXTRACT_SUBREG:
219  llvm_unreachable("Sub-register pseudos should have been eliminated.");
220  }
221  }
222  }
223 
224  return MadeChange;
225 }
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
unsigned getReg() const
getReg - Returns the register number.
unsigned getSubReg() const
unsigned const TargetRegisterInfo * TRI
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
AnalysisUsage & addPreservedID(const void *ID)
virtual const TargetInstrInfo * getInstrInfo() const
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:477
Represent the analysis usage information of a pass.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:286
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
#define DEBUG_TYPE
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
#define LLVM_DEBUG(X)
Definition: Debug.h:119
INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, "Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316