LLVM  6.0.0svn
Functions
GCNHazardRecognizer.cpp File Reference
#include "GCNHazardRecognizer.h"
#include "AMDGPUSubtarget.h"
#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "SIRegisterInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
#include <cassert>
#include <limits>
#include <set>
#include <vector>
Include dependency graph for GCNHazardRecognizer.cpp:

Go to the source code of this file.

Functions

static bool isDivFMas (unsigned Opcode)
 
static bool isSGetReg (unsigned Opcode)
 
static bool isSSetReg (unsigned Opcode)
 
static bool isRWLane (unsigned Opcode)
 
static bool isRFE (unsigned Opcode)
 
static bool isSMovRel (unsigned Opcode)
 
static unsigned getHWReg (const SIInstrInfo *TII, const MachineInstr &RegInstr)
 
static void addRegsToSet (iterator_range< MachineInstr::const_mop_iterator > Ops, std::set< unsigned > &Set)
 

Function Documentation

◆ addRegsToSet()

static void addRegsToSet ( iterator_range< MachineInstr::const_mop_iterator Ops,
std::set< unsigned > &  Set 
)
static

Definition at line 261 of file GCNHazardRecognizer.cpp.

References assert(), llvm::tgtok::Def, llvm::MachineInstr::defs(), llvm::SIInstrFlags::DPP, llvm::WebAssembly::End, llvm::MachineInstr::getDesc(), llvm::AMDGPUSubtarget::getGeneration(), getHWReg(), llvm::SISubtarget::getInstrInfo(), llvm::SIInstrInfo::getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineFunction::getRegInfo(), llvm::SIInstrInfo::getRegisterInfo(), llvm::SISubtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::SISubtarget::has12DWordStoreHazard(), llvm::SISubtarget::hasReadM0Hazard(), llvm::SISubtarget::hasSMovFedHazard(), llvm::AMDGPU::Hwreg::ID_TRAPSTS, llvm::MachineInstr::isDebugValue(), llvm::SIInstrInfo::isFLAT(), llvm::SIInstrInfo::isMIMG(), llvm::SIInstrInfo::isMTBUF(), llvm::SIInstrInfo::isMUBUF(), llvm::MachineOperand::isReg(), llvm::SIInstrInfo::isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::SIInstrInfo::isSMRD(), llvm::SIInstrInfo::isVALU(), llvm::SIRegisterInfo::isVGPR(), llvm::max(), llvm::MachineInstr::mayStore(), MI, MRI, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::SIInstrFlags::SMRD, llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, llvm::MachineInstr::uses(), llvm::SIInstrFlags::VALU, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

◆ getHWReg()

static unsigned getHWReg ( const SIInstrInfo TII,
const MachineInstr RegInstr 
)
static

◆ isDivFMas()

static bool isDivFMas ( unsigned  Opcode)
static

◆ isRFE()

static bool isRFE ( unsigned  Opcode)
static

◆ isRWLane()

static bool isRWLane ( unsigned  Opcode)
static

◆ isSGetReg()

static bool isSGetReg ( unsigned  Opcode)
static

◆ isSMovRel()

static bool isSMovRel ( unsigned  Opcode)
static

◆ isSSetReg()

static bool isSSetReg ( unsigned  Opcode)
static