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GCNHazardRecognizer.cpp
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1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements hazard recognizers for scheduling on GCN processors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "GCNHazardRecognizer.h"
15 #include "AMDGPUSubtarget.h"
16 #include "SIDefines.h"
17 #include "SIInstrInfo.h"
18 #include "SIRegisterInfo.h"
19 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm/MC/MCInstrDesc.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <limits>
30 #include <set>
31 #include <vector>
32 
33 using namespace llvm;
34 
35 //===----------------------------------------------------------------------===//
36 // Hazard Recoginizer Implementation
37 //===----------------------------------------------------------------------===//
38 
40  CurrCycleInstr(nullptr),
41  MF(MF),
42  ST(MF.getSubtarget<SISubtarget>()),
43  TII(*ST.getInstrInfo()),
44  TRI(TII.getRegisterInfo()),
45  ClauseUses(TRI.getNumRegUnits()),
46  ClauseDefs(TRI.getNumRegUnits()) {
47  MaxLookAhead = 5;
48 }
49 
52 }
53 
55  CurrCycleInstr = MI;
56 }
57 
58 static bool isDivFMas(unsigned Opcode) {
59  return Opcode == AMDGPU::V_DIV_FMAS_F32 || Opcode == AMDGPU::V_DIV_FMAS_F64;
60 }
61 
62 static bool isSGetReg(unsigned Opcode) {
63  return Opcode == AMDGPU::S_GETREG_B32;
64 }
65 
66 static bool isSSetReg(unsigned Opcode) {
67  return Opcode == AMDGPU::S_SETREG_B32 || Opcode == AMDGPU::S_SETREG_IMM32_B32;
68 }
69 
70 static bool isRWLane(unsigned Opcode) {
71  return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32;
72 }
73 
74 static bool isRFE(unsigned Opcode) {
75  return Opcode == AMDGPU::S_RFE_B64;
76 }
77 
78 static bool isSMovRel(unsigned Opcode) {
79  switch (Opcode) {
80  case AMDGPU::S_MOVRELS_B32:
81  case AMDGPU::S_MOVRELS_B64:
82  case AMDGPU::S_MOVRELD_B32:
83  case AMDGPU::S_MOVRELD_B64:
84  return true;
85  default:
86  return false;
87  }
88 }
89 
90 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) {
91  const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,
92  AMDGPU::OpName::simm16);
93  return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;
94 }
95 
98  MachineInstr *MI = SU->getInstr();
99 
100  if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0)
101  return NoopHazard;
102 
103  if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0)
104  return NoopHazard;
105 
106  if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0)
107  return NoopHazard;
108 
109  if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0)
110  return NoopHazard;
111 
112  if (isDivFMas(MI->getOpcode()) && checkDivFMasHazards(MI) > 0)
113  return NoopHazard;
114 
115  if (isRWLane(MI->getOpcode()) && checkRWLaneHazards(MI) > 0)
116  return NoopHazard;
117 
118  if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0)
119  return NoopHazard;
120 
121  if (isSSetReg(MI->getOpcode()) && checkSetRegHazards(MI) > 0)
122  return NoopHazard;
123 
124  if (isRFE(MI->getOpcode()) && checkRFEHazards(MI) > 0)
125  return NoopHazard;
126 
127  if ((TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) &&
128  checkReadM0Hazards(MI) > 0)
129  return NoopHazard;
130 
131  if (checkAnyInstHazards(MI) > 0)
132  return NoopHazard;
133 
134  return NoHazard;
135 }
136 
138  return PreEmitNoops(SU->getInstr());
139 }
140 
142  int WaitStates = std::max(0, checkAnyInstHazards(MI));
143 
144  if (SIInstrInfo::isSMRD(*MI))
145  return std::max(WaitStates, checkSMRDHazards(MI));
146 
147  if (SIInstrInfo::isVALU(*MI)) {
148  WaitStates = std::max(WaitStates, checkVALUHazards(MI));
149 
150  if (SIInstrInfo::isVMEM(*MI))
151  WaitStates = std::max(WaitStates, checkVMEMHazards(MI));
152 
153  if (SIInstrInfo::isDPP(*MI))
154  WaitStates = std::max(WaitStates, checkDPPHazards(MI));
155 
156  if (isDivFMas(MI->getOpcode()))
157  WaitStates = std::max(WaitStates, checkDivFMasHazards(MI));
158 
159  if (isRWLane(MI->getOpcode()))
160  WaitStates = std::max(WaitStates, checkRWLaneHazards(MI));
161 
162  if (TII.isVINTRP(*MI))
163  WaitStates = std::max(WaitStates, checkReadM0Hazards(MI));
164 
165  return WaitStates;
166  }
167 
168  if (isSGetReg(MI->getOpcode()))
169  return std::max(WaitStates, checkGetRegHazards(MI));
170 
171  if (isSSetReg(MI->getOpcode()))
172  return std::max(WaitStates, checkSetRegHazards(MI));
173 
174  if (isRFE(MI->getOpcode()))
175  return std::max(WaitStates, checkRFEHazards(MI));
176 
177  if (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()))
178  return std::max(WaitStates, checkReadM0Hazards(MI));
179 
180  return WaitStates;
181 }
182 
184  EmittedInstrs.push_front(nullptr);
185 }
186 
188  // When the scheduler detects a stall, it will call AdvanceCycle() without
189  // emitting any instructions.
190  if (!CurrCycleInstr)
191  return;
192 
193  unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);
194 
195  // Keep track of emitted instructions
196  EmittedInstrs.push_front(CurrCycleInstr);
197 
198  // Add a nullptr for each additional wait state after the first. Make sure
199  // not to add more than getMaxLookAhead() items to the list, since we
200  // truncate the list to that size right after this loop.
201  for (unsigned i = 1, e = std::min(NumWaitStates, getMaxLookAhead());
202  i < e; ++i) {
203  EmittedInstrs.push_front(nullptr);
204  }
205 
206  // getMaxLookahead() is the largest number of wait states we will ever need
207  // to insert, so there is no point in keeping track of more than that many
208  // wait states.
209  EmittedInstrs.resize(getMaxLookAhead());
210 
211  CurrCycleInstr = nullptr;
212 }
213 
215  llvm_unreachable("hazard recognizer does not support bottom-up scheduling.");
216 }
217 
218 //===----------------------------------------------------------------------===//
219 // Helper Functions
220 //===----------------------------------------------------------------------===//
221 
222 int GCNHazardRecognizer::getWaitStatesSince(
223  function_ref<bool(MachineInstr *)> IsHazard) {
224  int WaitStates = 0;
225  for (MachineInstr *MI : EmittedInstrs) {
226  if (MI) {
227  if (IsHazard(MI))
228  return WaitStates;
229 
230  unsigned Opcode = MI->getOpcode();
231  if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF ||
232  Opcode == AMDGPU::INLINEASM)
233  continue;
234  }
235  ++WaitStates;
236  }
238 }
239 
240 int GCNHazardRecognizer::getWaitStatesSinceDef(
241  unsigned Reg, function_ref<bool(MachineInstr *)> IsHazardDef) {
242  const SIRegisterInfo *TRI = ST.getRegisterInfo();
243 
244  auto IsHazardFn = [IsHazardDef, TRI, Reg] (MachineInstr *MI) {
245  return IsHazardDef(MI) && MI->modifiesRegister(Reg, TRI);
246  };
247 
248  return getWaitStatesSince(IsHazardFn);
249 }
250 
251 int GCNHazardRecognizer::getWaitStatesSinceSetReg(
252  function_ref<bool(MachineInstr *)> IsHazard) {
253  auto IsHazardFn = [IsHazard] (MachineInstr *MI) {
254  return isSSetReg(MI->getOpcode()) && IsHazard(MI);
255  };
256 
257  return getWaitStatesSince(IsHazardFn);
258 }
259 
260 //===----------------------------------------------------------------------===//
261 // No-op Hazard Detection
262 //===----------------------------------------------------------------------===//
263 
264 static void addRegUnits(const SIRegisterInfo &TRI,
265  BitVector &BV, unsigned Reg) {
266  for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI)
267  BV.set(*RUI);
268 }
269 
270 static void addRegsToSet(const SIRegisterInfo &TRI,
272  BitVector &Set) {
273  for (const MachineOperand &Op : Ops) {
274  if (Op.isReg())
275  addRegUnits(TRI, Set, Op.getReg());
276  }
277 }
278 
279 void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
280  // XXX: Do we need to worry about implicit operands
281  addRegsToSet(TRI, MI.defs(), ClauseDefs);
282  addRegsToSet(TRI, MI.uses(), ClauseUses);
283 }
284 
285 int GCNHazardRecognizer::checkSMEMSoftClauseHazards(MachineInstr *SMEM) {
286  // SMEM soft clause are only present on VI+, and only matter if xnack is
287  // enabled.
288  if (!ST.isXNACKEnabled())
289  return 0;
290 
291  resetClause();
292 
293  // A soft-clause is any group of consecutive SMEM instructions. The
294  // instructions in this group may return out of order and/or may be
295  // replayed (i.e. the same instruction issued more than once).
296  //
297  // In order to handle these situations correctly we need to make sure
298  // that when a clause has more than one instruction, no instruction in the
299  // clause writes to a register that is read another instruction in the clause
300  // (including itself). If we encounter this situaion, we need to break the
301  // clause by inserting a non SMEM instruction.
302 
303  for (MachineInstr *MI : EmittedInstrs) {
304  // When we hit a non-SMEM instruction then we have passed the start of the
305  // clause and we can stop.
306  if (!MI || !SIInstrInfo::isSMRD(*MI))
307  break;
308 
309  addClauseInst(*MI);
310  }
311 
312  if (ClauseDefs.none())
313  return 0;
314 
315  // FIXME: When we support stores, we need to make sure not to put loads and
316  // stores in the same clause if they use the same address. For now, just
317  // start a new clause whenever we see a store.
318  if (SMEM->mayStore())
319  return 1;
320 
321  addClauseInst(*SMEM);
322 
323  // If the set of defs and uses intersect then we cannot add this instruction
324  // to the clause, so we have a hazard.
325  return ClauseDefs.anyCommon(ClauseUses) ? 1 : 0;
326 }
327 
328 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) {
329  const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
330  int WaitStatesNeeded = 0;
331 
332  WaitStatesNeeded = checkSMEMSoftClauseHazards(SMRD);
333 
334  // This SMRD hazard only affects SI.
336  return WaitStatesNeeded;
337 
338  // A read of an SGPR by SMRD instruction requires 4 wait states when the
339  // SGPR was written by a VALU instruction.
340  int SmrdSgprWaitStates = 4;
341  auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };
342  auto IsBufferHazardDefFn = [this] (MachineInstr *MI) { return TII.isSALU(*MI); };
343 
344  bool IsBufferSMRD = TII.isBufferSMRD(*SMRD);
345 
346  for (const MachineOperand &Use : SMRD->uses()) {
347  if (!Use.isReg())
348  continue;
349  int WaitStatesNeededForUse =
350  SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn);
351  WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
352 
353  // This fixes what appears to be undocumented hardware behavior in SI where
354  // s_mov writing a descriptor and s_buffer_load_dword reading the descriptor
355  // needs some number of nops in between. We don't know how many we need, but
356  // let's use 4. This wasn't discovered before probably because the only
357  // case when this happens is when we expand a 64-bit pointer into a full
358  // descriptor and use s_buffer_load_dword instead of s_load_dword, which was
359  // probably never encountered in the closed-source land.
360  if (IsBufferSMRD) {
361  int WaitStatesNeededForUse =
362  SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
363  IsBufferHazardDefFn);
364  WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
365  }
366  }
367 
368  return WaitStatesNeeded;
369 }
370 
371 int GCNHazardRecognizer::checkVMEMHazards(MachineInstr* VMEM) {
372  const SIInstrInfo *TII = ST.getInstrInfo();
373 
375  return 0;
376 
377  const SIRegisterInfo &TRI = TII->getRegisterInfo();
378 
379  // A read of an SGPR by a VMEM instruction requires 5 wait states when the
380  // SGPR was written by a VALU Instruction.
381  int VmemSgprWaitStates = 5;
382  int WaitStatesNeeded = 0;
383  auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
384 
385  for (const MachineOperand &Use : VMEM->uses()) {
386  if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
387  continue;
388 
389  int WaitStatesNeededForUse =
390  VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn);
391  WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
392  }
393  return WaitStatesNeeded;
394 }
395 
396 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) {
397  const SIRegisterInfo *TRI = ST.getRegisterInfo();
398  const SIInstrInfo *TII = ST.getInstrInfo();
399 
400  // Check for DPP VGPR read after VALU VGPR write and EXEC write.
401  int DppVgprWaitStates = 2;
402  int DppExecWaitStates = 5;
403  int WaitStatesNeeded = 0;
404  auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
405 
406  for (const MachineOperand &Use : DPP->uses()) {
407  if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
408  continue;
409  int WaitStatesNeededForUse =
410  DppVgprWaitStates - getWaitStatesSinceDef(Use.getReg());
411  WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
412  }
413 
414  WaitStatesNeeded = std::max(
415  WaitStatesNeeded,
416  DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn));
417 
418  return WaitStatesNeeded;
419 }
420 
421 int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) {
422  const SIInstrInfo *TII = ST.getInstrInfo();
423 
424  // v_div_fmas requires 4 wait states after a write to vcc from a VALU
425  // instruction.
426  const int DivFMasWaitStates = 4;
427  auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
428  int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn);
429 
430  return DivFMasWaitStates - WaitStatesNeeded;
431 }
432 
433 int GCNHazardRecognizer::checkGetRegHazards(MachineInstr *GetRegInstr) {
434  const SIInstrInfo *TII = ST.getInstrInfo();
435  unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr);
436 
437  const int GetRegWaitStates = 2;
438  auto IsHazardFn = [TII, GetRegHWReg] (MachineInstr *MI) {
439  return GetRegHWReg == getHWReg(TII, *MI);
440  };
441  int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
442 
443  return GetRegWaitStates - WaitStatesNeeded;
444 }
445 
446 int GCNHazardRecognizer::checkSetRegHazards(MachineInstr *SetRegInstr) {
447  const SIInstrInfo *TII = ST.getInstrInfo();
448  unsigned HWReg = getHWReg(TII, *SetRegInstr);
449 
450  const int SetRegWaitStates =
452  auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
453  return HWReg == getHWReg(TII, *MI);
454  };
455  int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
456  return SetRegWaitStates - WaitStatesNeeded;
457 }
458 
459 int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) {
460  if (!MI.mayStore())
461  return -1;
462 
463  const SIInstrInfo *TII = ST.getInstrInfo();
464  unsigned Opcode = MI.getOpcode();
465  const MCInstrDesc &Desc = MI.getDesc();
466 
467  int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
468  int VDataRCID = -1;
469  if (VDataIdx != -1)
470  VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
471 
472  if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
473  // There is no hazard if the instruction does not use vector regs
474  // (like wbinvl1)
475  if (VDataIdx == -1)
476  return -1;
477  // For MUBUF/MTBUF instructions this hazard only exists if the
478  // instruction is not using a register in the soffset field.
479  const MachineOperand *SOffset =
480  TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
481  // If we have no soffset operand, then assume this field has been
482  // hardcoded to zero.
483  if (AMDGPU::getRegBitWidth(VDataRCID) > 64 &&
484  (!SOffset || !SOffset->isReg()))
485  return VDataIdx;
486  }
487 
488  // MIMG instructions create a hazard if they don't use a 256-bit T# and
489  // the store size is greater than 8 bytes and they have more than two bits
490  // of their dmask set.
491  // All our MIMG definitions use a 256-bit T#, so we can skip checking for them.
492  if (TII->isMIMG(MI)) {
493  int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
494  assert(SRsrcIdx != -1 &&
495  AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);
496  (void)SRsrcIdx;
497  }
498 
499  if (TII->isFLAT(MI)) {
500  int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
501  if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
502  return DataIdx;
503  }
504 
505  return -1;
506 }
507 
508 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) {
509  // This checks for the hazard where VMEM instructions that store more than
510  // 8 bytes can have there store data over written by the next instruction.
511  if (!ST.has12DWordStoreHazard())
512  return 0;
513 
514  const SIRegisterInfo *TRI = ST.getRegisterInfo();
515  const MachineRegisterInfo &MRI = VALU->getParent()->getParent()->getRegInfo();
516 
517  const int VALUWaitStates = 1;
518  int WaitStatesNeeded = 0;
519 
520  for (const MachineOperand &Def : VALU->defs()) {
521  if (!TRI->isVGPR(MRI, Def.getReg()))
522  continue;
523  unsigned Reg = Def.getReg();
524  auto IsHazardFn = [this, Reg, TRI] (MachineInstr *MI) {
525  int DataIdx = createsVALUHazard(*MI);
526  return DataIdx >= 0 &&
527  TRI->regsOverlap(MI->getOperand(DataIdx).getReg(), Reg);
528  };
529  int WaitStatesNeededForDef =
530  VALUWaitStates - getWaitStatesSince(IsHazardFn);
531  WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForDef);
532  }
533  return WaitStatesNeeded;
534 }
535 
536 int GCNHazardRecognizer::checkRWLaneHazards(MachineInstr *RWLane) {
537  const SIInstrInfo *TII = ST.getInstrInfo();
538  const SIRegisterInfo *TRI = ST.getRegisterInfo();
539  const MachineRegisterInfo &MRI =
540  RWLane->getParent()->getParent()->getRegInfo();
541 
542  const MachineOperand *LaneSelectOp =
543  TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);
544 
545  if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg()))
546  return 0;
547 
548  unsigned LaneSelectReg = LaneSelectOp->getReg();
549  auto IsHazardFn = [TII] (MachineInstr *MI) {
550  return TII->isVALU(*MI);
551  };
552 
553  const int RWLaneWaitStates = 4;
554  int WaitStatesSince = getWaitStatesSinceDef(LaneSelectReg, IsHazardFn);
555  return RWLaneWaitStates - WaitStatesSince;
556 }
557 
558 int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) {
560  return 0;
561 
562  const SIInstrInfo *TII = ST.getInstrInfo();
563 
564  const int RFEWaitStates = 1;
565 
566  auto IsHazardFn = [TII] (MachineInstr *MI) {
567  return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;
568  };
569  int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
570  return RFEWaitStates - WaitStatesNeeded;
571 }
572 
573 int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {
574  if (MI->isDebugValue())
575  return 0;
576 
577  const SIRegisterInfo *TRI = ST.getRegisterInfo();
578  if (!ST.hasSMovFedHazard())
579  return 0;
580 
581  // Check for any instruction reading an SGPR after a write from
582  // s_mov_fed_b32.
583  int MovFedWaitStates = 1;
584  int WaitStatesNeeded = 0;
585 
586  for (const MachineOperand &Use : MI->uses()) {
587  if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
588  continue;
589  auto IsHazardFn = [] (MachineInstr *MI) {
590  return MI->getOpcode() == AMDGPU::S_MOV_FED_B32;
591  };
592  int WaitStatesNeededForUse =
593  MovFedWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardFn);
594  WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
595  }
596 
597  return WaitStatesNeeded;
598 }
599 
600 int GCNHazardRecognizer::checkReadM0Hazards(MachineInstr *MI) {
601  if (!ST.hasReadM0Hazard())
602  return 0;
603 
604  const SIInstrInfo *TII = ST.getInstrInfo();
605  int SMovRelWaitStates = 1;
606  auto IsHazardFn = [TII] (MachineInstr *MI) {
607  return TII->isSALU(*MI);
608  };
609  return SMovRelWaitStates - getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn);
610 }
static bool isSMovRel(unsigned Opcode)
BitVector & set()
Definition: BitVector.h:398
Interface definition for SIRegisterInfo.
Generation getGeneration() const
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
AMDGPU specific subclass of TargetSubtarget.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:365
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:528
const SIInstrInfo * getInstrInfo() const override
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:89
static bool isRFE(unsigned Opcode)
static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV, unsigned Reg)
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:411
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:146
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:456
const HexagonInstrInfo * TII
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:440
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:299
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:634
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:395
static bool isSSetReg(unsigned Opcode)
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
unsigned PreEmitNoops(SUnit *SU) override
PreEmitNoops - This callback is invoked prior to emitting an instruction.
bool hasSMovFedHazard() const
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
unsigned MaxLookAhead
MaxLookAhead - Indicate the number of cycles in the scoreboard state.
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:512
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:639
static void addRegsToSet(const SIRegisterInfo &TRI, iterator_range< MachineInstr::const_mop_iterator > Ops, BitVector &Set)
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:378
unsigned const MachineRegisterInfo * MRI
bool anyCommon(const BitVector &RHS) const
Test if any common bits are set.
Definition: BitVector.h:507
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:354
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumWaitStates(const MachineInstr &MI) const
Return the number of wait states that result from executing this instruction.
bool has12DWordStoreHazard() const
const SIRegisterInfo * getRegisterInfo() const override
bool isDebugValue() const
Definition: MachineInstr.h:816
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:291
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
MachineOperand class - Representation of each machine instruction operand.
GCNHazardRecognizer(const MachineFunction &MF)
int64_t getImm() const
A range adaptor for a pair of iterators.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
static bool isRWLane(unsigned Opcode)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:202
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Interface definition for SIInstrInfo.
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:403
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:76
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:307
bool hasReadM0Hazard() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isBufferSMRD(const MachineInstr &MI) const
Definition: SIInstrInfo.h:419
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSGetReg(unsigned Opcode)
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
IRTranslator LLVM IR MI
static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
bool isXNACKEnabled() const
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:247
static bool isDivFMas(unsigned Opcode)