LLVM  8.0.0svn
GCNRegPressure.cpp
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1 //===- GCNRegPressure.cpp -------------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "GCNRegPressure.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
13 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/Config/llvm-config.h"
23 #include "llvm/MC/LaneBitmask.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
28 #include <algorithm>
29 #include <cassert>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "machine-scheduler"
34 
35 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
38  const LiveIntervals &LIS,
39  const MachineRegisterInfo &MRI) {
40  dbgs() << "Live regs at " << SI << ": "
41  << *LIS.getInstructionFromIndex(SI);
42  unsigned Num = 0;
43  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
44  const unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
45  if (!LIS.hasInterval(Reg))
46  continue;
47  const auto &LI = LIS.getInterval(Reg);
48  if (LI.hasSubRanges()) {
49  bool firstTime = true;
50  for (const auto &S : LI.subranges()) {
51  if (!S.liveAt(SI)) continue;
52  if (firstTime) {
53  dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
54  << '\n';
55  firstTime = false;
56  }
57  dbgs() << " " << S << '\n';
58  ++Num;
59  }
60  } else if (LI.liveAt(SI)) {
61  dbgs() << " " << LI << '\n';
62  ++Num;
63  }
64  }
65  if (!Num) dbgs() << " <none>\n";
66 }
67 
68 static bool isEqual(const GCNRPTracker::LiveRegSet &S1,
69  const GCNRPTracker::LiveRegSet &S2) {
70  if (S1.size() != S2.size())
71  return false;
72 
73  for (const auto &P : S1) {
74  auto I = S2.find(P.first);
75  if (I == S2.end() || I->second != P.second)
76  return false;
77  }
78  return true;
79 }
80 #endif
81 
82 ///////////////////////////////////////////////////////////////////////////////
83 // GCNRegPressure
84 
85 unsigned GCNRegPressure::getRegKind(unsigned Reg,
86  const MachineRegisterInfo &MRI) {
88  const auto RC = MRI.getRegClass(Reg);
89  auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
90  return STI->isSGPRClass(RC) ?
91  (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
92  (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
93 }
94 
95 void GCNRegPressure::inc(unsigned Reg,
96  LaneBitmask PrevMask,
97  LaneBitmask NewMask,
98  const MachineRegisterInfo &MRI) {
99  if (NewMask == PrevMask)
100  return;
101 
102  int Sign = 1;
103  if (NewMask < PrevMask) {
104  std::swap(NewMask, PrevMask);
105  Sign = -1;
106  }
107 #ifndef NDEBUG
108  const auto MaxMask = MRI.getMaxLaneMaskForVReg(Reg);
109 #endif
110  switch (auto Kind = getRegKind(Reg, MRI)) {
111  case SGPR32:
112  case VGPR32:
113  assert(PrevMask.none() && NewMask == MaxMask);
114  Value[Kind] += Sign;
115  break;
116 
117  case SGPR_TUPLE:
118  case VGPR_TUPLE:
119  assert(NewMask < MaxMask || NewMask == MaxMask);
120  assert(PrevMask < NewMask);
121 
122  Value[Kind == SGPR_TUPLE ? SGPR32 : VGPR32] +=
123  Sign * (~PrevMask & NewMask).getNumLanes();
124 
125  if (PrevMask.none()) {
126  assert(NewMask.any());
127  Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight();
128  }
129  break;
130 
131  default: llvm_unreachable("Unknown register kind");
132  }
133 }
134 
136  const GCNRegPressure& O,
137  unsigned MaxOccupancy) const {
138  const auto SGPROcc = std::min(MaxOccupancy,
140  const auto VGPROcc = std::min(MaxOccupancy,
142  const auto OtherSGPROcc = std::min(MaxOccupancy,
144  const auto OtherVGPROcc = std::min(MaxOccupancy,
146 
147  const auto Occ = std::min(SGPROcc, VGPROcc);
148  const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
149  if (Occ != OtherOcc)
150  return Occ > OtherOcc;
151 
152  bool SGPRImportant = SGPROcc < VGPROcc;
153  const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
154 
155  // if both pressures disagree on what is more important compare vgprs
156  if (SGPRImportant != OtherSGPRImportant) {
157  SGPRImportant = false;
158  }
159 
160  // compare large regs pressure
161  bool SGPRFirst = SGPRImportant;
162  for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
163  if (SGPRFirst) {
164  auto SW = getSGPRTuplesWeight();
165  auto OtherSW = O.getSGPRTuplesWeight();
166  if (SW != OtherSW)
167  return SW < OtherSW;
168  } else {
169  auto VW = getVGPRTuplesWeight();
170  auto OtherVW = O.getVGPRTuplesWeight();
171  if (VW != OtherVW)
172  return VW < OtherVW;
173  }
174  }
175  return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
176  (getVGPRNum() < O.getVGPRNum());
177 }
178 
179 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
182  OS << "VGPRs: " << getVGPRNum();
183  if (ST) OS << "(O" << ST->getOccupancyWithNumVGPRs(getVGPRNum()) << ')';
184  OS << ", SGPRs: " << getSGPRNum();
185  if (ST) OS << "(O" << ST->getOccupancyWithNumSGPRs(getSGPRNum()) << ')';
186  OS << ", LVGPR WT: " << getVGPRTuplesWeight()
187  << ", LSGPR WT: " << getSGPRTuplesWeight();
188  if (ST) OS << " -> Occ: " << getOccupancy(*ST);
189  OS << '\n';
190 }
191 #endif
192 
194  const MachineRegisterInfo &MRI) {
195  assert(MO.isDef() && MO.isReg() &&
197 
198  // We don't rely on read-undef flag because in case of tentative schedule
199  // tracking it isn't set correctly yet. This works correctly however since
200  // use mask has been tracked before using LIS.
201  return MO.getSubReg() == 0 ?
202  MRI.getMaxLaneMaskForVReg(MO.getReg()) :
204 }
205 
207  const MachineRegisterInfo &MRI,
208  const LiveIntervals &LIS) {
209  assert(MO.isUse() && MO.isReg() &&
211 
212  if (auto SubReg = MO.getSubReg())
214 
215  auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
216  if (MaxMask == LaneBitmask::getLane(0)) // cannot have subregs
217  return MaxMask;
218 
219  // For a tentative schedule LIS isn't updated yet but livemask should remain
220  // the same on any schedule. Subreg defs can be reordered but they all must
221  // dominate uses anyway.
222  auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
223  return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
224 }
225 
228  const MachineRegisterInfo &MRI) {
230  for (const auto &MO : MI.operands()) {
231  if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
232  continue;
233  if (!MO.isUse() || !MO.readsReg())
234  continue;
235 
236  auto const UsedMask = getUsedRegMask(MO, MRI, LIS);
237 
238  auto Reg = MO.getReg();
239  auto I = std::find_if(Res.begin(), Res.end(), [Reg](const RegisterMaskPair &RM) {
240  return RM.RegUnit == Reg;
241  });
242  if (I != Res.end())
243  I->LaneMask |= UsedMask;
244  else
245  Res.push_back(RegisterMaskPair(Reg, UsedMask));
246  }
247  return Res;
248 }
249 
250 ///////////////////////////////////////////////////////////////////////////////
251 // GCNRPTracker
252 
254  SlotIndex SI,
255  const LiveIntervals &LIS,
256  const MachineRegisterInfo &MRI) {
257  LaneBitmask LiveMask;
258  const auto &LI = LIS.getInterval(Reg);
259  if (LI.hasSubRanges()) {
260  for (const auto &S : LI.subranges())
261  if (S.liveAt(SI)) {
262  LiveMask |= S.LaneMask;
263  assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
264  LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
265  }
266  } else if (LI.liveAt(SI)) {
267  LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
268  }
269  return LiveMask;
270 }
271 
273  const LiveIntervals &LIS,
274  const MachineRegisterInfo &MRI) {
275  GCNRPTracker::LiveRegSet LiveRegs;
276  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
278  if (!LIS.hasInterval(Reg))
279  continue;
280  auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
281  if (LiveMask.any())
282  LiveRegs[Reg] = LiveMask;
283  }
284  return LiveRegs;
285 }
286 
288  const LiveRegSet *LiveRegsCopy,
289  bool After) {
290  const MachineFunction &MF = *MI.getMF();
291  MRI = &MF.getRegInfo();
292  if (LiveRegsCopy) {
293  if (&LiveRegs != LiveRegsCopy)
294  LiveRegs = *LiveRegsCopy;
295  } else {
296  LiveRegs = After ? getLiveRegsAfter(MI, LIS)
297  : getLiveRegsBefore(MI, LIS);
298  }
299 
300  MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
301 }
302 
304  const LiveRegSet *LiveRegsCopy) {
305  GCNRPTracker::reset(MI, LiveRegsCopy, true);
306 }
307 
309  assert(MRI && "call reset first");
310 
311  LastTrackedMI = &MI;
312 
313  if (MI.isDebugInstr())
314  return;
315 
316  auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
317 
318  // calc pressure at the MI (defs + uses)
319  auto AtMIPressure = CurPressure;
320  for (const auto &U : RegUses) {
321  auto LiveMask = LiveRegs[U.RegUnit];
322  AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
323  }
324  // update max pressure
325  MaxPressure = max(AtMIPressure, MaxPressure);
326 
327  for (const auto &MO : MI.defs()) {
328  if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
329  MO.isDead())
330  continue;
331 
332  auto Reg = MO.getReg();
333  auto I = LiveRegs.find(Reg);
334  if (I == LiveRegs.end())
335  continue;
336  auto &LiveMask = I->second;
337  auto PrevMask = LiveMask;
338  LiveMask &= ~getDefRegMask(MO, *MRI);
339  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
340  if (LiveMask.none())
341  LiveRegs.erase(I);
342  }
343  for (const auto &U : RegUses) {
344  auto &LiveMask = LiveRegs[U.RegUnit];
345  auto PrevMask = LiveMask;
346  LiveMask |= U.LaneMask;
347  CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
348  }
349  assert(CurPressure == getRegPressure(*MRI, LiveRegs));
350 }
351 
353  const LiveRegSet *LiveRegsCopy) {
354  MRI = &MI.getParent()->getParent()->getRegInfo();
355  LastTrackedMI = nullptr;
356  MBBEnd = MI.getParent()->end();
357  NextMI = &MI;
358  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
359  if (NextMI == MBBEnd)
360  return false;
361  GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
362  return true;
363 }
364 
366  assert(MRI && "call reset first");
367 
368  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
369  if (NextMI == MBBEnd)
370  return false;
371 
372  SlotIndex SI = LIS.getInstructionIndex(*NextMI).getBaseIndex();
373  assert(SI.isValid());
374 
375  // Remove dead registers or mask bits.
376  for (auto &It : LiveRegs) {
377  const LiveInterval &LI = LIS.getInterval(It.first);
378  if (LI.hasSubRanges()) {
379  for (const auto &S : LI.subranges()) {
380  if (!S.liveAt(SI)) {
381  auto PrevMask = It.second;
382  It.second &= ~S.LaneMask;
383  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
384  }
385  }
386  } else if (!LI.liveAt(SI)) {
387  auto PrevMask = It.second;
388  It.second = LaneBitmask::getNone();
389  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
390  }
391  if (It.second.none())
392  LiveRegs.erase(It.first);
393  }
394 
395  MaxPressure = max(MaxPressure, CurPressure);
396 
397  return true;
398 }
399 
401  LastTrackedMI = &*NextMI++;
402 
403  // Add new registers or mask bits.
404  for (const auto &MO : LastTrackedMI->defs()) {
405  if (!MO.isReg())
406  continue;
407  unsigned Reg = MO.getReg();
409  continue;
410  auto &LiveMask = LiveRegs[Reg];
411  auto PrevMask = LiveMask;
412  LiveMask |= getDefRegMask(MO, *MRI);
413  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
414  }
415 
416  MaxPressure = max(MaxPressure, CurPressure);
417 }
418 
420  // If we have just called reset live set is actual.
421  if ((NextMI == MBBEnd) || (LastTrackedMI && !advanceBeforeNext()))
422  return false;
423  advanceToNext();
424  return true;
425 }
426 
428  while (NextMI != End)
429  if (!advance()) return false;
430  return true;
431 }
432 
435  const LiveRegSet *LiveRegsCopy) {
436  reset(*Begin, LiveRegsCopy);
437  return advance(End);
438 }
439 
440 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
442 static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
443  const GCNRPTracker::LiveRegSet &TrackedLR,
444  const TargetRegisterInfo *TRI) {
445  for (auto const &P : TrackedLR) {
446  auto I = LISLR.find(P.first);
447  if (I == LISLR.end()) {
448  dbgs() << " " << printReg(P.first, TRI)
449  << ":L" << PrintLaneMask(P.second)
450  << " isn't found in LIS reported set\n";
451  }
452  else if (I->second != P.second) {
453  dbgs() << " " << printReg(P.first, TRI)
454  << " masks doesn't match: LIS reported "
455  << PrintLaneMask(I->second)
456  << ", tracked "
457  << PrintLaneMask(P.second)
458  << '\n';
459  }
460  }
461  for (auto const &P : LISLR) {
462  auto I = TrackedLR.find(P.first);
463  if (I == TrackedLR.end()) {
464  dbgs() << " " << printReg(P.first, TRI)
465  << ":L" << PrintLaneMask(P.second)
466  << " isn't found in tracked set\n";
467  }
468  }
469 }
470 
472  const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
473  const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
474  const auto &TrackedLR = LiveRegs;
475 
476  if (!isEqual(LISLR, TrackedLR)) {
477  dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
478  " LIS reported livesets mismatch:\n";
479  printLivesAt(SI, LIS, *MRI);
480  reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
481  return false;
482  }
483 
484  auto LISPressure = getRegPressure(*MRI, LISLR);
485  if (LISPressure != CurPressure) {
486  dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: ";
487  CurPressure.print(dbgs());
488  dbgs() << "LIS rpt: ";
489  LISPressure.print(dbgs());
490  return false;
491  }
492  return true;
493 }
494 
496  const MachineRegisterInfo &MRI) {
498  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
499  unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
500  auto It = LiveRegs.find(Reg);
501  if (It != LiveRegs.end() && It->second.any())
502  OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
503  << PrintLaneMask(It->second);
504  }
505  OS << '\n';
506 }
507 #endif
Interface definition for SIRegisterInfo.
A common definition of LaneBitmask for use in TableGen and CodeGen.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
AMDGPU specific subclass of TargetSubtarget.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
static void printLiveRegs(raw_ostream &OS, const LiveRegSet &LiveRegs, const MachineRegisterInfo &MRI)
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
This class represents lattice values for constants.
Definition: AllocatorList.h:24
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
unsigned getSGPRTuplesWeight() const
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:638
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
unsigned Reg
unsigned getSubReg() const
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:152
unsigned const TargetRegisterInfo * TRI
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
static LaneBitmask getDefRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI)
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:723
unsigned SubReg
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:751
#define LLVM_DUMP_METHOD
Definition: Compiler.h:74
unsigned getOccupancy(const GCNSubtarget &ST) const
bool isSGPRClass(const TargetRegisterClass *RC) const
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
unsigned getVGPRTuplesWeight() const
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
static constexpr LaneBitmask getLane(unsigned Lane)
Definition: LaneBitmask.h:85
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:176
#define P(N)
static bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool hasInterval(unsigned Reg) const
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:389
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
unsigned getSGPRNum() const
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
constexpr bool none() const
Definition: LaneBitmask.h:52
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:481
unsigned size() const
Definition: DenseMap.h:126
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1208
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
Definition: MachineInstr.h:999
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static SmallVector< RegisterMaskPair, 8 > collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
static LLVM_DUMP_METHOD void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedLR, const TargetRegisterInfo *TRI)
void printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
static LaneBitmask getUsedRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI, const LiveIntervals &LIS)
MachineOperand class - Representation of each machine instruction operand.
unsigned getVGPRNum() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:941
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
#define I(x, y, z)
Definition: MD5.cpp:58
constexpr bool any() const
Definition: LaneBitmask.h:53
iterator end()
Definition: DenseMap.h:109
bool isReg() const
isReg - Tests if this is a MO_Register operand.
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void print(raw_ostream &OS, const GCNSubtarget *ST=nullptr) const
LLVM Value Representation.
Definition: Value.h:73
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
unsigned getWeight() const
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
void recede(const MachineInstr &MI)
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)