LLVM  12.0.0git
GCNRegPressure.cpp
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1 //===- GCNRegPressure.cpp -------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the GCNRegPressure class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "GCNRegPressure.h"
15 #include "AMDGPUSubtarget.h"
16 #include "SIRegisterInfo.h"
17 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Config/llvm-config.h"
27 #include "llvm/MC/LaneBitmask.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
32 #include <algorithm>
33 #include <cassert>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "machine-scheduler"
38 
39 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
42  const LiveIntervals &LIS,
43  const MachineRegisterInfo &MRI) {
44  dbgs() << "Live regs at " << SI << ": "
45  << *LIS.getInstructionFromIndex(SI);
46  unsigned Num = 0;
47  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
48  const unsigned Reg = Register::index2VirtReg(I);
49  if (!LIS.hasInterval(Reg))
50  continue;
51  const auto &LI = LIS.getInterval(Reg);
52  if (LI.hasSubRanges()) {
53  bool firstTime = true;
54  for (const auto &S : LI.subranges()) {
55  if (!S.liveAt(SI)) continue;
56  if (firstTime) {
57  dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
58  << '\n';
59  firstTime = false;
60  }
61  dbgs() << " " << S << '\n';
62  ++Num;
63  }
64  } else if (LI.liveAt(SI)) {
65  dbgs() << " " << LI << '\n';
66  ++Num;
67  }
68  }
69  if (!Num) dbgs() << " <none>\n";
70 }
71 #endif
72 
74  const GCNRPTracker::LiveRegSet &S2) {
75  if (S1.size() != S2.size())
76  return false;
77 
78  for (const auto &P : S1) {
79  auto I = S2.find(P.first);
80  if (I == S2.end() || I->second != P.second)
81  return false;
82  }
83  return true;
84 }
85 
86 
87 ///////////////////////////////////////////////////////////////////////////////
88 // GCNRegPressure
89 
90 unsigned GCNRegPressure::getRegKind(unsigned Reg,
91  const MachineRegisterInfo &MRI) {
93  const auto RC = MRI.getRegClass(Reg);
94  auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
95  return STI->isSGPRClass(RC) ?
96  (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
97  STI->hasAGPRs(RC) ?
98  (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
99  (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
100 }
101 
102 void GCNRegPressure::inc(unsigned Reg,
103  LaneBitmask PrevMask,
104  LaneBitmask NewMask,
105  const MachineRegisterInfo &MRI) {
106  if (SIRegisterInfo::getNumCoveredRegs(NewMask) ==
108  return;
109 
110  int Sign = 1;
111  if (NewMask < PrevMask) {
112  std::swap(NewMask, PrevMask);
113  Sign = -1;
114  }
115 
116  switch (auto Kind = getRegKind(Reg, MRI)) {
117  case SGPR32:
118  case VGPR32:
119  case AGPR32:
120  Value[Kind] += Sign;
121  break;
122 
123  case SGPR_TUPLE:
124  case VGPR_TUPLE:
125  case AGPR_TUPLE:
126  assert(PrevMask < NewMask);
127 
128  Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] +=
129  Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
130 
131  if (PrevMask.none()) {
132  assert(NewMask.any());
133  Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight();
134  }
135  break;
136 
137  default: llvm_unreachable("Unknown register kind");
138  }
139 }
140 
142  const GCNRegPressure& O,
143  unsigned MaxOccupancy) const {
144  const auto SGPROcc = std::min(MaxOccupancy,
146  const auto VGPROcc = std::min(MaxOccupancy,
148  const auto OtherSGPROcc = std::min(MaxOccupancy,
150  const auto OtherVGPROcc = std::min(MaxOccupancy,
152 
153  const auto Occ = std::min(SGPROcc, VGPROcc);
154  const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
155  if (Occ != OtherOcc)
156  return Occ > OtherOcc;
157 
158  bool SGPRImportant = SGPROcc < VGPROcc;
159  const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
160 
161  // if both pressures disagree on what is more important compare vgprs
162  if (SGPRImportant != OtherSGPRImportant) {
163  SGPRImportant = false;
164  }
165 
166  // compare large regs pressure
167  bool SGPRFirst = SGPRImportant;
168  for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
169  if (SGPRFirst) {
170  auto SW = getSGPRTuplesWeight();
171  auto OtherSW = O.getSGPRTuplesWeight();
172  if (SW != OtherSW)
173  return SW < OtherSW;
174  } else {
175  auto VW = getVGPRTuplesWeight();
176  auto OtherVW = O.getVGPRTuplesWeight();
177  if (VW != OtherVW)
178  return VW < OtherVW;
179  }
180  }
181  return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
182  (getVGPRNum() < O.getVGPRNum());
183 }
184 
185 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
188  OS << "VGPRs: " << Value[VGPR32] << ' ';
189  OS << "AGPRs: " << Value[AGPR32];
190  if (ST) OS << "(O" << ST->getOccupancyWithNumVGPRs(getVGPRNum()) << ')';
191  OS << ", SGPRs: " << getSGPRNum();
192  if (ST) OS << "(O" << ST->getOccupancyWithNumSGPRs(getSGPRNum()) << ')';
193  OS << ", LVGPR WT: " << getVGPRTuplesWeight()
194  << ", LSGPR WT: " << getSGPRTuplesWeight();
195  if (ST) OS << " -> Occ: " << getOccupancy(*ST);
196  OS << '\n';
197 }
198 #endif
199 
201  const MachineRegisterInfo &MRI) {
202  assert(MO.isDef() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
203 
204  // We don't rely on read-undef flag because in case of tentative schedule
205  // tracking it isn't set correctly yet. This works correctly however since
206  // use mask has been tracked before using LIS.
207  return MO.getSubReg() == 0 ?
208  MRI.getMaxLaneMaskForVReg(MO.getReg()) :
210 }
211 
213  const MachineRegisterInfo &MRI,
214  const LiveIntervals &LIS) {
215  assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
216 
217  if (auto SubReg = MO.getSubReg())
219 
220  auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
221  if (SIRegisterInfo::getNumCoveredRegs(MaxMask) > 1) // cannot have subregs
222  return MaxMask;
223 
224  // For a tentative schedule LIS isn't updated yet but livemask should remain
225  // the same on any schedule. Subreg defs can be reordered but they all must
226  // dominate uses anyway.
227  auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
228  return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
229 }
230 
233  const MachineRegisterInfo &MRI) {
235  for (const auto &MO : MI.operands()) {
236  if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
237  continue;
238  if (!MO.isUse() || !MO.readsReg())
239  continue;
240 
241  auto const UsedMask = getUsedRegMask(MO, MRI, LIS);
242 
243  auto Reg = MO.getReg();
244  auto I = std::find_if(Res.begin(), Res.end(), [Reg](const RegisterMaskPair &RM) {
245  return RM.RegUnit == Reg;
246  });
247  if (I != Res.end())
248  I->LaneMask |= UsedMask;
249  else
250  Res.push_back(RegisterMaskPair(Reg, UsedMask));
251  }
252  return Res;
253 }
254 
255 ///////////////////////////////////////////////////////////////////////////////
256 // GCNRPTracker
257 
259  SlotIndex SI,
260  const LiveIntervals &LIS,
261  const MachineRegisterInfo &MRI) {
262  LaneBitmask LiveMask;
263  const auto &LI = LIS.getInterval(Reg);
264  if (LI.hasSubRanges()) {
265  for (const auto &S : LI.subranges())
266  if (S.liveAt(SI)) {
267  LiveMask |= S.LaneMask;
268  assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
269  LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
270  }
271  } else if (LI.liveAt(SI)) {
272  LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
273  }
274  return LiveMask;
275 }
276 
278  const LiveIntervals &LIS,
279  const MachineRegisterInfo &MRI) {
280  GCNRPTracker::LiveRegSet LiveRegs;
281  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
282  auto Reg = Register::index2VirtReg(I);
283  if (!LIS.hasInterval(Reg))
284  continue;
285  auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
286  if (LiveMask.any())
287  LiveRegs[Reg] = LiveMask;
288  }
289  return LiveRegs;
290 }
291 
293  const LiveRegSet *LiveRegsCopy,
294  bool After) {
295  const MachineFunction &MF = *MI.getMF();
296  MRI = &MF.getRegInfo();
297  if (LiveRegsCopy) {
298  if (&LiveRegs != LiveRegsCopy)
299  LiveRegs = *LiveRegsCopy;
300  } else {
301  LiveRegs = After ? getLiveRegsAfter(MI, LIS)
302  : getLiveRegsBefore(MI, LIS);
303  }
304 
305  MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
306 }
307 
309  const LiveRegSet *LiveRegsCopy) {
310  GCNRPTracker::reset(MI, LiveRegsCopy, true);
311 }
312 
314  assert(MRI && "call reset first");
315 
316  LastTrackedMI = &MI;
317 
318  if (MI.isDebugInstr())
319  return;
320 
321  auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
322 
323  // calc pressure at the MI (defs + uses)
324  auto AtMIPressure = CurPressure;
325  for (const auto &U : RegUses) {
326  auto LiveMask = LiveRegs[U.RegUnit];
327  AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
328  }
329  // update max pressure
330  MaxPressure = max(AtMIPressure, MaxPressure);
331 
332  for (const auto &MO : MI.operands()) {
333  if (!MO.isReg() || !MO.isDef() ||
334  !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
335  continue;
336 
337  auto Reg = MO.getReg();
338  auto I = LiveRegs.find(Reg);
339  if (I == LiveRegs.end())
340  continue;
341  auto &LiveMask = I->second;
342  auto PrevMask = LiveMask;
343  LiveMask &= ~getDefRegMask(MO, *MRI);
344  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
345  if (LiveMask.none())
346  LiveRegs.erase(I);
347  }
348  for (const auto &U : RegUses) {
349  auto &LiveMask = LiveRegs[U.RegUnit];
350  auto PrevMask = LiveMask;
351  LiveMask |= U.LaneMask;
352  CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
353  }
354  assert(CurPressure == getRegPressure(*MRI, LiveRegs));
355 }
356 
358  const LiveRegSet *LiveRegsCopy) {
359  MRI = &MI.getParent()->getParent()->getRegInfo();
360  LastTrackedMI = nullptr;
361  MBBEnd = MI.getParent()->end();
362  NextMI = &MI;
363  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
364  if (NextMI == MBBEnd)
365  return false;
366  GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
367  return true;
368 }
369 
371  assert(MRI && "call reset first");
372 
373  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
374  if (NextMI == MBBEnd)
375  return false;
376 
377  SlotIndex SI = LIS.getInstructionIndex(*NextMI).getBaseIndex();
378  assert(SI.isValid());
379 
380  // Remove dead registers or mask bits.
381  for (auto &It : LiveRegs) {
382  const LiveInterval &LI = LIS.getInterval(It.first);
383  if (LI.hasSubRanges()) {
384  for (const auto &S : LI.subranges()) {
385  if (!S.liveAt(SI)) {
386  auto PrevMask = It.second;
387  It.second &= ~S.LaneMask;
388  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
389  }
390  }
391  } else if (!LI.liveAt(SI)) {
392  auto PrevMask = It.second;
393  It.second = LaneBitmask::getNone();
394  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
395  }
396  if (It.second.none())
397  LiveRegs.erase(It.first);
398  }
399 
400  MaxPressure = max(MaxPressure, CurPressure);
401 
402  return true;
403 }
404 
406  LastTrackedMI = &*NextMI++;
407 
408  // Add new registers or mask bits.
409  for (const auto &MO : LastTrackedMI->operands()) {
410  if (!MO.isReg() || !MO.isDef())
411  continue;
412  Register Reg = MO.getReg();
413  if (!Register::isVirtualRegister(Reg))
414  continue;
415  auto &LiveMask = LiveRegs[Reg];
416  auto PrevMask = LiveMask;
417  LiveMask |= getDefRegMask(MO, *MRI);
418  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
419  }
420 
421  MaxPressure = max(MaxPressure, CurPressure);
422 }
423 
425  // If we have just called reset live set is actual.
426  if ((NextMI == MBBEnd) || (LastTrackedMI && !advanceBeforeNext()))
427  return false;
428  advanceToNext();
429  return true;
430 }
431 
433  while (NextMI != End)
434  if (!advance()) return false;
435  return true;
436 }
437 
440  const LiveRegSet *LiveRegsCopy) {
441  reset(*Begin, LiveRegsCopy);
442  return advance(End);
443 }
444 
445 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
447 static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
448  const GCNRPTracker::LiveRegSet &TrackedLR,
449  const TargetRegisterInfo *TRI) {
450  for (auto const &P : TrackedLR) {
451  auto I = LISLR.find(P.first);
452  if (I == LISLR.end()) {
453  dbgs() << " " << printReg(P.first, TRI)
454  << ":L" << PrintLaneMask(P.second)
455  << " isn't found in LIS reported set\n";
456  }
457  else if (I->second != P.second) {
458  dbgs() << " " << printReg(P.first, TRI)
459  << " masks doesn't match: LIS reported "
460  << PrintLaneMask(I->second)
461  << ", tracked "
462  << PrintLaneMask(P.second)
463  << '\n';
464  }
465  }
466  for (auto const &P : LISLR) {
467  auto I = TrackedLR.find(P.first);
468  if (I == TrackedLR.end()) {
469  dbgs() << " " << printReg(P.first, TRI)
470  << ":L" << PrintLaneMask(P.second)
471  << " isn't found in tracked set\n";
472  }
473  }
474 }
475 
477  const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
478  const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
479  const auto &TrackedLR = LiveRegs;
480 
481  if (!isEqual(LISLR, TrackedLR)) {
482  dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
483  " LIS reported livesets mismatch:\n";
484  printLivesAt(SI, LIS, *MRI);
485  reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
486  return false;
487  }
488 
489  auto LISPressure = getRegPressure(*MRI, LISLR);
490  if (LISPressure != CurPressure) {
491  dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: ";
492  CurPressure.print(dbgs());
493  dbgs() << "LIS rpt: ";
494  LISPressure.print(dbgs());
495  return false;
496  }
497  return true;
498 }
499 
501  const MachineRegisterInfo &MRI) {
503  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
504  unsigned Reg = Register::index2VirtReg(I);
505  auto It = LiveRegs.find(Reg);
506  if (It != LiveRegs.end() && It->second.any())
507  OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
508  << PrintLaneMask(It->second);
509  }
510  OS << '\n';
511 }
512 #endif
Interface definition for SIRegisterInfo.
A common definition of LaneBitmask for use in TableGen and CodeGen.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
AMDGPU specific subclass of TargetSubtarget.
static void printLiveRegs(raw_ostream &OS, const LiveRegSet &LiveRegs, const MachineRegisterInfo &MRI)
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:508
unsigned getSGPRTuplesWeight() const
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
unsigned Reg
unsigned getSubReg() const
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
unsigned const TargetRegisterInfo * TRI
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:85
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:559
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static LaneBitmask getDefRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI)
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:765
unsigned SubReg
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:793
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
unsigned getOccupancy(const GCNSubtarget &ST) const
bool isSGPRClass(const TargetRegisterClass *RC) const
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
static unsigned getNumCoveredRegs(LaneBitmask LM)
bool hasInterval(Register Reg) const
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
unsigned getVGPRTuplesWeight() const
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
#define P(N)
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:392
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned getSGPRNum() const
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:305
constexpr bool none() const
Definition: LaneBitmask.h:51
LiveInterval & getInterval(Register Reg)
unsigned size() const
Definition: DenseMap.h:100
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static SmallVector< RegisterMaskPair, 8 > collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
static LLVM_DUMP_METHOD void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedLR, const TargetRegisterInfo *TRI)
void printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
static LaneBitmask getUsedRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI, const LiveIntervals &LIS)
MachineOperand class - Representation of each machine instruction operand.
unsigned getVGPRNum() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:883
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:962
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Representation of each machine instruction.
Definition: MachineInstr.h:62
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
#define I(x, y, z)
Definition: MD5.cpp:59
iterator end()
Definition: DenseMap.h:83
bool isReg() const
isReg - Tests if this is a MO_Register operand.
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void print(raw_ostream &OS, const GCNSubtarget *ST=nullptr) const
LLVM Value Representation.
Definition: Value.h:74
This file defines the GCNRegPressure class, which tracks registry pressure by bookkeeping number of S...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
unsigned getWeight() const
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1518
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
void recede(const MachineInstr &MI)
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19