LLVM  12.0.0git
GCNRegPressure.cpp
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1 //===- GCNRegPressure.cpp -------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the GCNRegPressure class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "GCNRegPressure.h"
15 #include "AMDGPUSubtarget.h"
16 #include "SIRegisterInfo.h"
17 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Config/llvm-config.h"
27 #include "llvm/MC/LaneBitmask.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
32 #include <algorithm>
33 #include <cassert>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "machine-scheduler"
38 
39 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
42  const LiveIntervals &LIS,
43  const MachineRegisterInfo &MRI) {
44  dbgs() << "Live regs at " << SI << ": "
45  << *LIS.getInstructionFromIndex(SI);
46  unsigned Num = 0;
47  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
48  const unsigned Reg = Register::index2VirtReg(I);
49  if (!LIS.hasInterval(Reg))
50  continue;
51  const auto &LI = LIS.getInterval(Reg);
52  if (LI.hasSubRanges()) {
53  bool firstTime = true;
54  for (const auto &S : LI.subranges()) {
55  if (!S.liveAt(SI)) continue;
56  if (firstTime) {
57  dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
58  << '\n';
59  firstTime = false;
60  }
61  dbgs() << " " << S << '\n';
62  ++Num;
63  }
64  } else if (LI.liveAt(SI)) {
65  dbgs() << " " << LI << '\n';
66  ++Num;
67  }
68  }
69  if (!Num) dbgs() << " <none>\n";
70 }
71 #endif
72 
74  const GCNRPTracker::LiveRegSet &S2) {
75  if (S1.size() != S2.size())
76  return false;
77 
78  for (const auto &P : S1) {
79  auto I = S2.find(P.first);
80  if (I == S2.end() || I->second != P.second)
81  return false;
82  }
83  return true;
84 }
85 
86 
87 ///////////////////////////////////////////////////////////////////////////////
88 // GCNRegPressure
89 
90 unsigned GCNRegPressure::getRegKind(Register Reg,
91  const MachineRegisterInfo &MRI) {
92  assert(Reg.isVirtual());
93  const auto RC = MRI.getRegClass(Reg);
94  auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
95  return STI->isSGPRClass(RC) ?
96  (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
97  STI->hasAGPRs(RC) ?
98  (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
99  (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
100 }
101 
102 void GCNRegPressure::inc(unsigned Reg,
103  LaneBitmask PrevMask,
104  LaneBitmask NewMask,
105  const MachineRegisterInfo &MRI) {
106  if (SIRegisterInfo::getNumCoveredRegs(NewMask) ==
108  return;
109 
110  int Sign = 1;
111  if (NewMask < PrevMask) {
112  std::swap(NewMask, PrevMask);
113  Sign = -1;
114  }
115 
116  switch (auto Kind = getRegKind(Reg, MRI)) {
117  case SGPR32:
118  case VGPR32:
119  case AGPR32:
120  Value[Kind] += Sign;
121  break;
122 
123  case SGPR_TUPLE:
124  case VGPR_TUPLE:
125  case AGPR_TUPLE:
126  assert(PrevMask < NewMask);
127 
128  Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] +=
129  Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
130 
131  if (PrevMask.none()) {
132  assert(NewMask.any());
133  Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight();
134  }
135  break;
136 
137  default: llvm_unreachable("Unknown register kind");
138  }
139 }
140 
142  const GCNRegPressure& O,
143  unsigned MaxOccupancy) const {
144  const auto SGPROcc = std::min(MaxOccupancy,
146  const auto VGPROcc = std::min(MaxOccupancy,
148  const auto OtherSGPROcc = std::min(MaxOccupancy,
150  const auto OtherVGPROcc = std::min(MaxOccupancy,
152 
153  const auto Occ = std::min(SGPROcc, VGPROcc);
154  const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
155  if (Occ != OtherOcc)
156  return Occ > OtherOcc;
157 
158  bool SGPRImportant = SGPROcc < VGPROcc;
159  const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
160 
161  // if both pressures disagree on what is more important compare vgprs
162  if (SGPRImportant != OtherSGPRImportant) {
163  SGPRImportant = false;
164  }
165 
166  // compare large regs pressure
167  bool SGPRFirst = SGPRImportant;
168  for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
169  if (SGPRFirst) {
170  auto SW = getSGPRTuplesWeight();
171  auto OtherSW = O.getSGPRTuplesWeight();
172  if (SW != OtherSW)
173  return SW < OtherSW;
174  } else {
175  auto VW = getVGPRTuplesWeight();
176  auto OtherVW = O.getVGPRTuplesWeight();
177  if (VW != OtherVW)
178  return VW < OtherVW;
179  }
180  }
181  return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
182  (getVGPRNum() < O.getVGPRNum());
183 }
184 
185 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
188  OS << "VGPRs: " << Value[VGPR32] << ' ';
189  OS << "AGPRs: " << Value[AGPR32];
190  if (ST) OS << "(O" << ST->getOccupancyWithNumVGPRs(getVGPRNum()) << ')';
191  OS << ", SGPRs: " << getSGPRNum();
192  if (ST) OS << "(O" << ST->getOccupancyWithNumSGPRs(getSGPRNum()) << ')';
193  OS << ", LVGPR WT: " << getVGPRTuplesWeight()
194  << ", LSGPR WT: " << getSGPRTuplesWeight();
195  if (ST) OS << " -> Occ: " << getOccupancy(*ST);
196  OS << '\n';
197 }
198 #endif
199 
201  const MachineRegisterInfo &MRI) {
202  assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
203 
204  // We don't rely on read-undef flag because in case of tentative schedule
205  // tracking it isn't set correctly yet. This works correctly however since
206  // use mask has been tracked before using LIS.
207  return MO.getSubReg() == 0 ?
208  MRI.getMaxLaneMaskForVReg(MO.getReg()) :
210 }
211 
213  const MachineRegisterInfo &MRI,
214  const LiveIntervals &LIS) {
215  assert(MO.isUse() && MO.isReg() && MO.getReg().isVirtual());
216 
217  if (auto SubReg = MO.getSubReg())
219 
220  auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
221  if (SIRegisterInfo::getNumCoveredRegs(MaxMask) > 1) // cannot have subregs
222  return MaxMask;
223 
224  // For a tentative schedule LIS isn't updated yet but livemask should remain
225  // the same on any schedule. Subreg defs can be reordered but they all must
226  // dominate uses anyway.
227  auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
228  return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
229 }
230 
233  const MachineRegisterInfo &MRI) {
235  for (const auto &MO : MI.operands()) {
236  if (!MO.isReg() || !MO.getReg().isVirtual())
237  continue;
238  if (!MO.isUse() || !MO.readsReg())
239  continue;
240 
241  auto const UsedMask = getUsedRegMask(MO, MRI, LIS);
242 
243  auto Reg = MO.getReg();
244  auto I = std::find_if(Res.begin(), Res.end(), [Reg](const RegisterMaskPair &RM) {
245  return RM.RegUnit == Reg;
246  });
247  if (I != Res.end())
248  I->LaneMask |= UsedMask;
249  else
250  Res.push_back(RegisterMaskPair(Reg, UsedMask));
251  }
252  return Res;
253 }
254 
255 ///////////////////////////////////////////////////////////////////////////////
256 // GCNRPTracker
257 
259  SlotIndex SI,
260  const LiveIntervals &LIS,
261  const MachineRegisterInfo &MRI) {
262  LaneBitmask LiveMask;
263  const auto &LI = LIS.getInterval(Reg);
264  if (LI.hasSubRanges()) {
265  for (const auto &S : LI.subranges())
266  if (S.liveAt(SI)) {
267  LiveMask |= S.LaneMask;
268  assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
269  LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
270  }
271  } else if (LI.liveAt(SI)) {
272  LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
273  }
274  return LiveMask;
275 }
276 
278  const LiveIntervals &LIS,
279  const MachineRegisterInfo &MRI) {
280  GCNRPTracker::LiveRegSet LiveRegs;
281  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
282  auto Reg = Register::index2VirtReg(I);
283  if (!LIS.hasInterval(Reg))
284  continue;
285  auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
286  if (LiveMask.any())
287  LiveRegs[Reg] = LiveMask;
288  }
289  return LiveRegs;
290 }
291 
293  const LiveRegSet *LiveRegsCopy,
294  bool After) {
295  const MachineFunction &MF = *MI.getMF();
296  MRI = &MF.getRegInfo();
297  if (LiveRegsCopy) {
298  if (&LiveRegs != LiveRegsCopy)
299  LiveRegs = *LiveRegsCopy;
300  } else {
301  LiveRegs = After ? getLiveRegsAfter(MI, LIS)
302  : getLiveRegsBefore(MI, LIS);
303  }
304 
305  MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
306 }
307 
309  const LiveRegSet *LiveRegsCopy) {
310  GCNRPTracker::reset(MI, LiveRegsCopy, true);
311 }
312 
314  assert(MRI && "call reset first");
315 
316  LastTrackedMI = &MI;
317 
318  if (MI.isDebugInstr())
319  return;
320 
321  auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
322 
323  // calc pressure at the MI (defs + uses)
324  auto AtMIPressure = CurPressure;
325  for (const auto &U : RegUses) {
326  auto LiveMask = LiveRegs[U.RegUnit];
327  AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
328  }
329  // update max pressure
330  MaxPressure = max(AtMIPressure, MaxPressure);
331 
332  for (const auto &MO : MI.operands()) {
333  if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual() || MO.isDead())
334  continue;
335 
336  auto Reg = MO.getReg();
337  auto I = LiveRegs.find(Reg);
338  if (I == LiveRegs.end())
339  continue;
340  auto &LiveMask = I->second;
341  auto PrevMask = LiveMask;
342  LiveMask &= ~getDefRegMask(MO, *MRI);
343  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
344  if (LiveMask.none())
345  LiveRegs.erase(I);
346  }
347  for (const auto &U : RegUses) {
348  auto &LiveMask = LiveRegs[U.RegUnit];
349  auto PrevMask = LiveMask;
350  LiveMask |= U.LaneMask;
351  CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
352  }
353  assert(CurPressure == getRegPressure(*MRI, LiveRegs));
354 }
355 
357  const LiveRegSet *LiveRegsCopy) {
358  MRI = &MI.getParent()->getParent()->getRegInfo();
359  LastTrackedMI = nullptr;
360  MBBEnd = MI.getParent()->end();
361  NextMI = &MI;
362  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
363  if (NextMI == MBBEnd)
364  return false;
365  GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
366  return true;
367 }
368 
370  assert(MRI && "call reset first");
371 
372  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
373  if (NextMI == MBBEnd)
374  return false;
375 
376  SlotIndex SI = LIS.getInstructionIndex(*NextMI).getBaseIndex();
377  assert(SI.isValid());
378 
379  // Remove dead registers or mask bits.
380  for (auto &It : LiveRegs) {
381  const LiveInterval &LI = LIS.getInterval(It.first);
382  if (LI.hasSubRanges()) {
383  for (const auto &S : LI.subranges()) {
384  if (!S.liveAt(SI)) {
385  auto PrevMask = It.second;
386  It.second &= ~S.LaneMask;
387  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
388  }
389  }
390  } else if (!LI.liveAt(SI)) {
391  auto PrevMask = It.second;
392  It.second = LaneBitmask::getNone();
393  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
394  }
395  if (It.second.none())
396  LiveRegs.erase(It.first);
397  }
398 
399  MaxPressure = max(MaxPressure, CurPressure);
400 
401  return true;
402 }
403 
405  LastTrackedMI = &*NextMI++;
406 
407  // Add new registers or mask bits.
408  for (const auto &MO : LastTrackedMI->operands()) {
409  if (!MO.isReg() || !MO.isDef())
410  continue;
411  Register Reg = MO.getReg();
412  if (!Reg.isVirtual())
413  continue;
414  auto &LiveMask = LiveRegs[Reg];
415  auto PrevMask = LiveMask;
416  LiveMask |= getDefRegMask(MO, *MRI);
417  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
418  }
419 
420  MaxPressure = max(MaxPressure, CurPressure);
421 }
422 
424  // If we have just called reset live set is actual.
425  if ((NextMI == MBBEnd) || (LastTrackedMI && !advanceBeforeNext()))
426  return false;
427  advanceToNext();
428  return true;
429 }
430 
432  while (NextMI != End)
433  if (!advance()) return false;
434  return true;
435 }
436 
439  const LiveRegSet *LiveRegsCopy) {
440  reset(*Begin, LiveRegsCopy);
441  return advance(End);
442 }
443 
444 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
446 static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
447  const GCNRPTracker::LiveRegSet &TrackedLR,
448  const TargetRegisterInfo *TRI) {
449  for (auto const &P : TrackedLR) {
450  auto I = LISLR.find(P.first);
451  if (I == LISLR.end()) {
452  dbgs() << " " << printReg(P.first, TRI)
453  << ":L" << PrintLaneMask(P.second)
454  << " isn't found in LIS reported set\n";
455  }
456  else if (I->second != P.second) {
457  dbgs() << " " << printReg(P.first, TRI)
458  << " masks doesn't match: LIS reported "
459  << PrintLaneMask(I->second)
460  << ", tracked "
461  << PrintLaneMask(P.second)
462  << '\n';
463  }
464  }
465  for (auto const &P : LISLR) {
466  auto I = TrackedLR.find(P.first);
467  if (I == TrackedLR.end()) {
468  dbgs() << " " << printReg(P.first, TRI)
469  << ":L" << PrintLaneMask(P.second)
470  << " isn't found in tracked set\n";
471  }
472  }
473 }
474 
476  const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
477  const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
478  const auto &TrackedLR = LiveRegs;
479 
480  if (!isEqual(LISLR, TrackedLR)) {
481  dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
482  " LIS reported livesets mismatch:\n";
483  printLivesAt(SI, LIS, *MRI);
484  reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
485  return false;
486  }
487 
488  auto LISPressure = getRegPressure(*MRI, LISLR);
489  if (LISPressure != CurPressure) {
490  dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: ";
491  CurPressure.print(dbgs());
492  dbgs() << "LIS rpt: ";
493  LISPressure.print(dbgs());
494  return false;
495  }
496  return true;
497 }
498 
500  const MachineRegisterInfo &MRI) {
502  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
503  unsigned Reg = Register::index2VirtReg(I);
504  auto It = LiveRegs.find(Reg);
505  if (It != LiveRegs.end() && It->second.any())
506  OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
507  << PrintLaneMask(It->second);
508  }
509  OS << '\n';
510 }
511 #endif
Interface definition for SIRegisterInfo.
A common definition of LaneBitmask for use in TableGen and CodeGen.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
AMDGPU specific subclass of TargetSubtarget.
static void printLiveRegs(raw_ostream &OS, const LiveRegSet &LiveRegs, const MachineRegisterInfo &MRI)
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:508
unsigned getSGPRTuplesWeight() const
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:681
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
unsigned Reg
unsigned getSubReg() const
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:151
unsigned const TargetRegisterInfo * TRI
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:578
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static LaneBitmask getDefRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI)
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:770
unsigned SubReg
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:798
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
unsigned getOccupancy(const GCNSubtarget &ST) const
bool isSGPRClass(const TargetRegisterClass *RC) const
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
static unsigned getNumCoveredRegs(LaneBitmask LM)
bool hasInterval(Register Reg) const
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
unsigned getVGPRTuplesWeight() const
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
#define P(N)
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:393
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned getSGPRNum() const
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:339
constexpr bool none() const
Definition: LaneBitmask.h:51
LiveInterval & getInterval(Register Reg)
unsigned size() const
Definition: DenseMap.h:100
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static SmallVector< RegisterMaskPair, 8 > collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
static LLVM_DUMP_METHOD void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedLR, const TargetRegisterInfo *TRI)
void printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
static LaneBitmask getUsedRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI, const LiveIntervals &LIS)
MachineOperand class - Representation of each machine instruction operand.
unsigned getVGPRNum() const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:960
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:944
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:284
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Representation of each machine instruction.
Definition: MachineInstr.h:62
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:59
iterator end()
Definition: DenseMap.h:83
bool isReg() const
isReg - Tests if this is a MO_Register operand.
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void print(raw_ostream &OS, const GCNSubtarget *ST=nullptr) const
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
LLVM Value Representation.
Definition: Value.h:75
This file defines the GCNRegPressure class, which tracks registry pressure by bookkeeping number of S...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:50
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
unsigned getWeight() const
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1525
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
void recede(const MachineInstr &MI)
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19