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HexagonAsmBackend.cpp
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1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "Hexagon.h"
10 #include "HexagonFixupKinds.h"
17 #include "llvm/MC/MCAsmBackend.h"
18 #include "llvm/MC/MCAsmLayout.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/Support/Debug.h"
27 
28 #include <sstream>
29 
30 using namespace llvm;
31 using namespace Hexagon;
32 
33 #define DEBUG_TYPE "hexagon-asm-backend"
34 
36  ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
37 
38 namespace {
39 
40 class HexagonAsmBackend : public MCAsmBackend {
41  uint8_t OSABI;
42  StringRef CPU;
43  mutable uint64_t relaxedCnt;
44  std::unique_ptr <MCInstrInfo> MCII;
45  std::unique_ptr <MCInst *> RelaxTarget;
46  MCInst * Extender;
47 
48  void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
49  MCInst &HMB) const {
51  SmallString<256> Code;
52  raw_svector_ostream VecOS(Code);
53  E.encodeInstruction(HMB, VecOS, Fixups, *RF.getSubtargetInfo());
54 
55  // Update the fragment.
56  RF.setInst(HMB);
57  RF.getContents() = Code;
58  RF.getFixups() = Fixups;
59  }
60 
61 public:
62  HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
63  StringRef CPU)
64  : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU),
65  MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
66  Extender(nullptr) {}
67 
68  std::unique_ptr<MCObjectTargetWriter>
69  createObjectTargetWriter() const override {
70  return createHexagonELFObjectWriter(OSABI, CPU);
71  }
72 
73  void setExtender(MCContext &Context) const {
74  if (Extender == nullptr)
75  const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
76  }
77 
78  MCInst *takeExtender() const {
79  assert(Extender != nullptr);
80  MCInst * Result = Extender;
81  const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
82  return Result;
83  }
84 
85  unsigned getNumFixupKinds() const override {
87  }
88 
89  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
90  const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
91  // This table *must* be in same the order of fixup_* kinds in
92  // HexagonFixupKinds.h.
93  //
94  // namei offset bits flags
95  { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
96  { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
97  { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
98  { "fixup_Hexagon_LO16", 0, 32, 0 },
99  { "fixup_Hexagon_HI16", 0, 32, 0 },
100  { "fixup_Hexagon_32", 0, 32, 0 },
101  { "fixup_Hexagon_16", 0, 32, 0 },
102  { "fixup_Hexagon_8", 0, 32, 0 },
103  { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
104  { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
105  { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
106  { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
107  { "fixup_Hexagon_HL16", 0, 32, 0 },
108  { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
109  { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110  { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111  { "fixup_Hexagon_32_6_X", 0, 32, 0 },
112  { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113  { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114  { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
115  { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116  { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
117  { "fixup_Hexagon_16_X", 0, 32, 0 },
118  { "fixup_Hexagon_12_X", 0, 32, 0 },
119  { "fixup_Hexagon_11_X", 0, 32, 0 },
120  { "fixup_Hexagon_10_X", 0, 32, 0 },
121  { "fixup_Hexagon_9_X", 0, 32, 0 },
122  { "fixup_Hexagon_8_X", 0, 32, 0 },
123  { "fixup_Hexagon_7_X", 0, 32, 0 },
124  { "fixup_Hexagon_6_X", 0, 32, 0 },
125  { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
126  { "fixup_Hexagon_COPY", 0, 32, 0 },
127  { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
128  { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
129  { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
130  { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
131  { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
132  { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
133  { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
134  { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
135  { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
136  { "fixup_Hexagon_GOT_32", 0, 32, 0 },
137  { "fixup_Hexagon_GOT_16", 0, 32, 0 },
138  { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
139  { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
140  { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
141  { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
142  { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
143  { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
144  { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
145  { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
146  { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
147  { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
148  { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
149  { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
150  { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
151  { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
152  { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
153  { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
154  { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
155  { "fixup_Hexagon_IE_32", 0, 32, 0 },
156  { "fixup_Hexagon_IE_16", 0, 32, 0 },
157  { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
158  { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
159  { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
160  { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
161  { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
162  { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
163  { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
164  { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
165  { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
166  { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
167  { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
168  { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
169  { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
170  { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
171  { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
172  { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
173  { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
174  { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
175  { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
176  { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
177  { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
178  { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
179  { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
180  { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
181  { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
182  { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
183  { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
184  { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
185  { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
186  { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
187  { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
188  { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
189  { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
190  { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
191  { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
192  { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
193  };
194 
195  if (Kind < FirstTargetFixupKind)
196  return MCAsmBackend::getFixupKindInfo(Kind);
197 
198  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
199  "Invalid kind!");
200  return Infos[Kind - FirstTargetFixupKind];
201  }
202 
203  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
204  const MCValue &Target) override {
205  MCFixupKind Kind = Fixup.getKind();
206 
207  switch((unsigned)Kind) {
208  default:
209  llvm_unreachable("Unknown Fixup Kind!");
210 
211  case fixup_Hexagon_LO16:
212  case fixup_Hexagon_HI16:
213  case fixup_Hexagon_16:
214  case fixup_Hexagon_8:
219  case fixup_Hexagon_HL16:
221  case fixup_Hexagon_16_X:
222  case fixup_Hexagon_12_X:
223  case fixup_Hexagon_11_X:
224  case fixup_Hexagon_10_X:
225  case fixup_Hexagon_9_X:
226  case fixup_Hexagon_8_X:
227  case fixup_Hexagon_7_X:
228  case fixup_Hexagon_6_X:
229  case fixup_Hexagon_COPY:
258  case fixup_Hexagon_IE_32:
259  case fixup_Hexagon_IE_16:
299  // These relocations should always have a relocation recorded
300  return true;
301 
303  //IsResolved = false;
304  break;
305 
316  if (DisableFixup)
317  return true;
318  break;
319 
320  case FK_Data_1:
321  case FK_Data_2:
322  case FK_Data_4:
323  case FK_PCRel_4:
324  case fixup_Hexagon_32:
325  // Leave these relocations alone as they are used for EH.
326  return false;
327  }
328  return false;
329  }
330 
331  /// getFixupKindNumBytes - The number of bytes the fixup may change.
332  static unsigned getFixupKindNumBytes(unsigned Kind) {
333  switch (Kind) {
334  default:
335  return 0;
336 
337  case FK_Data_1:
338  return 1;
339  case FK_Data_2:
340  return 2;
341  case FK_Data_4: // this later gets mapped to R_HEX_32
342  case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
343  case fixup_Hexagon_32:
357  return 4;
358  }
359  }
360 
361  // Make up for left shift when encoding the operand.
362  static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) {
363  switch((unsigned)Kind) {
364  default:
365  break;
366 
372  Value >>= 2;
373  break;
374 
380  Value &= 0x3f;
381  break;
382 
386  Value >>= 6;
387  break;
388  }
389  return (Value);
390  }
391 
392  void HandleFixupError(const int bits, const int align_bits,
393  const int64_t FixupValue, const char *fixupStr) const {
394  // Error: value 1124 out of range: -1024-1023 when resolving
395  // symbol in file xprtsock.S
396  const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
397  const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
398  std::stringstream errStr;
399  errStr << "\nError: value " <<
400  FixupValue <<
401  " out of range: " <<
402  IntMin.getSExtValue() <<
403  "-" <<
404  IntMax.getSExtValue() <<
405  " when resolving " <<
406  fixupStr <<
407  " fixup\n";
408  llvm_unreachable(errStr.str().c_str());
409  }
410 
411  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
412  /// data fragment, at the offset specified by the fixup and following the
413  /// fixup kind as appropriate.
414  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
415  const MCValue &Target, MutableArrayRef<char> Data,
416  uint64_t FixupValue, bool IsResolved,
417  const MCSubtargetInfo *STI) const override {
418 
419  // When FixupValue is 0 the relocation is external and there
420  // is nothing for us to do.
421  if (!FixupValue) return;
422 
423  MCFixupKind Kind = Fixup.getKind();
424  uint64_t Value;
425  uint32_t InstMask;
426  uint32_t Reloc;
427 
428  // LLVM gives us an encoded value, we have to convert it back
429  // to a real offset before we can use it.
430  uint32_t Offset = Fixup.getOffset();
431  unsigned NumBytes = getFixupKindNumBytes(Kind);
432  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
433  char *InstAddr = Data.data() + Offset;
434 
435  Value = adjustFixupValue(Kind, FixupValue);
436  if(!Value)
437  return;
438  int sValue = (int)Value;
439 
440  switch((unsigned)Kind) {
441  default:
442  return;
443 
445  if (!(isIntN(7, sValue)))
446  HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
449  InstMask = 0x00001f18; // Word32_B7
450  Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
451  ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
452  break;
453 
455  if (!(isIntN(9, sValue)))
456  HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
459  InstMask = 0x003000fe; // Word32_B9
460  Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
461  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
462  break;
463 
464  // Since the existing branches that use this relocation cannot be
465  // extended, they should only be fixed up if the target is within range.
467  if (!(isIntN(13, sValue)))
468  HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
471  InstMask = 0x00202ffe; // Word32_B13
472  Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
473  (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
474  ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
475  break;
476 
478  if (!(isIntN(15, sValue)))
479  HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
482  InstMask = 0x00df20fe; // Word32_B15
483  Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
484  (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
485  (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
486  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
487  break;
488 
490  if (!(isIntN(22, sValue)))
491  HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
494  InstMask = 0x01ff3ffe; // Word32_B22
495  Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
496  ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
497  break;
498 
500  InstMask = 0x0fff3fff; // Word32_X26
501  Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
502  (Value & 0x3fff); // Value 13-0 = Target 13-0
503  break;
504 
505  case FK_Data_1:
506  case FK_Data_2:
507  case FK_Data_4:
508  case fixup_Hexagon_32:
509  InstMask = 0xffffffff; // Word32
510  Reloc = Value;
511  break;
512  }
513 
514  LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
515  << (unsigned)Kind << ")\n");
516  LLVM_DEBUG(
517  uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
518  (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
519  dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
520  dbgs().write_hex(FixupValue)
521  << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
522  dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
523 
524  // For each byte of the fragment that the fixup touches, mask in the
525  // bits from the fixup value. The Value has been "split up" into the
526  // appropriate bitfields above.
527  for (unsigned i = 0; i < NumBytes; i++){
528  InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
529  InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
530  }
531 
532  LLVM_DEBUG(uint32_t NewData = 0;
533  for (unsigned i = 0; i < NumBytes; i++) NewData |=
534  (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
535  dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
536  }
537 
538  bool isInstRelaxable(MCInst const &HMI) const {
539  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
540  bool Relaxable = false;
541  // Branches and loop-setup insns are handled as necessary by relaxation.
544  MCID.isBranch()) ||
546  MCID.isBranch()) ||
548  HMI.getOpcode() != Hexagon::C4_addipc))
549  if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
550  Relaxable = true;
551  MCOperand const &Operand =
554  Relaxable = false;
555  }
556 
557  return Relaxable;
558  }
559 
560  /// MayNeedRelaxation - Check whether the given instruction may need
561  /// relaxation.
562  ///
563  /// \param Inst - The instruction to test.
564  bool mayNeedRelaxation(MCInst const &Inst,
565  const MCSubtargetInfo &STI) const override {
566  return true;
567  }
568 
569  /// fixupNeedsRelaxation - Target specific predicate for whether a given
570  /// fixup requires the associated instruction to be relaxed.
571  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
572  uint64_t Value,
573  const MCRelaxableFragment *DF,
574  const MCAsmLayout &Layout,
575  const bool WasForced) const override {
576  MCInst const &MCB = DF->getInst();
578 
579  *RelaxTarget = nullptr;
580  MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
581  MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
582  bool Relaxable = isInstRelaxable(MCI);
583  if (Relaxable == false)
584  return false;
585  // If we cannot resolve the fixup value, it requires relaxation.
586  if (!Resolved) {
587  switch ((unsigned)Fixup.getKind()) {
589  // GetFixupCount assumes B22 won't relax
591  default:
592  return false;
593  break;
597  case fixup_Hexagon_B7_PCREL: {
599  ++relaxedCnt;
600  *RelaxTarget = &MCI;
601  setExtender(Layout.getAssembler().getContext());
602  return true;
603  } else {
604  return false;
605  }
606  break;
607  }
608  }
609  }
610 
611  MCFixupKind Kind = Fixup.getKind();
612  int64_t sValue = Value;
613  int64_t maxValue;
614 
615  switch ((unsigned)Kind) {
617  maxValue = 1 << 8;
618  break;
620  maxValue = 1 << 10;
621  break;
623  maxValue = 1 << 16;
624  break;
626  maxValue = 1 << 23;
627  break;
628  default:
629  maxValue = INT64_MAX;
630  break;
631  }
632 
633  bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
634 
635  if (isFarAway) {
637  ++relaxedCnt;
638  *RelaxTarget = &MCI;
639  setExtender(Layout.getAssembler().getContext());
640  return true;
641  }
642  }
643 
644  return false;
645  }
646 
647  /// Simple predicate for targets where !Resolved implies requiring relaxation
648  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
649  const MCRelaxableFragment *DF,
650  const MCAsmLayout &Layout) const override {
651  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
652  }
653 
654  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
655  MCInst &Res) const override {
657  "Hexagon relaxInstruction only works on bundles");
658 
659  Res.setOpcode(Hexagon::BUNDLE);
661  // Copy the results into the bundle.
662  bool Update = false;
663  for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
664  MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
665 
666  // if immediate extender needed, add it in
667  if (*RelaxTarget == &CrntHMI) {
668  Update = true;
670  "No room to insert extender for relaxation");
671 
672  MCInst *HMIx = takeExtender();
674  *MCII, CrntHMI,
677  *RelaxTarget = nullptr;
678  }
679  // now copy over the original instruction(the one we may have extended)
680  Res.addOperand(MCOperand::createInst(I.getInst()));
681  }
682  (void)Update;
683  assert(Update && "Didn't find relaxation target");
684  }
685 
686  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
687  static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
688  ParseIn = 0x00004000, // In packet parse-bits.
689  ParseEnd = 0x0000c000; // End of packet parse-bits.
690 
691  while(Count % HEXAGON_INSTR_SIZE) {
692  LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
693  << Count % HEXAGON_INSTR_SIZE << "/"
694  << HEXAGON_INSTR_SIZE << "\n");
695  --Count;
696  OS << '\0';
697  }
698 
699  while(Count) {
700  Count -= HEXAGON_INSTR_SIZE;
701  // Close the packet whenever a multiple of the maximum packet size remains
702  uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
703  ParseIn: ParseEnd;
704  support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
705  }
706  return true;
707  }
708 
709  void finishLayout(MCAssembler const &Asm,
710  MCAsmLayout &Layout) const override {
711  for (auto I : Layout.getSectionOrder()) {
712  auto &Fragments = I->getFragmentList();
713  for (auto &J : Fragments) {
714  switch (J.getKind()) {
715  default:
716  break;
717  case MCFragment::FT_Align: {
718  auto Size = Asm.computeFragmentSize(Layout, J);
719  for (auto K = J.getIterator();
720  K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
721  --K;
722  switch (K->getKind()) {
723  default:
724  break;
725  case MCFragment::FT_Align: {
726  // Don't pad before other alignments
727  Size = 0;
728  break;
729  }
731  MCContext &Context = Asm.getContext();
732  auto &RF = cast<MCRelaxableFragment>(*K);
733  auto &Inst = const_cast<MCInst &>(RF.getInst());
734  while (Size > 0 && HexagonMCInstrInfo::bundleSize(Inst) < 4) {
735  MCInst *Nop = new (Context) MCInst;
736  Nop->setOpcode(Hexagon::A2_nop);
738  Size -= 4;
739  if (!HexagonMCChecker(
740  Context, *MCII, *RF.getSubtargetInfo(), Inst,
741  *Context.getRegisterInfo(), false)
742  .check()) {
743  Inst.erase(Inst.end() - 1);
744  Size = 0;
745  }
746  }
747  bool Error = HexagonMCShuffle(Context, true, *MCII,
748  *RF.getSubtargetInfo(), Inst);
749  //assert(!Error);
750  (void)Error;
751  ReplaceInstruction(Asm.getEmitter(), RF, Inst);
752  Layout.invalidateFragmentsFrom(&RF);
753  Size = 0; // Only look back one instruction
754  break;
755  }
756  }
757  }
758  }
759  }
760  }
761  }
762  }
763 }; // class HexagonAsmBackend
764 
765 } // namespace
766 
767 // MCAsmBackend
769  const MCSubtargetInfo &STI,
770  MCRegisterInfo const & /*MRI*/,
771  const MCTargetOptions &Options) {
772  const Triple &TT = STI.getTargetTriple();
773  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
774 
775  StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
776  return new HexagonAsmBackend(T, TT, OSABI, CPUString);
777 }
static MCInstrInfo * createMCInstrInfo()
iterator end()
Definition: MCInst.h:193
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:300
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
bool isBundle(MCInst const &MCI)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
demanded bits
#define HEXAGON_INSTR_SIZE
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:534
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:276
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:73
const Triple & getTargetTriple() const
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
MCContext & getContext() const
Definition: MCAssembler.h:284
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
MCCodeEmitter & getEmitter() const
Definition: MCAssembler.h:294
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
void erase(iterator I)
Definition: MCInst.h:189
#define INT64_MAX
Definition: DataTypes.h:77
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
A four-byte fixup.
Definition: MCFixup.h:25
Context object for machine code objects.
Definition: MCContext.h:62
static cl::opt< bool > DisableFixup("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"))
MCInst const & instruction(MCInst const &MCB, size_t Index)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
const MCExpr * getExpr() const
Definition: MCInst.h:95
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
SmallVectorImpl< char > & getContents()
Definition: MCFragment.h:197
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
StringRef selectHexagonCPU(StringRef CPU)
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
int64_t getImm() const
Definition: MCInst.h:75
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
Definition: MCFragment.cpp:51
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
SmallVectorImpl< MCFixup > & getFixups()
Definition: MCFragment.h:223
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
Definition: MCAsmLayout.h:65
uint32_t getOffset() const
Definition: MCFixup.h:124
Definition for classes that emit Hexagon machine code from MCInsts.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:23
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
A four-byte pc relative fixup.
Definition: MCFixup.h:29
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
StringRef getCPU() const
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Definition: MCFragment.h:173
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:143
const MCInst & getInst() const
Definition: MCFragment.h:281
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
uint64_t computeFragmentSize(const MCAsmLayout &Layout, const MCFragment &F) const
Compute the effective fragment size assuming it is laid out at the given SectionAddress and FragmentO...
size_t bundleSize(MCInst const &MCI)
T * data() const
Definition: ArrayRef.h:328
Target independent information on a fixup kind.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:544
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
#define HEXAGON_PACKET_SIZE
LLVM Value Representation.
Definition: Value.h:72
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
Check for a valid bundle.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
unsigned getOpcode() const
Definition: MCInst.h:171
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool mustNotExtend(MCExpr const &Expr)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
A two-byte fixup.
Definition: MCFixup.h:24
void setInst(const MCInst &Value)
Definition: MCFragment.h:282
MCFixupKind getKind() const
Definition: MCFixup.h:122