LLVM  10.0.0svn
HexagonAsmPrinter.cpp
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1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
11 // the output mechanism used by `llc'.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonAsmPrinter.h"
16 #include "Hexagon.h"
17 #include "HexagonInstrInfo.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Twine.h"
28 #include "llvm/BinaryFormat/ELF.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCDirectives.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCRegisterInfo.h"
41 #include "llvm/MC/MCSectionELF.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Support/Casting.h"
49 #include <algorithm>
50 #include <cassert>
51 #include <cstdint>
52 #include <string>
53 
54 using namespace llvm;
55 
56 namespace llvm {
57 
58 void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
59  MCInst &MCB, HexagonAsmPrinter &AP);
60 
61 } // end namespace llvm
62 
63 #define DEBUG_TYPE "asm-printer"
64 
65 // Given a scalar register return its pair.
66 inline static unsigned getHexagonRegisterPair(unsigned Reg,
67  const MCRegisterInfo *RI) {
68  assert(Hexagon::IntRegsRegClass.contains(Reg));
69  MCSuperRegIterator SR(Reg, RI, false);
70  unsigned Pair = *SR;
71  assert(Hexagon::DoubleRegsRegClass.contains(Pair));
72  return Pair;
73 }
74 
75 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
76  raw_ostream &O) {
77  const MachineOperand &MO = MI->getOperand(OpNo);
78 
79  switch (MO.getType()) {
80  default:
81  llvm_unreachable ("<unknown operand type>");
84  return;
86  O << MO.getImm();
87  return;
89  MO.getMBB()->getSymbol()->print(O, MAI);
90  return;
92  GetCPISymbol(MO.getIndex())->print(O, MAI);
93  return;
95  PrintSymbolOperand(MO, O);
96  return;
97  }
98 }
99 
100 // isBlockOnlyReachableByFallthrough - We need to override this since the
101 // default AsmPrinter does not print labels for any basic block that
102 // is only reachable by a fall through. That works for all cases except
103 // for the case in which the basic block is reachable by a fall through but
104 // through an indirect from a jump table. In this case, the jump table
105 // will contain a label not defined by AsmPrinter.
107  const MachineBasicBlock *MBB) const {
108  if (MBB->hasAddressTaken())
109  return false;
111 }
112 
113 /// PrintAsmOperand - Print out an operand for an inline asm expression.
115  const char *ExtraCode,
116  raw_ostream &OS) {
117  // Does this asm operand have a single letter operand modifier?
118  if (ExtraCode && ExtraCode[0]) {
119  if (ExtraCode[1] != 0)
120  return true; // Unknown modifier.
121 
122  switch (ExtraCode[0]) {
123  default:
124  // See if this is a generic print operand
125  return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
126  case 'L':
127  case 'H': { // The highest-numbered register of a pair.
128  const MachineOperand &MO = MI->getOperand(OpNo);
129  const MachineFunction &MF = *MI->getParent()->getParent();
131  if (!MO.isReg())
132  return true;
133  Register RegNumber = MO.getReg();
134  // This should be an assert in the frontend.
135  if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
136  RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
137  Hexagon::isub_lo :
138  Hexagon::isub_hi);
139  OS << HexagonInstPrinter::getRegisterName(RegNumber);
140  return false;
141  }
142  case 'I':
143  // Write 'i' if an integer constant, otherwise nothing. Used to print
144  // addi vs add, etc.
145  if (MI->getOperand(OpNo).isImm())
146  OS << "i";
147  return false;
148  }
149  }
150 
151  printOperand(MI, OpNo, OS);
152  return false;
153 }
154 
156  unsigned OpNo,
157  const char *ExtraCode,
158  raw_ostream &O) {
159  if (ExtraCode && ExtraCode[0])
160  return true; // Unknown modifier.
161 
162  const MachineOperand &Base = MI->getOperand(OpNo);
163  const MachineOperand &Offset = MI->getOperand(OpNo+1);
164 
165  if (Base.isReg())
166  printOperand(MI, OpNo, O);
167  else
168  llvm_unreachable("Unimplemented");
169 
170  if (Offset.isImm()) {
171  if (Offset.getImm())
172  O << "+#" << Offset.getImm();
173  } else {
174  llvm_unreachable("Unimplemented");
175  }
176 
177  return false;
178 }
179 
181  MCStreamer &OutStreamer, const MCOperand &Imm,
182  int AlignSize) {
183  MCSymbol *Sym;
184  int64_t Value;
185  if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
186  StringRef sectionPrefix;
187  std::string ImmString;
188  StringRef Name;
189  if (AlignSize == 8) {
190  Name = ".CONST_0000000000000000";
191  sectionPrefix = ".gnu.linkonce.l8";
192  ImmString = utohexstr(Value);
193  } else {
194  Name = ".CONST_00000000";
195  sectionPrefix = ".gnu.linkonce.l4";
196  ImmString = utohexstr(static_cast<uint32_t>(Value));
197  }
198 
199  std::string symbolName = // Yes, leading zeros are kept.
200  Name.drop_back(ImmString.size()).str() + ImmString;
201  std::string sectionName = sectionPrefix.str() + symbolName;
202 
203  MCSectionELF *Section = OutStreamer.getContext().getELFSection(
205  OutStreamer.SwitchSection(Section);
206 
207  Sym = AP.OutContext.getOrCreateSymbol(Twine(symbolName));
208  if (Sym->isUndefined()) {
209  OutStreamer.EmitLabel(Sym);
210  OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global);
211  OutStreamer.EmitIntValue(Value, AlignSize);
212  OutStreamer.EmitCodeAlignment(AlignSize);
213  }
214  } else {
215  assert(Imm.isExpr() && "Expected expression and found none");
216  const MachineOperand &MO = MI.getOperand(1);
217  assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
218  MCSymbol *MOSymbol = nullptr;
219  if (MO.isGlobal())
220  MOSymbol = AP.getSymbol(MO.getGlobal());
221  else if (MO.isCPI())
222  MOSymbol = AP.GetCPISymbol(MO.getIndex());
223  else if (MO.isJTI())
224  MOSymbol = AP.GetJTISymbol(MO.getIndex());
225  else
226  llvm_unreachable("Unknown operand type!");
227 
228  StringRef SymbolName = MOSymbol->getName();
229  std::string LitaName = ".CONST_" + SymbolName.str();
230 
231  MCSectionELF *Section = OutStreamer.getContext().getELFSection(
233 
234  OutStreamer.SwitchSection(Section);
235  Sym = AP.OutContext.getOrCreateSymbol(Twine(LitaName));
236  if (Sym->isUndefined()) {
237  OutStreamer.EmitLabel(Sym);
238  OutStreamer.EmitSymbolAttribute(Sym, MCSA_Local);
239  OutStreamer.EmitValue(Imm.getExpr(), AlignSize);
240  OutStreamer.EmitCodeAlignment(AlignSize);
241  }
242  }
243  return Sym;
244 }
245 
246 static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
247  unsigned VectorSize, MCContext &Ctx) {
248  MCInst T;
249  T.setOpcode(Inst.getOpcode());
250  for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
251  if (i != OpNo) {
252  T.addOperand(Inst.getOperand(i));
253  continue;
254  }
255  MCOperand &ImmOp = Inst.getOperand(i);
256  const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
257  int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
258  auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
259  auto *NewHE = HexagonMCExpr::create(NewCE, Ctx);
261  }
262  return T;
263 }
264 
266  const MachineInstr &MI) {
267  MCInst &MappedInst = static_cast <MCInst &>(Inst);
268  const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
269  const MachineFunction &MF = *MI.getParent()->getParent();
270  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
271  unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
272 
273  switch (Inst.getOpcode()) {
274  default:
275  return;
276 
277  case Hexagon::A2_iconst: {
278  Inst.setOpcode(Hexagon::A2_addi);
279  MCOperand Reg = Inst.getOperand(0);
280  MCOperand S16 = Inst.getOperand(1);
283  Inst.clear();
284  Inst.addOperand(Reg);
285  Inst.addOperand(MCOperand::createReg(Hexagon::R0));
286  Inst.addOperand(S16);
287  break;
288  }
289 
290  case Hexagon::A2_tfrf: {
292  Inst.setOpcode(Hexagon::A2_paddif);
293  Inst.addOperand(MCOperand::createExpr(Zero));
294  break;
295  }
296 
297  case Hexagon::A2_tfrt: {
299  Inst.setOpcode(Hexagon::A2_paddit);
300  Inst.addOperand(MCOperand::createExpr(Zero));
301  break;
302  }
303 
304  case Hexagon::A2_tfrfnew: {
306  Inst.setOpcode(Hexagon::A2_paddifnew);
307  Inst.addOperand(MCOperand::createExpr(Zero));
308  break;
309  }
310 
311  case Hexagon::A2_tfrtnew: {
313  Inst.setOpcode(Hexagon::A2_padditnew);
314  Inst.addOperand(MCOperand::createExpr(Zero));
315  break;
316  }
317 
318  case Hexagon::A2_zxtb: {
320  Inst.setOpcode(Hexagon::A2_andir);
321  Inst.addOperand(MCOperand::createExpr(C255));
322  break;
323  }
324 
325  // "$dst = CONST64(#$src1)",
326  case Hexagon::CONST64:
327  if (!OutStreamer->hasRawTextSupport()) {
328  const MCOperand &Imm = MappedInst.getOperand(1);
329  MCSectionSubPair Current = OutStreamer->getCurrentSection();
330 
331  MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8);
332 
333  OutStreamer->SwitchSection(Current.first, Current.second);
334  MCInst TmpInst;
335  MCOperand &Reg = MappedInst.getOperand(0);
336  TmpInst.setOpcode(Hexagon::L2_loadrdgp);
337  TmpInst.addOperand(Reg);
340  MappedInst = TmpInst;
341 
342  }
343  break;
344  case Hexagon::CONST32:
345  if (!OutStreamer->hasRawTextSupport()) {
346  MCOperand &Imm = MappedInst.getOperand(1);
347  MCSectionSubPair Current = OutStreamer->getCurrentSection();
348  MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4);
349  OutStreamer->SwitchSection(Current.first, Current.second);
350  MCInst TmpInst;
351  MCOperand &Reg = MappedInst.getOperand(0);
352  TmpInst.setOpcode(Hexagon::L2_loadrigp);
353  TmpInst.addOperand(Reg);
356  MappedInst = TmpInst;
357  }
358  break;
359 
360  // C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
361  // C2_or during instruction selection itself but it results
362  // into suboptimal code.
363  case Hexagon::C2_pxfer_map: {
364  MCOperand &Ps = Inst.getOperand(1);
365  MappedInst.setOpcode(Hexagon::C2_or);
366  MappedInst.addOperand(Ps);
367  return;
368  }
369 
370  // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
371  // The insn is mapped from the 4 operand to the 3 operand raw form taking
372  // 3 register pairs.
373  case Hexagon::M2_vrcmpys_acc_s1: {
374  MCOperand &Rt = Inst.getOperand(3);
375  assert(Rt.isReg() && "Expected register and none was found");
376  unsigned Reg = RI->getEncodingValue(Rt.getReg());
377  if (Reg & 1)
378  MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
379  else
380  MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
381  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
382  return;
383  }
384  case Hexagon::M2_vrcmpys_s1: {
385  MCOperand &Rt = Inst.getOperand(2);
386  assert(Rt.isReg() && "Expected register and none was found");
387  unsigned Reg = RI->getEncodingValue(Rt.getReg());
388  if (Reg & 1)
389  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
390  else
391  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
392  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
393  return;
394  }
395 
396  case Hexagon::M2_vrcmpys_s1rp: {
397  MCOperand &Rt = Inst.getOperand(2);
398  assert(Rt.isReg() && "Expected register and none was found");
399  unsigned Reg = RI->getEncodingValue(Rt.getReg());
400  if (Reg & 1)
401  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
402  else
403  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
404  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
405  return;
406  }
407 
408  case Hexagon::A4_boundscheck: {
409  MCOperand &Rs = Inst.getOperand(1);
410  assert(Rs.isReg() && "Expected register and none was found");
411  unsigned Reg = RI->getEncodingValue(Rs.getReg());
412  if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
413  MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
414  else // raw:lo
415  MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
416  Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
417  return;
418  }
419 
420  case Hexagon::PS_call_nr:
421  Inst.setOpcode(Hexagon::J2_call);
422  break;
423 
424  case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
425  MCOperand &MO = MappedInst.getOperand(2);
426  int64_t Imm;
427  MCExpr const *Expr = MO.getExpr();
428  bool Success = Expr->evaluateAsAbsolute(Imm);
429  assert(Success && "Expected immediate and none was found");
430  (void)Success;
431  MCInst TmpInst;
432  if (Imm == 0) {
433  TmpInst.setOpcode(Hexagon::S2_vsathub);
434  TmpInst.addOperand(MappedInst.getOperand(0));
435  TmpInst.addOperand(MappedInst.getOperand(1));
436  MappedInst = TmpInst;
437  return;
438  }
439  TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
440  TmpInst.addOperand(MappedInst.getOperand(0));
441  TmpInst.addOperand(MappedInst.getOperand(1));
442  const MCExpr *One = MCConstantExpr::create(1, OutContext);
443  const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
444  TmpInst.addOperand(
446  MappedInst = TmpInst;
447  return;
448  }
449 
450  case Hexagon::S5_vasrhrnd_goodsyntax:
451  case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
452  MCOperand &MO2 = MappedInst.getOperand(2);
453  MCExpr const *Expr = MO2.getExpr();
454  int64_t Imm;
455  bool Success = Expr->evaluateAsAbsolute(Imm);
456  assert(Success && "Expected immediate and none was found");
457  (void)Success;
458  MCInst TmpInst;
459  if (Imm == 0) {
460  TmpInst.setOpcode(Hexagon::A2_combinew);
461  TmpInst.addOperand(MappedInst.getOperand(0));
462  MCOperand &MO1 = MappedInst.getOperand(1);
463  unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
464  unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
465  // Add a new operand for the second register in the pair.
466  TmpInst.addOperand(MCOperand::createReg(High));
467  TmpInst.addOperand(MCOperand::createReg(Low));
468  MappedInst = TmpInst;
469  return;
470  }
471 
472  if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
473  TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
474  else
475  TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
476  TmpInst.addOperand(MappedInst.getOperand(0));
477  TmpInst.addOperand(MappedInst.getOperand(1));
478  const MCExpr *One = MCConstantExpr::create(1, OutContext);
479  const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
480  TmpInst.addOperand(
482  MappedInst = TmpInst;
483  return;
484  }
485 
486  // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
487  case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
488  MCOperand &MO = Inst.getOperand(2);
489  MCExpr const *Expr = MO.getExpr();
490  int64_t Imm;
491  bool Success = Expr->evaluateAsAbsolute(Imm);
492  assert(Success && "Expected immediate and none was found");
493  (void)Success;
494  MCInst TmpInst;
495  if (Imm == 0) {
496  TmpInst.setOpcode(Hexagon::A2_tfr);
497  TmpInst.addOperand(MappedInst.getOperand(0));
498  TmpInst.addOperand(MappedInst.getOperand(1));
499  MappedInst = TmpInst;
500  return;
501  }
502  TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
503  TmpInst.addOperand(MappedInst.getOperand(0));
504  TmpInst.addOperand(MappedInst.getOperand(1));
505  const MCExpr *One = MCConstantExpr::create(1, OutContext);
506  const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
507  TmpInst.addOperand(
509  MappedInst = TmpInst;
510  return;
511  }
512 
513  // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
514  case Hexagon::A2_tfrpi: {
515  MCInst TmpInst;
516  MCOperand &Rdd = MappedInst.getOperand(0);
517  MCOperand &MO = MappedInst.getOperand(1);
518 
519  TmpInst.setOpcode(Hexagon::A2_combineii);
520  TmpInst.addOperand(Rdd);
521  int64_t Imm;
522  bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
523  if (Success && Imm < 0) {
524  const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
526  TmpInst.addOperand(MCOperand::createExpr(E));
527  } else {
528  const MCExpr *Zero = MCConstantExpr::create(0, OutContext);
530  TmpInst.addOperand(MCOperand::createExpr(E));
531  }
532  TmpInst.addOperand(MO);
533  MappedInst = TmpInst;
534  return;
535  }
536 
537  // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
538  case Hexagon::A2_tfrp: {
539  MCOperand &MO = MappedInst.getOperand(1);
540  unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
541  unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
542  MO.setReg(High);
543  // Add a new operand for the second register in the pair.
544  MappedInst.addOperand(MCOperand::createReg(Low));
545  MappedInst.setOpcode(Hexagon::A2_combinew);
546  return;
547  }
548 
549  case Hexagon::A2_tfrpt:
550  case Hexagon::A2_tfrpf: {
551  MCOperand &MO = MappedInst.getOperand(2);
552  unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
553  unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
554  MO.setReg(High);
555  // Add a new operand for the second register in the pair.
556  MappedInst.addOperand(MCOperand::createReg(Low));
557  MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
558  ? Hexagon::C2_ccombinewt
559  : Hexagon::C2_ccombinewf);
560  return;
561  }
562 
563  case Hexagon::A2_tfrptnew:
564  case Hexagon::A2_tfrpfnew: {
565  MCOperand &MO = MappedInst.getOperand(2);
566  unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
567  unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
568  MO.setReg(High);
569  // Add a new operand for the second register in the pair.
570  MappedInst.addOperand(MCOperand::createReg(Low));
571  MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
572  ? Hexagon::C2_ccombinewnewt
573  : Hexagon::C2_ccombinewnewf);
574  return;
575  }
576 
577  case Hexagon::M2_mpysmi: {
578  MCOperand &Imm = MappedInst.getOperand(2);
579  MCExpr const *Expr = Imm.getExpr();
580  int64_t Value;
581  bool Success = Expr->evaluateAsAbsolute(Value);
582  assert(Success);
583  (void)Success;
584  if (Value < 0 && Value > -256) {
585  MappedInst.setOpcode(Hexagon::M2_mpysin);
588  } else
589  MappedInst.setOpcode(Hexagon::M2_mpysip);
590  return;
591  }
592 
593  case Hexagon::A2_addsp: {
594  MCOperand &Rt = Inst.getOperand(1);
595  assert(Rt.isReg() && "Expected register and none was found");
596  unsigned Reg = RI->getEncodingValue(Rt.getReg());
597  if (Reg & 1)
598  MappedInst.setOpcode(Hexagon::A2_addsph);
599  else
600  MappedInst.setOpcode(Hexagon::A2_addspl);
601  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
602  return;
603  }
604 
605  case Hexagon::V6_vd0: {
606  MCInst TmpInst;
607  assert(Inst.getOperand(0).isReg() &&
608  "Expected register and none was found");
609 
610  TmpInst.setOpcode(Hexagon::V6_vxor);
611  TmpInst.addOperand(Inst.getOperand(0));
612  TmpInst.addOperand(Inst.getOperand(0));
613  TmpInst.addOperand(Inst.getOperand(0));
614  MappedInst = TmpInst;
615  return;
616  }
617 
618  case Hexagon::V6_vdd0: {
619  MCInst TmpInst;
620  assert (Inst.getOperand(0).isReg() &&
621  "Expected register and none was found");
622 
623  TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
624  TmpInst.addOperand(Inst.getOperand(0));
625  TmpInst.addOperand(Inst.getOperand(0));
626  TmpInst.addOperand(Inst.getOperand(0));
627  MappedInst = TmpInst;
628  return;
629  }
630 
631  case Hexagon::V6_vL32Ub_pi:
632  case Hexagon::V6_vL32b_cur_pi:
633  case Hexagon::V6_vL32b_nt_cur_pi:
634  case Hexagon::V6_vL32b_pi:
635  case Hexagon::V6_vL32b_nt_pi:
636  case Hexagon::V6_vL32b_nt_tmp_pi:
637  case Hexagon::V6_vL32b_tmp_pi:
638  MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
639  return;
640 
641  case Hexagon::V6_vL32Ub_ai:
642  case Hexagon::V6_vL32b_ai:
643  case Hexagon::V6_vL32b_cur_ai:
644  case Hexagon::V6_vL32b_nt_ai:
645  case Hexagon::V6_vL32b_nt_cur_ai:
646  case Hexagon::V6_vL32b_nt_tmp_ai:
647  case Hexagon::V6_vL32b_tmp_ai:
648  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
649  return;
650 
651  case Hexagon::V6_vS32Ub_pi:
652  case Hexagon::V6_vS32b_new_pi:
653  case Hexagon::V6_vS32b_nt_new_pi:
654  case Hexagon::V6_vS32b_nt_pi:
655  case Hexagon::V6_vS32b_pi:
656  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
657  return;
658 
659  case Hexagon::V6_vS32Ub_ai:
660  case Hexagon::V6_vS32b_ai:
661  case Hexagon::V6_vS32b_new_ai:
662  case Hexagon::V6_vS32b_nt_ai:
663  case Hexagon::V6_vS32b_nt_new_ai:
664  MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
665  return;
666 
667  case Hexagon::V6_vL32b_cur_npred_pi:
668  case Hexagon::V6_vL32b_cur_pred_pi:
669  case Hexagon::V6_vL32b_npred_pi:
670  case Hexagon::V6_vL32b_nt_cur_npred_pi:
671  case Hexagon::V6_vL32b_nt_cur_pred_pi:
672  case Hexagon::V6_vL32b_nt_npred_pi:
673  case Hexagon::V6_vL32b_nt_pred_pi:
674  case Hexagon::V6_vL32b_nt_tmp_npred_pi:
675  case Hexagon::V6_vL32b_nt_tmp_pred_pi:
676  case Hexagon::V6_vL32b_pred_pi:
677  case Hexagon::V6_vL32b_tmp_npred_pi:
678  case Hexagon::V6_vL32b_tmp_pred_pi:
679  MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
680  return;
681 
682  case Hexagon::V6_vL32b_cur_npred_ai:
683  case Hexagon::V6_vL32b_cur_pred_ai:
684  case Hexagon::V6_vL32b_npred_ai:
685  case Hexagon::V6_vL32b_nt_cur_npred_ai:
686  case Hexagon::V6_vL32b_nt_cur_pred_ai:
687  case Hexagon::V6_vL32b_nt_npred_ai:
688  case Hexagon::V6_vL32b_nt_pred_ai:
689  case Hexagon::V6_vL32b_nt_tmp_npred_ai:
690  case Hexagon::V6_vL32b_nt_tmp_pred_ai:
691  case Hexagon::V6_vL32b_pred_ai:
692  case Hexagon::V6_vL32b_tmp_npred_ai:
693  case Hexagon::V6_vL32b_tmp_pred_ai:
694  MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
695  return;
696 
697  case Hexagon::V6_vS32Ub_npred_pi:
698  case Hexagon::V6_vS32Ub_pred_pi:
699  case Hexagon::V6_vS32b_new_npred_pi:
700  case Hexagon::V6_vS32b_new_pred_pi:
701  case Hexagon::V6_vS32b_npred_pi:
702  case Hexagon::V6_vS32b_nqpred_pi:
703  case Hexagon::V6_vS32b_nt_new_npred_pi:
704  case Hexagon::V6_vS32b_nt_new_pred_pi:
705  case Hexagon::V6_vS32b_nt_npred_pi:
706  case Hexagon::V6_vS32b_nt_nqpred_pi:
707  case Hexagon::V6_vS32b_nt_pred_pi:
708  case Hexagon::V6_vS32b_nt_qpred_pi:
709  case Hexagon::V6_vS32b_pred_pi:
710  case Hexagon::V6_vS32b_qpred_pi:
711  MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
712  return;
713 
714  case Hexagon::V6_vS32Ub_npred_ai:
715  case Hexagon::V6_vS32Ub_pred_ai:
716  case Hexagon::V6_vS32b_new_npred_ai:
717  case Hexagon::V6_vS32b_new_pred_ai:
718  case Hexagon::V6_vS32b_npred_ai:
719  case Hexagon::V6_vS32b_nqpred_ai:
720  case Hexagon::V6_vS32b_nt_new_npred_ai:
721  case Hexagon::V6_vS32b_nt_new_pred_ai:
722  case Hexagon::V6_vS32b_nt_npred_ai:
723  case Hexagon::V6_vS32b_nt_nqpred_ai:
724  case Hexagon::V6_vS32b_nt_pred_ai:
725  case Hexagon::V6_vS32b_nt_qpred_ai:
726  case Hexagon::V6_vS32b_pred_ai:
727  case Hexagon::V6_vS32b_qpred_ai:
728  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
729  return;
730 
731  // V65+
732  case Hexagon::V6_vS32b_srls_ai:
733  MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
734  return;
735 
736  case Hexagon::V6_vS32b_srls_pi:
737  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
738  return;
739  }
740 }
741 
742 /// Print out a single Hexagon MI to the current output stream.
744  MCInst MCB;
745  MCB.setOpcode(Hexagon::BUNDLE);
747  const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
748 
749  if (MI->isBundle()) {
750  const MachineBasicBlock* MBB = MI->getParent();
752 
753  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
754  if (!MII->isDebugInstr() && !MII->isImplicitDef())
755  HexagonLowerToMC(MCII, &*MII, MCB, *this);
756  } else {
757  HexagonLowerToMC(MCII, MI, MCB, *this);
758  }
759 
760  const MachineFunction &MF = *MI->getParent()->getParent();
761  const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
762  if (MI->isBundle() && HII.getBundleNoShuf(*MI))
764 
765  MCContext &Ctx = OutStreamer->getContext();
766  bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, *Subtarget, Ctx,
767  MCB, nullptr);
768  assert(Ok); (void)Ok;
769  if (HexagonMCInstrInfo::bundleSize(MCB) == 0)
770  return;
771  OutStreamer->EmitInstruction(MCB, getSubtargetInfo());
772 }
773 
776 }
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:331
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:228
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
MachineBasicBlock reference.
static MCSymbol * smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize)
unsigned const TargetRegisterInfo * TRI
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t High
return AArch64::GPR64RegClass contains(Reg)
MCContext & getContext() const
Definition: MCStreamer.h:251
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
.local (ELF)
Definition: MCDirectives.h:35
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:65
bool isBundle() const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:554
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
Register getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
const MCExpr * getExpr() const
Definition: MCInst.h:95
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:128
void EmitInstruction(const MachineInstr *MI) override
Print out a single Hexagon MI to the current output stream.
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:159
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false)
Definition: MCExpr.cpp:169
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI)
void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP)
void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB)
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:189
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
bool isExpr() const
Definition: MCInst.h:60
self_iterator getIterator()
Definition: ilist_node.h:81
unsigned getNumOperands() const
Definition: MCInst.h:181
static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx)
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:395
void LLVMInitializeHexagonAsmPrinter()
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
std::pair< MCSection *, const MCExpr * > MCSectionSubPair
Definition: MCStreamer.h:57
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:443
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:258
MachineOperand class - Representation of each machine instruction operand.
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
int64_t getImm() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
#define Success
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
.type _foo,
Definition: MCDirectives.h:30
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:129
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
PrintAsmOperand - Print out an operand for an inline asm expression.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:128
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS)
Print the MachineOperand as a symbol.
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:70
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:424
LLVM Value Representation.
Definition: Value.h:73
static char const * getRegisterName(unsigned RegNo)
const HexagonInstrInfo * getInstrInfo() const override
LLVM_NODISCARD StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:628
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:397
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
Address of indexed Constant in Constant Pool.
Register getReg() const
getReg - Returns the register number.
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:171
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
Target & getTheHexagonTarget()
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
std::string utohexstr(uint64_t X, bool LowerCase=false)
Definition: StringExtras.h:124
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
void setExpr(const MCExpr *Val)
Definition: MCInst.h:100