LLVM  9.0.0svn
HexagonAsmPrinter.cpp
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1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
11 // the output mechanism used by `llc'.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonAsmPrinter.h"
16 #include "Hexagon.h"
17 #include "HexagonInstrInfo.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/BinaryFormat/ELF.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCDirectives.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/MC/MCSectionELF.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Support/Casting.h"
48 #include <algorithm>
49 #include <cassert>
50 #include <cstdint>
51 #include <string>
52 
53 using namespace llvm;
54 
55 namespace llvm {
56 
57 void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
58  MCInst &MCB, HexagonAsmPrinter &AP);
59 
60 } // end namespace llvm
61 
62 #define DEBUG_TYPE "asm-printer"
63 
64 // Given a scalar register return its pair.
65 inline static unsigned getHexagonRegisterPair(unsigned Reg,
66  const MCRegisterInfo *RI) {
67  assert(Hexagon::IntRegsRegClass.contains(Reg));
68  MCSuperRegIterator SR(Reg, RI, false);
69  unsigned Pair = *SR;
70  assert(Hexagon::DoubleRegsRegClass.contains(Pair));
71  return Pair;
72 }
73 
74 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
75  raw_ostream &O) {
76  const MachineOperand &MO = MI->getOperand(OpNo);
77 
78  switch (MO.getType()) {
79  default:
80  llvm_unreachable ("<unknown operand type>");
83  return;
85  O << MO.getImm();
86  return;
88  MO.getMBB()->getSymbol()->print(O, MAI);
89  return;
91  GetCPISymbol(MO.getIndex())->print(O, MAI);
92  return;
94  // Computing the address of a global symbol, not calling it.
95  getSymbol(MO.getGlobal())->print(O, MAI);
96  printOffset(MO.getOffset(), O);
97  return;
98  }
99 }
100 
101 // isBlockOnlyReachableByFallthrough - We need to override this since the
102 // default AsmPrinter does not print labels for any basic block that
103 // is only reachable by a fall through. That works for all cases except
104 // for the case in which the basic block is reachable by a fall through but
105 // through an indirect from a jump table. In this case, the jump table
106 // will contain a label not defined by AsmPrinter.
108  const MachineBasicBlock *MBB) const {
109  if (MBB->hasAddressTaken())
110  return false;
112 }
113 
114 /// PrintAsmOperand - Print out an operand for an inline asm expression.
116  const char *ExtraCode,
117  raw_ostream &OS) {
118  // Does this asm operand have a single letter operand modifier?
119  if (ExtraCode && ExtraCode[0]) {
120  if (ExtraCode[1] != 0)
121  return true; // Unknown modifier.
122 
123  switch (ExtraCode[0]) {
124  default:
125  // See if this is a generic print operand
126  return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
127  case 'L':
128  case 'H': { // The highest-numbered register of a pair.
129  const MachineOperand &MO = MI->getOperand(OpNo);
130  const MachineFunction &MF = *MI->getParent()->getParent();
132  if (!MO.isReg())
133  return true;
134  unsigned RegNumber = MO.getReg();
135  // This should be an assert in the frontend.
136  if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
137  RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
138  Hexagon::isub_lo :
139  Hexagon::isub_hi);
140  OS << HexagonInstPrinter::getRegisterName(RegNumber);
141  return false;
142  }
143  case 'I':
144  // Write 'i' if an integer constant, otherwise nothing. Used to print
145  // addi vs add, etc.
146  if (MI->getOperand(OpNo).isImm())
147  OS << "i";
148  return false;
149  }
150  }
151 
152  printOperand(MI, OpNo, OS);
153  return false;
154 }
155 
157  unsigned OpNo,
158  const char *ExtraCode,
159  raw_ostream &O) {
160  if (ExtraCode && ExtraCode[0])
161  return true; // Unknown modifier.
162 
163  const MachineOperand &Base = MI->getOperand(OpNo);
164  const MachineOperand &Offset = MI->getOperand(OpNo+1);
165 
166  if (Base.isReg())
167  printOperand(MI, OpNo, O);
168  else
169  llvm_unreachable("Unimplemented");
170 
171  if (Offset.isImm()) {
172  if (Offset.getImm())
173  O << "+#" << Offset.getImm();
174  } else {
175  llvm_unreachable("Unimplemented");
176  }
177 
178  return false;
179 }
180 
182  MCStreamer &OutStreamer, const MCOperand &Imm,
183  int AlignSize) {
184  MCSymbol *Sym;
185  int64_t Value;
186  if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
187  StringRef sectionPrefix;
188  std::string ImmString;
189  StringRef Name;
190  if (AlignSize == 8) {
191  Name = ".CONST_0000000000000000";
192  sectionPrefix = ".gnu.linkonce.l8";
193  ImmString = utohexstr(Value);
194  } else {
195  Name = ".CONST_00000000";
196  sectionPrefix = ".gnu.linkonce.l4";
197  ImmString = utohexstr(static_cast<uint32_t>(Value));
198  }
199 
200  std::string symbolName = // Yes, leading zeros are kept.
201  Name.drop_back(ImmString.size()).str() + ImmString;
202  std::string sectionName = sectionPrefix.str() + symbolName;
203 
204  MCSectionELF *Section = OutStreamer.getContext().getELFSection(
206  OutStreamer.SwitchSection(Section);
207 
208  Sym = AP.OutContext.getOrCreateSymbol(Twine(symbolName));
209  if (Sym->isUndefined()) {
210  OutStreamer.EmitLabel(Sym);
211  OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global);
212  OutStreamer.EmitIntValue(Value, AlignSize);
213  OutStreamer.EmitCodeAlignment(AlignSize);
214  }
215  } else {
216  assert(Imm.isExpr() && "Expected expression and found none");
217  const MachineOperand &MO = MI.getOperand(1);
218  assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
219  MCSymbol *MOSymbol = nullptr;
220  if (MO.isGlobal())
221  MOSymbol = AP.getSymbol(MO.getGlobal());
222  else if (MO.isCPI())
223  MOSymbol = AP.GetCPISymbol(MO.getIndex());
224  else if (MO.isJTI())
225  MOSymbol = AP.GetJTISymbol(MO.getIndex());
226  else
227  llvm_unreachable("Unknown operand type!");
228 
229  StringRef SymbolName = MOSymbol->getName();
230  std::string LitaName = ".CONST_" + SymbolName.str();
231 
232  MCSectionELF *Section = OutStreamer.getContext().getELFSection(
234 
235  OutStreamer.SwitchSection(Section);
236  Sym = AP.OutContext.getOrCreateSymbol(Twine(LitaName));
237  if (Sym->isUndefined()) {
238  OutStreamer.EmitLabel(Sym);
239  OutStreamer.EmitSymbolAttribute(Sym, MCSA_Local);
240  OutStreamer.EmitValue(Imm.getExpr(), AlignSize);
241  OutStreamer.EmitCodeAlignment(AlignSize);
242  }
243  }
244  return Sym;
245 }
246 
247 static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
248  unsigned VectorSize, MCContext &Ctx) {
249  MCInst T;
250  T.setOpcode(Inst.getOpcode());
251  for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
252  if (i != OpNo) {
253  T.addOperand(Inst.getOperand(i));
254  continue;
255  }
256  MCOperand &ImmOp = Inst.getOperand(i);
257  const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
258  int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
259  auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
260  auto *NewHE = HexagonMCExpr::create(NewCE, Ctx);
262  }
263  return T;
264 }
265 
267  const MachineInstr &MI) {
268  MCInst &MappedInst = static_cast <MCInst &>(Inst);
269  const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
270  const MachineFunction &MF = *MI.getParent()->getParent();
271  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
272  unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
273 
274  switch (Inst.getOpcode()) {
275  default:
276  return;
277 
278  case Hexagon::A2_iconst: {
279  Inst.setOpcode(Hexagon::A2_addi);
280  MCOperand Reg = Inst.getOperand(0);
281  MCOperand S16 = Inst.getOperand(1);
284  Inst.clear();
285  Inst.addOperand(Reg);
286  Inst.addOperand(MCOperand::createReg(Hexagon::R0));
287  Inst.addOperand(S16);
288  break;
289  }
290 
291  case Hexagon::A2_tfrf: {
293  Inst.setOpcode(Hexagon::A2_paddif);
294  Inst.addOperand(MCOperand::createExpr(Zero));
295  break;
296  }
297 
298  case Hexagon::A2_tfrt: {
300  Inst.setOpcode(Hexagon::A2_paddit);
301  Inst.addOperand(MCOperand::createExpr(Zero));
302  break;
303  }
304 
305  case Hexagon::A2_tfrfnew: {
307  Inst.setOpcode(Hexagon::A2_paddifnew);
308  Inst.addOperand(MCOperand::createExpr(Zero));
309  break;
310  }
311 
312  case Hexagon::A2_tfrtnew: {
314  Inst.setOpcode(Hexagon::A2_padditnew);
315  Inst.addOperand(MCOperand::createExpr(Zero));
316  break;
317  }
318 
319  case Hexagon::A2_zxtb: {
321  Inst.setOpcode(Hexagon::A2_andir);
322  Inst.addOperand(MCOperand::createExpr(C255));
323  break;
324  }
325 
326  // "$dst = CONST64(#$src1)",
327  case Hexagon::CONST64:
328  if (!OutStreamer->hasRawTextSupport()) {
329  const MCOperand &Imm = MappedInst.getOperand(1);
330  MCSectionSubPair Current = OutStreamer->getCurrentSection();
331 
332  MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8);
333 
334  OutStreamer->SwitchSection(Current.first, Current.second);
335  MCInst TmpInst;
336  MCOperand &Reg = MappedInst.getOperand(0);
337  TmpInst.setOpcode(Hexagon::L2_loadrdgp);
338  TmpInst.addOperand(Reg);
341  MappedInst = TmpInst;
342 
343  }
344  break;
345  case Hexagon::CONST32:
346  if (!OutStreamer->hasRawTextSupport()) {
347  MCOperand &Imm = MappedInst.getOperand(1);
348  MCSectionSubPair Current = OutStreamer->getCurrentSection();
349  MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4);
350  OutStreamer->SwitchSection(Current.first, Current.second);
351  MCInst TmpInst;
352  MCOperand &Reg = MappedInst.getOperand(0);
353  TmpInst.setOpcode(Hexagon::L2_loadrigp);
354  TmpInst.addOperand(Reg);
357  MappedInst = TmpInst;
358  }
359  break;
360 
361  // C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
362  // C2_or during instruction selection itself but it results
363  // into suboptimal code.
364  case Hexagon::C2_pxfer_map: {
365  MCOperand &Ps = Inst.getOperand(1);
366  MappedInst.setOpcode(Hexagon::C2_or);
367  MappedInst.addOperand(Ps);
368  return;
369  }
370 
371  // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
372  // The insn is mapped from the 4 operand to the 3 operand raw form taking
373  // 3 register pairs.
374  case Hexagon::M2_vrcmpys_acc_s1: {
375  MCOperand &Rt = Inst.getOperand(3);
376  assert(Rt.isReg() && "Expected register and none was found");
377  unsigned Reg = RI->getEncodingValue(Rt.getReg());
378  if (Reg & 1)
379  MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
380  else
381  MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
382  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
383  return;
384  }
385  case Hexagon::M2_vrcmpys_s1: {
386  MCOperand &Rt = Inst.getOperand(2);
387  assert(Rt.isReg() && "Expected register and none was found");
388  unsigned Reg = RI->getEncodingValue(Rt.getReg());
389  if (Reg & 1)
390  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
391  else
392  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
393  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
394  return;
395  }
396 
397  case Hexagon::M2_vrcmpys_s1rp: {
398  MCOperand &Rt = Inst.getOperand(2);
399  assert(Rt.isReg() && "Expected register and none was found");
400  unsigned Reg = RI->getEncodingValue(Rt.getReg());
401  if (Reg & 1)
402  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
403  else
404  MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
405  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
406  return;
407  }
408 
409  case Hexagon::A4_boundscheck: {
410  MCOperand &Rs = Inst.getOperand(1);
411  assert(Rs.isReg() && "Expected register and none was found");
412  unsigned Reg = RI->getEncodingValue(Rs.getReg());
413  if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
414  MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
415  else // raw:lo
416  MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
417  Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
418  return;
419  }
420 
421  case Hexagon::PS_call_nr:
422  Inst.setOpcode(Hexagon::J2_call);
423  break;
424 
425  case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
426  MCOperand &MO = MappedInst.getOperand(2);
427  int64_t Imm;
428  MCExpr const *Expr = MO.getExpr();
429  bool Success = Expr->evaluateAsAbsolute(Imm);
430  assert(Success && "Expected immediate and none was found");
431  (void)Success;
432  MCInst TmpInst;
433  if (Imm == 0) {
434  TmpInst.setOpcode(Hexagon::S2_vsathub);
435  TmpInst.addOperand(MappedInst.getOperand(0));
436  TmpInst.addOperand(MappedInst.getOperand(1));
437  MappedInst = TmpInst;
438  return;
439  }
440  TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
441  TmpInst.addOperand(MappedInst.getOperand(0));
442  TmpInst.addOperand(MappedInst.getOperand(1));
443  const MCExpr *One = MCConstantExpr::create(1, OutContext);
444  const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
445  TmpInst.addOperand(
447  MappedInst = TmpInst;
448  return;
449  }
450 
451  case Hexagon::S5_vasrhrnd_goodsyntax:
452  case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
453  MCOperand &MO2 = MappedInst.getOperand(2);
454  MCExpr const *Expr = MO2.getExpr();
455  int64_t Imm;
456  bool Success = Expr->evaluateAsAbsolute(Imm);
457  assert(Success && "Expected immediate and none was found");
458  (void)Success;
459  MCInst TmpInst;
460  if (Imm == 0) {
461  TmpInst.setOpcode(Hexagon::A2_combinew);
462  TmpInst.addOperand(MappedInst.getOperand(0));
463  MCOperand &MO1 = MappedInst.getOperand(1);
464  unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
465  unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
466  // Add a new operand for the second register in the pair.
467  TmpInst.addOperand(MCOperand::createReg(High));
468  TmpInst.addOperand(MCOperand::createReg(Low));
469  MappedInst = TmpInst;
470  return;
471  }
472 
473  if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
474  TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
475  else
476  TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
477  TmpInst.addOperand(MappedInst.getOperand(0));
478  TmpInst.addOperand(MappedInst.getOperand(1));
479  const MCExpr *One = MCConstantExpr::create(1, OutContext);
480  const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
481  TmpInst.addOperand(
483  MappedInst = TmpInst;
484  return;
485  }
486 
487  // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
488  case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
489  MCOperand &MO = Inst.getOperand(2);
490  MCExpr const *Expr = MO.getExpr();
491  int64_t Imm;
492  bool Success = Expr->evaluateAsAbsolute(Imm);
493  assert(Success && "Expected immediate and none was found");
494  (void)Success;
495  MCInst TmpInst;
496  if (Imm == 0) {
497  TmpInst.setOpcode(Hexagon::A2_tfr);
498  TmpInst.addOperand(MappedInst.getOperand(0));
499  TmpInst.addOperand(MappedInst.getOperand(1));
500  MappedInst = TmpInst;
501  return;
502  }
503  TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
504  TmpInst.addOperand(MappedInst.getOperand(0));
505  TmpInst.addOperand(MappedInst.getOperand(1));
506  const MCExpr *One = MCConstantExpr::create(1, OutContext);
507  const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
508  TmpInst.addOperand(
510  MappedInst = TmpInst;
511  return;
512  }
513 
514  // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
515  case Hexagon::A2_tfrpi: {
516  MCInst TmpInst;
517  MCOperand &Rdd = MappedInst.getOperand(0);
518  MCOperand &MO = MappedInst.getOperand(1);
519 
520  TmpInst.setOpcode(Hexagon::A2_combineii);
521  TmpInst.addOperand(Rdd);
522  int64_t Imm;
523  bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
524  if (Success && Imm < 0) {
525  const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
527  TmpInst.addOperand(MCOperand::createExpr(E));
528  } else {
529  const MCExpr *Zero = MCConstantExpr::create(0, OutContext);
531  TmpInst.addOperand(MCOperand::createExpr(E));
532  }
533  TmpInst.addOperand(MO);
534  MappedInst = TmpInst;
535  return;
536  }
537 
538  // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
539  case Hexagon::A2_tfrp: {
540  MCOperand &MO = MappedInst.getOperand(1);
541  unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
542  unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
543  MO.setReg(High);
544  // Add a new operand for the second register in the pair.
545  MappedInst.addOperand(MCOperand::createReg(Low));
546  MappedInst.setOpcode(Hexagon::A2_combinew);
547  return;
548  }
549 
550  case Hexagon::A2_tfrpt:
551  case Hexagon::A2_tfrpf: {
552  MCOperand &MO = MappedInst.getOperand(2);
553  unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
554  unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
555  MO.setReg(High);
556  // Add a new operand for the second register in the pair.
557  MappedInst.addOperand(MCOperand::createReg(Low));
558  MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
559  ? Hexagon::C2_ccombinewt
560  : Hexagon::C2_ccombinewf);
561  return;
562  }
563 
564  case Hexagon::A2_tfrptnew:
565  case Hexagon::A2_tfrpfnew: {
566  MCOperand &MO = MappedInst.getOperand(2);
567  unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
568  unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
569  MO.setReg(High);
570  // Add a new operand for the second register in the pair.
571  MappedInst.addOperand(MCOperand::createReg(Low));
572  MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
573  ? Hexagon::C2_ccombinewnewt
574  : Hexagon::C2_ccombinewnewf);
575  return;
576  }
577 
578  case Hexagon::M2_mpysmi: {
579  MCOperand &Imm = MappedInst.getOperand(2);
580  MCExpr const *Expr = Imm.getExpr();
581  int64_t Value;
582  bool Success = Expr->evaluateAsAbsolute(Value);
583  assert(Success);
584  (void)Success;
585  if (Value < 0 && Value > -256) {
586  MappedInst.setOpcode(Hexagon::M2_mpysin);
589  } else
590  MappedInst.setOpcode(Hexagon::M2_mpysip);
591  return;
592  }
593 
594  case Hexagon::A2_addsp: {
595  MCOperand &Rt = Inst.getOperand(1);
596  assert(Rt.isReg() && "Expected register and none was found");
597  unsigned Reg = RI->getEncodingValue(Rt.getReg());
598  if (Reg & 1)
599  MappedInst.setOpcode(Hexagon::A2_addsph);
600  else
601  MappedInst.setOpcode(Hexagon::A2_addspl);
602  Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
603  return;
604  }
605 
606  case Hexagon::V6_vd0: {
607  MCInst TmpInst;
608  assert(Inst.getOperand(0).isReg() &&
609  "Expected register and none was found");
610 
611  TmpInst.setOpcode(Hexagon::V6_vxor);
612  TmpInst.addOperand(Inst.getOperand(0));
613  TmpInst.addOperand(Inst.getOperand(0));
614  TmpInst.addOperand(Inst.getOperand(0));
615  MappedInst = TmpInst;
616  return;
617  }
618 
619  case Hexagon::V6_vdd0: {
620  MCInst TmpInst;
621  assert (Inst.getOperand(0).isReg() &&
622  "Expected register and none was found");
623 
624  TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
625  TmpInst.addOperand(Inst.getOperand(0));
626  TmpInst.addOperand(Inst.getOperand(0));
627  TmpInst.addOperand(Inst.getOperand(0));
628  MappedInst = TmpInst;
629  return;
630  }
631 
632  case Hexagon::V6_vL32Ub_pi:
633  case Hexagon::V6_vL32b_cur_pi:
634  case Hexagon::V6_vL32b_nt_cur_pi:
635  case Hexagon::V6_vL32b_pi:
636  case Hexagon::V6_vL32b_nt_pi:
637  case Hexagon::V6_vL32b_nt_tmp_pi:
638  case Hexagon::V6_vL32b_tmp_pi:
639  MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
640  return;
641 
642  case Hexagon::V6_vL32Ub_ai:
643  case Hexagon::V6_vL32b_ai:
644  case Hexagon::V6_vL32b_cur_ai:
645  case Hexagon::V6_vL32b_nt_ai:
646  case Hexagon::V6_vL32b_nt_cur_ai:
647  case Hexagon::V6_vL32b_nt_tmp_ai:
648  case Hexagon::V6_vL32b_tmp_ai:
649  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
650  return;
651 
652  case Hexagon::V6_vS32Ub_pi:
653  case Hexagon::V6_vS32b_new_pi:
654  case Hexagon::V6_vS32b_nt_new_pi:
655  case Hexagon::V6_vS32b_nt_pi:
656  case Hexagon::V6_vS32b_pi:
657  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
658  return;
659 
660  case Hexagon::V6_vS32Ub_ai:
661  case Hexagon::V6_vS32b_ai:
662  case Hexagon::V6_vS32b_new_ai:
663  case Hexagon::V6_vS32b_nt_ai:
664  case Hexagon::V6_vS32b_nt_new_ai:
665  MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
666  return;
667 
668  case Hexagon::V6_vL32b_cur_npred_pi:
669  case Hexagon::V6_vL32b_cur_pred_pi:
670  case Hexagon::V6_vL32b_npred_pi:
671  case Hexagon::V6_vL32b_nt_cur_npred_pi:
672  case Hexagon::V6_vL32b_nt_cur_pred_pi:
673  case Hexagon::V6_vL32b_nt_npred_pi:
674  case Hexagon::V6_vL32b_nt_pred_pi:
675  case Hexagon::V6_vL32b_nt_tmp_npred_pi:
676  case Hexagon::V6_vL32b_nt_tmp_pred_pi:
677  case Hexagon::V6_vL32b_pred_pi:
678  case Hexagon::V6_vL32b_tmp_npred_pi:
679  case Hexagon::V6_vL32b_tmp_pred_pi:
680  MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
681  return;
682 
683  case Hexagon::V6_vL32b_cur_npred_ai:
684  case Hexagon::V6_vL32b_cur_pred_ai:
685  case Hexagon::V6_vL32b_npred_ai:
686  case Hexagon::V6_vL32b_nt_cur_npred_ai:
687  case Hexagon::V6_vL32b_nt_cur_pred_ai:
688  case Hexagon::V6_vL32b_nt_npred_ai:
689  case Hexagon::V6_vL32b_nt_pred_ai:
690  case Hexagon::V6_vL32b_nt_tmp_npred_ai:
691  case Hexagon::V6_vL32b_nt_tmp_pred_ai:
692  case Hexagon::V6_vL32b_pred_ai:
693  case Hexagon::V6_vL32b_tmp_npred_ai:
694  case Hexagon::V6_vL32b_tmp_pred_ai:
695  MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
696  return;
697 
698  case Hexagon::V6_vS32Ub_npred_pi:
699  case Hexagon::V6_vS32Ub_pred_pi:
700  case Hexagon::V6_vS32b_new_npred_pi:
701  case Hexagon::V6_vS32b_new_pred_pi:
702  case Hexagon::V6_vS32b_npred_pi:
703  case Hexagon::V6_vS32b_nqpred_pi:
704  case Hexagon::V6_vS32b_nt_new_npred_pi:
705  case Hexagon::V6_vS32b_nt_new_pred_pi:
706  case Hexagon::V6_vS32b_nt_npred_pi:
707  case Hexagon::V6_vS32b_nt_nqpred_pi:
708  case Hexagon::V6_vS32b_nt_pred_pi:
709  case Hexagon::V6_vS32b_nt_qpred_pi:
710  case Hexagon::V6_vS32b_pred_pi:
711  case Hexagon::V6_vS32b_qpred_pi:
712  MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
713  return;
714 
715  case Hexagon::V6_vS32Ub_npred_ai:
716  case Hexagon::V6_vS32Ub_pred_ai:
717  case Hexagon::V6_vS32b_new_npred_ai:
718  case Hexagon::V6_vS32b_new_pred_ai:
719  case Hexagon::V6_vS32b_npred_ai:
720  case Hexagon::V6_vS32b_nqpred_ai:
721  case Hexagon::V6_vS32b_nt_new_npred_ai:
722  case Hexagon::V6_vS32b_nt_new_pred_ai:
723  case Hexagon::V6_vS32b_nt_npred_ai:
724  case Hexagon::V6_vS32b_nt_nqpred_ai:
725  case Hexagon::V6_vS32b_nt_pred_ai:
726  case Hexagon::V6_vS32b_nt_qpred_ai:
727  case Hexagon::V6_vS32b_pred_ai:
728  case Hexagon::V6_vS32b_qpred_ai:
729  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
730  return;
731 
732  // V65+
733  case Hexagon::V6_vS32b_srls_ai:
734  MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
735  return;
736 
737  case Hexagon::V6_vS32b_srls_pi:
738  MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
739  return;
740  }
741 }
742 
743 /// Print out a single Hexagon MI to the current output stream.
745  MCInst MCB;
746  MCB.setOpcode(Hexagon::BUNDLE);
748  const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
749 
750  if (MI->isBundle()) {
751  const MachineBasicBlock* MBB = MI->getParent();
753 
754  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
755  if (!MII->isDebugInstr() && !MII->isImplicitDef())
756  HexagonLowerToMC(MCII, &*MII, MCB, *this);
757  } else {
758  HexagonLowerToMC(MCII, MI, MCB, *this);
759  }
760 
761  const MachineFunction &MF = *MI->getParent()->getParent();
762  const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
763  if (MI->isBundle() && HII.getBundleNoShuf(*MI))
765 
766  MCContext &Ctx = OutStreamer->getContext();
767  bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, *Subtarget, Ctx,
768  MCB, nullptr);
769  assert(Ok); (void)Ok;
770  if (HexagonMCInstrInfo::bundleSize(MCB) == 0)
771  return;
772  OutStreamer->EmitInstruction(MCB, getSubtargetInfo());
773 }
774 
777 }
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:93
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void clear()
Definition: MCInst.h:188
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:88
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:227
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
MachineBasicBlock reference.
static MCSymbol * smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize)
unsigned const TargetRegisterInfo * TRI
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:96
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t High
return AArch64::GPR64RegClass contains(Reg)
MCContext & getContext() const
Definition: MCStreamer.h:250
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
MCSuperRegIterator enumerates all super-registers of Reg.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
.local (ELF)
Definition: MCDirectives.h:35
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
Definition: MCContext.h:62
bool isBundle() const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:544
#define T
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
const MCExpr * getExpr() const
Definition: MCInst.h:95
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:128
void EmitInstruction(const MachineInstr *MI) override
Print out a single Hexagon MI to the current output stream.
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:159
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI)
void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP)
void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB)
Address of a global value.
Streaming machine code generation interface.
Definition: MCStreamer.h:188
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:84
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
const GlobalValue * getGlobal() const
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:78
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
bool isExpr() const
Definition: MCInst.h:60
self_iterator getIterator()
Definition: ilist_node.h:81
unsigned getNumOperands() const
Definition: MCInst.h:181
static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx)
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:385
void LLVMInitializeHexagonAsmPrinter()
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
std::pair< MCSection *, const MCExpr * > MCSectionSubPair
Definition: MCStreamer.h:56
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:440
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:256
MachineOperand class - Representation of each machine instruction operand.
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
int64_t getImm() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
#define Success
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
.type _foo,
Definition: MCDirectives.h:30
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:123
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
PrintAsmOperand - Print out an operand for an inline asm expression.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:128
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:70
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:388
LLVM Value Representation.
Definition: Value.h:72
static char const * getRegisterName(unsigned RegNo)
const HexagonInstrInfo * getInstrInfo() const override
LLVM_NODISCARD StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:628
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:351
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
Address of indexed Constant in Constant Pool.
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getOpcode() const
Definition: MCInst.h:171
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
Target & getTheHexagonTarget()
std::string utohexstr(uint64_t X, bool LowerCase=false)
Definition: StringExtras.h:124
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
void setExpr(const MCExpr *Val)
Definition: MCInst.h:100