LLVM  6.0.0svn
HexagonBitTracker.h
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1 //===- HexagonBitTracker.h --------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
12 
13 #include "BitTracker.h"
14 #include "llvm/ADT/DenseMap.h"
15 #include <cstdint>
16 
17 namespace llvm {
18 
19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineFrameInfo;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineRegisterInfo;
25 
31 
33  const HexagonInstrInfo &tii, MachineFunction &mf);
34 
35  bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
36  CellMapType &Outputs) const override;
37  bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
38  BranchTargetList &Targets, bool &FallsThru) const override;
39 
40  BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
41 
42  uint16_t getPhysRegBitWidth(unsigned Reg) const override;
43 
45  const TargetRegisterClass &RC, unsigned Idx) const override;
46 
50 
51 private:
52  bool evaluateLoad(const MachineInstr &MI, const CellMapType &Inputs,
53  CellMapType &Outputs) const;
54  bool evaluateFormalCopy(const MachineInstr &MI, const CellMapType &Inputs,
55  CellMapType &Outputs) const;
56 
57  unsigned getNextPhysReg(unsigned PReg, unsigned Width) const;
58  unsigned getVirtRegFor(unsigned PReg) const;
59 
60  // Type of formal parameter extension.
61  struct ExtType {
62  enum { SExt, ZExt };
63 
64  ExtType() = default;
65  ExtType(char t, uint16_t w) : Type(t), Width(w) {}
66 
67  char Type = 0;
68  uint16_t Width = 0;
69  };
70  // Map VR -> extension type.
72  RegExtMap VRX;
73 };
74 
75 } // end namespace llvm
76 
77 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override
MachineFrameInfo & MFI
const HexagonInstrInfo & TII
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
SetVector< const MachineBasicBlock * > BranchTargetList
Definition: BitTracker.h:43
BitTracker::CellMapType CellMapType
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
uint16_t getPhysRegBitWidth(unsigned Reg) const override
std::map< unsigned, RegisterCell > CellMapType
Definition: BitTracker.h:44
MachineFunction & MF
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
A vector that has set insertion semantics.
Definition: SetVector.h:41
IRTranslator LLVM IR MI