LLVM  10.0.0svn
HexagonDepTimingClasses.h
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1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // Automatically generated file, please consult code owner before editing.
9 //===----------------------------------------------------------------------===//
10 
11 
12 #ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
13 #define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
14 
15 #include "HexagonInstrInfo.h"
16 
17 namespace llvm {
18 
19 inline bool is_TC3x(unsigned SchedClass) {
20  switch (SchedClass) {
21  case Hexagon::Sched::tc_05d3a09b:
22  case Hexagon::Sched::tc_0d8f5752:
23  case Hexagon::Sched::tc_13bfbcf9:
24  case Hexagon::Sched::tc_174516e8:
25  case Hexagon::Sched::tc_1a2fd869:
26  case Hexagon::Sched::tc_1c4528a2:
27  case Hexagon::Sched::tc_32779c6f:
28  case Hexagon::Sched::tc_5b54b33f:
29  case Hexagon::Sched::tc_6b25e783:
30  case Hexagon::Sched::tc_76851da1:
31  case Hexagon::Sched::tc_9debc299:
32  case Hexagon::Sched::tc_a9d88b22:
33  case Hexagon::Sched::tc_bafaade3:
34  case Hexagon::Sched::tc_bcf98408:
35  case Hexagon::Sched::tc_bdceeac1:
36  case Hexagon::Sched::tc_c8ce0b5c:
37  case Hexagon::Sched::tc_d1aa9eaa:
38  case Hexagon::Sched::tc_d773585a:
39  case Hexagon::Sched::tc_df3319ed:
40  return true;
41  default:
42  return false;
43  }
44 }
45 
46 inline bool is_TC2early(unsigned SchedClass) {
47  switch (SchedClass) {
48  case Hexagon::Sched::tc_b4407292:
49  case Hexagon::Sched::tc_fc3999b4:
50  return true;
51  default:
52  return false;
53  }
54 }
55 
56 inline bool is_TC4x(unsigned SchedClass) {
57  switch (SchedClass) {
58  case Hexagon::Sched::tc_2f7c551d:
59  case Hexagon::Sched::tc_2ff964b4:
60  case Hexagon::Sched::tc_3a867367:
61  case Hexagon::Sched::tc_3b470976:
62  case Hexagon::Sched::tc_4560740b:
63  case Hexagon::Sched::tc_a58fd5cc:
64  case Hexagon::Sched::tc_b8bffe55:
65  return true;
66  default:
67  return false;
68  }
69 }
70 
71 inline bool is_TC2(unsigned SchedClass) {
72  switch (SchedClass) {
73  case Hexagon::Sched::tc_002cb246:
74  case Hexagon::Sched::tc_14b5c689:
75  case Hexagon::Sched::tc_1c80410a:
76  case Hexagon::Sched::tc_4414d8b1:
77  case Hexagon::Sched::tc_6132ba3d:
78  case Hexagon::Sched::tc_61830035:
79  case Hexagon::Sched::tc_679309b8:
80  case Hexagon::Sched::tc_703e822c:
81  case Hexagon::Sched::tc_779080bf:
82  case Hexagon::Sched::tc_784490da:
83  case Hexagon::Sched::tc_88b4f13d:
84  case Hexagon::Sched::tc_9461ff31:
85  case Hexagon::Sched::tc_9e313203:
86  case Hexagon::Sched::tc_a813cf9a:
87  case Hexagon::Sched::tc_bfec0f01:
88  case Hexagon::Sched::tc_cf8126ae:
89  case Hexagon::Sched::tc_d08ee0f4:
90  case Hexagon::Sched::tc_e4a7f9f0:
91  case Hexagon::Sched::tc_f429765c:
92  case Hexagon::Sched::tc_f675fee8:
93  case Hexagon::Sched::tc_f9058dd7:
94  return true;
95  default:
96  return false;
97  }
98 }
99 
100 inline bool is_TC1(unsigned SchedClass) {
101  switch (SchedClass) {
102  case Hexagon::Sched::tc_0663f615:
103  case Hexagon::Sched::tc_0a705168:
104  case Hexagon::Sched::tc_0ae0825c:
105  case Hexagon::Sched::tc_1b6f7cec:
106  case Hexagon::Sched::tc_1fc97744:
107  case Hexagon::Sched::tc_20cdee80:
108  case Hexagon::Sched::tc_2332b92e:
109  case Hexagon::Sched::tc_2eabeebe:
110  case Hexagon::Sched::tc_3d495a39:
111  case Hexagon::Sched::tc_4c5ba658:
112  case Hexagon::Sched::tc_56336eb0:
113  case Hexagon::Sched::tc_56f114f4:
114  case Hexagon::Sched::tc_57890846:
115  case Hexagon::Sched::tc_5a2711e5:
116  case Hexagon::Sched::tc_5b7c0967:
117  case Hexagon::Sched::tc_640086b5:
118  case Hexagon::Sched::tc_643b4717:
119  case Hexagon::Sched::tc_85c9c08f:
120  case Hexagon::Sched::tc_85d5d03f:
121  case Hexagon::Sched::tc_862b3e70:
122  case Hexagon::Sched::tc_946df596:
123  case Hexagon::Sched::tc_9c3ecd83:
124  case Hexagon::Sched::tc_9fc3dae0:
125  case Hexagon::Sched::tc_a1123dda:
126  case Hexagon::Sched::tc_a1c00888:
127  case Hexagon::Sched::tc_ae53734a:
128  case Hexagon::Sched::tc_b31c2e97:
129  case Hexagon::Sched::tc_b4b5c03a:
130  case Hexagon::Sched::tc_b51dc29a:
131  case Hexagon::Sched::tc_cd374165:
132  case Hexagon::Sched::tc_cfd8378a:
133  case Hexagon::Sched::tc_d5b7b0c1:
134  case Hexagon::Sched::tc_d9d43ecb:
135  case Hexagon::Sched::tc_db2bce9c:
136  case Hexagon::Sched::tc_de4df740:
137  case Hexagon::Sched::tc_de554571:
138  case Hexagon::Sched::tc_e78647bd:
139  return true;
140  default:
141  return false;
142  }
143 }
144 } // namespace llvm
145 
146 #endif
bool is_TC2early(unsigned SchedClass)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool is_TC1(unsigned SchedClass)
bool is_TC2(unsigned SchedClass)
bool is_TC3x(unsigned SchedClass)
bool is_TC4x(unsigned SchedClass)