LLVM  6.0.0svn
HexagonDepTimingClasses.h
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1 //===--- HexagonDepTimingClasses.h ----------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 #ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
10 #define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
11 
12 #include "HexagonInstrInfo.h"
13 
14 namespace llvm {
15 
16 inline bool is_TC3x(unsigned SchedClass) {
17  switch (SchedClass) {
18  case Hexagon::Sched::tc_1000eb10:
19  case Hexagon::Sched::tc_2aaab1e0:
20  case Hexagon::Sched::tc_4997da4a:
21  case Hexagon::Sched::tc_5d806107:
22  case Hexagon::Sched::tc_6264c5e0:
23  case Hexagon::Sched::tc_69bb508b:
24  case Hexagon::Sched::tc_8c8041e6:
25  case Hexagon::Sched::tc_8cb685d9:
26  case Hexagon::Sched::tc_a12a5971:
27  case Hexagon::Sched::tc_ae0722f7:
28  case Hexagon::Sched::tc_ae2c2dc2:
29  case Hexagon::Sched::tc_bc5561d8:
30  case Hexagon::Sched::tc_d6a805a8:
31  case Hexagon::Sched::tc_f055fbb6:
32  case Hexagon::Sched::tc_feb4974b:
33  return true;
34  default:
35  return false;
36  }
37 }
38 
39 inline bool is_TC2early(unsigned SchedClass) {
40  switch (SchedClass) {
41  case Hexagon::Sched::tc_35fb9d13:
42  case Hexagon::Sched::tc_cbe45117:
43  return true;
44  default:
45  return false;
46  }
47 }
48 
49 inline bool is_TC4x(unsigned SchedClass) {
50  switch (SchedClass) {
51  case Hexagon::Sched::tc_09c86199:
52  case Hexagon::Sched::tc_2d1e6f5c:
53  case Hexagon::Sched::tc_2e55aa16:
54  case Hexagon::Sched::tc_3bea1824:
55  case Hexagon::Sched::tc_e836c161:
56  case Hexagon::Sched::tc_f1aa2cdb:
57  return true;
58  default:
59  return false;
60  }
61 }
62 
63 inline bool is_TC2(unsigned SchedClass) {
64  switch (SchedClass) {
65  case Hexagon::Sched::tc_090485bb:
66  case Hexagon::Sched::tc_1fe8323c:
67  case Hexagon::Sched::tc_37326008:
68  case Hexagon::Sched::tc_3c10f809:
69  case Hexagon::Sched::tc_47ab9233:
70  case Hexagon::Sched::tc_485bb57c:
71  case Hexagon::Sched::tc_511f28f6:
72  case Hexagon::Sched::tc_583510c7:
73  case Hexagon::Sched::tc_63cd9d2d:
74  case Hexagon::Sched::tc_76c4c5ef:
75  case Hexagon::Sched::tc_7ca2ea10:
76  case Hexagon::Sched::tc_87601822:
77  case Hexagon::Sched::tc_88fa2da6:
78  case Hexagon::Sched::tc_94e6ffd9:
79  case Hexagon::Sched::tc_ab1b5e74:
80  case Hexagon::Sched::tc_b0f50e3c:
81  case Hexagon::Sched::tc_bd16579e:
82  case Hexagon::Sched::tc_c0cd91a8:
83  case Hexagon::Sched::tc_ca280e8b:
84  case Hexagon::Sched::tc_cd321066:
85  case Hexagon::Sched::tc_d95f4e98:
86  case Hexagon::Sched::tc_e17ce9ad:
87  case Hexagon::Sched::tc_f1240c08:
88  case Hexagon::Sched::tc_faab1248:
89  return true;
90  default:
91  return false;
92  }
93 }
94 
95 inline bool is_TC1(unsigned SchedClass) {
96  switch (SchedClass) {
97  case Hexagon::Sched::tc_07ac815d:
98  case Hexagon::Sched::tc_1b6011fb:
99  case Hexagon::Sched::tc_1b834fe7:
100  case Hexagon::Sched::tc_1e062b18:
101  case Hexagon::Sched::tc_1f9668cc:
102  case Hexagon::Sched::tc_43068634:
103  case Hexagon::Sched::tc_47f0b7ad:
104  case Hexagon::Sched::tc_537e2013:
105  case Hexagon::Sched::tc_548f402d:
106  case Hexagon::Sched::tc_5fa2857c:
107  case Hexagon::Sched::tc_5fe9fcd0:
108  case Hexagon::Sched::tc_78b3c689:
109  case Hexagon::Sched::tc_7c2dcd4d:
110  case Hexagon::Sched::tc_81a23d44:
111  case Hexagon::Sched::tc_821c4233:
112  case Hexagon::Sched::tc_92d1833c:
113  case Hexagon::Sched::tc_9a13af9d:
114  case Hexagon::Sched::tc_9c18c9a5:
115  case Hexagon::Sched::tc_9df8b0dc:
116  case Hexagon::Sched::tc_9f518242:
117  case Hexagon::Sched::tc_a1fb80e1:
118  case Hexagon::Sched::tc_a333d2a9:
119  case Hexagon::Sched::tc_a87879e8:
120  case Hexagon::Sched::tc_aad55963:
121  case Hexagon::Sched::tc_b08b653e:
122  case Hexagon::Sched::tc_b324366f:
123  case Hexagon::Sched::tc_b5bfaa60:
124  case Hexagon::Sched::tc_b86c7e8b:
125  case Hexagon::Sched::tc_c58f771a:
126  case Hexagon::Sched::tc_d108a090:
127  case Hexagon::Sched::tc_d1b5a4b6:
128  case Hexagon::Sched::tc_d2609065:
129  case Hexagon::Sched::tc_d63b71d1:
130  case Hexagon::Sched::tc_e2c31426:
131  case Hexagon::Sched::tc_e8c7a357:
132  case Hexagon::Sched::tc_eb07ef6f:
133  case Hexagon::Sched::tc_f16d5b17:
134  return true;
135  default:
136  return false;
137  }
138 }
139 } // namespace llvm
140 
141 #endif
bool is_TC2early(unsigned SchedClass)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool is_TC1(unsigned SchedClass)
bool is_TC2(unsigned SchedClass)
bool is_TC3x(unsigned SchedClass)
bool is_TC4x(unsigned SchedClass)