LLVM  7.0.0svn
HexagonDepTimingClasses.h
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1 //===- HexagonDepTimingClasses.h ------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // Automatically generated file, please consult code owner before editing.
10 //===----------------------------------------------------------------------===//
11 
12 
13 
14 #ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
15 #define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H
16 
17 #include "HexagonInstrInfo.h"
18 
19 namespace llvm {
20 
21 inline bool is_TC3x(unsigned SchedClass) {
22  switch (SchedClass) {
23  case Hexagon::Sched::tc_16d0d8d5:
24  case Hexagon::Sched::tc_1853ea6d:
25  case Hexagon::Sched::tc_60571023:
26  case Hexagon::Sched::tc_7934b9df:
27  case Hexagon::Sched::tc_8fd5f294:
28  case Hexagon::Sched::tc_b9c0b731:
29  case Hexagon::Sched::tc_bcc96cee:
30  case Hexagon::Sched::tc_c6ce9b3f:
31  case Hexagon::Sched::tc_c6ebf8dd:
32  case Hexagon::Sched::tc_c82dc1ff:
33  case Hexagon::Sched::tc_caaebcba:
34  case Hexagon::Sched::tc_cf59f215:
35  case Hexagon::Sched::tc_e913dc32:
36  return true;
37  default:
38  return false;
39  }
40 }
41 
42 inline bool is_TC2early(unsigned SchedClass) {
43  switch (SchedClass) {
44  case Hexagon::Sched::tc_14cd4cfa:
45  case Hexagon::Sched::tc_2a160009:
46  return true;
47  default:
48  return false;
49  }
50 }
51 
52 inline bool is_TC4x(unsigned SchedClass) {
53  switch (SchedClass) {
54  case Hexagon::Sched::tc_038a1342:
55  case Hexagon::Sched::tc_4d99bca9:
56  case Hexagon::Sched::tc_6792d5ff:
57  case Hexagon::Sched::tc_9c00ce8d:
58  case Hexagon::Sched::tc_d580173f:
59  case Hexagon::Sched::tc_f3eaa14b:
60  return true;
61  default:
62  return false;
63  }
64 }
65 
66 inline bool is_TC2(unsigned SchedClass) {
67  switch (SchedClass) {
68  case Hexagon::Sched::tc_00afc57e:
69  case Hexagon::Sched::tc_1b9c9ee5:
70  case Hexagon::Sched::tc_234a11a5:
71  case Hexagon::Sched::tc_2b6f77c6:
72  case Hexagon::Sched::tc_41d5298e:
73  case Hexagon::Sched::tc_5ba5997d:
74  case Hexagon::Sched::tc_84df2cd3:
75  case Hexagon::Sched::tc_87735c3b:
76  case Hexagon::Sched::tc_897d1a9d:
77  case Hexagon::Sched::tc_976ddc4f:
78  case Hexagon::Sched::tc_b44c6e2a:
79  case Hexagon::Sched::tc_b9c4623f:
80  case Hexagon::Sched::tc_c2f7d806:
81  case Hexagon::Sched::tc_c74f796f:
82  case Hexagon::Sched::tc_d088982c:
83  case Hexagon::Sched::tc_ef84f62f:
84  case Hexagon::Sched::tc_f49e76f4:
85  return true;
86  default:
87  return false;
88  }
89 }
90 
91 inline bool is_TC1(unsigned SchedClass) {
92  switch (SchedClass) {
93  case Hexagon::Sched::tc_181af5d0:
94  case Hexagon::Sched::tc_1b82a277:
95  case Hexagon::Sched::tc_1e856f58:
96  case Hexagon::Sched::tc_351fed2d:
97  case Hexagon::Sched::tc_3669266a:
98  case Hexagon::Sched::tc_3cb8ea06:
99  case Hexagon::Sched::tc_452f85af:
100  case Hexagon::Sched::tc_481e5e5c:
101  case Hexagon::Sched::tc_49eb22c8:
102  case Hexagon::Sched::tc_523fcf30:
103  case Hexagon::Sched::tc_52d7bbea:
104  case Hexagon::Sched::tc_53bc8a6a:
105  case Hexagon::Sched::tc_540fdfbc:
106  case Hexagon::Sched::tc_55050d58:
107  case Hexagon::Sched::tc_609d2efe:
108  case Hexagon::Sched::tc_68cb12ce:
109  case Hexagon::Sched::tc_6ebb4a12:
110  case Hexagon::Sched::tc_6efc556e:
111  case Hexagon::Sched::tc_73043bf4:
112  case Hexagon::Sched::tc_7a830544:
113  case Hexagon::Sched::tc_855b0b61:
114  case Hexagon::Sched::tc_8fe6b782:
115  case Hexagon::Sched::tc_90f3e30c:
116  case Hexagon::Sched::tc_97743097:
117  case Hexagon::Sched::tc_99be14ca:
118  case Hexagon::Sched::tc_9faf76ae:
119  case Hexagon::Sched::tc_a46f0df5:
120  case Hexagon::Sched::tc_a904d137:
121  case Hexagon::Sched::tc_b9488031:
122  case Hexagon::Sched::tc_be706f30:
123  case Hexagon::Sched::tc_c6aa82f7:
124  case Hexagon::Sched::tc_cde8b071:
125  case Hexagon::Sched::tc_d6bf0472:
126  case Hexagon::Sched::tc_dbdffe3d:
127  case Hexagon::Sched::tc_e0739b8c:
128  case Hexagon::Sched::tc_e1e99bfa:
129  case Hexagon::Sched::tc_e9fae2d6:
130  case Hexagon::Sched::tc_f2704b9a:
131  case Hexagon::Sched::tc_f8eeed7a:
132  return true;
133  default:
134  return false;
135  }
136 }
137 } // namespace llvm
138 
139 #endif
bool is_TC2early(unsigned SchedClass)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool is_TC1(unsigned SchedClass)
bool is_TC2(unsigned SchedClass)
bool is_TC3x(unsigned SchedClass)
bool is_TC4x(unsigned SchedClass)