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HexagonDisassembler.cpp
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1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "hexagon-disassembler"
11 
12 #include "Hexagon.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Endian.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <memory>
35 
36 using namespace llvm;
37 using namespace Hexagon;
38 
40 
41 namespace {
42 
43 /// \brief Hexagon disassembler for all Hexagon platforms.
44 class HexagonDisassembler : public MCDisassembler {
45 public:
46  std::unique_ptr<MCInstrInfo const> const MCII;
47  std::unique_ptr<MCInst *> CurrentBundle;
48  mutable MCInst const *CurrentExtender;
49 
50  HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
51  MCInstrInfo const *MCII)
52  : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
53  CurrentExtender(nullptr) {}
54 
55  DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
56  ArrayRef<uint8_t> Bytes, uint64_t Address,
57  raw_ostream &VStream, raw_ostream &CStream,
58  bool &Complete) const;
59  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
60  ArrayRef<uint8_t> Bytes, uint64_t Address,
61  raw_ostream &VStream,
62  raw_ostream &CStream) const override;
63  void remapInstruction(MCInst &Instr) const;
64 };
65 
66 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
67  int64_t Value) {
68  MCInstrInfo MCII = *Disassembler.MCII;
69  if (!Disassembler.CurrentExtender ||
70  MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
71  return Value;
72  unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
73  uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
74  int64_t Bits;
75  bool Success =
76  Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
77  Bits);
78  assert(Success);
79  (void)Success;
80  uint64_t Upper26 = static_cast<uint64_t>(Bits);
81  uint64_t Operand = Upper26 | Lower6;
82  return Operand;
83 }
84 static HexagonDisassembler const &disassembler(void const *Decoder) {
85  return *static_cast<HexagonDisassembler const *>(Decoder);
86 }
87 template <size_t T>
88 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
89  HexagonDisassembler const &Disassembler = disassembler(Decoder);
90  int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
91  int64_t Extended = SignExtend64<32>(FullValue);
92  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
93 }
94 }
95 
96 // Forward declare these because the auto-generated code will reference them.
97 // Definitions are further down.
98 
99 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
100  uint64_t Address,
101  const void *Decoder);
103  unsigned RegNo,
104  uint64_t Address,
105  const void *Decoder);
106 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
107  uint64_t Address,
108  const void *Decoder);
109 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
110  uint64_t Address,
111  const void *Decoder);
112 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
113  uint64_t Address,
114  const void *Decoder);
115 static DecodeStatus
117  uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
119  uint64_t Address,
120  const void *Decoder);
121 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
122  uint64_t Address,
123  const void *Decoder);
124 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
125  uint64_t Address,
126  const void *Decoder);
127 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
128  uint64_t Address,
129  const void *Decoder);
130 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
131  uint64_t Address,
132  const void *Decoder);
133 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
134  uint64_t Address,
135  const void *Decoder);
136 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
137  uint64_t Address,
138  const void *Decoder);
139 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
140  uint64_t Address,
141  const void *Decoder);
142 
143 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
144  uint64_t Address, const void *Decoder);
145 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
146  uint64_t /*Address*/, const void *Decoder);
147 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
148  const void *Decoder);
149 
150 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
151  const void *Decoder) {
152  signedDecoder<4>(MI, tmp, Decoder);
154 }
155 static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
156  const void *Decoder) {
157  signedDecoder<14>(MI, tmp, Decoder);
159 }
160 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
161  const void *Decoder) {
162  signedDecoder<8>(MI, tmp, Decoder);
164 }
165 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
166  const void *Decoder) {
167  signedDecoder<7>(MI, tmp, Decoder);
169 }
170 static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
171  const void *Decoder) {
172  signedDecoder<12>(MI, tmp, Decoder);
174 }
175 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
176  const void *Decoder) {
177  signedDecoder<3>(MI, tmp, Decoder);
179 }
180 static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
181  const void *Decoder) {
182  signedDecoder<13>(MI, tmp, Decoder);
184 }
185 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
186  const void *Decoder) {
187  signedDecoder<6>(MI, tmp, Decoder);
189 }
190 static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
191  const void *Decoder) {
192  signedDecoder<9>(MI, tmp, Decoder);
194 }
195 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
196  const void *Decoder) {
197  signedDecoder<5>(MI, tmp, Decoder);
199 }
200 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
201  const void *Decoder) {
202  signedDecoder<6>(MI, tmp, Decoder);
204 }
205 #include "HexagonGenDisassemblerTables.inc"
206 
208  const MCSubtargetInfo &STI,
209  MCContext &Ctx) {
210  return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
211 }
212 
216 }
217 
218 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
219  ArrayRef<uint8_t> Bytes,
220  uint64_t Address,
221  raw_ostream &os,
222  raw_ostream &cs) const {
224  bool Complete = false;
225  Size = 0;
226 
227  *CurrentBundle = &MI;
228  MI.setOpcode(Hexagon::BUNDLE);
230  while (Result == Success && !Complete) {
231  if (Bytes.size() < HEXAGON_INSTR_SIZE)
232  return MCDisassembler::Fail;
233  MCInst *Inst = new (getContext()) MCInst;
234  Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
237  Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
238  }
239  if (Result == MCDisassembler::Fail)
240  return Result;
242  return MCDisassembler::Fail;
243  HexagonMCChecker Checker(getContext(), *MCII, STI, MI,
244  *getContext().getRegisterInfo(), false);
245  if (!Checker.check())
246  return MCDisassembler::Fail;
247  remapInstruction(MI);
249 }
250 
252  for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
253  auto &MI = const_cast<MCInst &>(*I.getInst());
254  switch (MI.getOpcode()) {
255  case Hexagon::S2_allocframe:
256  if (MI.getOperand(0).getReg() == Hexagon::R29) {
257  MI.setOpcode(Hexagon::S6_allocframe_to_raw);
258  MI.erase(MI.begin () + 1);
259  MI.erase(MI.begin ());
260  }
261  break;
262  case Hexagon::L2_deallocframe:
263  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
264  MI.getOperand(1).getReg() == Hexagon::R30) {
265  MI.setOpcode(L6_deallocframe_map_to_raw);
266  MI.erase(MI.begin () + 1);
267  MI.erase(MI.begin ());
268  }
269  break;
270  case Hexagon::L4_return:
271  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
272  MI.getOperand(1).getReg() == Hexagon::R30) {
273  MI.setOpcode(L6_return_map_to_raw);
274  MI.erase(MI.begin () + 1);
275  MI.erase(MI.begin ());
276  }
277  break;
278  case Hexagon::L4_return_t:
279  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
280  MI.getOperand(2).getReg() == Hexagon::R30) {
281  MI.setOpcode(L4_return_map_to_raw_t);
282  MI.erase(MI.begin () + 2);
283  MI.erase(MI.begin ());
284  }
285  break;
286  case Hexagon::L4_return_f:
287  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
288  MI.getOperand(2).getReg() == Hexagon::R30) {
289  MI.setOpcode(L4_return_map_to_raw_f);
290  MI.erase(MI.begin () + 2);
291  MI.erase(MI.begin ());
292  }
293  break;
294  case Hexagon::L4_return_tnew_pt:
295  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
296  MI.getOperand(2).getReg() == Hexagon::R30) {
297  MI.setOpcode(L4_return_map_to_raw_tnew_pt);
298  MI.erase(MI.begin () + 2);
299  MI.erase(MI.begin ());
300  }
301  break;
302  case Hexagon::L4_return_fnew_pt:
303  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
304  MI.getOperand(2).getReg() == Hexagon::R30) {
305  MI.setOpcode(L4_return_map_to_raw_fnew_pt);
306  MI.erase(MI.begin () + 2);
307  MI.erase(MI.begin ());
308  }
309  break;
310  case Hexagon::L4_return_tnew_pnt:
311  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
312  MI.getOperand(2).getReg() == Hexagon::R30) {
313  MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
314  MI.erase(MI.begin () + 2);
315  MI.erase(MI.begin ());
316  }
317  break;
318  case Hexagon::L4_return_fnew_pnt:
319  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
320  MI.getOperand(2).getReg() == Hexagon::R30) {
321  MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
322  MI.erase(MI.begin () + 2);
323  MI.erase(MI.begin ());
324  }
325  break;
326  }
327  }
328 }
329 
330 static void adjustDuplex(MCInst &MI, MCContext &Context) {
331  switch (MI.getOpcode()) {
332  case Hexagon::SA1_setin1:
333  MI.insert(MI.begin() + 1,
335  break;
336  case Hexagon::SA1_dec:
337  MI.insert(MI.begin() + 2,
339  break;
340  default:
341  break;
342  }
343 }
344 
345 DecodeStatus HexagonDisassembler::getSingleInstruction(
346  MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
347  raw_ostream &os, raw_ostream &cs, bool &Complete) const {
348  assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
349 
351 
352  auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
353  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
355  if (BundleSize == 0)
357  else if (BundleSize == 1)
359  else
360  return DecodeStatus::Fail;
361  }
362 
363  CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
365 
367  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
369  unsigned duplexIClass;
370  uint8_t const *DecodeLow, *DecodeHigh;
371  duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
372  switch (duplexIClass) {
373  default:
374  return MCDisassembler::Fail;
375  case 0:
376  DecodeLow = DecoderTableSUBINSN_L132;
377  DecodeHigh = DecoderTableSUBINSN_L132;
378  break;
379  case 1:
380  DecodeLow = DecoderTableSUBINSN_L232;
381  DecodeHigh = DecoderTableSUBINSN_L132;
382  break;
383  case 2:
384  DecodeLow = DecoderTableSUBINSN_L232;
385  DecodeHigh = DecoderTableSUBINSN_L232;
386  break;
387  case 3:
388  DecodeLow = DecoderTableSUBINSN_A32;
389  DecodeHigh = DecoderTableSUBINSN_A32;
390  break;
391  case 4:
392  DecodeLow = DecoderTableSUBINSN_L132;
393  DecodeHigh = DecoderTableSUBINSN_A32;
394  break;
395  case 5:
396  DecodeLow = DecoderTableSUBINSN_L232;
397  DecodeHigh = DecoderTableSUBINSN_A32;
398  break;
399  case 6:
400  DecodeLow = DecoderTableSUBINSN_S132;
401  DecodeHigh = DecoderTableSUBINSN_A32;
402  break;
403  case 7:
404  DecodeLow = DecoderTableSUBINSN_S232;
405  DecodeHigh = DecoderTableSUBINSN_A32;
406  break;
407  case 8:
408  DecodeLow = DecoderTableSUBINSN_S132;
409  DecodeHigh = DecoderTableSUBINSN_L132;
410  break;
411  case 9:
412  DecodeLow = DecoderTableSUBINSN_S132;
413  DecodeHigh = DecoderTableSUBINSN_L232;
414  break;
415  case 10:
416  DecodeLow = DecoderTableSUBINSN_S132;
417  DecodeHigh = DecoderTableSUBINSN_S132;
418  break;
419  case 11:
420  DecodeLow = DecoderTableSUBINSN_S232;
421  DecodeHigh = DecoderTableSUBINSN_S132;
422  break;
423  case 12:
424  DecodeLow = DecoderTableSUBINSN_S232;
425  DecodeHigh = DecoderTableSUBINSN_L132;
426  break;
427  case 13:
428  DecodeLow = DecoderTableSUBINSN_S232;
429  DecodeHigh = DecoderTableSUBINSN_L232;
430  break;
431  case 14:
432  DecodeLow = DecoderTableSUBINSN_S232;
433  DecodeHigh = DecoderTableSUBINSN_S232;
434  break;
435  }
436  MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
437  MCInst *MILow = new (getContext()) MCInst;
438  MCInst *MIHigh = new (getContext()) MCInst;
439  auto TmpExtender = CurrentExtender;
440  CurrentExtender =
441  nullptr; // constant extenders in duplex must always be in slot 1
442  Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
443  this, STI);
444  CurrentExtender = TmpExtender;
445  if (Result != DecodeStatus::Success)
446  return DecodeStatus::Fail;
447  adjustDuplex(*MILow, getContext());
448  Result = decodeInstruction(
449  DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
450  if (Result != DecodeStatus::Success)
451  return DecodeStatus::Fail;
452  adjustDuplex(*MIHigh, getContext());
453  MCOperand OPLow = MCOperand::createInst(MILow);
454  MCOperand OPHigh = MCOperand::createInst(MIHigh);
455  MI.addOperand(OPLow);
456  MI.addOperand(OPHigh);
457  Complete = true;
458  } else {
459  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
461  Complete = true;
462 
463  if (CurrentExtender != nullptr)
464  Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
465  Address, this, STI);
466 
467  if (Result != MCDisassembler::Success)
468  Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
469  STI);
470 
471  if (Result != MCDisassembler::Success &&
472  STI.getFeatureBits()[Hexagon::ExtensionHVX])
473  Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
474  Address, this, STI);
475 
476  }
477 
478  switch (MI.getOpcode()) {
479  case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
480  case Hexagon::J4_cmpeqn1_f_jumpnv_t:
481  case Hexagon::J4_cmpeqn1_fp0_jump_nt:
482  case Hexagon::J4_cmpeqn1_fp0_jump_t:
483  case Hexagon::J4_cmpeqn1_fp1_jump_nt:
484  case Hexagon::J4_cmpeqn1_fp1_jump_t:
485  case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
486  case Hexagon::J4_cmpeqn1_t_jumpnv_t:
487  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
488  case Hexagon::J4_cmpeqn1_tp0_jump_t:
489  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
490  case Hexagon::J4_cmpeqn1_tp1_jump_t:
491  case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
492  case Hexagon::J4_cmpgtn1_f_jumpnv_t:
493  case Hexagon::J4_cmpgtn1_fp0_jump_nt:
494  case Hexagon::J4_cmpgtn1_fp0_jump_t:
495  case Hexagon::J4_cmpgtn1_fp1_jump_nt:
496  case Hexagon::J4_cmpgtn1_fp1_jump_t:
497  case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
498  case Hexagon::J4_cmpgtn1_t_jumpnv_t:
499  case Hexagon::J4_cmpgtn1_tp0_jump_nt:
500  case Hexagon::J4_cmpgtn1_tp0_jump_t:
501  case Hexagon::J4_cmpgtn1_tp1_jump_nt:
502  case Hexagon::J4_cmpgtn1_tp1_jump_t:
503  MI.insert(MI.begin() + 1,
504  MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
505  break;
506  default:
507  break;
508  }
509 
510  if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
511  unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
512  MCOperand &MCO = MI.getOperand(OpIndex);
513  assert(MCO.isReg() && "New value consumers must be registers");
514  unsigned Register =
515  getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
516  if ((Register & 0x6) == 0)
517  // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
518  return MCDisassembler::Fail;
519  unsigned Lookback = (Register & 0x6) >> 1;
520  unsigned Offset = 1;
521  bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
522  bool PrevVector = false;
523  auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
524  auto i = Instructions.end() - 1;
525  for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
526  if (i == n)
527  // Couldn't find producer
528  return MCDisassembler::Fail;
529  bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
530  if (Vector && !CurrentVector)
531  // Skip scalars when calculating distances for vectors
532  ++Lookback;
533  if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
534  ++Lookback;
535  PrevVector = CurrentVector;
536  if (Offset == Lookback)
537  break;
538  }
539  auto const &Inst = *i->getInst();
540  bool SubregBit = (Register & 0x1) != 0;
541  if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
542  // If subreg bit is set we're selecting the second produced newvalue
543  unsigned Producer = SubregBit ?
546  assert(Producer != Hexagon::NoRegister);
547  MCO.setReg(Producer);
548  } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
549  unsigned Producer =
551  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
552  Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
553  else if (SubregBit)
554  // Hexagon PRM 10.11 New-value operands
555  // Nt[0] is reserved and should always be encoded as zero.
556  return MCDisassembler::Fail;
557  assert(Producer != Hexagon::NoRegister);
558  MCO.setReg(Producer);
559  } else
560  return MCDisassembler::Fail;
561  }
562 
563  if (CurrentExtender != nullptr) {
564  MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
565  ? *MI.getOperand(1).getInst()
566  : MI;
567  if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
568  !HexagonMCInstrInfo::isExtended(*MCII, Inst))
569  return MCDisassembler::Fail;
570  }
571  return Result;
572 }
573 
574 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
575  ArrayRef<MCPhysReg> Table) {
576  if (RegNo < Table.size()) {
577  Inst.addOperand(MCOperand::createReg(Table[RegNo]));
579  }
580 
581  return MCDisassembler::Fail;
582 }
583 
585  uint64_t Address,
586  const void *Decoder) {
587  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
588 }
589 
590 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
591  uint64_t Address,
592  const void *Decoder) {
593  static const MCPhysReg IntRegDecoderTable[] = {
594  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
595  Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
596  Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
597  Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
598  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
599  Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
600  Hexagon::R30, Hexagon::R31};
601 
602  return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
603 }
604 
606  unsigned RegNo,
607  uint64_t Address,
608  const void *Decoder) {
609  static const MCPhysReg GeneralSubRegDecoderTable[] = {
610  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
611  Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
612  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
613  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
614  };
615 
616  return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
617 }
618 
619 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
620  uint64_t /*Address*/,
621  const void *Decoder) {
622  static const MCPhysReg HvxVRDecoderTable[] = {
623  Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
624  Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
625  Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
626  Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
627  Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
628  Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
629  Hexagon::V30, Hexagon::V31};
630 
631  return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
632 }
633 
634 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
635  uint64_t /*Address*/,
636  const void *Decoder) {
637  static const MCPhysReg DoubleRegDecoderTable[] = {
638  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
639  Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
640  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
641  Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
642 
643  return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
644 }
645 
647  MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
648  static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
649  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
650  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
651 
652  return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
653 }
654 
655 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
656  uint64_t /*Address*/,
657  const void *Decoder) {
658  static const MCPhysReg HvxWRDecoderTable[] = {
659  Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
660  Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
661  Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
662  Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
663 
664  return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable));
665 }
666 
667 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
668  uint64_t /*Address*/,
669  const void *Decoder) {
670  static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
671  Hexagon::P2, Hexagon::P3};
672 
673  return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
674 }
675 
676 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
677  uint64_t /*Address*/,
678  const void *Decoder) {
679  static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
680  Hexagon::Q2, Hexagon::Q3};
681 
682  return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
683 }
684 
685 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
686  uint64_t /*Address*/,
687  const void *Decoder) {
688  using namespace Hexagon;
689 
690  static const MCPhysReg CtrlRegDecoderTable[] = {
691  /* 0 */ SA0, LC0, SA1, LC1,
692  /* 4 */ P3_0, C5, M0, M1,
693  /* 8 */ USR, PC, UGP, GP,
694  /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
695  /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
696  /* 20 */ 0, 0, 0, 0,
697  /* 24 */ 0, 0, 0, 0,
698  /* 28 */ 0, 0, UTIMERLO, UTIMERHI
699  };
700 
701  if (RegNo >= array_lengthof(CtrlRegDecoderTable))
702  return MCDisassembler::Fail;
703 
704  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
705  if (CtrlRegDecoderTable[RegNo] == NoRegister)
706  return MCDisassembler::Fail;
707 
708  unsigned Register = CtrlRegDecoderTable[RegNo];
709  Inst.addOperand(MCOperand::createReg(Register));
711 }
712 
713 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
714  uint64_t /*Address*/,
715  const void *Decoder) {
716  using namespace Hexagon;
717 
718  static const MCPhysReg CtrlReg64DecoderTable[] = {
719  /* 0 */ C1_0, 0, C3_2, 0,
720  /* 4 */ C5_4, 0, C7_6, 0,
721  /* 8 */ C9_8, 0, C11_10, 0,
722  /* 12 */ CS, 0, UPCYCLE, 0,
723  /* 16 */ C17_16, 0, PKTCOUNT, 0,
724  /* 20 */ 0, 0, 0, 0,
725  /* 24 */ 0, 0, 0, 0,
726  /* 28 */ 0, 0, UTIMER, 0
727  };
728 
729  if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
730  return MCDisassembler::Fail;
731 
732  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
733  if (CtrlReg64DecoderTable[RegNo] == NoRegister)
734  return MCDisassembler::Fail;
735 
736  unsigned Register = CtrlReg64DecoderTable[RegNo];
737  Inst.addOperand(MCOperand::createReg(Register));
739 }
740 
741 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
742  uint64_t /*Address*/,
743  const void *Decoder) {
744  unsigned Register = 0;
745  switch (RegNo) {
746  case 0:
747  Register = Hexagon::M0;
748  break;
749  case 1:
750  Register = Hexagon::M1;
751  break;
752  default:
753  return MCDisassembler::Fail;
754  }
755  Inst.addOperand(MCOperand::createReg(Register));
757 }
758 
759 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
760  uint64_t /*Address*/,
761  const void *Decoder) {
762  HexagonDisassembler const &Disassembler = disassembler(Decoder);
763  int64_t FullValue = fullValue(Disassembler, MI, tmp);
764  assert(FullValue >= 0 && "Negative in unsigned decoder");
765  HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
767 }
768 
769 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
770  uint64_t /*Address*/, const void *Decoder) {
771  HexagonDisassembler const &Disassembler = disassembler(Decoder);
772  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
773  tmp = SignExtend64(tmp, Bits);
774  signedDecoder<32>(MI, tmp, Decoder);
776 }
777 
778 // custom decoder for various jump/call immediates
779 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
780  const void *Decoder) {
781  HexagonDisassembler const &Disassembler = disassembler(Decoder);
782  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
783  // r13_2 is not extendable, so if there are no extent bits, it's r13_2
784  if (Bits == 0)
785  Bits = 15;
786  uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
787  uint32_t Extended = FullValue + Address;
788  if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
789  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
791 }
792 
793 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
794  uint64_t /*Address*/,
795  const void *Decoder) {
796  using namespace Hexagon;
797 
798  static const MCPhysReg GuestRegDecoderTable[] = {
799  /* 0 */ GELR, GSR, GOSP, G3,
800  /* 4 */ G4, G5, G6, G7,
801  /* 8 */ G8, G9, G10, G11,
802  /* 12 */ G12, G13, G14, G15,
803  /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
804  /* 20 */ G20, G21, G22, G23,
805  /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
806  /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
807  };
808 
809  if (RegNo >= array_lengthof(GuestRegDecoderTable))
810  return MCDisassembler::Fail;
811  if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
812  return MCDisassembler::Fail;
813 
814  unsigned Register = GuestRegDecoderTable[RegNo];
815  Inst.addOperand(MCOperand::createReg(Register));
817 }
818 
820  uint64_t /*Address*/,
821  const void *Decoder) {
822  using namespace Hexagon;
823 
824  static const MCPhysReg GuestReg64DecoderTable[] = {
825  /* 0 */ G1_0, 0, G3_2, 0,
826  /* 4 */ G5_4, 0, G7_6, 0,
827  /* 8 */ G9_8, 0, G11_10, 0,
828  /* 12 */ G13_12, 0, G15_14, 0,
829  /* 16 */ G17_16, 0, G19_18, 0,
830  /* 20 */ G21_20, 0, G23_22, 0,
831  /* 24 */ G25_24, 0, G27_26, 0,
832  /* 28 */ G29_28, 0, G31_30, 0
833  };
834 
835  if (RegNo >= array_lengthof(GuestReg64DecoderTable))
836  return MCDisassembler::Fail;
837  if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
838  return MCDisassembler::Fail;
839 
840  unsigned Register = GuestReg64DecoderTable[RegNo];
841  Inst.addOperand(MCOperand::createReg(Register));
843 }
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
iterator begin()
Definition: MCInst.h:194
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
LLVMContext & Context
static void remapInstruction(Instruction *I, ValueToValueMapTy &VMap)
Convert the instruction operands from referencing the current values into those specified by VMap...
Definition: LoopUnroll.cpp:66
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
DecodeStatus
Ternary decode status.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
Superclass for all disassemblers.
static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:58
static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
#define R2(n)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isImmext(MCInst const &MCI)
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
#define Fail
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void erase(iterator I)
Definition: MCInst.h:192
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
const MCInst * getInst() const
Definition: MCInst.h:106
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:199
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeHexagonDisassembler()
static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
const T * data() const
Definition: ArrayRef.h:146
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned IntRegDecoderTable[]
void setOpcode(unsigned Op)
Definition: MCInst.h:173
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:725
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Promote Memory to Register
Definition: Mem2Reg.cpp:110
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static void adjustDuplex(MCInst &MI, MCContext &Context)
Target - Wrapper for Target specific information.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:179
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:144
#define Success
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
size_t size() const
Definition: MCInst.h:193
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
#define I(x, y, z)
Definition: MD5.cpp:58
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
uint32_t read32le(const void *P)
Definition: Endian.h:369
Generic base class for all target subtargets.
size_t bundleSize(MCInst const &MCI)
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:741
bool check(bool FullCheck=true)
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:71
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define HEXAGON_INSTR_SIZE
Definition: Hexagon.h:30
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
Check for a valid bundle.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
unsigned getOpcode() const
Definition: MCInst.h:174
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
#define HEXAGON_MAX_PACKET_SIZE
Definition: Hexagon.h:34
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
Target & getTheHexagonTarget()
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)