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HexagonDisassembler.cpp
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1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #define DEBUG_TYPE "hexagon-disassembler"
10 
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/Endian.h"
29 #include <cassert>
30 #include <cstddef>
31 #include <cstdint>
32 #include <memory>
33 
34 using namespace llvm;
35 using namespace Hexagon;
36 
38 
39 namespace {
40 
41 /// Hexagon disassembler for all Hexagon platforms.
42 class HexagonDisassembler : public MCDisassembler {
43 public:
44  std::unique_ptr<MCInstrInfo const> const MCII;
45  std::unique_ptr<MCInst *> CurrentBundle;
46  mutable MCInst const *CurrentExtender;
47 
48  HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
49  MCInstrInfo const *MCII)
50  : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
51  CurrentExtender(nullptr) {}
52 
53  DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
54  ArrayRef<uint8_t> Bytes, uint64_t Address,
55  raw_ostream &VStream, raw_ostream &CStream,
56  bool &Complete) const;
57  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
58  ArrayRef<uint8_t> Bytes, uint64_t Address,
59  raw_ostream &VStream,
60  raw_ostream &CStream) const override;
61  void remapInstruction(MCInst &Instr) const;
62 };
63 
64 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
65  int64_t Value) {
66  MCInstrInfo MCII = *Disassembler.MCII;
67  if (!Disassembler.CurrentExtender ||
68  MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
69  return Value;
70  unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
71  uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
72  int64_t Bits;
73  bool Success =
74  Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
75  Bits);
76  assert(Success);
77  (void)Success;
78  uint64_t Upper26 = static_cast<uint64_t>(Bits);
79  uint64_t Operand = Upper26 | Lower6;
80  return Operand;
81 }
82 static HexagonDisassembler const &disassembler(void const *Decoder) {
83  return *static_cast<HexagonDisassembler const *>(Decoder);
84 }
85 template <size_t T>
86 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
87  HexagonDisassembler const &Disassembler = disassembler(Decoder);
88  int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
89  int64_t Extended = SignExtend64<32>(FullValue);
90  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
91 }
92 }
93 
94 // Forward declare these because the auto-generated code will reference them.
95 // Definitions are further down.
96 
97 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
98  uint64_t Address,
99  const void *Decoder);
101  unsigned RegNo,
102  uint64_t Address,
103  const void *Decoder);
104 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
105  uint64_t Address,
106  const void *Decoder);
107 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
108  uint64_t Address,
109  const void *Decoder);
110 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111  uint64_t Address,
112  const void *Decoder);
113 static DecodeStatus
115  uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
117  uint64_t Address,
118  const void *Decoder);
120  unsigned RegNo,
121  uint64_t Address,
122  const void *Decoder);
123 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
124  uint64_t Address,
125  const void *Decoder);
126 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
127  uint64_t Address,
128  const void *Decoder);
129 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
130  uint64_t Address,
131  const void *Decoder);
132 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
133  uint64_t Address,
134  const void *Decoder);
135 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
136  uint64_t Address,
137  const void *Decoder);
138 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
139  uint64_t Address,
140  const void *Decoder);
141 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
142  uint64_t Address,
143  const void *Decoder);
144 
145 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
146  uint64_t Address, const void *Decoder);
147 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
148  uint64_t /*Address*/, const void *Decoder);
149 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
150  const void *Decoder);
151 #include "HexagonDepDecoders.inc"
152 #include "HexagonGenDisassemblerTables.inc"
153 
155  const MCSubtargetInfo &STI,
156  MCContext &Ctx) {
157  return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
158 }
159 
163 }
164 
165 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
166  ArrayRef<uint8_t> Bytes,
167  uint64_t Address,
168  raw_ostream &os,
169  raw_ostream &cs) const {
171  bool Complete = false;
172  Size = 0;
173 
174  *CurrentBundle = &MI;
175  MI.setOpcode(Hexagon::BUNDLE);
177  while (Result == Success && !Complete) {
178  if (Bytes.size() < HEXAGON_INSTR_SIZE)
179  return MCDisassembler::Fail;
180  MCInst *Inst = new (getContext()) MCInst;
181  Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
184  Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
185  }
186  if (Result == MCDisassembler::Fail)
187  return Result;
189  return MCDisassembler::Fail;
190  HexagonMCChecker Checker(getContext(), *MCII, STI, MI,
191  *getContext().getRegisterInfo(), false);
192  if (!Checker.check())
193  return MCDisassembler::Fail;
194  remapInstruction(MI);
196 }
197 
199  for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
200  auto &MI = const_cast<MCInst &>(*I.getInst());
201  switch (MI.getOpcode()) {
202  case Hexagon::S2_allocframe:
203  if (MI.getOperand(0).getReg() == Hexagon::R29) {
204  MI.setOpcode(Hexagon::S6_allocframe_to_raw);
205  MI.erase(MI.begin () + 1);
206  MI.erase(MI.begin ());
207  }
208  break;
209  case Hexagon::L2_deallocframe:
210  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
211  MI.getOperand(1).getReg() == Hexagon::R30) {
212  MI.setOpcode(L6_deallocframe_map_to_raw);
213  MI.erase(MI.begin () + 1);
214  MI.erase(MI.begin ());
215  }
216  break;
217  case Hexagon::L4_return:
218  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
219  MI.getOperand(1).getReg() == Hexagon::R30) {
220  MI.setOpcode(L6_return_map_to_raw);
221  MI.erase(MI.begin () + 1);
222  MI.erase(MI.begin ());
223  }
224  break;
225  case Hexagon::L4_return_t:
226  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
227  MI.getOperand(2).getReg() == Hexagon::R30) {
228  MI.setOpcode(L4_return_map_to_raw_t);
229  MI.erase(MI.begin () + 2);
230  MI.erase(MI.begin ());
231  }
232  break;
233  case Hexagon::L4_return_f:
234  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
235  MI.getOperand(2).getReg() == Hexagon::R30) {
236  MI.setOpcode(L4_return_map_to_raw_f);
237  MI.erase(MI.begin () + 2);
238  MI.erase(MI.begin ());
239  }
240  break;
241  case Hexagon::L4_return_tnew_pt:
242  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
243  MI.getOperand(2).getReg() == Hexagon::R30) {
244  MI.setOpcode(L4_return_map_to_raw_tnew_pt);
245  MI.erase(MI.begin () + 2);
246  MI.erase(MI.begin ());
247  }
248  break;
249  case Hexagon::L4_return_fnew_pt:
250  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
251  MI.getOperand(2).getReg() == Hexagon::R30) {
252  MI.setOpcode(L4_return_map_to_raw_fnew_pt);
253  MI.erase(MI.begin () + 2);
254  MI.erase(MI.begin ());
255  }
256  break;
257  case Hexagon::L4_return_tnew_pnt:
258  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
259  MI.getOperand(2).getReg() == Hexagon::R30) {
260  MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
261  MI.erase(MI.begin () + 2);
262  MI.erase(MI.begin ());
263  }
264  break;
265  case Hexagon::L4_return_fnew_pnt:
266  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
267  MI.getOperand(2).getReg() == Hexagon::R30) {
268  MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
269  MI.erase(MI.begin () + 2);
270  MI.erase(MI.begin ());
271  }
272  break;
273  }
274  }
275 }
276 
277 static void adjustDuplex(MCInst &MI, MCContext &Context) {
278  switch (MI.getOpcode()) {
279  case Hexagon::SA1_setin1:
280  MI.insert(MI.begin() + 1,
282  break;
283  case Hexagon::SA1_dec:
284  MI.insert(MI.begin() + 2,
286  break;
287  default:
288  break;
289  }
290 }
291 
292 DecodeStatus HexagonDisassembler::getSingleInstruction(
293  MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
294  raw_ostream &os, raw_ostream &cs, bool &Complete) const {
295  assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
296 
298 
299  auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
300  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
302  if (BundleSize == 0)
304  else if (BundleSize == 1)
306  else
307  return DecodeStatus::Fail;
308  }
309 
310  CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
312 
314  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
316  unsigned duplexIClass;
317  uint8_t const *DecodeLow, *DecodeHigh;
318  duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
319  switch (duplexIClass) {
320  default:
321  return MCDisassembler::Fail;
322  case 0:
323  DecodeLow = DecoderTableSUBINSN_L132;
324  DecodeHigh = DecoderTableSUBINSN_L132;
325  break;
326  case 1:
327  DecodeLow = DecoderTableSUBINSN_L232;
328  DecodeHigh = DecoderTableSUBINSN_L132;
329  break;
330  case 2:
331  DecodeLow = DecoderTableSUBINSN_L232;
332  DecodeHigh = DecoderTableSUBINSN_L232;
333  break;
334  case 3:
335  DecodeLow = DecoderTableSUBINSN_A32;
336  DecodeHigh = DecoderTableSUBINSN_A32;
337  break;
338  case 4:
339  DecodeLow = DecoderTableSUBINSN_L132;
340  DecodeHigh = DecoderTableSUBINSN_A32;
341  break;
342  case 5:
343  DecodeLow = DecoderTableSUBINSN_L232;
344  DecodeHigh = DecoderTableSUBINSN_A32;
345  break;
346  case 6:
347  DecodeLow = DecoderTableSUBINSN_S132;
348  DecodeHigh = DecoderTableSUBINSN_A32;
349  break;
350  case 7:
351  DecodeLow = DecoderTableSUBINSN_S232;
352  DecodeHigh = DecoderTableSUBINSN_A32;
353  break;
354  case 8:
355  DecodeLow = DecoderTableSUBINSN_S132;
356  DecodeHigh = DecoderTableSUBINSN_L132;
357  break;
358  case 9:
359  DecodeLow = DecoderTableSUBINSN_S132;
360  DecodeHigh = DecoderTableSUBINSN_L232;
361  break;
362  case 10:
363  DecodeLow = DecoderTableSUBINSN_S132;
364  DecodeHigh = DecoderTableSUBINSN_S132;
365  break;
366  case 11:
367  DecodeLow = DecoderTableSUBINSN_S232;
368  DecodeHigh = DecoderTableSUBINSN_S132;
369  break;
370  case 12:
371  DecodeLow = DecoderTableSUBINSN_S232;
372  DecodeHigh = DecoderTableSUBINSN_L132;
373  break;
374  case 13:
375  DecodeLow = DecoderTableSUBINSN_S232;
376  DecodeHigh = DecoderTableSUBINSN_L232;
377  break;
378  case 14:
379  DecodeLow = DecoderTableSUBINSN_S232;
380  DecodeHigh = DecoderTableSUBINSN_S232;
381  break;
382  }
383  MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
384  MCInst *MILow = new (getContext()) MCInst;
385  MCInst *MIHigh = new (getContext()) MCInst;
386  auto TmpExtender = CurrentExtender;
387  CurrentExtender =
388  nullptr; // constant extenders in duplex must always be in slot 1
389  Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
390  this, STI);
391  CurrentExtender = TmpExtender;
392  if (Result != DecodeStatus::Success)
393  return DecodeStatus::Fail;
394  adjustDuplex(*MILow, getContext());
395  Result = decodeInstruction(
396  DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
397  if (Result != DecodeStatus::Success)
398  return DecodeStatus::Fail;
399  adjustDuplex(*MIHigh, getContext());
400  MCOperand OPLow = MCOperand::createInst(MILow);
401  MCOperand OPHigh = MCOperand::createInst(MIHigh);
402  MI.addOperand(OPLow);
403  MI.addOperand(OPHigh);
404  Complete = true;
405  } else {
406  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
408  Complete = true;
409 
410  if (CurrentExtender != nullptr)
411  Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
412  Address, this, STI);
413 
414  if (Result != MCDisassembler::Success)
415  Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
416  STI);
417 
418  if (Result != MCDisassembler::Success &&
419  STI.getFeatureBits()[Hexagon::ExtensionHVX])
420  Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
421  Address, this, STI);
422 
423  }
424 
425  switch (MI.getOpcode()) {
426  case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
427  case Hexagon::J4_cmpeqn1_f_jumpnv_t:
428  case Hexagon::J4_cmpeqn1_fp0_jump_nt:
429  case Hexagon::J4_cmpeqn1_fp0_jump_t:
430  case Hexagon::J4_cmpeqn1_fp1_jump_nt:
431  case Hexagon::J4_cmpeqn1_fp1_jump_t:
432  case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
433  case Hexagon::J4_cmpeqn1_t_jumpnv_t:
434  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
435  case Hexagon::J4_cmpeqn1_tp0_jump_t:
436  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
437  case Hexagon::J4_cmpeqn1_tp1_jump_t:
438  case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
439  case Hexagon::J4_cmpgtn1_f_jumpnv_t:
440  case Hexagon::J4_cmpgtn1_fp0_jump_nt:
441  case Hexagon::J4_cmpgtn1_fp0_jump_t:
442  case Hexagon::J4_cmpgtn1_fp1_jump_nt:
443  case Hexagon::J4_cmpgtn1_fp1_jump_t:
444  case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
445  case Hexagon::J4_cmpgtn1_t_jumpnv_t:
446  case Hexagon::J4_cmpgtn1_tp0_jump_nt:
447  case Hexagon::J4_cmpgtn1_tp0_jump_t:
448  case Hexagon::J4_cmpgtn1_tp1_jump_nt:
449  case Hexagon::J4_cmpgtn1_tp1_jump_t:
450  MI.insert(MI.begin() + 1,
451  MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
452  break;
453  default:
454  break;
455  }
456 
457  if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
458  unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
459  MCOperand &MCO = MI.getOperand(OpIndex);
460  assert(MCO.isReg() && "New value consumers must be registers");
461  unsigned Register =
462  getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
463  if ((Register & 0x6) == 0)
464  // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
465  return MCDisassembler::Fail;
466  unsigned Lookback = (Register & 0x6) >> 1;
467  unsigned Offset = 1;
468  bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
469  bool PrevVector = false;
470  auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
471  auto i = Instructions.end() - 1;
472  for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
473  if (i == n)
474  // Couldn't find producer
475  return MCDisassembler::Fail;
476  bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
477  if (Vector && !CurrentVector)
478  // Skip scalars when calculating distances for vectors
479  ++Lookback;
480  if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
481  ++Lookback;
482  PrevVector = CurrentVector;
483  if (Offset == Lookback)
484  break;
485  }
486  auto const &Inst = *i->getInst();
487  bool SubregBit = (Register & 0x1) != 0;
488  if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
489  // If subreg bit is set we're selecting the second produced newvalue
490  unsigned Producer = SubregBit ?
493  assert(Producer != Hexagon::NoRegister);
494  MCO.setReg(Producer);
495  } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
496  unsigned Producer =
498  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
499  Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
500  else if (SubregBit)
501  // Hexagon PRM 10.11 New-value operands
502  // Nt[0] is reserved and should always be encoded as zero.
503  return MCDisassembler::Fail;
504  assert(Producer != Hexagon::NoRegister);
505  MCO.setReg(Producer);
506  } else
507  return MCDisassembler::Fail;
508  }
509 
510  if (CurrentExtender != nullptr) {
511  MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
512  ? *MI.getOperand(1).getInst()
513  : MI;
514  if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
515  !HexagonMCInstrInfo::isExtended(*MCII, Inst))
516  return MCDisassembler::Fail;
517  }
518  return Result;
519 }
520 
521 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
522  ArrayRef<MCPhysReg> Table) {
523  if (RegNo < Table.size()) {
524  Inst.addOperand(MCOperand::createReg(Table[RegNo]));
526  }
527 
528  return MCDisassembler::Fail;
529 }
530 
532  uint64_t Address,
533  const void *Decoder) {
534  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
535 }
536 
537 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
538  uint64_t Address,
539  const void *Decoder) {
540  static const MCPhysReg IntRegDecoderTable[] = {
541  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
542  Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
543  Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
544  Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
545  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
546  Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
547  Hexagon::R30, Hexagon::R31};
548 
549  return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
550 }
551 
553  unsigned RegNo,
554  uint64_t Address,
555  const void *Decoder) {
556  static const MCPhysReg GeneralSubRegDecoderTable[] = {
557  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
558  Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
559  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
560  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
561  };
562 
563  return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
564 }
565 
566 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
567  uint64_t /*Address*/,
568  const void *Decoder) {
569  static const MCPhysReg HvxVRDecoderTable[] = {
570  Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
571  Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
572  Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
573  Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
574  Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
575  Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
576  Hexagon::V30, Hexagon::V31};
577 
578  return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
579 }
580 
581 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
582  uint64_t /*Address*/,
583  const void *Decoder) {
584  static const MCPhysReg DoubleRegDecoderTable[] = {
585  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
586  Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
587  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
588  Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
589 
590  return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
591 }
592 
594  MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
595  static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
596  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
597  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
598 
599  return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
600 }
601 
602 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
603  uint64_t /*Address*/,
604  const void *Decoder) {
605  static const MCPhysReg HvxWRDecoderTable[] = {
606  Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
607  Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
608  Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
609  Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
610 
611  return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable));
612 }
613 
614 LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
616  unsigned RegNo,
617  uint64_t /*Address*/,
618  const void *Decoder) {
619  static const MCPhysReg HvxVQRDecoderTable[] = {
620  Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
621  Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
622 
623  return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
624 }
625 
626 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
627  uint64_t /*Address*/,
628  const void *Decoder) {
629  static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
630  Hexagon::P2, Hexagon::P3};
631 
632  return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
633 }
634 
635 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
636  uint64_t /*Address*/,
637  const void *Decoder) {
638  static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
639  Hexagon::Q2, Hexagon::Q3};
640 
641  return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
642 }
643 
644 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
645  uint64_t /*Address*/,
646  const void *Decoder) {
647  using namespace Hexagon;
648 
649  static const MCPhysReg CtrlRegDecoderTable[] = {
650  /* 0 */ SA0, LC0, SA1, LC1,
651  /* 4 */ P3_0, C5, M0, M1,
652  /* 8 */ USR, PC, UGP, GP,
653  /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
654  /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
655  /* 20 */ 0, 0, 0, 0,
656  /* 24 */ 0, 0, 0, 0,
657  /* 28 */ 0, 0, UTIMERLO, UTIMERHI
658  };
659 
660  if (RegNo >= array_lengthof(CtrlRegDecoderTable))
661  return MCDisassembler::Fail;
662 
663  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
664  if (CtrlRegDecoderTable[RegNo] == NoRegister)
665  return MCDisassembler::Fail;
666 
667  unsigned Register = CtrlRegDecoderTable[RegNo];
668  Inst.addOperand(MCOperand::createReg(Register));
670 }
671 
672 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
673  uint64_t /*Address*/,
674  const void *Decoder) {
675  using namespace Hexagon;
676 
677  static const MCPhysReg CtrlReg64DecoderTable[] = {
678  /* 0 */ C1_0, 0, C3_2, 0,
679  /* 4 */ C5_4, 0, C7_6, 0,
680  /* 8 */ C9_8, 0, C11_10, 0,
681  /* 12 */ CS, 0, UPCYCLE, 0,
682  /* 16 */ C17_16, 0, PKTCOUNT, 0,
683  /* 20 */ 0, 0, 0, 0,
684  /* 24 */ 0, 0, 0, 0,
685  /* 28 */ 0, 0, UTIMER, 0
686  };
687 
688  if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
689  return MCDisassembler::Fail;
690 
691  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
692  if (CtrlReg64DecoderTable[RegNo] == NoRegister)
693  return MCDisassembler::Fail;
694 
695  unsigned Register = CtrlReg64DecoderTable[RegNo];
696  Inst.addOperand(MCOperand::createReg(Register));
698 }
699 
700 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
701  uint64_t /*Address*/,
702  const void *Decoder) {
703  unsigned Register = 0;
704  switch (RegNo) {
705  case 0:
706  Register = Hexagon::M0;
707  break;
708  case 1:
709  Register = Hexagon::M1;
710  break;
711  default:
712  return MCDisassembler::Fail;
713  }
714  Inst.addOperand(MCOperand::createReg(Register));
716 }
717 
718 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
719  uint64_t /*Address*/,
720  const void *Decoder) {
721  HexagonDisassembler const &Disassembler = disassembler(Decoder);
722  int64_t FullValue = fullValue(Disassembler, MI, tmp);
723  assert(FullValue >= 0 && "Negative in unsigned decoder");
724  HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
726 }
727 
728 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
729  uint64_t /*Address*/, const void *Decoder) {
730  HexagonDisassembler const &Disassembler = disassembler(Decoder);
731  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
732  tmp = SignExtend64(tmp, Bits);
733  signedDecoder<32>(MI, tmp, Decoder);
735 }
736 
737 // custom decoder for various jump/call immediates
738 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
739  const void *Decoder) {
740  HexagonDisassembler const &Disassembler = disassembler(Decoder);
741  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
742  // r13_2 is not extendable, so if there are no extent bits, it's r13_2
743  if (Bits == 0)
744  Bits = 15;
745  uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
746  uint32_t Extended = FullValue + Address;
747  if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
748  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
750 }
751 
752 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
753  uint64_t /*Address*/,
754  const void *Decoder) {
755  using namespace Hexagon;
756 
757  static const MCPhysReg GuestRegDecoderTable[] = {
758  /* 0 */ GELR, GSR, GOSP, G3,
759  /* 4 */ G4, G5, G6, G7,
760  /* 8 */ G8, G9, G10, G11,
761  /* 12 */ G12, G13, G14, G15,
762  /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
763  /* 20 */ G20, G21, G22, G23,
764  /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
765  /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
766  };
767 
768  if (RegNo >= array_lengthof(GuestRegDecoderTable))
769  return MCDisassembler::Fail;
770  if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
771  return MCDisassembler::Fail;
772 
773  unsigned Register = GuestRegDecoderTable[RegNo];
774  Inst.addOperand(MCOperand::createReg(Register));
776 }
777 
779  uint64_t /*Address*/,
780  const void *Decoder) {
781  using namespace Hexagon;
782 
783  static const MCPhysReg GuestReg64DecoderTable[] = {
784  /* 0 */ G1_0, 0, G3_2, 0,
785  /* 4 */ G5_4, 0, G7_6, 0,
786  /* 8 */ G9_8, 0, G11_10, 0,
787  /* 12 */ G13_12, 0, G15_14, 0,
788  /* 16 */ G17_16, 0, G19_18, 0,
789  /* 20 */ G21_20, 0, G23_22, 0,
790  /* 24 */ G25_24, 0, G27_26, 0,
791  /* 28 */ G29_28, 0, G31_30, 0
792  };
793 
794  if (RegNo >= array_lengthof(GuestReg64DecoderTable))
795  return MCDisassembler::Fail;
796  if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
797  return MCDisassembler::Fail;
798 
799  unsigned Register = GuestReg64DecoderTable[RegNo];
800  Inst.addOperand(MCOperand::createReg(Register));
802 }
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
iterator begin()
Definition: MCInst.h:191
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
DecodeStatus
Ternary decode status.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
Superclass for all disassemblers.
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:57
#define HEXAGON_INSTR_SIZE
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
#define R2(n)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isImmext(MCInst const &MCI)
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
#define Fail
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void erase(iterator I)
Definition: MCInst.h:189
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
const MCInst * getInst() const
Definition: MCInst.h:105
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:196
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void remapInstruction(Instruction *I, ValueToValueMapTy &VMap)
Convert the instruction operands from referencing the current values into those specified by VMap...
Definition: LoopUnroll.cpp:65
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
#define HEXAGON_MAX_PACKET_SIZE
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeHexagonDisassembler()
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
const T * data() const
Definition: ArrayRef.h:145
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned IntRegDecoderTable[]
void setOpcode(unsigned Op)
Definition: MCInst.h:170
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Promote Memory to Register
Definition: Mem2Reg.cpp:109
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static void adjustDuplex(MCInst &MI, MCContext &Context)
Target - Wrapper for Target specific information.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:178
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:143
#define Success
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
size_t size() const
Definition: MCInst.h:190
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define I(x, y, z)
Definition: MD5.cpp:58
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
uint32_t read32le(const void *P)
Definition: Endian.h:383
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
size_t bundleSize(MCInst const &MCI)
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:748
bool check(bool FullCheck=true)
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:70
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
Check for a valid bundle.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getOpcode() const
Definition: MCInst.h:171
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
Target & getTheHexagonTarget()
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)