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HexagonDisassembler.cpp
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1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "hexagon-disassembler"
11 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/Support/Endian.h"
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <memory>
34 
35 using namespace llvm;
36 using namespace Hexagon;
37 
39 
40 namespace {
41 
42 /// Hexagon disassembler for all Hexagon platforms.
43 class HexagonDisassembler : public MCDisassembler {
44 public:
45  std::unique_ptr<MCInstrInfo const> const MCII;
46  std::unique_ptr<MCInst *> CurrentBundle;
47  mutable MCInst const *CurrentExtender;
48 
49  HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
50  MCInstrInfo const *MCII)
51  : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
52  CurrentExtender(nullptr) {}
53 
54  DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
55  ArrayRef<uint8_t> Bytes, uint64_t Address,
56  raw_ostream &VStream, raw_ostream &CStream,
57  bool &Complete) const;
58  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
59  ArrayRef<uint8_t> Bytes, uint64_t Address,
60  raw_ostream &VStream,
61  raw_ostream &CStream) const override;
62  void remapInstruction(MCInst &Instr) const;
63 };
64 
65 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
66  int64_t Value) {
67  MCInstrInfo MCII = *Disassembler.MCII;
68  if (!Disassembler.CurrentExtender ||
69  MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
70  return Value;
71  unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
72  uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
73  int64_t Bits;
74  bool Success =
75  Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
76  Bits);
77  assert(Success);
78  (void)Success;
79  uint64_t Upper26 = static_cast<uint64_t>(Bits);
80  uint64_t Operand = Upper26 | Lower6;
81  return Operand;
82 }
83 static HexagonDisassembler const &disassembler(void const *Decoder) {
84  return *static_cast<HexagonDisassembler const *>(Decoder);
85 }
86 template <size_t T>
87 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
88  HexagonDisassembler const &Disassembler = disassembler(Decoder);
89  int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
90  int64_t Extended = SignExtend64<32>(FullValue);
91  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
92 }
93 }
94 
95 // Forward declare these because the auto-generated code will reference them.
96 // Definitions are further down.
97 
98 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
99  uint64_t Address,
100  const void *Decoder);
102  unsigned RegNo,
103  uint64_t Address,
104  const void *Decoder);
105 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
106  uint64_t Address,
107  const void *Decoder);
108 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
109  uint64_t Address,
110  const void *Decoder);
111 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
112  uint64_t Address,
113  const void *Decoder);
114 static DecodeStatus
116  uint64_t Address, const void *Decoder);
117 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
118  uint64_t Address,
119  const void *Decoder);
120 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
121  uint64_t Address,
122  const void *Decoder);
123 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
124  uint64_t Address,
125  const void *Decoder);
126 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
127  uint64_t Address,
128  const void *Decoder);
129 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
130  uint64_t Address,
131  const void *Decoder);
132 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
133  uint64_t Address,
134  const void *Decoder);
135 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
136  uint64_t Address,
137  const void *Decoder);
138 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
139  uint64_t Address,
140  const void *Decoder);
141 
142 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
143  uint64_t Address, const void *Decoder);
144 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
145  uint64_t /*Address*/, const void *Decoder);
146 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
147  const void *Decoder);
148 
149 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
150  const void *Decoder) {
151  signedDecoder<4>(MI, tmp, Decoder);
153 }
154 static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
155  const void *Decoder) {
156  signedDecoder<14>(MI, tmp, Decoder);
158 }
159 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
160  const void *Decoder) {
161  signedDecoder<8>(MI, tmp, Decoder);
163 }
164 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
165  const void *Decoder) {
166  signedDecoder<7>(MI, tmp, Decoder);
168 }
169 static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
170  const void *Decoder) {
171  signedDecoder<12>(MI, tmp, Decoder);
173 }
174 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
175  const void *Decoder) {
176  signedDecoder<3>(MI, tmp, Decoder);
178 }
179 static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
180  const void *Decoder) {
181  signedDecoder<13>(MI, tmp, Decoder);
183 }
184 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
185  const void *Decoder) {
186  signedDecoder<6>(MI, tmp, Decoder);
188 }
189 static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
190  const void *Decoder) {
191  signedDecoder<9>(MI, tmp, Decoder);
193 }
194 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
195  const void *Decoder) {
196  signedDecoder<5>(MI, tmp, Decoder);
198 }
199 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
200  const void *Decoder) {
201  signedDecoder<6>(MI, tmp, Decoder);
203 }
204 #include "HexagonGenDisassemblerTables.inc"
205 
207  const MCSubtargetInfo &STI,
208  MCContext &Ctx) {
209  return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
210 }
211 
215 }
216 
217 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
218  ArrayRef<uint8_t> Bytes,
219  uint64_t Address,
220  raw_ostream &os,
221  raw_ostream &cs) const {
223  bool Complete = false;
224  Size = 0;
225 
226  *CurrentBundle = &MI;
227  MI.setOpcode(Hexagon::BUNDLE);
229  while (Result == Success && !Complete) {
230  if (Bytes.size() < HEXAGON_INSTR_SIZE)
231  return MCDisassembler::Fail;
232  MCInst *Inst = new (getContext()) MCInst;
233  Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
236  Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
237  }
238  if (Result == MCDisassembler::Fail)
239  return Result;
241  return MCDisassembler::Fail;
242  HexagonMCChecker Checker(getContext(), *MCII, STI, MI,
243  *getContext().getRegisterInfo(), false);
244  if (!Checker.check())
245  return MCDisassembler::Fail;
246  remapInstruction(MI);
248 }
249 
251  for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
252  auto &MI = const_cast<MCInst &>(*I.getInst());
253  switch (MI.getOpcode()) {
254  case Hexagon::S2_allocframe:
255  if (MI.getOperand(0).getReg() == Hexagon::R29) {
256  MI.setOpcode(Hexagon::S6_allocframe_to_raw);
257  MI.erase(MI.begin () + 1);
258  MI.erase(MI.begin ());
259  }
260  break;
261  case Hexagon::L2_deallocframe:
262  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
263  MI.getOperand(1).getReg() == Hexagon::R30) {
264  MI.setOpcode(L6_deallocframe_map_to_raw);
265  MI.erase(MI.begin () + 1);
266  MI.erase(MI.begin ());
267  }
268  break;
269  case Hexagon::L4_return:
270  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
271  MI.getOperand(1).getReg() == Hexagon::R30) {
272  MI.setOpcode(L6_return_map_to_raw);
273  MI.erase(MI.begin () + 1);
274  MI.erase(MI.begin ());
275  }
276  break;
277  case Hexagon::L4_return_t:
278  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
279  MI.getOperand(2).getReg() == Hexagon::R30) {
280  MI.setOpcode(L4_return_map_to_raw_t);
281  MI.erase(MI.begin () + 2);
282  MI.erase(MI.begin ());
283  }
284  break;
285  case Hexagon::L4_return_f:
286  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
287  MI.getOperand(2).getReg() == Hexagon::R30) {
288  MI.setOpcode(L4_return_map_to_raw_f);
289  MI.erase(MI.begin () + 2);
290  MI.erase(MI.begin ());
291  }
292  break;
293  case Hexagon::L4_return_tnew_pt:
294  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
295  MI.getOperand(2).getReg() == Hexagon::R30) {
296  MI.setOpcode(L4_return_map_to_raw_tnew_pt);
297  MI.erase(MI.begin () + 2);
298  MI.erase(MI.begin ());
299  }
300  break;
301  case Hexagon::L4_return_fnew_pt:
302  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
303  MI.getOperand(2).getReg() == Hexagon::R30) {
304  MI.setOpcode(L4_return_map_to_raw_fnew_pt);
305  MI.erase(MI.begin () + 2);
306  MI.erase(MI.begin ());
307  }
308  break;
309  case Hexagon::L4_return_tnew_pnt:
310  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
311  MI.getOperand(2).getReg() == Hexagon::R30) {
312  MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
313  MI.erase(MI.begin () + 2);
314  MI.erase(MI.begin ());
315  }
316  break;
317  case Hexagon::L4_return_fnew_pnt:
318  if (MI.getOperand(0).getReg() == Hexagon::D15 &&
319  MI.getOperand(2).getReg() == Hexagon::R30) {
320  MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
321  MI.erase(MI.begin () + 2);
322  MI.erase(MI.begin ());
323  }
324  break;
325  }
326  }
327 }
328 
329 static void adjustDuplex(MCInst &MI, MCContext &Context) {
330  switch (MI.getOpcode()) {
331  case Hexagon::SA1_setin1:
332  MI.insert(MI.begin() + 1,
334  break;
335  case Hexagon::SA1_dec:
336  MI.insert(MI.begin() + 2,
338  break;
339  default:
340  break;
341  }
342 }
343 
344 DecodeStatus HexagonDisassembler::getSingleInstruction(
345  MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
346  raw_ostream &os, raw_ostream &cs, bool &Complete) const {
347  assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
348 
350 
351  auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
352  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
354  if (BundleSize == 0)
356  else if (BundleSize == 1)
358  else
359  return DecodeStatus::Fail;
360  }
361 
362  CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
364 
366  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
368  unsigned duplexIClass;
369  uint8_t const *DecodeLow, *DecodeHigh;
370  duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
371  switch (duplexIClass) {
372  default:
373  return MCDisassembler::Fail;
374  case 0:
375  DecodeLow = DecoderTableSUBINSN_L132;
376  DecodeHigh = DecoderTableSUBINSN_L132;
377  break;
378  case 1:
379  DecodeLow = DecoderTableSUBINSN_L232;
380  DecodeHigh = DecoderTableSUBINSN_L132;
381  break;
382  case 2:
383  DecodeLow = DecoderTableSUBINSN_L232;
384  DecodeHigh = DecoderTableSUBINSN_L232;
385  break;
386  case 3:
387  DecodeLow = DecoderTableSUBINSN_A32;
388  DecodeHigh = DecoderTableSUBINSN_A32;
389  break;
390  case 4:
391  DecodeLow = DecoderTableSUBINSN_L132;
392  DecodeHigh = DecoderTableSUBINSN_A32;
393  break;
394  case 5:
395  DecodeLow = DecoderTableSUBINSN_L232;
396  DecodeHigh = DecoderTableSUBINSN_A32;
397  break;
398  case 6:
399  DecodeLow = DecoderTableSUBINSN_S132;
400  DecodeHigh = DecoderTableSUBINSN_A32;
401  break;
402  case 7:
403  DecodeLow = DecoderTableSUBINSN_S232;
404  DecodeHigh = DecoderTableSUBINSN_A32;
405  break;
406  case 8:
407  DecodeLow = DecoderTableSUBINSN_S132;
408  DecodeHigh = DecoderTableSUBINSN_L132;
409  break;
410  case 9:
411  DecodeLow = DecoderTableSUBINSN_S132;
412  DecodeHigh = DecoderTableSUBINSN_L232;
413  break;
414  case 10:
415  DecodeLow = DecoderTableSUBINSN_S132;
416  DecodeHigh = DecoderTableSUBINSN_S132;
417  break;
418  case 11:
419  DecodeLow = DecoderTableSUBINSN_S232;
420  DecodeHigh = DecoderTableSUBINSN_S132;
421  break;
422  case 12:
423  DecodeLow = DecoderTableSUBINSN_S232;
424  DecodeHigh = DecoderTableSUBINSN_L132;
425  break;
426  case 13:
427  DecodeLow = DecoderTableSUBINSN_S232;
428  DecodeHigh = DecoderTableSUBINSN_L232;
429  break;
430  case 14:
431  DecodeLow = DecoderTableSUBINSN_S232;
432  DecodeHigh = DecoderTableSUBINSN_S232;
433  break;
434  }
435  MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
436  MCInst *MILow = new (getContext()) MCInst;
437  MCInst *MIHigh = new (getContext()) MCInst;
438  auto TmpExtender = CurrentExtender;
439  CurrentExtender =
440  nullptr; // constant extenders in duplex must always be in slot 1
441  Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
442  this, STI);
443  CurrentExtender = TmpExtender;
444  if (Result != DecodeStatus::Success)
445  return DecodeStatus::Fail;
446  adjustDuplex(*MILow, getContext());
447  Result = decodeInstruction(
448  DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
449  if (Result != DecodeStatus::Success)
450  return DecodeStatus::Fail;
451  adjustDuplex(*MIHigh, getContext());
452  MCOperand OPLow = MCOperand::createInst(MILow);
453  MCOperand OPHigh = MCOperand::createInst(MIHigh);
454  MI.addOperand(OPLow);
455  MI.addOperand(OPHigh);
456  Complete = true;
457  } else {
458  if ((Instruction & HexagonII::INST_PARSE_MASK) ==
460  Complete = true;
461 
462  if (CurrentExtender != nullptr)
463  Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
464  Address, this, STI);
465 
466  if (Result != MCDisassembler::Success)
467  Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
468  STI);
469 
470  if (Result != MCDisassembler::Success &&
471  STI.getFeatureBits()[Hexagon::ExtensionHVX])
472  Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
473  Address, this, STI);
474 
475  }
476 
477  switch (MI.getOpcode()) {
478  case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
479  case Hexagon::J4_cmpeqn1_f_jumpnv_t:
480  case Hexagon::J4_cmpeqn1_fp0_jump_nt:
481  case Hexagon::J4_cmpeqn1_fp0_jump_t:
482  case Hexagon::J4_cmpeqn1_fp1_jump_nt:
483  case Hexagon::J4_cmpeqn1_fp1_jump_t:
484  case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
485  case Hexagon::J4_cmpeqn1_t_jumpnv_t:
486  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
487  case Hexagon::J4_cmpeqn1_tp0_jump_t:
488  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
489  case Hexagon::J4_cmpeqn1_tp1_jump_t:
490  case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
491  case Hexagon::J4_cmpgtn1_f_jumpnv_t:
492  case Hexagon::J4_cmpgtn1_fp0_jump_nt:
493  case Hexagon::J4_cmpgtn1_fp0_jump_t:
494  case Hexagon::J4_cmpgtn1_fp1_jump_nt:
495  case Hexagon::J4_cmpgtn1_fp1_jump_t:
496  case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
497  case Hexagon::J4_cmpgtn1_t_jumpnv_t:
498  case Hexagon::J4_cmpgtn1_tp0_jump_nt:
499  case Hexagon::J4_cmpgtn1_tp0_jump_t:
500  case Hexagon::J4_cmpgtn1_tp1_jump_nt:
501  case Hexagon::J4_cmpgtn1_tp1_jump_t:
502  MI.insert(MI.begin() + 1,
503  MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
504  break;
505  default:
506  break;
507  }
508 
509  if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
510  unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
511  MCOperand &MCO = MI.getOperand(OpIndex);
512  assert(MCO.isReg() && "New value consumers must be registers");
513  unsigned Register =
514  getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
515  if ((Register & 0x6) == 0)
516  // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
517  return MCDisassembler::Fail;
518  unsigned Lookback = (Register & 0x6) >> 1;
519  unsigned Offset = 1;
520  bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
521  bool PrevVector = false;
522  auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
523  auto i = Instructions.end() - 1;
524  for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
525  if (i == n)
526  // Couldn't find producer
527  return MCDisassembler::Fail;
528  bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
529  if (Vector && !CurrentVector)
530  // Skip scalars when calculating distances for vectors
531  ++Lookback;
532  if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
533  ++Lookback;
534  PrevVector = CurrentVector;
535  if (Offset == Lookback)
536  break;
537  }
538  auto const &Inst = *i->getInst();
539  bool SubregBit = (Register & 0x1) != 0;
540  if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
541  // If subreg bit is set we're selecting the second produced newvalue
542  unsigned Producer = SubregBit ?
545  assert(Producer != Hexagon::NoRegister);
546  MCO.setReg(Producer);
547  } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
548  unsigned Producer =
550  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
551  Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
552  else if (SubregBit)
553  // Hexagon PRM 10.11 New-value operands
554  // Nt[0] is reserved and should always be encoded as zero.
555  return MCDisassembler::Fail;
556  assert(Producer != Hexagon::NoRegister);
557  MCO.setReg(Producer);
558  } else
559  return MCDisassembler::Fail;
560  }
561 
562  if (CurrentExtender != nullptr) {
563  MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
564  ? *MI.getOperand(1).getInst()
565  : MI;
566  if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
567  !HexagonMCInstrInfo::isExtended(*MCII, Inst))
568  return MCDisassembler::Fail;
569  }
570  return Result;
571 }
572 
573 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
574  ArrayRef<MCPhysReg> Table) {
575  if (RegNo < Table.size()) {
576  Inst.addOperand(MCOperand::createReg(Table[RegNo]));
578  }
579 
580  return MCDisassembler::Fail;
581 }
582 
584  uint64_t Address,
585  const void *Decoder) {
586  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
587 }
588 
589 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
590  uint64_t Address,
591  const void *Decoder) {
592  static const MCPhysReg IntRegDecoderTable[] = {
593  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
594  Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
595  Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
596  Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
597  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
598  Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
599  Hexagon::R30, Hexagon::R31};
600 
601  return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
602 }
603 
605  unsigned RegNo,
606  uint64_t Address,
607  const void *Decoder) {
608  static const MCPhysReg GeneralSubRegDecoderTable[] = {
609  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
610  Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
611  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
612  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
613  };
614 
615  return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
616 }
617 
618 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
619  uint64_t /*Address*/,
620  const void *Decoder) {
621  static const MCPhysReg HvxVRDecoderTable[] = {
622  Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
623  Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
624  Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
625  Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
626  Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
627  Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
628  Hexagon::V30, Hexagon::V31};
629 
630  return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
631 }
632 
633 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
634  uint64_t /*Address*/,
635  const void *Decoder) {
636  static const MCPhysReg DoubleRegDecoderTable[] = {
637  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
638  Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
639  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
640  Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
641 
642  return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
643 }
644 
646  MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
647  static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
648  Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
649  Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
650 
651  return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
652 }
653 
654 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
655  uint64_t /*Address*/,
656  const void *Decoder) {
657  static const MCPhysReg HvxWRDecoderTable[] = {
658  Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
659  Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
660  Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
661  Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
662 
663  return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable));
664 }
665 
666 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
667  uint64_t /*Address*/,
668  const void *Decoder) {
669  static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
670  Hexagon::P2, Hexagon::P3};
671 
672  return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
673 }
674 
675 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
676  uint64_t /*Address*/,
677  const void *Decoder) {
678  static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
679  Hexagon::Q2, Hexagon::Q3};
680 
681  return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
682 }
683 
684 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
685  uint64_t /*Address*/,
686  const void *Decoder) {
687  using namespace Hexagon;
688 
689  static const MCPhysReg CtrlRegDecoderTable[] = {
690  /* 0 */ SA0, LC0, SA1, LC1,
691  /* 4 */ P3_0, C5, M0, M1,
692  /* 8 */ USR, PC, UGP, GP,
693  /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
694  /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
695  /* 20 */ 0, 0, 0, 0,
696  /* 24 */ 0, 0, 0, 0,
697  /* 28 */ 0, 0, UTIMERLO, UTIMERHI
698  };
699 
700  if (RegNo >= array_lengthof(CtrlRegDecoderTable))
701  return MCDisassembler::Fail;
702 
703  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
704  if (CtrlRegDecoderTable[RegNo] == NoRegister)
705  return MCDisassembler::Fail;
706 
707  unsigned Register = CtrlRegDecoderTable[RegNo];
708  Inst.addOperand(MCOperand::createReg(Register));
710 }
711 
712 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
713  uint64_t /*Address*/,
714  const void *Decoder) {
715  using namespace Hexagon;
716 
717  static const MCPhysReg CtrlReg64DecoderTable[] = {
718  /* 0 */ C1_0, 0, C3_2, 0,
719  /* 4 */ C5_4, 0, C7_6, 0,
720  /* 8 */ C9_8, 0, C11_10, 0,
721  /* 12 */ CS, 0, UPCYCLE, 0,
722  /* 16 */ C17_16, 0, PKTCOUNT, 0,
723  /* 20 */ 0, 0, 0, 0,
724  /* 24 */ 0, 0, 0, 0,
725  /* 28 */ 0, 0, UTIMER, 0
726  };
727 
728  if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
729  return MCDisassembler::Fail;
730 
731  static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
732  if (CtrlReg64DecoderTable[RegNo] == NoRegister)
733  return MCDisassembler::Fail;
734 
735  unsigned Register = CtrlReg64DecoderTable[RegNo];
736  Inst.addOperand(MCOperand::createReg(Register));
738 }
739 
740 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
741  uint64_t /*Address*/,
742  const void *Decoder) {
743  unsigned Register = 0;
744  switch (RegNo) {
745  case 0:
746  Register = Hexagon::M0;
747  break;
748  case 1:
749  Register = Hexagon::M1;
750  break;
751  default:
752  return MCDisassembler::Fail;
753  }
754  Inst.addOperand(MCOperand::createReg(Register));
756 }
757 
758 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
759  uint64_t /*Address*/,
760  const void *Decoder) {
761  HexagonDisassembler const &Disassembler = disassembler(Decoder);
762  int64_t FullValue = fullValue(Disassembler, MI, tmp);
763  assert(FullValue >= 0 && "Negative in unsigned decoder");
764  HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
766 }
767 
768 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
769  uint64_t /*Address*/, const void *Decoder) {
770  HexagonDisassembler const &Disassembler = disassembler(Decoder);
771  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
772  tmp = SignExtend64(tmp, Bits);
773  signedDecoder<32>(MI, tmp, Decoder);
775 }
776 
777 // custom decoder for various jump/call immediates
778 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
779  const void *Decoder) {
780  HexagonDisassembler const &Disassembler = disassembler(Decoder);
781  unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
782  // r13_2 is not extendable, so if there are no extent bits, it's r13_2
783  if (Bits == 0)
784  Bits = 15;
785  uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
786  uint32_t Extended = FullValue + Address;
787  if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
788  HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
790 }
791 
792 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
793  uint64_t /*Address*/,
794  const void *Decoder) {
795  using namespace Hexagon;
796 
797  static const MCPhysReg GuestRegDecoderTable[] = {
798  /* 0 */ GELR, GSR, GOSP, G3,
799  /* 4 */ G4, G5, G6, G7,
800  /* 8 */ G8, G9, G10, G11,
801  /* 12 */ G12, G13, G14, G15,
802  /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
803  /* 20 */ G20, G21, G22, G23,
804  /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
805  /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
806  };
807 
808  if (RegNo >= array_lengthof(GuestRegDecoderTable))
809  return MCDisassembler::Fail;
810  if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
811  return MCDisassembler::Fail;
812 
813  unsigned Register = GuestRegDecoderTable[RegNo];
814  Inst.addOperand(MCOperand::createReg(Register));
816 }
817 
819  uint64_t /*Address*/,
820  const void *Decoder) {
821  using namespace Hexagon;
822 
823  static const MCPhysReg GuestReg64DecoderTable[] = {
824  /* 0 */ G1_0, 0, G3_2, 0,
825  /* 4 */ G5_4, 0, G7_6, 0,
826  /* 8 */ G9_8, 0, G11_10, 0,
827  /* 12 */ G13_12, 0, G15_14, 0,
828  /* 16 */ G17_16, 0, G19_18, 0,
829  /* 20 */ G21_20, 0, G23_22, 0,
830  /* 24 */ G25_24, 0, G27_26, 0,
831  /* 28 */ G29_28, 0, G31_30, 0
832  };
833 
834  if (RegNo >= array_lengthof(GuestReg64DecoderTable))
835  return MCDisassembler::Fail;
836  if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
837  return MCDisassembler::Fail;
838 
839  unsigned Register = GuestReg64DecoderTable[RegNo];
840  Inst.addOperand(MCOperand::createReg(Register));
842 }
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
iterator begin()
Definition: MCInst.h:194
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
#define R4(n)
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
DecodeStatus
Ternary decode status.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
Superclass for all disassemblers.
static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:58
#define HEXAGON_INSTR_SIZE
static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
#define R2(n)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isImmext(MCInst const &MCI)
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
#define Fail
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void erase(iterator I)
Definition: MCInst.h:192
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
Context object for machine code objects.
Definition: MCContext.h:63
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
const MCInst * getInst() const
Definition: MCInst.h:106
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:199
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void remapInstruction(Instruction *I, ValueToValueMapTy &VMap)
Convert the instruction operands from referencing the current values into those specified by VMap...
Definition: LoopUnroll.cpp:66
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
#define HEXAGON_MAX_PACKET_SIZE
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeHexagonDisassembler()
static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
const T * data() const
Definition: ArrayRef.h:146
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned IntRegDecoderTable[]
void setOpcode(unsigned Op)
Definition: MCInst.h:173
#define R6(n)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:900
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Promote Memory to Register
Definition: Mem2Reg.cpp:110
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static void adjustDuplex(MCInst &MI, MCContext &Context)
Target - Wrapper for Target specific information.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:179
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:144
#define Success
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
size_t size() const
Definition: MCInst.h:193
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
#define I(x, y, z)
Definition: MD5.cpp:58
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
uint32_t read32le(const void *P)
Definition: Endian.h:369
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:47
size_t bundleSize(MCInst const &MCI)
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:749
bool check(bool FullCheck=true)
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:71
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
Check for a valid bundle.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder)
unsigned getOpcode() const
Definition: MCInst.h:174
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
Target & getTheHexagonTarget()
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)